An anti-interference frame synchronization method, device and medium in high-speed frequency hopping communication

Abstract

The application discloses an anti-interference frame synchronization method in high-speed frequency hopping communication, equipment and medium, the anti-interference frame synchronization method in high-speed frequency hopping communication includes: combining interference detection based on communication receiving end and single synchronization pulse correlation value multi-feature joint decision, constantly interference detection is carried out to receiving end synchronization pulse signal, and the position of interference point is marked, according to the number of non-interference marked points in synchronization pulse and the synchronization correlation value calculated from non-interference marked points and the threshold value set, multi-feature joint decision is carried out, to carry out error correction processing to the correlation value of current pulse, and the accumulation of multiple synchronization pulse correlation values, by setting reasonable threshold, the correct frame synchronization position is finally detected. The application can be in the case where interference exists, through interference detection and single pulse correlation value multi-feature joint decision technology, can realize the great improvement of anti-interference frame synchronization performance under the premise of not increasing additional resources.

Description

Technical Field

[0001] This application belongs to the field of wireless communication technology, and particularly relates to an anti-interference frame synchronization method, device, and medium in high-speed frequency hopping communication. It is applicable to situations where interference signals in communication transmission cause frame synchronization performance to degrade and fail to meet communication requirements. Background Technology

[0002] In data communication, to ensure demodulation performance, frame synchronization of the received signal is necessary to determine its time synchronization position for subsequent demodulation and decoding operations. However, in high-speed frequency-hopping communication environments with interference, frame synchronization performance is affected by the interference signal, leading to decreased detection probability, increased false alarm probability, and consequently, degraded demodulation performance. In particular, under conditions of strong interference or low receiver sensitivity, frame synchronization may even be completely impossible. Summary of the Invention

[0003] The purpose of this application is to overcome the problems of the prior art by combining interference detection and multi-feature joint decision technology of single-pulse correlation value in high-speed frequency hopping communication systems, and to disclose an anti-interference frame synchronization method, device, and medium in high-speed frequency hopping communication. This invention can effectively reduce the impact of interference signals on frame synchronization performance in high-speed frequency hopping communication systems when interference signals are present, ensuring correct frame synchronization of communication signals without increasing resources, and improving the anti-interference performance of the communication system.

[0004] On the one hand, the objective of this application is achieved through the following technical solution: An anti-interference frame synchronization method for high-speed frequency hopping communication, the method comprising: By combining interference detection at the receiving end with multi-feature joint decision based on the correlation value of a single synchronization pulse, interference detection is continuously performed on the receiving end synchronization pulse signal, and the location of interference points is marked. Based on the number of non-interference marked points in the synchronization pulse, the synchronization correlation value calculated from the non-interference marked points, and the set threshold value, multi-feature joint decision is performed to correct the correlation value of the current pulse. The correlation values ​​of multiple synchronization pulses are accumulated, and by setting a reasonable threshold, the correct frame synchronization position is finally detected.

[0005] According to a preferred embodiment, the anti-interference frame synchronization method in high-speed frequency hopping communication specifically includes: S1: Perform interference detection on the signal at the communication receiving end, and mark the receiving signal for interference based on the interference detection results; S2: During the quantization process of the received signal, non-interference markers are quantized normally, while the quantization value of interference markers is 0. S3: Calculate the correlation value of a single synchronization pulse at the current moment; S4: Count the number of non-zero pulses in the current pulse; S5: Perform multi-feature joint decision on the correlation value of a single synchronization pulse to correct the correlation value of the current pulse; S6: Accumulate the correlation values ​​of multiple synchronization pulses to obtain the frame synchronization correlation value at the current moment; S7: Perform a threshold judgment on the frame synchronization correlation value at the current moment to obtain information on whether frame synchronization has been successful.

[0006] Step S7, by setting a reasonable threshold, can greatly improve the anti-interference capability of the communication system in a high-speed frequency hopping communication environment where interference exists, achieve performance improvement of frame synchronization under interference conditions, and ensure correct signal reception.

[0007] According to a preferred embodiment, step S5 includes: if the single-pulse correlation value / the number of non-zero synchronization pulses If the number of synchronization symbols is greater than or equal to the threshold value cor_TH, and the number of non-zero current synchronization pulses is greater than or equal to the threshold value num_TH, then the new value of the correlation value of the current single synchronization pulse is: single pulse correlation value / number of non-zero synchronization pulses. The number of synchronization symbols is set; otherwise, the correlation value of the single synchronization pulse remains unchanged.

[0008] On the other hand, this application also discloses: An electronic device includes: at least one processor; and a memory communicatively connected to said at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the aforementioned method by executing the instructions stored in the memory.

[0009] On the other hand, this application also discloses: A computer-readable storage medium for storing instructions that, when executed, cause the aforementioned method to be implemented.

[0010] The aforementioned main solution and its various further alternative solutions can be freely combined to form multiple solutions, all of which are solutions that can be adopted and are claimed in this application. Those skilled in the art, after understanding the solution of this application, will realize that there are many combinations based on the prior art and common general knowledge, all of which are technical solutions to be protected in this application, and will not be exhaustively listed here.

[0011] The beneficial effects of this application are: This application can significantly improve the frame synchronization performance against interference without increasing additional resources by using interference detection and multi-feature joint decision technology based on single-pulse correlation values ​​in the presence of interference.

[0012] This application detects interference in the received signal, marks the location of the interfered signal, quantizes the marked and unmarked signals separately, and then calculates a new single-pulse synchronization correlation value based on the number of non-interference markers in the synchronization pulse, the synchronization correlation value calculated from the non-interference markers, and a reasonably set threshold value. Multiple synchronization pulse correlation values ​​are then accumulated, and a reasonable threshold is set. This significantly improves the system's anti-interference capability in high-speed frequency-hopping communication environments where interference exists, enhances frame synchronization performance under interference conditions, and ensures correct signal reception. Attached Figure Description

[0013] Figure 1 This is a flowchart illustrating the anti-interference frame synchronization method in high-speed frequency hopping communication of this application; Figure 2 This is the frame synchronization detection probability performance of Embodiment 1 of this application under the condition of 14 synchronization pulses and single pulse synchronization symbol number = 52; Figure 3 This is a schematic diagram of the equipment structure in this application. Detailed Implementation

[0014] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0015] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0016] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0017] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0018] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0019] Furthermore, it should be noted that unless otherwise specified in this application, the specific structures, connections, positions, power sources, etc. involved are all things that a person skilled in the art can know without creative effort based on the prior art.

[0020] Example 1 refer to Figure 1 and Figure 2 As shown, this embodiment uses 14 synchronization pulses and a single pulse synchronization symbol count of 52 as an example to perform anti-interference frame synchronization at the communication receiving end. The anti-interference frame synchronization method proposed in this embodiment for high-speed frequency hopping communication includes the following steps.

[0021] Step 1: Perform interference detection on the signal at the communication receiving end, and mark the receiving signal as having interference based on the interference detection results.

[0022] Step 2: During the receiving signal quantization process, non-interference markers are quantized normally, while interference markers are quantized to a value of 0.

[0023] Step 3: Calculate the correlation value cor of a single synchronization pulse at the current moment: Assume the received data is: The data interval is the symbol rate, the length is 52, and the local correlation code is... The value is ±1. Therefore, the relevant result is: .

[0024] Step 4: Count the number of non-zero pulses (num) in the current pulse.

[0025] Step 5: Perform multi-feature joint decision on the correlation value of a single synchronization pulse, including but not limited to: if cor / num If 52 >= the threshold value cor_TH, and the number of non-zero current synchronization pulses num >= the threshold value num_TH, then the new value cor_new of the current synchronization pulse correlation value is: cor / num 52, otherwise, keep the correlation value of the single synchronization pulse unchanged.

[0026] Step 6: Accumulate the correlation values ​​of the 12 synchronization pulses to obtain the frame synchronization correlation value corALL at the current moment.

[0027] Step 7: Perform a threshold decision, corALL_Th, on the current frame synchronization correlation value corALL to determine whether frame synchronization has been successful. By setting a reasonable threshold, Step 7 can significantly improve the anti-interference capability of the communication system in high-speed frequency hopping communication environments with interference, thereby enhancing frame synchronization performance under interference conditions and ensuring correct signal reception, thus improving the system's anti-interference performance.

[0028] Example 2 like Figure 3 As shown in Embodiment 1, this embodiment also discloses an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; the specific connection medium between the processor and the memory is not limited in this embodiment.

[0029] Figure 3 This example illustrates the connection between the processor and memory via a bus. The bus... Figure 3 The connections between other components are shown in thick lines for illustrative purposes only and should not be construed as limiting. Buses can be categorized into address buses, data buses, control buses, etc., but for ease of representation, [the specific bus type is not shown here]. Figure 3 A single thick line is used to represent a processor, but this does not mean there is only one bus or one type of bus. Alternatively, a processor can also be called a controller; there is no restriction on the name.

[0030] In this embodiment, the memory stores instructions executable by the at least one processor. By executing the instructions stored in the memory, the at least one processor performs the method described in Embodiment 1. The processor can implement... Figure 3 The functions of each module in the device are shown.

[0031] The processor is the control center of the device. It can connect to various parts of the control device through various interfaces and lines. By running or executing instructions stored in memory and calling data stored in memory, it can monitor the device's various functions and process data, thereby enabling overall monitoring of the device.

[0032] In an alternative design, the processor may include one or more processing units. The processor may integrate an application processor and a modem processor, wherein the application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may also not be integrated into the processor. In some embodiments, the processor and memory may be implemented on the same chip; in some embodiments, they may also be implemented separately on separate chips.

[0033] The processor can be a general-purpose processor, such as a CPU, digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the anti-interference frame synchronization method in high-speed frequency hopping communication disclosed in the embodiments of this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0034] Memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), and electrically erasable programmable read-only memory (EPROM). Only memory (EEPROM), magnetic storage, magnetic disks, optical disks, etc. A memory is any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited thereto. The memory in embodiments of this invention can also be a circuit or any other device capable of performing storage functions for storing program instructions and / or data.

[0035] By designing and programming the processor, the code corresponding to the anti-interference frame synchronization method in high-speed frequency hopping communication described in the foregoing embodiments can be embedded into the chip, thereby enabling the chip to execute the steps of the method described in the foregoing embodiments during operation. How to design and program the processor is a technique well-known to those skilled in the art, and will not be elaborated upon here.

[0036] Example 3 Based on Embodiment 1, this embodiment also discloses: a computer-readable storage medium for storing instructions that, when executed, cause the method described in Embodiment 1 to be implemented.

[0037] In some alternative embodiments, the present invention also provides a method for anti-interference frame synchronization in high-speed frequency hopping communication, which can also be implemented as a program product including program code. When the program product is run on a device, the program code is used to cause the control device to perform the steps in the method for anti-interference frame synchronization in high-speed frequency hopping communication according to various exemplary embodiments of the present invention as described above.

[0038] It should be noted that although several units or sub-units of the apparatus have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the invention, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units. Furthermore, although the operation of the method of the invention is described in a specific order in the drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0039] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can be implemented in one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs) containing computer-usable program code. The form of a computer program product implemented on ROM, optical memory, etc.

[0040] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a server, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0041] Program code for performing the operations of this invention can be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0042] In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0043] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0044] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

Claims

1. A method for anti-interference frame synchronization in high-speed frequency hopping communication, characterized in that, The anti-interference frame synchronization method in high-speed frequency hopping communication includes: By combining interference detection at the communication receiver with multi-feature joint decision based on the correlation value of a single synchronization pulse, interference detection is continuously performed on the receiver synchronization pulse signal, and the location of interference points is marked. Based on the number of non-interference marked points in the synchronization pulse, the synchronization correlation value calculated from the non-interference marked points, and the set threshold value, multi-feature joint decision is performed to correct the correlation value of the current pulse. The correlation values ​​of multiple synchronization pulses are accumulated, and by setting a threshold, the correct frame synchronization position is finally detected.

2. The anti-interference frame synchronization method in high-speed frequency hopping communication as described in claim 1, characterized in that, The anti-interference frame synchronization method in high-speed frequency hopping communication specifically includes: S1: Perform interference detection on the signal at the communication receiving end, and mark the receiving signal for interference based on the interference detection results; S2: During the quantization process of the received signal, non-interference markers are quantized normally, while the quantization value of interference markers is 0. S3: Calculate the correlation value cor of a single synchronization pulse at the current moment; S4: Count the number of non-zero pulses in the current pulse; S5: Perform multi-feature joint decision on the correlation value of a single synchronization pulse to correct the correlation value of the current pulse; S6: Accumulate the correlation values ​​of multiple synchronization pulses to obtain the frame synchronization correlation value at the current moment; S7: Perform a threshold judgment on the frame synchronization correlation value at the current moment to obtain information on whether frame synchronization has been successful.

3. The anti-interference frame synchronization method in high-speed frequency hopping communication as described in claim 2, characterized in that, Step S5 includes: If the single-pulse correlation value / the number of non-zero synchronization pulses If the number of synchronization symbols is greater than or equal to the threshold value cor_TH, and the number of non-zero current synchronization pulses is greater than or equal to the threshold value num_TH, then the new value of the correlation value of the current single synchronization pulse is: single pulse correlation value / number of non-zero synchronization pulses. The number of synchronization symbols is set; otherwise, the correlation value of the single synchronization pulse remains unchanged.

4. An electronic device, characterized in that, include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions executable by the at least one processor, which executes the instructions stored in the memory to perform the method as described in any one of claims 1 to 4.

5. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store instructions that, when executed, cause the method as described in any one of claims 1 to 4 to be implemented.

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