A method, device and medium for implementing package testing of a memory chip

Abstract

The application discloses a kind of for realizing the package test method, equipment and medium of storage chip, it is related to package electrical measurement analysis technical field, comprising: collection package electrical connection parameter, according to package electrical connection parameter establishes electrical measurement position association, extracts electrical stress sensitive area from electrical measurement position association, and sequentially arranges to electrical stress sensitive area, generates electrical measurement drive sequence;Injection hierarchical electrical excitation signal to electrical measurement drive sequence, and synchronous collection electrical response characteristic parameter, decouples analysis is carried out to electrical response characteristic parameter, generates electrical characteristic response data;Around electrical abnormal propagation path implementation reverse compensation electrical excitation and adjacent node contrast verification, obtain verification response data, and the electrical response change trend before and after compensation is carried out to verification response data consistency comparison and convergence analysis, generates electrical performance test scheme.The application improves the abnormal positioning accuracy and enhances electrical performance test scheme reliability.

Description

Technical Field

[0001] This invention relates to the field of packaging electrical testing and analysis technology, and in particular to a packaging testing method, equipment and medium for memory chips. Background Technology

[0002] With the continuous evolution of memory chips in high-density packaging, multi-layer interconnects, and micro-pitch structures, packaging testing methods are gradually shifting from the traditional combination of functional testing and functional verification to a comprehensive testing mode oriented towards electrical connection integrity and dynamic electrical characteristic evaluation. In existing methods, parameters such as voltage, current, and impedance of the packaged memory chip are usually collected through test probes or built-in self-test structures, and each test node is scanned point by point in combination with test sequences to obtain electrical response information of the package under different operating states. Some methods introduce timing sampling and statistical analysis methods to perform trend analysis and anomaly identification on electrical response data to complete the detection of typical defects such as open circuit, short circuit, and poor contact.

[0003] Existing methods mostly focus on determining the electrical characteristics of static nodes or local areas, lacking a systematic description and correlation analysis mechanism for the propagation path of electrical anomalies between different connection nodes. This results in problems of discontinuous information and insufficient correlation in the process of anomaly localization and cause determination. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a packaging and testing method for memory chips that solves the problems of difficult description of electrical anomaly propagation paths and insufficient correlation of anomaly location.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a packaging test method for implementing a memory chip, comprising: acquiring packaging electrical connection parameters; establishing electrical test location associations based on the packaging electrical connection parameters; extracting electrical stress sensitive regions from the electrical test location associations; sequentially arranging the electrical stress sensitive regions to generate an electrical test drive sequence; injecting hierarchical electrical excitation signals into the electrical test drive sequence and simultaneously acquiring electrical response characteristic parameters; performing decoupling analysis on the electrical response characteristic parameters to generate electrical characteristic response data; performing time stamp matching and continuous sequence reconstruction on the electrical characteristic response data to obtain time-series electrical response records; performing abnormal fluctuation identification and time-series association analysis on the time-series electrical response records to generate an electrical anomaly propagation path; implementing reverse compensation electrical excitation around the electrical anomaly propagation path and comparing and verifying with adjacent nodes to obtain verification response data; and performing consistency comparison and convergence analysis on the electrical response change trends of the verification response data before and after compensation to generate an electrical performance test scheme.

[0008] As a preferred embodiment of the packaging and testing method for memory chips described in this invention, the specific steps for generating the electrical test drive sequence are as follows:

[0009] The package interconnect data of the package is identified by node encoding, the node encoding data is obtained, and the connectivity relationship of the node encoding data is parsed and constructed to generate package electrical connection parameters;

[0010] Each connection node in the encapsulated electrical connection parameters is matched one by one with the electrical test access point to obtain the corresponding access data, and the connection data is merged and connected to generate the electrical test location association.

[0011] Based on the correlation of electrical measurement locations, the path structure characteristics of each connection node are analyzed item by item to obtain structural characteristic parameters. The structural characteristic parameters are then filtered for sensitivity according to structural complexity to generate electrical stress sensitive areas.

[0012] Based on the electrical stress sensitive region, the adjacent acceptance sorting of each connection node is performed to obtain the node sorting data, and the connection and resolution are performed according to the node sorting data to generate a sensitive access sequence.

[0013] The sensitive access sequence is mapped and orchestrated to obtain the driving timing, and the driving timing is uniformly configured and sequentially expanded to generate the electrical test driving sequence.

[0014] As a preferred embodiment of the packaging and testing method for memory chips described in this invention, the specific steps of injecting graded electrical excitation signals into the electrical test drive sequence and simultaneously acquiring electrical response characteristic parameters are as follows:

[0015] A graded electrical excitation signal is injected into the electrical measurement drive sequence one by one, and a micro-amplitude perturbation is superimposed at each excitation stage to generate a graded excitation sequence.

[0016] Based on the hierarchical excitation sequence, the current connected node and its adjacent connected nodes are synchronously sampled at multiple time points to obtain the changes in electrical response. The changes in electrical response are then time-series correlated and identified to generate response sampling data.

[0017] The sampling time in the response sampling data is segmented and time-series processed to obtain the changes in electrical characteristics. The changes in electrical characteristics are then normalized to generate electrical response characteristic parameters.

[0018] As a preferred embodiment of the packaging and testing method for memory chips described in this invention, the specific steps for generating electrical characteristic response data are as follows:

[0019] The changes in electrical characteristics of electrical response parameters in different sampling segments are segmented and compared with adjacent correlations to construct the perturbation propagation relationship.

[0020] The intrinsic conduction component and the coupled disturbance component in the disturbance propagation relationship are separated and calculated to generate decoupled response data;

[0021] Based on the decoupled response data, the response changes of the same connection node at different excitation stages are checked for longitudinal consistency to obtain longitudinally consistent data. Then, the response changes of the longitudinally consistent data at the same sampling time are compared and analyzed laterally to generate intrinsic response data.

[0022] The response information of the intrinsic response data is sequentially integrated to obtain integrated response data, and the integrated response data is then arranged into nodes to generate electrical characteristic response data.

[0023] As a preferred embodiment of the packaging and testing method for memory chips described in this invention, the specific steps for performing time-stamp matching and continuous sequence reconstruction on the electrical characteristic response data to obtain time-series electrical response records are as follows:

[0024] The electrical characteristic response data is grouped by time and classified by node to obtain time slot group data. Based on the time slot group data, the time markers in each connected node are corrected in order to generate time-aligned data.

[0025] Based on time-aligned data, response break intervals are identified. Interpolation and sequential splicing are performed on the changes before and after the response break intervals to obtain reconstructed response data. The reconstructed response data is combined with the response constraints of adjacent connected nodes and boundary limits are applied to generate continuous response data.

[0026] Differential calculations are performed on the response changes of continuous response data between adjacent time slots to obtain response change data. The response change data is then written into the time slot positions in chronological order to generate a time-series electrical response record.

[0027] As a preferred embodiment of the packaging and testing method for memory chips described in this invention, the specific steps for generating the electrical anomaly propagation path are as follows:

[0028] Abnormal fluctuations and abnormal segments are identified and filtered for response changes in adjacent time slots of time-series electrical response records, generating abnormal segment data.

[0029] Based on the abnormal fragment data, abnormal fragments of the same connection node are continuously spliced ​​together, and the abnormal fragments between adjacent connection nodes are subjected to continuity analysis to generate propagation connection data.

[0030] The strength of the transmission connection data is determined and the transmission connection is screened. The transmission connection data that meets the transmission conditions are sequentially concatenated and the path is extended to generate abnormal transmission chain data.

[0031] The start and end nodes of each propagation chain segment in the abnormal propagation chain data are identified and arranged in chronological order. Chain segments that can be continuously connected are merged to generate an electrical abnormality propagation path.

[0032] As a preferred embodiment of the packaging and testing method for memory chips described in this invention, the specific steps for implementing reverse compensation electrical excitation and comparing verification with adjacent nodes around the electrical anomaly propagation path to obtain verification response data are as follows:

[0033] The chain segment reverse sorting extraction is performed on the electrical anomaly propagation path to obtain path node data. The path node data is then combined with the anomaly propagation direction and time slot position and directional timing marking is performed to generate reverse compensation queue data.

[0034] Reverse electrical excitation is loaded node by node according to the reverse compensation queue data order to construct compensation response data. The excitation amplitude and application order in the compensation response data are adjusted to obtain compensation excitation data. The compensation excitation data is then synchronously sampled to generate verification sampling data.

[0035] The differences in electrical response changes in the verification sampling data are sorted out to obtain the corresponding response information, and the corresponding response information is correlated and arranged to generate verification response data.

[0036] As a preferred embodiment of the packaging and testing method for memory chips described in this invention, the specific steps for performing consistency comparison and convergence analysis on the electrical response change trend of the verification response data before and after compensation to generate an electrical performance test plan are as follows:

[0037] The voltage, current, and phase changes of the verification response data before and after compensation are trend-expanded and compared with the direction to obtain trend comparison data. Based on the trend comparison data, the consistency of the response changes is compared, and the convergence of the response changes is determined to generate convergence judgment data.

[0038] The convergence determination data is uniformly organized and arranged in order to obtain the compensation status. The compensation status is then classified and the test path is integrated to generate an electrical performance test plan.

[0039] In a second aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, wherein when the computer program is executed by the processor, it implements any step of the packaging and testing method for implementing a memory chip as described in the first aspect of the present invention.

[0040] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the packaging and testing method for implementing a memory chip as described in the first aspect of the present invention.

[0041] The beneficial effects of this invention are as follows: By injecting graded electrical excitation signals into the electrical test drive sequence and combining them with an impedance perturbation decoupling algorithm to separate and analyze the electrical response characteristic parameters, the intrinsic conduction component and the coupled perturbation component are effectively distinguished, thereby obtaining electrical characteristic response data with structural consistency and physical interpretability, providing a high-purity foundation for functional testing and anomaly identification; at the same time, by time stamp matching and continuous sequence reconstruction, and combined with the electrical anomaly determination method, a directional and continuous electrical anomaly propagation path is formed, and then by reverse compensation electrical excitation and comparison verification with adjacent nodes, the reverse confirmation of the anomaly propagation relationship and the location of the cause are completed, improving the anomaly location accuracy and enhancing the reliability of the electrical performance testing scheme. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the generation of the electrical measurement drive sequence.

[0044] Figure 2 This is a schematic diagram of the electrical characteristic response data.

[0045] Figure 3 This is a schematic diagram illustrating the propagation path of electrical anomalies.

[0046] Figure 4 A schematic diagram is generated for the electrical performance testing scheme.

[0047] Figure 5 This is a thermal diagram of the equivalent impedance change. Detailed Implementation

[0048] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0050] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0051] Reference Figures 1-5 This is one embodiment of the present invention, which provides a packaging and testing method for implementing a memory chip, including the following steps:

[0052] S1. Collect the encapsulation electrical connection parameters, establish electrical test position association based on the encapsulation electrical connection parameters, extract the electrical stress sensitive area from the electrical test position association, and arrange the electrical stress sensitive area in sequence to generate the electrical test drive sequence.

[0053] S1.1. The package interconnection data of the package is identified by node encoding, the node encoding data is obtained, and the connectivity relationship of the node encoding data is parsed and constructed to generate the package electrical connection parameters.

[0054] It should be noted that the package interconnection data of the package is read item by item according to the connection position, connection level and connection direction, and a unique node identifier is assigned to each connection node according to the preset encoding rules to generate node encoding data. Based on the node encoding data, the connection positions before and after, the connection positions above and below, and the adjacent connection positions corresponding to each node identifier are compared item by item to determine whether there is an actual conductive relationship between each node, and the nodes that meet the conductive relationship are associated with each other according to the connection order. Then, the corresponding association content is organized to clarify the connection start point, connection end point and connection path between each connection node, and the package electrical connection parameters are generated.

[0055] It should also be noted that the coding rules are used to uniformly express and uniquely identify the connection position, connection level and connection direction in the encapsulated interconnection data, so as to ensure the consistency and comparability of the node coding data; and to classify and define according to the wiring relationship, inter-layer connection method and connection topology to form a standardized coding basis.

[0056] S1.2 Match each connection node in the encapsulated electrical connection parameters with the electrical test access point one by one, obtain the corresponding access data, and perform connectivity verification and merging on the corresponding access data to generate electrical test location association.

[0057] It should be noted that each connection node in the encapsulated electrical connection parameters is read item by item according to node identifier, connection position and connection path, and compared with the corresponding electrical test access point in the spatial location to determine whether a path correspondence is formed and obtain the access corresponding data; the connection continuity, path integrity and position consistency of the access corresponding data are verified, and the correspondence that meets the conditions and points to the same connection area are merged and organized to generate electrical test location association.

[0058] It should also be noted that electrical measurement location association is used to establish the correspondence between connection nodes and electrical measurement access points. By uniformly mapping the connection path, spatial location, and conduction relationship, a one-to-one correspondence is formed between the electrical excitation application position and the electrical response acquisition position of each connection node, thereby ensuring the path consistency and sampling accuracy of the electrical measurement process; at the same time, it provides a reliable positioning basis and structural basis for subsequent identification of electrical stress sensitive areas, analysis of electrical response characteristics, and analysis of abnormal propagation paths.

[0059] S1.3. Based on the correlation of electrical measurement locations, the path structure characteristics of each connection node are analyzed item by item to obtain structural characteristic parameters. The structural characteristic parameters are then filtered for sensitivity according to structural complexity to generate electrical stress sensitive areas.

[0060] It should be noted that, based on the correlation of electrical measurement locations, the connection paths, transition locations, branches, and inter-layer transitions of the connection nodes are read item by item, and the connection relationships before and after are analyzed according to the connection extension order. The number of turning points, the number of branches, the number of cross-layers, and the density of adjacency are counted to obtain structural characteristic parameters. The structural characteristic parameters are compared according to the structural complexity, and connection nodes with frequent turning points, concentrated branches, cross-layer intersections, and close adjacency are selected. They are then merged according to spatial adjacency relationships to generate electrical stress sensitive areas.

[0061] S1.4. Based on the electrical stress sensitive area, the adjacent acceptance sorting of each connection node is performed to obtain the node sorting data, and the connection resolution is performed according to the node sorting data to generate a sensitive access sequence.

[0062] It should be noted that, based on the electrically sensitive region, the adjacency relationship of nodes is first read according to the spatial coordinates of the connection nodes in the electrically sensitive region, the entrance of the connection path, and the exit of the connection path. Connection nodes with direct conduction relationship and located on the same continuous connection path are identified as candidate receiving nodes. Then, taking the connection node corresponding to the direction of electric excitation entry as the starting node, candidate receiving nodes are searched level by level along the exit direction of the connection path. The spatial distance between the candidate receiving node and the current connection node is checked to see if it is within the adjacency range, whether there is a continuous conduction segment in the connection path, and whether the path receiving direction is consistent with the direction of electric excitation transmission. Candidate receiving nodes that meet the requirements of adjacency range, continuous conduction segment, and consistent transmission direction are written into the node sorting data. Subsequently, cross-receiving, skip-receiving, and duplicate-receiving in the node sorting data are resolved. Cross-receiving is retained first according to the receiving relationship with longer continuous path length. Skip-receiving is re-sorted after filling in the missing intermediate connecting nodes. Duplicate-receiving is retained according to the first stable receiving position and subsequent duplicate positions are deleted. Finally, the access order of connecting nodes is rearranged according to the resolved node sorting data, so that the connecting nodes form an access chain with spatial adjacency, continuous path, and consistent direction, generating a sensitive access sequence.

[0063] S1.5. Map and arrange the sensitive access sequence to obtain the driving timing, and perform unified configuration and sequential expansion of the driving timing to generate the electrical test driving sequence.

[0064] It should be noted that each connection node in the sensitive access sequence is read item by item according to the access order, electrical measurement access position and path connection relationship. The arrangement position is mapped to the excitation application order and sampling trigger order to obtain the driving timing sequence. Then, the timing positions of each timing sequence are uniformly configured to clarify the access start point, end point and connection relationship, and are expanded and connected in sequence to generate the electrical measurement driving sequence.

[0065] It should also be noted that the electrical measurement drive sequence transforms the sensitive access sequence into an electrical excitation sequence, so that the connected nodes are excited sequentially along the path, ensuring that the response acquisition sequence is consistent and the path is continuous, thus providing a basis for subsequent analysis.

[0066] S2. Inject graded electrical excitation signals into the electrical measurement drive sequence and simultaneously collect electrical response characteristic parameters. Perform decoupling analysis on the electrical response characteristic parameters to generate electrical characteristic response data.

[0067] S2.1. Inject graded electrical excitation signals into the electrical measurement drive sequence one by one, and superimpose micro-amplitude perturbations at each excitation stage to generate a graded excitation sequence.

[0068] It should be noted that electrical excitation is applied to each drive position in the electrical measurement drive sequence in the order of access, and the electrical excitation intensity and application stage are divided according to the preset excitation level, so that each drive position forms a progressively changing electrical excitation process in different stages; after the electrical excitation of each stage is completed, a small-amplitude perturbation with limited amplitude and matching action time is superimposed on the corresponding stage, and the small-amplitude perturbation and electrical excitation are kept to correspond in the same drive position and the same excitation stage; the excitation stage and small-amplitude perturbation of each drive position are continuously arranged in sequence to generate a hierarchical excitation sequence.

[0069] It should also be noted that the excitation hierarchy is used to control the electrical excitation in stages and with progressive intensity, so that different connection nodes exhibit distinguishable changes in electrical response at each stage, which facilitates feature analysis and disturbance separation; it is formed based on resistance distribution, node load-bearing capacity and historical response patterns.

[0070] The graded electrical excitation signal applies electrical excitation in stages, enabling the connection nodes to produce distinguishable responses. Combined with micro-amplitude perturbations, it separates intrinsic and coupling effects, thereby improving the ability to analyze electrical characteristics and locate anomalies.

[0071] S2.2. Based on the hierarchical excitation sequence, perform multi-time synchronous sampling on the current connected node and adjacent connected nodes to obtain the electrical response change, and perform time-series correlation identification on the electrical response change to generate response sampling data.

[0072] It should be noted that, according to the hierarchical excitation sequence, the sampling triggering order is first established according to the excitation stage and application time corresponding to each driving position. The current connected node is determined as the main sampling object, and connected nodes that have spatial adjacency or conduction connection with the current connected node are determined as adjacent connected nodes. Then, continuous sampling points are set around each excitation stage before, during and after application. Under the same sampling triggering order, the voltage changes, current changes and phase changes of the current connected node and adjacent connected nodes are read synchronously to form a synchronous response record. Subsequently, using adjacent sampling points as the calculation unit, the difference operation is performed on the same type of electrical response of the same connected node to obtain the electrical response change. The electrical response change of the current connected node and the electrical response change of the adjacent connected nodes are synchronously matched and organized to retain the sequential relationship between the main path response and the adjacent response. The electrical response change is associated and identified according to the connected node position, excitation stage, sampling point order and time sequence, and continuously written according to the application order of the hierarchical excitation sequence to generate response sampling data.

[0073] It should also be noted that the response sampling data is used to record the voltage, current and phase changes of each connection node at different excitation stages and multiple moments. By corresponding the sampling results with the location of the connection node, the excitation stage and the time sequence, the temporal expression and structured organization of the electrical response process are realized, thereby ensuring that the response changes are traceable and comparable, and providing a reliable data foundation for subsequent electrical feature extraction, disturbance decoupling analysis and abnormal fluctuation identification.

[0074] S2.3. The sampling time in the response sampling data is segmented and time-series organized to obtain the electrical characteristic change, and the electrical characteristic change is normalized to generate electrical response characteristic parameters.

[0075] It should be noted that the response sampling data is read item by item according to the excitation stage, connection node position, and sampling time sequence. First, sampling moments belonging to the same excitation stage and with continuous time intervals are grouped into the same sampling segment, and the interval position between different excitation stages is used as the segment boundary. Then, within each sampling segment, the voltage change, current change, and phase change of adjacent sampling moments are read in chronological order. The difference between the later sampling moment and the previous sampling moment is calculated, and the direction, magnitude, and order of the difference are recorded to obtain the electrical characteristic change. The electrical characteristic change is assigned to the corresponding connection node according to the connection node position. Then, the electrical characteristic change under the same connection node is stage-based according to the excitation stage, and the synchronous change relationship, sequential change relationship, and directional continuity relationship among voltage change, current change, and phase change are uniformly organized. The organized electrical characteristic change is arranged according to the connection node position, excitation stage, and sampling segment order to form electrical response characteristic parameters that can characterize the direction, strength, and continuity of response changes.

[0076] It should also be noted that the electrical characteristic change is used to characterize the differences in voltage, current and phase changes between adjacent sampling times of each connected node. By performing difference calculation and sequential sorting on the continuous sampling data, the dynamic change characteristics of the electrical response are extracted, so that the response change process is transformed from static numerical values ​​into comparable change information, thereby providing a key basis for subsequent electrical characteristic straightening, disturbance propagation relationship construction and decoupling analysis.

[0077] S2.4. Perform segmented matching and neighbor correlation comparison on the changes in electrical characteristics of electrical response characteristic parameters in different sampling segments to construct the disturbance propagation relationship.

[0078] It should be noted that the electrical characteristic changes of each connection node in different sampling segments of the electrical response characteristic parameters are read item by item, and the electrical characteristic changes of the same connection node in the sampling segments before and after are matched according to the position of the connection node and the order of the sampling segments. In the segment matching, the electrical characteristic change at the end of the previous sampling segment and the electrical characteristic change at the beginning of the next sampling segment are extracted first, and the direction of change, the pattern of change, and the magnitude of change are compared to see if they are consistent. When the direction of change does not reverse, the pattern of change continues, and the magnitude of change does not suddenly break, it is determined that there is a continuous change relationship between the sampling segments before and after. Then, the electrical characteristic changes of adjacent connection nodes in the same sampling segment are compared by neighbor correlation. In the neighbor correlation comparison, the adjacent connection nodes are first compared according to the sampling time. The electrical characteristic changes of the nodes are matched one-to-one, comparing whether the change directions are the same, whether the order of the changes is adjacent, and whether the change amplitudes have a forward-backward transmission characteristic. When two adjacent connected nodes show consistent directions and corresponding amplitude changes at the same or adjacent sampling times, a synchronous response relationship is determined. When the change direction of the latter connected node is consistent with that of the former connected node, and the change occurs later than that of the former connected node, while the change amplitude shows a successor-to-successor relationship with that of the former connected node, a delayed response relationship is determined. Finally, the results of the successor-to-successor determination of continuous changes between the sampling segments of the same connected node are matched with the synchronous or delayed response relationships between adjacent connected nodes to clarify the temporal continuation path of the disturbance and the transmission path between adjacent nodes, thus generating the disturbance transmission relationship.

[0079] S2.5 Separate and calculate the intrinsic conduction component and the coupled disturbance component in the disturbance propagation relationship to generate decoupled response data.

[0080] It should be noted that the response paths, response order, and adjacent influence relationships of each connection node in the disturbance propagation relationship are read item by item. Based on the response correspondence of each connection node in the current sampling segment and adjacent sampling segments in the disturbance propagation relationship, the changes in electrical characteristics are calculated separately. First, the response part that directly corresponds to the current connection node and changes continuously along the connection path is extracted to determine the intrinsic conduction component. Then, the response part formed by the transmission of adjacent connection nodes and that has coupling characteristics in response order and adjacent correlation is extracted to determine the coupled disturbance component. Then, the intrinsic conduction component and the coupled disturbance component are sorted and bound to the corresponding connection node and the corresponding sampling segment to generate decoupled response data.

[0081] It should also be noted that the decoupling response data is used to characterize the separation results of the intrinsic conduction response of each connected node under electrical excitation and the influence of adjacent coupling disturbance. By splitting and correspondingly identifying the hybrid electrical response, the true conduction characteristics of each connected node can be accurately expressed, thereby eliminating the interference influence between adjacent nodes, improving the accuracy and interpretability of electrical response analysis, and providing a reliable basis for subsequent consistency verification and anomaly propagation identification.

[0082] The expression for separating and calculating the changes in electrical characteristics is as follows:

[0083] ;

[0084] in, The electrical characteristics are distributed at intervals. For the same connection node arranged in chronological order in the sampling segments, the [number]th ... Individual electrical characteristic changes; For the same connection node arranged in chronological order in the sampling segments, the [number]th ... Individual electrical characteristic changes; This is a sequence number mapping obtained after sorting all sample segments of the same connection node by time. The interval number after sorting; This represents the total number of samples taken from the same connected node. This is the sequence number identifier for the connected nodes.

[0085] S2.6. Based on the decoupled response data, perform vertical consistency verification on the response changes of the same connection node at different excitation stages, obtain vertical consistency data, and perform horizontal comparative analysis on the response changes of the vertical consistency data at the same sampling time to generate intrinsic response data.

[0086] It should be noted that, based on the decoupled response data, the intrinsic conduction components of the same connection node in different excitation stages are extracted according to the location of the connection node, and arranged into a stage response chain according to the order of the excitation stages. The response changes of adjacent excitation stages in the stage response chain are read segment by segment, and the consistency of the change direction, the correspondence of the response occurrence order with the excitation stage order, and the presence of breaks or reverse jumps in the change continuation process are checked respectively. The response changes with consistent direction, corresponding order, and continuous continuation are identified as consistent continuity content, and longitudinal consistent data is obtained. The response changes of each connection node in the longitudinal consistent data are read at the same sampling time, and the synchronization of the response occurrence time between different connection nodes, the correspondence of the response position with the node mapping relationship in the electrical measurement drive sequence, and the continuity of the change direction and change amplitude are checked. Finally, the response changes that meet the requirements of synchronization, position correspondence, and continuous transition are merged, and residual disturbance content that does not have longitudinal continuity or lateral correspondence is removed to generate intrinsic response data.

[0087] It should also be noted that the intrinsic response data is used to characterize the actual electrical response changes of each connected node after removing adjacent coupling disturbances. By performing consistency verification and horizontal comparison on the decoupling response results, the response changes are kept consistent and correspond to each other under different excitation stages and at the same sampling time, thereby ensuring the stability and comparability of the response results and providing a reliable basis for subsequent response integration and abnormal fluctuation identification.

[0088] S2.7. Sequentially integrate the response information of the intrinsic response data to obtain integrated response data, and perform node mapping on the integrated response data to generate electrical characteristic response data.

[0089] It should be noted that the response changes, sampling time positions, and excitation phase sequences of each connection node in the intrinsic response data are read item by item. The response information is then continuously integrated according to the order of the connection nodes and the time sequence of the sampling times. Response information belonging to the same connection node and being consecutive is merged into the corresponding arrangement position to obtain integrated response data. The positions of each connection node in the integrated response data are then arranged item by item with the corresponding response information to clarify the node position, response order, and correspondence of each connection node in the overall arrangement. The node mapping is then completed according to the node order to generate electrical characteristic response data.

[0090] like Figure 5 As shown, the consistency between the identification results of electrical anomaly propagation paths and the actual propagation paths is compared. By displaying the corresponding paths with the actual paths, the degree of matching of the paths in terms of connection node positions, propagation order, and continuation direction is intuitively reflected. When the overall overlap between the two is high, it indicates that the electrical anomaly propagation path construction process has high accuracy in terms of time continuity, spatial connection, and anomaly continuation judgment, thereby verifying the reliability and effectiveness of electrical anomaly propagation paths in anomaly localization and cause analysis.

[0091] It should also be noted that the electrical characteristic response data is used to uniformly express and structurally integrate the voltage, current and phase changes of each connection node under electrical excitation, so that the electrical response information of each connection node is comparable and continuous, thereby providing a reliable basis for subsequent time alignment, abnormal fluctuation identification and electrical anomaly propagation path analysis.

[0092] Electrical characteristic response data is used to uniformly express and structurally integrate the voltage, current and phase changes of each connected node under electrical excitation. By sequentially integrating and mapping the intrinsic response data, the response information of each connected node is made continuous and comparable, thus providing a reliable data foundation and structural basis for subsequent time alignment, abnormal fluctuation identification and abnormal propagation path analysis.

[0093] S3. Perform time-stamp matching and continuous sequence reconstruction on the electrical characteristic response data to obtain time-series electrical response records. Perform abnormal fluctuation identification and time-series correlation analysis on the time-series electrical response records to generate electrical anomaly propagation paths.

[0094] S3.1 Based on time-aligned data, identify response break intervals, perform interpolation and sequential splicing on the changes before and after the response break intervals to obtain reconstructed response data, combine the reconstructed response data with the response constraints of adjacent connected nodes and limit the boundaries to generate continuous response data.

[0095] It should be noted that, based on time-aligned data, the response values ​​of the same connected node at consecutive time positions are read according to the node's location, and the interval length, response change direction, and response change amplitude of adjacent time positions are recorded sequentially as time continuity features. The time continuity features are checked segment by segment. If there is an unrecorded intermediate time position between two consecutive time positions, and the response change direction from the previous time position to the next time position is not reversed, the response change amplitude does not suddenly increase, and adjacent connected nodes maintain the same direction or gradual change within the corresponding time range, the missing segment between the two consecutive time positions is identified as a response break interval. The slope of change is calculated along the initial and final response values ​​of the response break interval, and combined with the values ​​before and after the response break interval... The direction of change of adjacent time positions is analyzed, and supplementary response values ​​are generated point by point for each missing time position within the response break interval, so that the supplementary response values ​​transition continuously along the trend of change. The supplemented response values ​​are inserted into the corresponding missing time positions in chronological order and concatenated with the response values ​​before and after the response break interval to obtain the reconstructed response data. The response range, position boundary and continuity conditions of adjacent connected nodes at the same time position are read, and the reconstructed response data is checked for range, position and continuity item by item. Response values ​​that exceed the response range are recycled according to the allowable range of adjacent connected nodes, response positions that cross the position boundary are corrected according to the connection path boundary, and response segments that are broken in the direction of change are smoothed again according to the trend of continuity to generate continuous response data.

[0096] S3.2 Perform differential calculation on the response changes of continuous response data between adjacent time slots to obtain response change data, and write the response change data into the time slot positions in chronological order to generate a time-series electrical response record.

[0097] It should be noted that the continuous response data is grouped according to the location of the connection nodes. Within each connection node group, the response values ​​of the previous time slot and the response values ​​of the next time slot are read in chronological order. The response value of the next time slot is subtracted from the response value of the previous time slot to obtain the response difference between adjacent time slots. The positive and negative directions, absolute change amplitude, and corresponding positions of the preceding and following time slots of the response difference are recorded simultaneously. The calculation continues to slide along the time slots sequentially, so that each connection node forms a continuous arrangement of response change data between adjacent time slots. The response change data is associated and identified according to the connection node position, the position of the previous time slot, the position of the next time slot, and the direction of response change. The response change data is then written to the corresponding time slot position of the next time slot, so that the next time slot retains both the current response value and the change information relative to the previous time slot. Finally, the written response change data is organized according to the order of the connection node positions and the order of the time slots to generate a time-series electrical response record that can characterize the response change direction, response change amplitude, and time continuity of each connection node.

[0098] S3.3. Identify abnormal fluctuations and filter abnormal segments in the response changes of the time-series electrical response record in adjacent time slots to generate abnormal segment data.

[0099] It should be noted that the response changes of each connected node in the time-series electrical response record are read item by item in the corresponding time slots of the previous and subsequent time slots. The direction of the response change between the previous and subsequent time slots is compared to see if there is a sudden change, if the magnitude of the change deviates abnormally, and if the continuity of the change is interrupted. When the response change in the subsequent time slot is reversed in direction relative to the response change in the previous time slot, the difference in change increases abnormally, or the connection between changes is suddenly broken, it is judged as an abnormal fluctuation. The response changes judged as abnormal fluctuations are extracted continuously according to the position of the connected node and the order of the time slots. The adjacent and continuous abnormal fluctuation content is merged and filtered to generate abnormal fragment data.

[0100] S3.4. Based on the abnormal fragment data, continuously splice the abnormal fragments of the same connection node, and perform a continuity analysis on the abnormal fragments between adjacent connection nodes to generate propagation connection data.

[0101] It should be noted that, based on the abnormal fragment data, abnormal fragments of the same connection node in adjacent time slots are read one by one in chronological order, and the end time slot and the start time slot are compared to see if they are adjacent, if the direction of change is consistent, and if the content of change is continuous. When they are adjacent, if the direction is consistent, and if they are continuous, they are spliced ​​together. The abnormal fragments spliced ​​between adjacent connection nodes are compared one by one in terms of time continuity, positional adjacency, and directional consistency. The corresponding relationships that meet the conditions are filtered and organized to generate propagation connection data.

[0102] S3.5. Determine and filter the strength of the propagation connection data, and sequentially connect and extend the path of the propagation connection data that meet the acceptance conditions to generate abnormal propagation chain data.

[0103] It should be noted that the propagation connection data is read item by item according to the location of the connection node, the time sequence of succession, and the continuation of abnormal changes. The continuity of the time interval of abnormal changes, the adjacency of the locations, and the consistency of the strength of the changes are compared. When the conditions of continuity, adjacency, and consistent continuation are met, it is determined that it has high succession strength and the corresponding propagation connection is selected. The connection is then concatenated in chronological order and the direction of the connection location extension. The termination node is connected to the starting node in sequence and expanded along the direction of change continuation to generate abnormal propagation chain data.

[0104] It should also be noted that the continuity condition is used to determine whether the response changes between adjacent times or adjacent connected nodes have a continuous connection relationship. By comprehensively judging whether the direction of change is consistent, whether the change amplitude transitions smoothly, and whether the time sequence is continuous, the continuity condition is determined when the direction is consistent, the amplitude has no sudden change, and the connection between the time periods is established. This ensures the continuity and traceability of the response data in time and space, and provides a basis for subsequent path construction and anomaly propagation analysis.

[0105] S3.6. Identify the start and end nodes and arrange the time sequence of each propagation chain segment in the abnormal propagation chain data, and merge the continuously connected chain segments to generate the electrical abnormality propagation path.

[0106] It should be noted that the abnormal propagation chain data is read item by item according to the location of the connecting node and the start and end time of the abnormality, and the starting and ending nodes of each chain segment are marked and arranged in chronological order. Then, the ending node and starting node of adjacent chain segments are compared to determine whether the positions are adjacent, whether the time is continuous, and whether the direction of abnormal change is consistent. For example, if the current abnormal node is located at an adjacent node in the connecting path and does not cross a non-connecting area, the next time slot is immediately followed by the previous time slot without interval or jump, and the abnormal changes of both show a continuous increase or decrease in the same direction without reversal, then the connection condition is met. Conversely, if there is a position jump, time gap, or reversal of the change direction, the connection condition is not met. When the connection condition is met, the chain segments that can be continuously connected are merged to generate an electrical abnormality propagation path.

[0107] It should also be noted that the propagation path of electrical anomalies is used to characterize the direction, sequence, and range of propagation of abnormal fluctuations between each connecting node. By continuously expressing the temporal and spatial connections of abnormal changes, the entire process from the generation to the spread of the anomaly becomes traceable, thus providing a basis for the location of the anomaly's cause and subsequent verification.

[0108] S4. Implement reverse compensation electrical excitation around the electrical anomaly propagation path and compare and verify with adjacent nodes to obtain verification response data. Then, conduct consistency comparison and convergence analysis on the electrical response change trend before and after compensation to generate an electrical performance test plan.

[0109] S4.1. Perform chain segment reverse sorting extraction on the electrical anomaly propagation path to obtain path node data, and combine the path node data with the anomaly propagation direction and time slot position and perform directional timing marking to generate reverse compensation queue data.

[0110] It should be noted that each propagation chain segment in the electrical anomaly propagation path is read in reverse order from the termination node to the starting node. The positions of the connecting nodes, the sequence of the chain segments, and the corresponding time slot positions in each propagation chain segment are extracted sequentially. The connecting nodes obtained after reverse reading are rearranged in the order of termination node priority and starting node subsequent to obtain path node data. The path node data is matched with the anomaly propagation direction and the corresponding time slot position item by item. Each connecting node is marked with the reverse compensation direction and the corresponding time sequence, and the reverse compensation queue data is generated by queuing according to the marked sequence.

[0111] S4.2. Apply reverse compensation electrical excitation sequentially to the reverse compensation queue data, obtain compensation excitation data, and synchronously sample the compensation excitation data to generate verification sampling data.

[0112] It should be noted that reverse compensation electrical excitation is applied to each connected node in the order of the reverse compensation queue data to ensure that the reverse compensation direction and the direction timing mark are consistent. The compensation position, compensation order and corresponding compensation time are recorded to obtain compensation excitation data. Based on the compensation excitation data, synchronous sampling is performed on the connected nodes and adjacent connected nodes before, during and after the application. The voltage change, current change and phase change are organized according to the position and time order of the connected nodes to generate verification sampling data.

[0113] S4.3. Load the reverse electric excitation node by node according to the reverse compensation queue data sequence to construct the compensation response data, adjust the excitation amplitude and application order in the compensation response data, obtain the compensation excitation data, and synchronously sample the compensation excitation data to generate verification sampling data.

[0114] It should be noted that, based on the reverse compensation queue data, the connection node positions, reverse compensation directions, and corresponding time sequences are read item by item in the queue order. The read connection node positions are used as the reverse electrical excitation loading positions, the reverse compensation directions are used as the reverse electrical excitation application directions, and the corresponding time sequences are used as the reverse electrical excitation loading sequences. The voltage, current, and phase changes of each connection node before, during, and after application are recorded sequentially to construct compensation response data. The response changes of the preceding and following connection nodes in the compensation response data at the same compensation stage are read, the difference in changes between the preceding and following connection nodes is calculated, and the difference in changes is checked along the reverse compensation direction to see if it decreases progressively. The response end position of the preceding connection node and the response start position of the following connection node are then read, and the two response positions are checked to see if they are adjacent. The response change directions of the preceding and following connection nodes are then read. The order of response occurrence and the magnitude of response change are analyzed. If the direction of response change is consistent, the order of response occurrence is sequential, and the magnitude of response change transitions smoothly, the application order of the preceding and following connection nodes is retained. If there are position jumps, direction reversals, order inversions, or abrupt changes in magnitude, these are marked as abnormal connection positions. Based on the change difference and abnormal connection positions, the excitation amplitude and application order of the reverse electrical excitation are adjusted. For connection nodes with excessively large response change amplitudes, the excitation amplitude is reduced; for connection nodes with insufficient response change amplitudes, the excitation amplitude is supplemented; for connection nodes with inverted order or time gaps, the application order is rearranged to obtain compensated excitation data. Based on the compensated excitation data, according to the compensated connection node position, excitation amplitude, and application order, voltage changes, current changes, and phase changes are synchronously collected for the connection node and adjacent connection nodes, and continuously organized according to the sampling time order to generate verification sampling data.

[0115] It should also be noted that the compensation excitation data is used to record the location, order, and time information of the electrical excitation applied by each connected node during the reverse compensation process. By performing reverse excitation control on the anomaly propagation path, the changes in electrical response can be traced back and verified in a targeted manner, thereby judging the correctness and reversibility of the anomaly propagation relationship, and providing a basis for subsequent consistency comparison and convergence analysis, thus improving the accuracy of anomaly location and verification.

[0116] S4.4. Differences in the electrical response changes in the verification sampling data are sorted out to obtain the corresponding response information, and the corresponding response information is correlated and arranged to generate verification response data.

[0117] It should be noted that the verification sampling data is read item by item according to the connection node position and sampling time sequence. The voltage change, current change and phase change before and after compensation are matched one by one. The change difference, change direction and sequence relationship of the same connection node at the corresponding time are calculated to obtain the corresponding response information. The corresponding response information is arranged continuously according to the connection node position, compensation sequence and time sequence. The corresponding response information that can be connected and whose change direction is corresponding is merged in sequence to generate verification response data.

[0118] It should also be noted that the corresponding response information is used to characterize the differences and continuity of voltage, current and phase changes of the same connection node at the same sampling time before and after compensation. By correspondingly identifying the difference, direction and sequence of changes, the response changes before and after compensation are comparable and traceable, thereby providing a basis for subsequent consistency comparison and convergence determination, and improving the accuracy of the anomaly verification process.

[0119] S4.5. Perform trend expansion and direction comparison on the voltage, current and phase changes of the verification response data before and after compensation, obtain trend comparison data, perform consistency comparison on the response changes based on the trend comparison data, determine the convergence of the response changes, and generate convergence judgment data.

[0120] It should be noted that the changes in electrical response of each connection node before and after compensation in the verification response data are read item by item according to the connection node position and sampling time. The voltage changes, current changes and phase changes before and after compensation are expanded accordingly, and the direction of change, sequence and continuity of change are compared to obtain trend comparison data. Based on the trend comparison data, the response changes of the same connection node are compared for consistency to determine whether the direction of change after compensation is corresponding and whether the change process tends to be concentrated. When the direction of change remains consistent after compensation and the change amplitude gradually decreases and no longer expands, it is determined that the convergence requirement is met, and the judgment results are sorted to generate convergence judgment data.

[0121] S4.6. Unify and arrange the convergence judgment data in a unified manner, obtain the compensation status, classify the compensation status and integrate the test path to generate an electrical performance test plan.

[0122] It should be noted that the convergence judgment content, compensation order, and path correspondence of each connection node in the convergence judgment data are read item by item, and then uniformly organized according to the connection node position and compensation order. The contents with the same judgment category and adjacent paths are arranged in order to obtain the compensation status. Based on the convergence status, path position, and connection relationship of each connection node in the compensation status, a classification decision is made to determine whether to retain the path, adjust the order, or replan it. The path contents are then integrated according to the test execution order to generate an electrical performance test plan.

[0123] This embodiment also provides a computer device suitable for implementing a packaging and testing method for a memory chip, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the packaging and testing method for a memory chip as proposed in the above embodiment.

[0124] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0125] This embodiment also provides a storage medium storing a computer program thereon. When executed by a processor, the program implements the packaging and testing method for a memory chip as described in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0126] In summary, this invention achieves effective differentiation between intrinsic conduction components and coupled perturbation components by injecting graded electrical excitation signals into the electrical test drive sequence and combining this with an impedance perturbation decoupling algorithm to separate and analyze electrical response characteristic parameters. This results in electrical characteristic response data with structural consistency and physical interpretability, providing a high-purity foundation for functional testing and anomaly identification. Simultaneously, by using time stamp matching and continuous sequence reconstruction, combined with an electrical anomaly determination method, a directional and continuous electrical anomaly propagation path is formed. Then, through reverse compensation electrical excitation and comparison verification with adjacent nodes, the reverse confirmation of the anomaly propagation relationship and the location of its cause are completed, improving the anomaly location accuracy and enhancing the reliability of the electrical performance testing scheme.

[0127] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A packaging and testing method for implementing memory chips, characterized in that, include: Collect the encapsulation electrical connection parameters, establish electrical measurement position association based on the encapsulation electrical connection parameters, extract the electrical stress sensitive area from the electrical measurement position association, and arrange the electrical stress sensitive area in sequence to generate the electrical measurement drive sequence; A graded electrical excitation signal is injected into the electrical measurement drive sequence, and electrical response characteristic parameters are collected simultaneously. The electrical response characteristic parameters are then decoupled and analyzed to generate electrical characteristic response data. Time signature matching and continuous sequence reconstruction are performed on electrical characteristic response data to obtain time-series electrical response records. Abnormal fluctuations and time-series correlation analysis are performed on the time-series electrical response records to generate electrical anomaly propagation paths. The reverse compensation electrical excitation along the propagation path of electrical anomalies is compared and verified with adjacent nodes to obtain verification response data. The consistency and convergence of the electrical response change trends before and after compensation are compared and analyzed to generate an electrical performance test plan.

2. The packaging and testing method for implementing a memory chip as described in claim 1, characterized in that, The specific steps for generating the electrical measurement drive sequence are as follows: The package interconnect data of the package is identified by node encoding, the node encoding data is obtained, and the connectivity relationship of the node encoding data is parsed and constructed to generate package electrical connection parameters; Each connection node in the encapsulated electrical connection parameters is matched one by one with the electrical test access point to obtain the corresponding access data, and the connection data is merged and connected to generate the electrical test location association. Based on the correlation of electrical measurement locations, the path structure characteristics of each connection node are analyzed item by item to obtain structural characteristic parameters. The structural characteristic parameters are then filtered for sensitivity according to structural complexity to generate electrical stress sensitive areas. Based on the electrical stress sensitive region, the adjacent acceptance sorting of each connection node is performed to obtain the node sorting data, and the connection and resolution are performed according to the node sorting data to generate a sensitive access sequence. The sensitive access sequence is mapped and orchestrated to obtain the driving timing, and the driving timing is uniformly configured and sequentially expanded to generate the electrical test driving sequence.

3. The packaging and testing method for implementing a memory chip as described in claim 2, characterized in that, The specific steps for injecting graded electrical excitation signals into the electrical measurement drive sequence and simultaneously acquiring electrical response characteristic parameters are as follows: A graded electrical excitation signal is injected into the electrical measurement drive sequence one by one, and a micro-amplitude perturbation is superimposed at each excitation stage to generate a graded excitation sequence. Based on the hierarchical excitation sequence, the current connected node and its adjacent connected nodes are synchronously sampled at multiple time points to obtain the changes in electrical response. The changes in electrical response are then time-series correlated and identified to generate response sampling data. The sampling time in the response sampling data is segmented and time-series processed to obtain the changes in electrical characteristics. The changes in electrical characteristics are then normalized to generate electrical response characteristic parameters.

4. The packaging and testing method for implementing a memory chip as described in claim 1, characterized in that, The specific steps for generating the electrical characteristic response data are as follows: The changes in electrical characteristics of electrical response parameters in different sampling segments are segmented and compared with adjacent correlations to construct the perturbation propagation relationship. The intrinsic conduction component and the coupled disturbance component in the disturbance propagation relationship are separated and calculated to generate decoupled response data; Based on the decoupled response data, the response changes of the same connection node at different excitation stages are checked for longitudinal consistency to obtain longitudinally consistent data. Then, the response changes of the longitudinally consistent data at the same sampling time are compared and analyzed laterally to generate intrinsic response data. The response information of the intrinsic response data is sequentially integrated to obtain integrated response data, and the integrated response data is then arranged into nodes to generate electrical characteristic response data.

5. The packaging and testing method for implementing a memory chip as described in claim 4, characterized in that, The specific steps for performing time-stamp matching and continuous sequence reconstruction on the electrical characteristic response data to obtain time-series electrical response records are as follows: The electrical characteristic response data is grouped by time and classified by node to obtain time slot group data. Based on the time slot group data, the time markers in each connected node are corrected in order to generate time-aligned data. Based on time-aligned data, response break intervals are identified. Interpolation and sequential splicing are performed on the changes before and after the response break intervals to obtain reconstructed response data. The reconstructed response data is combined with the response constraints of adjacent connected nodes and boundary limits are applied to generate continuous response data. Differential calculations are performed on the response changes of continuous response data between adjacent time slots to obtain response change data. The response change data is then written into the time slot positions in chronological order to generate a time-series electrical response record.

6. The packaging and testing method for implementing a memory chip as described in claim 1, characterized in that, The specific steps for generating the electrical anomaly propagation path are as follows: Abnormal fluctuations and abnormal segments are identified and filtered for response changes in adjacent time slots of time-series electrical response records, generating abnormal segment data. Based on the abnormal fragment data, abnormal fragments of the same connection node are continuously spliced ​​together, and the abnormal fragments between adjacent connection nodes are subjected to continuity analysis to generate propagation connection data. The strength of the transmission connection data is determined and the transmission connection is screened. The transmission connection data that meets the transmission conditions are sequentially concatenated and the path is extended to generate abnormal transmission chain data. The start and end nodes of each propagation chain segment in the abnormal propagation chain data are identified and arranged in chronological order. Chain segments that can be continuously connected are merged to generate an electrical abnormality propagation path.

7. The packaging and testing method for implementing a memory chip as described in claim 1, characterized in that, The specific steps for implementing reverse compensation electrical excitation around the electrical anomaly propagation path and comparing it with adjacent nodes to verify and obtain verification response data are as follows: The chain segment reverse sorting extraction is performed on the electrical anomaly propagation path to obtain path node data. The path node data is then combined with the anomaly propagation direction and time slot position and directional timing marking is performed to generate reverse compensation queue data. Reverse electrical excitation is loaded node by node according to the reverse compensation queue data order to construct compensation response data. The excitation amplitude and application order in the compensation response data are adjusted to obtain compensation excitation data. The compensation excitation data is then synchronously sampled to generate verification sampling data. The differences in electrical response changes in the verification sampling data are sorted out to obtain the corresponding response information, and the corresponding response information is correlated and arranged to generate verification response data.

8. The packaging and testing method for implementing a memory chip as described in claim 7, characterized in that, The process involves comparing the consistency and convergence of the electrical response trends before and after compensation in the verification response data to generate an electrical performance test plan. The specific steps are as follows: The voltage, current, and phase changes of the verification response data before and after compensation are trend-expanded and compared with the direction to obtain trend comparison data. Based on the trend comparison data, the consistency of the response changes is compared, and the convergence of the response changes is determined to generate convergence judgment data. The convergence determination data is uniformly organized and arranged in order to obtain the compensation status. The compensation status is then classified and the test path is integrated to generate an electrical performance test plan.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the packaging and testing method for implementing a memory chip as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the packaging and testing method for implementing a memory chip as described in any one of claims 1 to 8.

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