An energy-saving LED display screen with reverse common cathode and a driving method thereof

Abstract

The application discloses an energy-saving LED display screen with a reverse common cathode and a driving method thereof, and belongs to the technical field of LED display. The application aims at the problem that the single voltage power supply of the traditional common anode LED display screen leads to high power consumption and serious heat generation of the first display content LED, and adopts a reverse common cathode structure of dynamic anode voltage switching + cathode time-sharing gating: the ICND2018 row driving IC provides switchable double voltages for the common anode of the LED, outputs 2.6~2.8V low voltage when the first display content is displayed, and outputs 3.6~3.8V standard voltage when the second display content and the third display content are displayed; three pieces of ICND1065L16 channel constant current sink column driving IC are matched to independently control the three-color cathodes of the first display content, the second display content and the third display content, and precise power supply of color separation is realized. Under the premise of being fully compatible with the existing SMDTOP three-in-one common anode lamp beads, the first display content LED loop voltage difference is reduced from 1.8V to 0.8V, and the power consumption of the single first display content lamp is reduced by about 55%.

Description

Technical Field

[0001] This invention relates to the field of LED display technology, and more specifically, to an energy-saving LED display screen with reverse common cathode and its driving method. Background Technology

[0002] With the widespread application of LED displays in outdoor advertising, traffic guidance, sports venues, and other fields, their high power consumption has become increasingly prominent. Under constant current drive characteristics, reducing the LED supply voltage is the core way to achieve energy saving.

[0003] There are significant color differences in the forward conduction voltage of LEDs: the forward conduction voltage of the first display content LED is approximately 2.0V, while the forward conduction voltage of the third and second display content LEDs is approximately 3.2V. Traditional common-anode LED displays use SMDTOP three-in-one common-anode LEDs, with the three anodes connected together, providing only a single global power supply voltage (typically 3.6~3.8V). This results in the first display content LED bearing an excess voltage difference of approximately 1.8V, all of which is converted into heat. This not only causes serious energy waste but also leads to high heat generation and low light energy conversion efficiency of the first display content LED, resulting in a significant increase in screen temperature and requiring a larger heat dissipation structure. Furthermore, it accelerates the aging and degradation of the LED chips and driver ICs.

[0004] Existing energy-saving solutions mostly use common cathode LEDs to achieve color-coded power supply, but this requires replacing the entire LED supply chain and re-molding, resulting in a significant increase in mass production costs and incompatibility with existing mature common anode production processes.

[0005] In view of this, we propose an energy-saving LED display with reverse common cathode and its driving method. Summary of the Invention

[0006] The purpose of this invention is to solve the problem of high power consumption and severe heat generation of the first display content LED caused by the inability of traditional common anode LED displays to provide color-separated power supply. The invention provides a reverse common cathode energy-saving LED display and its driving method that does not require replacement of LED chips and is compatible with existing production processes. By dynamically controlling the anode voltage and time-divisionally selecting the cathode, the invention achieves low-voltage and precise driving of the first display content LED, resulting in significant energy-saving effects.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] An energy-saving LED display with reverse common cathode includes a control module, a clock module, a row drive module, a column drive module, and a 64-row × 16-column common anode LED matrix;

[0009] The horizontal drive module consists of eight cascaded ICND2018 horizontal drive ICs. Each ICND2018 horizontal drive IC has a horizontal drive VCC terminal, a horizontal drive VDD2.7V terminal, a horizontal drive VDD3.7V terminal, a horizontal drive GND terminal, a horizontal drive RCLK terminal, a horizontal drive SDI terminal, a horizontal drive DCLK clock terminal, and eight horizontal drive output terminals. The horizontal drive VCC terminal is connected to the 5V system auxiliary power supply. The horizontal drive VDD2.7V terminal is uniformly connected to the dedicated power supply for the first display content (VCC_R=2.6~2.8V). The horizontal drive VDD3.7V terminal is uniformly connected to the dedicated power supply for the second and third display contents (VCC_GB=3.6~3.8V). The horizontal drive output terminals are respectively connected to the 64 horizontal lines (line0~line63) of the LED matrix.

[0010] The column driver module consists of three independent ICND1065L16-channel constant current sink column driver ICs: UR1 (first display content column driver), UG1 (third display content column driver), and UB1 (second display content column driver). Each ICND1065L16-channel constant current sink column driver IC has a column driver SDI_1 terminal, a column driver SDI_2 terminal, a column driver SDI_3 terminal, a column driver DCLK clock terminal, a column driver ROW terminal, a column driver LE terminal, a column driver GND terminal, and 16 column driver output terminals. The column driver output terminal of the first display content column driver UR1 is connected to the 16 first display content cathode lines (R0~R15) of the LED matrix; the column driver output terminal of the third display content column driver UG1 is connected to the 16 third display content cathode lines (G0~G15) of the LED matrix; and the column driver output terminal of the second display content column driver UB1 is connected to the 16 second display content cathode lines (B0~B15) of the LED matrix.

[0011] It also includes a voltage regulator circuit and a protection circuit for stabilizing the display voltage;

[0012] The voltage regulator circuit includes an input-stage multi-stage voltage regulation and filtering unit, a horizontal drive output spike suppression unit, and a dual-power supply isolation voltage regulator unit.

[0013] The input stage multi-stage voltage regulation and filtering unit is respectively set at the input terminals of VCC_R power supply, VCC_GB power supply and 5V auxiliary power supply. The input stage of each power supply is connected in series with a self-resetting fuse, a π-type LC filter circuit and a low dropout linear regulator pre-filter capacitor. The π-type LC filter circuit uses a 10μH power inductor combined with a 100μF electrolytic capacitor and a 0.1μF ceramic capacitor to further suppress the output voltage ripple of each stage of the power supply to below 20mV.

[0014] The row drive output spike suppression unit is set between the eight row drive outputs of each ICND2018 row drive IC and the row lines of the LED matrix. Each row drive output is connected in series with a 1Ω high-precision current limiting resistor, and then connected in parallel with a 0.1μF high-frequency ceramic capacitor and a bidirectional TVS diode with a breakdown voltage of 4.5V. This is used to suppress voltage overshoot and current spikes generated during the anode voltage switching process, and to control the voltage overshoot amplitude to within 3%.

[0015] The dual-power supply isolation voltage regulator unit is located between the output terminals of the VCC_R power supply and the VCC_GB power supply. It uses a 0Ω ferrite bead to achieve high-frequency isolation at a single point common ground. At the same time, a three-stage filter array consisting of a 1000μF low ESR electrolytic capacitor, a 10μF tantalum capacitor, and a 0.01μF ceramic capacitor is connected in parallel at the output terminals of the two power supplies to eliminate voltage drops and crosstalk during dual-power supply switching.

[0016] The protection circuit includes a power input abnormality protection unit, an anode voltage switching timing protection unit, an output channel independent short circuit protection unit, and a power-on / off timing protection unit.

[0017] The power input abnormality protection unit includes a reverse connection protection diode, an input overvoltage detection chip, and an input undervoltage detection chip. The reverse connection protection diode is connected in series to the positive input terminal of each power supply. The sampling terminals of the input overvoltage detection chip and the input undervoltage detection chip are respectively connected to the output terminals of the VCC_R power supply, the VCC_GB power supply, and the 5V auxiliary power supply. The overvoltage threshold of the VCC_R power supply is set to 3.0V and the undervoltage threshold is set to 2.4V. The overvoltage threshold of the VCC_GB power supply is set to 4.0V and the undervoltage threshold is set to 3.4V. When the input voltage is detected to exceed the threshold range, the output of the corresponding power supply is immediately cut off, and an coded abnormal signal is sent to the control module.

[0018] The anode voltage switching timing protection unit is integrated into the timer module of the control module. It precisely controls the time interval between column driver shutdown and anode voltage switching through hardware timer. It ensures that all column driver outputs are completely shut down (shutdown time ≤ 100ns) before sending voltage switching command to ICND2018 row driver IC. The minimum time interval is set to 200ns, which completely avoids pixel color crossing and driver IC current surge during voltage switching.

[0019] The independent short-circuit protection unit for each output channel is set on each row line and each cathode line. Each line is connected in series with a 10mΩ high-precision current sampling resistor. The two ends of the sampling resistor are connected to the input of a high-speed comparator with a response time of ≤50ns. The output of the high-speed comparator is connected to the external interrupt pin of the control module. When the channel current exceeds 300mA, the high-speed comparator immediately triggers an interrupt. The control module shuts down the corresponding row channel and column channel within 1μs and locks the fault state until manual reset.

[0020] The control module is electrically connected to the clock module, row drive module and column drive module respectively, and is used to output control signals and grayscale data to realize the synchronous control of dynamic anode voltage switching and cathode time-division gating;

[0021] It also includes peripheral circuitry for the display, which includes signal input interface circuitry, non-volatile storage circuitry, multi-point temperature monitoring and protection circuitry, multi-screen cascade communication interface circuitry, ambient light automatic brightness adjustment circuitry, and fault indication and alarm circuitry.

[0022] The signal input interface circuit integrates an HDMI 1.4 interface, a VGA interface, a USB 2.0 interface, and an LVDS differential interface. Each interface has a built-in ESD electrostatic protection diode, with an electrostatic protection level of not less than ±8kV contact discharge and ±15kV air discharge. The output terminals of all interfaces are connected to the corresponding video input and data pins of the control module to receive display data, control commands, and firmware upgrade data from external video sources.

[0023] The non-volatile storage circuit uses a serial Flash chip with an SPI interface. The CS, CLK, MOSI, and MISO pins of the chip are connected to the corresponding pins of the SPI bus of the control module. The storage capacity is not less than 16MB and is used to store system firmware, LED grayscale calibration data, brightness parameter configuration table and user-defined display modes. The data retention time after power failure is not less than 10 years and the number of erase and write cycles is not less than 100,000.

[0024] The multi-point temperature monitoring and protection circuit includes three NTC thermistors and a 12-bit high-precision temperature acquisition chip. The three NTC thermistors are respectively mounted on the center of the back of the LED matrix, the surface of the heat sink of the row driver module, and the surface of the heat sink of the column driver module. The analog input terminal of the temperature acquisition chip is connected to each NTC thermistor, and the digital output terminal is connected to the I2C bus pin of the control module. The temperature of key parts of the screen is collected in real time. When the temperature of any monitoring point exceeds the preset threshold, the control module automatically executes the stepped brightness reduction protection or emergency shutdown protection.

[0025] The multi-screen cascaded communication interface circuit includes an RS485 interface and a CAN bus interface. The RS485 interface has a built-in opto-isolator and surge protection circuit, and the CAN bus interface conforms to the ISO11898-2 standard. Both are connected to the corresponding communication pins of the control module, supporting a cascaded network of up to 256 displays with a communication distance of no less than 1200 meters, and is compatible with Modbus-RTU and CANopen standard communication protocols.

[0026] The ambient light automatic brightness adjustment circuit includes a silicon photovoltaic cell photosensitive sensor and a signal conditioning circuit. The photosensitive sensor is installed in the non-display area on the front of the housing. The signal conditioning circuit converts the current signal output by the photosensitive sensor into a 0~3.3V voltage signal and inputs it into the ADC pin of the control module. The control module linearly adjusts the overall output brightness of the LED matrix within the range of 0~100% according to the real-time collected ambient light intensity.

[0027] The fault indication and alarm circuit includes a red fault LED indicator and an active buzzer, which are respectively connected to two GPIO pins of the control module. When the system detects abnormal power supply, driver IC failure, temperature over-limit, or communication interruption, the red fault LED indicator flashes at different frequencies to indicate the fault type, while the active buzzer emits intermittent alarm sounds and sends the corresponding fault code to the host computer through the multi-screen cascaded communication interface.

[0028] Furthermore, the ICND2018 row driver IC has a built-in dual voltage switching array with a voltage switching speed of less than 500ns, a single-channel output current of greater than or equal to 500mA, and built-in overcurrent and overtemperature protection circuits.

[0029] Furthermore, the ICND1065L16-channel constant current sink column driver IC has a built-in 14-bit PWM grayscale controller, with a constant current output accuracy error of less than ±3%, an output leakage current of less than 1μA, and a turn-off time of less than 100ns.

[0030] Furthermore, both the VCC_R power supply and the VCC_GB power supply adopt a two-stage power supply architecture of switching power supply plus linear regulator, with voltage ripple of less than 50mV, and the ground of the two power supplies is a single point common ground.

[0031] A method for driving an energy-saving LED display with a reverse common cathode includes the following steps:

[0032] S21 Power-On Initialization and Dual Power Supply Connection: After system power-on, the ICND2018 horizontal driver IC automatically completes internal register initialization, and all horizontal driver outputs default to high-impedance shutdown. The horizontal driver VCC terminal is connected to the 5V system auxiliary power supply to power the chip's logic circuit. The horizontal driver VDD 2.7V terminal is uniformly connected to the 2.6~2.8VVCC_R power supply dedicated to the first display content, and the horizontal driver VDD 3.7V terminal is uniformly connected to the 3.6~3.8VVCC_GB power supply dedicated to the second and third display content. The horizontal driver GND terminal shares a common ground with the power module output. After initialization, the chip automatically loads the factory default protection parameters: single-channel overcurrent protection threshold 500mA, chip junction temperature over-temperature protection threshold 150℃, and temperature recovery threshold 120℃.

[0033] The S22 row address and color command shift input: The control module serially inputs 16 bits of control data to the row driver SDI pin of the first cascaded ICND2018 row driver IC via the SPI bus. The high 8 bits are the row address codes (0x00~0x3F) corresponding to the 64 rows, and the low 8 bits are the color control commands (0x01 represents the first display content mode, 0x02 represents the second and third display content modes). The row driver DCLK clock pin receives a 20MHz global synchronization clock output from the control module, with one bit shifted on each rising edge of the clock. The eight cascaded ICND2018 ICs sequentially transmit the data, with the total transmission time for all 64 rows of control data being 128 clock cycles (6.4μs).

[0034] S23 Row Data Latching and Row Selection: After all cascaded ICND2018s have completed data shifting, the control module synchronously outputs a high-level latch pulse with a pulse width ≥100ns to the row driver RCLK pin of all row driver ICs, latching the row address and color instruction in the shift register into the internal latch. Simultaneously, based on the latched row address encoding, the ICND2018 only selects the output channel of the corresponding row, while the remaining 63 row channels remain in a high-impedance off state.

[0035] The S24 dynamic anode voltage selection ICND2018, based on the latched color control command, quickly selects the corresponding supply voltage output to the selected row line via a built-in dual-voltage switching array: if the color command is 0x01 (first display content), the switching array connects to the row driver VDD 2.7V terminal, and the row line outputs a voltage of 2.6~2.8V; if the color command is 0x02 (second or third display content), the switching array connects to the row driver VDD 3.7V terminal, and the row line outputs a voltage of 3.6~3.8V. The entire voltage switching process is completed within 500ns, with a voltage overshoot of less than 5% and no significant voltage drop.

[0036] The S25 row drive output is synchronized with time-sharing. After the selected row line outputs a stable voltage, the ICND2018 forwards a synchronization signal to the column drive module through the control module, notifying the column drive module to activate the cathode output of the corresponding color. During output, the built-in overcurrent protection circuit monitors the single-channel output current in real time. If the current exceeds 500mA, the channel is immediately shut down, and a fault code is sent back to the control module through the SDI pin. The built-in overtemperature protection circuit monitors the chip junction temperature in real time. If the junction temperature exceeds 150℃, all output channels are shut down, and operation automatically resumes when the temperature drops below 120℃.

[0037] S26 Line Scan End and Output Reset: After the first, second, and third display content display time slots of the line have all been executed, the control module outputs a reset pulse to the line driver RCLK terminal. ICND2018 resets all line driver output terminals to the high-impedance off state and clears the data in the internal latches and shift registers, preparing to receive the line address and color instructions of the next line.

[0038] S11 Power-on Initialization and Constant Current Setting: After system power-on, the ICND1065L16-channel constant current sink column driver IC automatically completes internal register initialization. All 16 column driver outputs are in the off state by default, with output leakage current less than 1μA. The column driver GND terminal and the power module output terminal share a common ground. Through a 1.2kΩ high-precision metal film resistor connected to the R_EXT pin, the chip's global constant current output value is set to 25mA, and the constant current output accuracy error is controlled within ±3%.

[0039] The S12 serial grayscale data shift input allows the control module to serially input 14-bit grayscale data of the corresponding color to three independent column driver ICs based on the image content to be displayed: the first display content grayscale data is input to the column driver SDI_1 terminal of the first display content column driver UR1, the third display content grayscale data is input to the column driver SDI_2 terminal of the third display content column driver UG1, and the second display content grayscale data is input to the column driver SDI_3 terminal of the second display content column driver UB1. The column driver DCLK clock terminal receives a 20MHz global synchronization clock, and one bit of data is shifted on each rising edge of the clock. The total transmission time of grayscale data for the 16 channels of a single chip is 224 clock cycles (11.2μs).

[0040] S13 row data latch: After the grayscale data of all channels has been shifted, the control module synchronously outputs a high-level latch pulse with a pulse width of ≥80ns to the column driver LE terminal of the three ICND1065L16 channel constant current Sink column driver ICs, latching the grayscale data in the shift register into the internal grayscale register in batches, waiting for the PWM signal to be generated and output.

[0041] The ICND1065L features a built-in 14-bit PWM grayscale controller, which generates PWM drive signals with corresponding duty cycles based on the latched grayscale data, enabling 16384 levels of grayscale display. The PWM carrier frequency is set to 2kHz to ensure no visual flicker for the human eye while avoiding electromagnetic interference and switching losses caused by excessively high frequencies.

[0042] The S15 constant current sink output features time-division enabling. Upon receiving the row synchronization signal forwarded by the row driver module, the control module outputs a high-level enable signal to the column driver ROW terminal of the corresponding color column driver IC. To reduce peak power supply current and output voltage ripple, the ICND1065L's built-in time-division turn-on control unit divides the 16 outputs into 4 groups, each with 4 channels, which are turned on sequentially at 200ns intervals, with each group having an equal turn-on time. During output, the chip's internal constant current control circuit adjusts the on-resistance of the output transistors in real time to ensure that the output current remains constant at 25mA for different channels and grayscale levels.

[0043] S16 Row Scan End and Status Reset: After the display time slot for the corresponding color in that row ends, the control module outputs a low-level shutdown signal to the column driver ROW terminal. The ICND1065L immediately shuts down all column driver outputs, with a channel shutdown time of less than 100ns. Simultaneously, the chip automatically clears the data in its internal grayscale register and shift register, preparing to receive the grayscale data for the next row.

[0044] S31. Controller Synchronous Command Sending: After system power-on, the control module (STM32F407 microcontroller) first completes its own GPIO, SPI, and timer initialization, and then sends initialization commands to the clock module, row driver module, and column driver module. The clock module outputs a 20MHz high-precision global synchronization clock signal to all modules, ensuring that the timing deviation between row and column drivers is less than 10ns. The power supply module outputs stable VCC_R (2.7V±0.1V), VCC_GB (3.7V±0.1V), and 5V auxiliary power, with output voltage ripple less than 50mV.

[0045] S32. All column driver ICs are turned off. The control module simultaneously outputs a low-level turn-off signal to the column driver ROW terminals of the first display content column driver UR1, the third display content column driver UG1, and the second display content column driver UB1. All column driver output terminals are turned off within 100ns to avoid current spikes and pixel crosstalk during subsequent anode voltage switching.

[0046] S33, ICND2018 latches row data. The control module serially inputs the row address code of the Nth row (N=0~63) and the first display content display instruction (0x01) to the eight cascaded ICND2018 row driver ICs, and outputs latch pulses to the row driver RCLK pins of all row driver ICs. After the ICND2018 latches the data, only the row channel of the Nth row is selected, and the other row channels remain high-impedance off.

[0047] S34 and UR1 latch the grayscale data of the first display content in the Nth row. The control module serially inputs the 14-bit grayscale data of the first display content (16 pixels in the Nth row) to the column driver SDI_1 terminal of the first display content column driver UR1, and simultaneously inputs pure black grayscale data (0x0000) to the third display content column driver UG1 and the second display content column driver UB1. Then, latch pulses are synchronously output to the column driver LE terminals of the three column driver ICs to complete the grayscale data latching.

[0048] S35. Only UR1 outputs. ICND2018 displays the first display content according to the latched first display content display instruction. It quickly switches the row line voltage of the Nth row from a high impedance state to 2.6~2.8VVCC_R through the built-in dual voltage switching array. The voltage switching process is completed within 500ns. After the row line voltage stabilizes, it enters the first display content display time slot.

[0049] S36. At the end of the first display content time slot, all column driver outputs are turned off. The control module only outputs a high-level enable signal to the column driver ROW terminal of the first display content column driver UR1, while the third display content column driver UG1 and the second display content column driver UB1 remain off. UR1 outputs a 25mA constant current sink current in a 4-group time-conduction mode based on the latched grayscale data of the first display content, lighting up the corresponding first display content pixel in the Nth row. The duration of the first display content time slot is dynamically adjusted according to the grayscale level, with a maximum duration of 125μs.

[0050] S37. The controller synchronously sends an instruction to shut down all column drivers again. After the first display content display time slot ends, the control module immediately outputs a low-level shutdown signal to all three ICND1065L16 channel constant current Sink column driver ICs. All column driver outputs are shut down within 100ns to prepare for anode voltage switching.

[0051] S38 and ICND2018 switch the row line voltage of the selected row to VCC_GB. The control module sends the second display content and third display content display command (0x02) to ICND2018 row driver IC. ICND2018 quickly switches the row line voltage of the Nth row from 2.6~2.8VVCC_R to 3.6~3.8VVCC_GB through a dual voltage switching array. The voltage switching process is completed within 500ns. After the row line voltage stabilizes, the second display content and third display content display time slot is entered.

[0052] S39 and UG1 / UB1 respectively latch the grayscale data of the third and second display contents. The control module serially inputs the 14-bit grayscale data of the Nth row and 16th pixel of the third display content to the column driver SDI_2 terminal of the third display content column driver UG1, and serially inputs the 14-bit grayscale data of the Nth row and 16th pixel of the second display content to the column driver SDI_3 terminal of the second display content column driver UB1. At the same time, it inputs pure black grayscale data (0x0000) to the first display content column driver UR1. Then, it synchronously outputs latch pulses to the column driver LE terminals of the three column driver ICs to complete the latching of the grayscale data of the second and third display contents.

[0053] S310: Only UG1 / UB1 outputs. The control module simultaneously outputs a high-level enable signal to the column driver ROW terminal of the third display content column driver UG1 and the second display content column driver UB1, while the first display content column driver UR1 remains off. UG1 and UB1 output a 25mA constant current sink current in a 4-group time-conduction mode based on the latched grayscale data, illuminating the corresponding third and second display content pixels in the Nth row. The time slot duration of the second and third display content is equal to that of the first display content, with a maximum duration of 125μs.

[0054] S311. When the second and third display content time slots end, all column driver outputs are turned off. After the second and third display content display time slots have finished counting down, the control module outputs a low-level shutdown signal to all ICND1065L16 channel constant current Sink column driver ICs, turning off all column driver outputs. Simultaneously, a reset pulse is output to the ICND2018 row driver IC, resetting the row channel of row N to a high-impedance shutdown state, completing the full scan of row N.

[0055] S312, Proceed to the next line scan, repeating steps S32 to S311, sequentially completing the scanning and display of lines N+1 to 63. Once all 64 lines have been scanned, the next frame display cycle begins, with a frame refresh rate of 60Hz to ensure no visual flicker for the human eye. This linkage driving method allows for precise color-coded power supply to the three LEDs representing the first, second, and third display contents, while maintaining full compatibility with existing common-anode LEDs.

[0056] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0057] 1. Significant energy saving effect: By dynamically switching the anode voltage, the voltage difference of the first display content LED circuit is reduced from the traditional 1.8V to 0.8V, the power consumption of a single first display content lamp is reduced by about 55%, and the overall power consumption of the screen is reduced by 25%~35%, which greatly reduces operating costs.

[0058] 2. Extremely strong compatibility: Fully compatible with existing SMDTOP three-in-one common anode LED chips, standard driver IC packaging and manufacturing processes, without the need to change the supply chain, avoiding the cost of re-molding and production line modification.

[0059] 3. Improved reliability: Significantly reduces the heat generated by the LEDs of the primary display content, resulting in more uniform screen temperature rise, greatly reducing heat dissipation pressure, simplifying heat dissipation design, and extending the lifespan of LED beads and driver ICs.

[0060] 4. Optimized display effect: Adopting 14-bit high-precision PWM grayscale drive, the brightness consistency is better, the LED decay rate of the first displayed content is slowed down, and the color is more stable over long-term use.

[0061] 5. Low mass production cost: Hardware costs only increase by 3% to 5%, mainly due to the incremental costs of dual power supplies and line drive ICs. The investment can be recovered through energy-saving benefits within 1 to 2 years. Attached Figure Description

[0062] Figure 1 This is a schematic diagram of the overall structure assembly of the present invention;

[0063] Figure 2 This is a system architecture block diagram of the present invention;

[0064] Figure 3 This is a diagram of the LED matrix driving topology of the present invention;

[0065] Figure 4 This is a pinout diagram of the ICND2018 row driver IC;

[0066] Figure 5 Pin diagram of ICND1065L16 channel constant current sink column driver IC;

[0067] Figure 6 This is a schematic diagram of the overall circuit connection of the present invention;

[0068] Figure 7 Workflow diagram for ICND1065L16-channel constant current sink column driver IC;

[0069] Figure 8The flowchart for the ICND2018 row driver IC;

[0070] Figure 9 This is a flowchart illustrating the core linkage between the ICND2018 row driver IC and the ICND1065L16 channel constant current sink column driver IC.

[0071] The labels in the diagram represent the following: 1. Monitor; 2. Rotating bracket; 3. Base; 4. Housing; 5. Circuit board; 6. ICND2018 row driver IC; 61. Row driver VCC terminal; 62. Row driver VDD 2.7V terminal; 63. Row driver VDD 3.7V terminal; 64. Row driver GND terminal; 65. Row driver RCLK terminal; 66. Row driver SDI terminal; 67. Row driver DCLK clock terminal; 68. Row driver output terminal; 7. ICND1065L16-channel constant current sink column driver IC; 71. Column driver SDI_1 terminal; 72. Column driver SDI_2 terminal; 73. Column driver SDI_3 terminal; 74. Column driver DCLK clock terminal; 75. Column driver ROW terminal; 76. Column driver LE terminal; 77. Column driver GND terminal; 8. Clock module; 9. Control module; 10. LED matrix. Detailed Implementation

[0072] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0073] Example 1

[0074] This embodiment provides an energy-saving LED display screen with reverse common cathode, such as... Figures 1-9 As shown, the display includes a housing 4, a rotating bracket 2, a base 3, a circuit board 5 installed inside the housing 4, and a 64-row × 16-column common anode LED matrix 10 installed on the front of the housing 4. The bottom of the housing 4 is rotatably connected to the base 3 via the rotating bracket 2, allowing for free adjustment of the display screen angle.

[0075] The circuit board 5 integrates a control module 9, a clock module 8, a row driver module, a column driver module, and a power supply module. The control module 9 uses an STM32F407 microcontroller, and the clock module 8 uses a 20MHz active crystal oscillator to output high-precision clock signals to the control module 9, the row driver module, and the column driver module to ensure synchronous operation of the system.

[0076] The row driver module consists of eight cascaded ICND2018 row driver ICs (6). Each ICND2018 row driver IC6 has a built-in dual-voltage switching array with a voltage switching speed of less than 500ns and a single-channel output current greater than or equal to 500mA. It also has built-in overcurrent protection and overtemperature protection circuits. The row driver SDI pins (66) of the eight ICND2018 row driver ICs (66) are cascaded sequentially. The row driver SDI pin (66) of the first ICND2018 row driver IC (66) is connected to the SPI output of the control module 9. The row driver DCLK clock pins (67) and RCLK pins (65) of all ICND2018 row driver ICs (66) are connected in parallel to the corresponding pins of the control module 9. Each ICND2018 horizontal driver IC6 has eight horizontal driver output terminals 68 connected to eight horizontal lines of the LED matrix 10, driving a total of 64 horizontal lines. The ICND2018 horizontal driver IC6 also includes a horizontal driver VCC terminal 61, a horizontal driver VDD2.7V terminal 62, a horizontal driver GND terminal 64, and a horizontal driver VDD3.7V terminal. The horizontal driver VCC terminal 61 is electrically connected to the driving voltage and is used to power the ICND2018 horizontal driver IC6. The horizontal driver VDD2.7V terminal 62 is electrically connected to an external 2.7V input voltage and is used to provide 2.7V voltage when driving blue-green LEDs for display. The horizontal driver GND terminal 64 is electrically connected to a common cathode to realize the circuit loop. The horizontal driver VDD3.7V terminal 63 is electrically connected to an external 3.7V input voltage and is used to provide 3.7V voltage when driving low-voltage LEDs for display.

[0077] The column drive module consists of three independent ICND1065L16-channel constant current sink column drive ICs7: low-voltage column drive UR1, green column drive UG1, and blue column drive UB1. Each ICND1065L16-channel constant current sink column drive IC7 has a built-in 14-bit PWM grayscale controller, with a constant current output accuracy error of less than ±3%, output leakage current of less than 1μA, and channel turn-off time of less than 100ns. It also has a built-in time-division turn-on control unit, supporting 16 outputs to be turned on in 4 groups sequentially, which can effectively reduce power supply ripple. The column driver DCLK clock terminal 74, column driver LE terminal 76, and column driver ROW terminal 75 of three ICND1065L16-channel constant current sink column driver ICs are connected in parallel to the corresponding pins of the control module 9. The column driver SDI_R terminal 71 of the low-voltage column driver UR1 is connected to the low-voltage grayscale data output terminal of the control module 9, the column driver SDI_G terminal 72 of the green column driver UG1 is connected to the green grayscale data output terminal of the control module 9, and the column driver SDI_B terminal 73 of the blue column driver UB1 is connected to the blue grayscale data output terminal of the control module 9. Each ICND1065L16-channel constant current sink column driver IC7 has a 1.2kΩ precision resistor connected to its R_EXT pin, setting the global constant current output value to 25mA. The ICND1065L16-channel constant current sink column driver IC7 also includes a column driver GND terminal 77, which is used to electrically connect with the common cathode to realize the circuit loop.

[0078] The power module includes a VCC_R power supply, a VCC_GB power supply, and a 5V auxiliary power supply. The VCC_R power supply outputs 2.7V±0.1V, providing dedicated power for low-voltage LEDs; the VCC_GB power supply outputs 3.7V±0.1V, providing dedicated power for high-voltage LEDs; the 5V auxiliary power supply powers the logic circuits of the control module 9, clock module 8, and driver IC. Both the VCC_R and VCC_GB power supplies adopt a two-stage power supply architecture of "switching power supply + low dropout linear regulator (LDO)," with an output voltage ripple of less than 50mV. The grounding terminals of the two power supplies share a common ground at a single point at the output of the power module, effectively suppressing ground loop interference.

[0079] The common anode LED matrix 10 uses standard SMD2121TOP three-in-one common anode LEDs. The common anode of each LED is connected to the corresponding row line, the low-voltage cathode is connected to the corresponding low-voltage cathode line, the green cathode is connected to the corresponding green cathode line, and the blue cathode is connected to the corresponding blue cathode line, which is fully compatible with existing LEDs and surface mount technology.

[0080] Example 2

[0081] like Figure 7 As shown, this embodiment provides a method for using ICND2018 row driver IC6, including the following steps:

[0082] This embodiment provides a method for using the ICND2018 row driver IC in a reverse common cathode energy-saving LED display as described in Embodiment 1, in conjunction with the appendix. Figure 8 The workflow shown includes the following steps:

[0083] S21 Power-On Initialization and Dual Power Supply Connection: After system power-on, the ICND2018 horizontal driver IC automatically completes internal register initialization, and all horizontal driver outputs default to high-impedance shutdown. The horizontal driver VCC terminal is connected to the 5V system auxiliary power supply to power the chip's logic circuit. The horizontal driver VDD 2.7V terminal is uniformly connected to the 2.6~2.8VVCC_R power supply dedicated to the first display content, and the horizontal driver VDD 3.7V terminal is uniformly connected to the 3.6~3.8VVCC_GB power supply dedicated to the second and third display content. The horizontal driver GND terminal shares a common ground with the power module output. After initialization, the chip automatically loads the factory default protection parameters: single-channel overcurrent protection threshold 500mA, chip junction temperature over-temperature protection threshold 150℃, and temperature recovery threshold 120℃.

[0084] The S22 row address and color command shift input: The control module serially inputs 16 bits of control data to the row driver SDI pin of the first cascaded ICND2018 row driver IC via the SPI bus. The high 8 bits are the row address codes (0x00~0x3F) corresponding to the 64 rows, and the low 8 bits are the color control commands (0x01 represents the first display content mode, 0x02 represents the second and third display content modes). The row driver DCLK clock pin receives a 20MHz global synchronization clock output from the control module, with one bit shifted on each rising edge of the clock. The eight cascaded ICND2018 ICs sequentially transmit the data, with the total transmission time for all 64 rows of control data being 128 clock cycles (6.4μs).

[0085] S23 Row Data Latching and Row Selection: After all cascaded ICND2018s have completed data shifting, the control module synchronously outputs a high-level latch pulse with a pulse width ≥100ns to the row driver RCLK pin of all row driver ICs, latching the row address and color instruction in the shift register into the internal latch. Simultaneously, based on the latched row address encoding, the ICND2018 only selects the output channel of the corresponding row, while the remaining 63 row channels remain in a high-impedance off state.

[0086] The S24 dynamic anode voltage selection ICND2018, based on the latched color control command, quickly selects the corresponding supply voltage output to the selected row line via a built-in dual-voltage switching array: if the color command is 0x01 (first display content), the switching array connects to the row driver VDD 2.7V terminal, and the row line outputs a voltage of 2.6~2.8V; if the color command is 0x02 (second or third display content), the switching array connects to the row driver VDD 3.7V terminal, and the row line outputs a voltage of 3.6~3.8V. The entire voltage switching process is completed within 500ns, with a voltage overshoot of less than 5% and no significant voltage drop.

[0087] The S25 row drive output is synchronized with time-sharing. After the selected row line outputs a stable voltage, the ICND2018 forwards a synchronization signal to the column drive module through the control module, notifying the column drive module to activate the cathode output of the corresponding color. During output, the built-in overcurrent protection circuit monitors the single-channel output current in real time. If the current exceeds 500mA, the channel is immediately shut down, and a fault code is sent back to the control module through the SDI pin. The built-in overtemperature protection circuit monitors the chip junction temperature in real time. If the junction temperature exceeds 150℃, all output channels are shut down, and operation automatically resumes when the temperature drops below 120℃.

[0088] S26 Line Scan End and Output Reset: After the first, second, and third display content time slots of the line have all been executed, the control module outputs a reset pulse to the line driver RCLK terminal. The ICND2018 resets all line driver output terminals to the high-impedance off state and clears the data in the internal latches and shift registers, preparing to receive the line address and color instructions of the next line.

[0089] Example 3

[0090] This embodiment provides a method for using the ICND1065L16-channel constant current sink column driver IC in a reverse common cathode energy-saving LED display as described in Embodiment 1, in conjunction with the attached... Figure 7 The workflow shown includes the following steps:

[0091] S11 Power-on Initialization and Constant Current Setting: After system power-on, the ICND1065L16-channel constant current sink column driver IC automatically completes internal register initialization. All 16 column driver outputs are in the off state by default, with output leakage current less than 1μA. The column driver GND terminal and the power module output terminal share a common ground. Through a 1.2kΩ high-precision metal film resistor connected to the R_EXT pin, the chip's global constant current output value is set to 25mA, and the constant current output accuracy error is controlled within ±3%.

[0092] The S12 serial grayscale data shift input allows the control module to serially input 14-bit grayscale data of the corresponding color to three independent column driver ICs based on the image content to be displayed: the first display content grayscale data is input to the column driver SDI_1 terminal of the first display content column driver UR1, the third display content grayscale data is input to the column driver SDI_2 terminal of the third display content column driver UG1, and the second display content grayscale data is input to the column driver SDI_3 terminal of the second display content column driver UB1. The column driver DCLK clock terminal receives a 20MHz global synchronization clock, and one bit of data is shifted on each rising edge of the clock. The total transmission time of grayscale data for the 16 channels of a single chip is 224 clock cycles (11.2μs).

[0093] S13 row data latch: After the grayscale data of all channels has been shifted, the control module synchronously outputs a high-level latch pulse with a pulse width of ≥80ns to the column driver LE terminal of the three ICND1065L16 channel constant current Sink column driver ICs, latching the grayscale data in the shift register into the internal grayscale register in batches, waiting for the PWM signal to be generated and output.

[0094] The ICND1065L features a built-in 14-bit PWM grayscale controller, which generates PWM drive signals with corresponding duty cycles based on the latched grayscale data, enabling 16384 levels of grayscale display. The PWM carrier frequency is set to 2kHz to ensure no visual flicker for the human eye while avoiding electromagnetic interference and switching losses caused by excessively high frequencies.

[0095] The S15 constant current sink output features time-division enabling. Upon receiving the row synchronization signal forwarded by the row driver module, the control module outputs a high-level enable signal to the column driver ROW terminal of the corresponding color column driver IC. To reduce peak power supply current and output voltage ripple, the ICND1065L's built-in time-division turn-on control unit divides the 16 outputs into 4 groups, each with 4 channels, which are turned on sequentially at 200ns intervals, with each group having an equal turn-on time. During output, the chip's internal constant current control circuit adjusts the on-resistance of the output transistors in real time to ensure that the output current remains constant at 25mA for different channels and grayscale levels.

[0096] S16 Row Scan End and Status Reset: After the display time slot for the corresponding color in that row ends, the control module outputs a low-level shutdown signal to the column driver ROW terminal. The ICND1065L immediately shuts down all column driver outputs, with a channel shutdown time of less than 100ns. Simultaneously, the chip automatically clears the data in its internal grayscale register and shift register, preparing to receive the grayscale data for the next row.

[0097] Example 4

[0098] This embodiment provides an overall driving method for a reverse common cathode energy-saving LED display screen as described in Embodiment 1, namely, a method for the coordinated use of the ICND2018 row driver IC and the ICND1065L16 channel constant current sink column driver IC, combined with the appendix. Figure 9 The core linkage process shown achieves precise synchronous control of dynamic anode voltage switching and cathode time-division gating, including the following steps:

[0099] The S31 controller synchronously sends commands. After the system powers on, the control module (STM32F407 microcontroller) first initializes its own GPIO, SPI, and timers, and then sends initialization commands to the clock module, row driver module, and column driver module. The clock module outputs a 20MHz high-precision global synchronization clock signal to all modules, ensuring that the timing deviation between row and column drivers is less than 10ns. The power supply module outputs stable VCC_R (2.7V±0.1V), VCC_GB (3.7V±0.1V), and 5V auxiliary power, with output voltage ripple less than 50mV.

[0100] When all column driver ICs of S32 are turned off, the control module simultaneously outputs a low-level turn-off signal to the column driver ROW terminals of the first display content column driver UR1, the third display content column driver UG1, and the second display content column driver UB1. All column driver output terminals are turned off within 100ns to avoid current spikes and pixel crosstalk during subsequent anode voltage switching.

[0101] The S33ICND2018 latches row data. The control module serially inputs the row address code of the Nth row (N=0~63) and the first display content display instruction (0x01) to eight cascaded ICND2018 row driver ICs, and outputs latch pulses to the row driver RCLK pins of all row driver ICs. After the ICND2018 latches the data, only the row channel of the Nth row is selected, while the other row channels remain high-impedance off.

[0102] The S34UR1 latches the grayscale data of the first display content in the Nth row. The control module serially inputs the 14-bit grayscale data of the first display content (16 pixels in the Nth row) to the column driver SDI_1 terminal of the first display content column driver UR1, and simultaneously inputs pure black grayscale data (0x0000) to the third display content column driver UG1 and the second display content column driver UB1. Then, latch pulses are synchronously output to the column driver LE terminals of the three column driver ICs to complete the grayscale data latching.

[0103] S35 only outputs UR1. ICND2018 displays the first display content according to the latched first display content display instruction. It quickly switches the row line voltage of the Nth row from a high impedance state to 2.6~2.8VVCC_R through the built-in dual voltage switching array. The voltage switching process is completed within 500ns. After the row line voltage stabilizes, it enters the first display content display time slot.

[0104] When the first display content time slot of S36 ends, all column driver outputs are turned off. The control module only outputs a high-level enable signal to the column driver ROW terminal of the first display content column driver UR1, while the third display content column driver UG1 and the second display content column driver UB1 remain off. UR1 outputs a 25mA constant current sink current in a 4-group time-conduction mode based on the latched grayscale data of the first display content, lighting up the corresponding first display content pixel in the Nth row. The duration of the first display content time slot is dynamically adjusted according to the grayscale level, with a maximum duration of 125μs.

[0105] When the first display content time slot of S37 ends, all column drivers are turned off again. After the first display content display time slot ends, the control module immediately outputs a low-level shutdown signal to all three ICND1065L16 channel constant current Sink column driver ICs. All column driver outputs are turned off within 100ns to prepare for anode voltage switching.

[0106] The S38ICND2018 switches the row line voltage of the selected row to VCC_GB. The control module sends the second and third display content display instructions (0x02) to the ICND2018 row driver IC. The ICND2018 quickly switches the row line voltage of the Nth row from 2.6~2.8VVCC_R to 3.6~3.8VVCC_GB through a dual voltage switching array. The voltage switching process is completed within 500ns. After the row line voltage stabilizes, the second and third display content display time slots are entered.

[0107] S39UG1 / UB1 latches the grayscale data of the third and second display contents respectively. The control module serially inputs the 14-bit grayscale data of the Nth row and 16th pixel of the third display content to the column driver SDI_2 terminal of the third display content column driver UG1, and serially inputs the 14-bit grayscale data of the Nth row and 16th pixel of the second display content to the column driver SDI_3 terminal of the second display content column driver UB1. At the same time, it inputs pure black grayscale data (0x0000) to the first display content column driver UR1. Then, it synchronously outputs latch pulses to the column driver LE terminals of the three column driver ICs to complete the latching of the grayscale data of the second and third display contents.

[0108] S310 only enables the output of the second and third display content column drivers UG1 / UB1. Simultaneously, the control module outputs a high-level enable signal to the column driver ROW terminals of both the third and second display content column drivers UG1 and UB1, while the first display content column driver UR1 remains off. UG1 and UB1 output a 25mA constant current sink current in a 4-group time-controlled manner based on the latched grayscale data, illuminating the corresponding pixels of the third and second display content in the Nth row. The time slot duration for the second and third display content is equal to that of the first display content, with a maximum duration of 125μs.

[0109] When the time slot for displaying the second and third content of S311 ends, all column driver outputs are turned off. After the time slot for displaying the second and third content ends, the control module outputs a low-level shutdown signal to all ICND1065L16 channel constant current Sink column driver ICs, turning off all column driver outputs. Simultaneously, a reset pulse is output to the ICND2018 row driver IC, resetting the row channel of row N to a high-impedance shutdown state, completing the full scan of row N.

[0110] S312 proceeds to the next line scan, repeating steps S32 to S311, sequentially completing the scanning and display of lines N+1 to 63. Once all 64 lines are scanned, the next frame display cycle begins, with a frame refresh rate of 60Hz to ensure no visual flicker for the human eye. This linkage driving method allows for precise color-coded power supply to the three LEDs representing the first, second, and third display contents, while maintaining full compatibility with existing common-anode LEDs.

[0111] Comparative Example 1

[0112] This comparative example uses the exact same hardware as Example 1 (the same 64-row × 16-column SMD2121TOP three-in-one common anode LED matrix, the same housing structure, and the same control module and clock module), only replacing the driving architecture with a traditional common anode single voltage driving scheme, in order to compare and verify the energy-saving effect, temperature rise characteristics and economic advantages of the present invention.

[0113] Horizontal drive module: Uses 8 cascaded ordinary single-voltage horizontal drive ICs (replacing ICND2018), which only support a single global power supply voltage output;

[0114] Power supply module: Only a single 3.7V±0.1V main power supply and a 5V auxiliary power supply are retained, and the dedicated power supply for the first display content of VCC_R is removed;

[0115] Driving method: Traditional common anode constant current drive is adopted, all row lines output a uniform 3.7V voltage, and three ICND1065L16-channel constant current sink column driver ICs simultaneously output the three-color cathode current of the first display content, the second display content, and the third display content, without dynamic voltage switching and cathode time-division gating logic.

[0116] The remaining hardware parameters (LED bead BIN level, constant current output value 25mA, frame refresh rate 60Hz, PWM carrier frequency 2kHz) are completely consistent with those of Example 1.

[0117] All tests were conducted in a standard laboratory environment: ambient temperature 25℃±1℃, relative humidity 50%±5%, windless environment, and data were collected after the system had been running continuously and stably for 24 hours.

[0118] Power consumption test: A high-precision power meter (accuracy ±0.1W) was used to measure the total power consumption at the power input terminal.

[0119] Temperature rise test: The surface temperature of the LED beads, the surface temperature of the driver IC and the highest surface temperature of the screen were measured using a thermal imager (accuracy ±0.1℃) on the outside of the first display content. The junction temperature of the LED beads in the first display content was measured using a thermocouple.

[0120] Luminous decay test: The initial luminous flux of the LED beads was measured using an integrating sphere system. After being continuously lit for 1000 hours, the luminous decay rate was calculated.

[0121] Display all content in the first position (all pixels of the first-position content are fully lit). 12.6W 28.0W 55.0% The power consumption of the single first display LED decreased from 70mW to 31.5mW, and the circuit voltage difference decreased from 1.8V to 0.8V. The second display shows all content (all pixels in the third display are fully lit). 19.8W 20.1W 1.5% The LED power supply voltage for the second and third display contents is the same as that of the traditional solution, and the power consumption is basically the same. The entire content of the third display is shown (all pixels of the content in the second display are fully lit). 20.2W 20.5W 1.5% Same as above Full white display (all pixels are fully illuminated in RGB mode) 52.6W 68.6W 23.3% Approaching the theoretical minimum energy saving value Standard advertisement layout (first displayed content occupies 30%, second and third displayed content occupy 70%) 41.2W 56.8W 27.5% Typical display scenarios for outdoor advertising screens Traffic guidance screen (first displayed content occupies 50%, second displayed content and third displayed content occupy 50%) 36.4W 54.2W 32.8% Typical display scenarios of traffic guidance screens Average total power consumption 40.1W 57.3W 30.0% Industry-wide weighted average value for comprehensive display scenarios

[0122] Table 1

[0123] The first display content is the junction temperature of the LED beads. 62.3℃ 87.5℃ 25.2℃ The third display content is the junction temperature of the LED beads. 58.7℃ 59.1℃ 0.4℃ The second display content is the junction temperature of the LED beads. 59.2℃ 59.6℃ 0.4℃ Maximum surface temperature of line driver IC 45.6℃ 52.1℃ 6.5℃ Highest surface temperature of column driver IC 43.2℃ 43.8℃ 0.6℃ Highest surface temperature of the screen 48.5℃ 61.2℃ 12.7℃ Screen surface temperature uniformity ±3.2℃ ±8.7℃ -

[0124] Table 2

[0125] The first display content is the LED light decay rate over 1000 hours. 2.1% 5.8% 63.8% The third display content LED light decay rate over 1000 hours 1.8% 1.9% 5.3% The second display content shows the LED's light decay rate over 1000 hours. 1.9% 2.0% 5.0% The first display content is based on the theoretical lifespan of the LED (light decay to 70%). 80,000 hours 35,000 hours 128.6% Overall theoretical lifespan of the screen 65,000 hours 32,000 hours 103.1%

[0126] Table 3

[0127] Single module hardware cost 104 yuan 100 yuan +4 yuan (+4%) The incremental cost is the price difference between the dual power supply module and the ICND2018 row driver IC. Annual operating electricity cost (calculated based on 12 hours of operation per day and an industrial electricity price of 0.8 yuan / kWh) 140.5 yuan 200.7 yuan -60.2 yuan / year Annual maintenance costs 15 yuan 35 yuan -20 yuan / year This invention has a lower failure rate and a simplified heat dissipation structure. Investment recovery period 0.5 years - - The incremental cost can be recovered within 6 months through energy savings alone.

[0128] Table 4

[0129] Energy-saving effect verification: The present invention has indeed achieved the design goal of reducing the power consumption of a single first display content lamp by about 55% and the overall power consumption of the screen by 25% to 35%. The energy-saving advantage is even more prominent in application scenarios where the proportion of the first display content is high (such as traffic guidance screens and festival celebration screens).

[0130] Reliability improvement verification: The junction temperature of the LED for the first display content is reduced by more than 25°C, and the maximum surface temperature of the screen is reduced by 12.7°C. This completely solves the problems of overheating of the LED beads for the first display content and uneven local temperature rise in traditional common anode displays, and extends the service life of the devices by more than double.

[0131] Economic feasibility verification: The mass production hardware cost of this invention only increases by 3% to 5%, but the annual operating cost is reduced by about 30%, and the investment payback period is only 0.5 to 1 year, which is far better than the industry average and has extremely high market promotion value;

[0132] Compatibility verification: This invention achieves the above advantages while being fully compatible with existing SMDTOP three-in-one common anode LED beads and manufacturing processes. It can quickly achieve large-scale mass production without changing the supply chain or modifying the production line.

[0133] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended technical solutions and their equivalents.

Claims

1. An energy-saving LED display screen with reverse common cathode, characterized in that: Includes a control module (9), a clock module (8), a row drive module, a column drive module, and a 64-row × 16-column common anode LED matrix (10). The row driver module consists of eight cascaded ICND2018 row driver ICs (6); The column drive module consists of three independent ICND1065L16-channel constant current sink column drive ICs (7); The control module (9) is electrically connected to the clock module (8), the row drive module and the column drive module respectively, and is used to output control signals and grayscale data to realize the synchronous control of dynamic anode voltage switching and cathode time-division gating; The ICND2018 line driver IC (6) is provided with a line driver VCC terminal (61), a line driver VDD2.7V terminal (62), a line driver VDD3.7V terminal (63), a line driver GND terminal (64), a line driver RCLK terminal (65), a line driver SDI terminal (66), a line driver DCLK clock terminal (67), and 8 line driver output terminals (68). The line driver VCC terminal (61) is connected to a 5V system auxiliary power supply. The line driver VDD2.7V terminal (62) is uniformly connected to a dedicated power supply for the first display content (VCC_R=2.6~2.8V). The line driver VDD3.7V terminal (63) is uniformly connected to a dedicated power supply for the second and third display contents (VCC_GB=3.6~3.8V). The line driver output terminals (68) are respectively connected to the 64 line lines of the LED matrix (10).

2. The energy-saving LED display screen with reverse common cathode according to claim 1, characterized in that: The first display content column driver UR1, the third display content column driver UG1, and the second display content column driver UB1 are respectively; each ICND1065L16-channel constant current Sink column driver IC (7) is provided with column driver SDI_1 terminal (71), column driver SDI_2 terminal (72), column driver SDI_3 terminal (73), column driver DCLK clock terminal (74), column driver ROW terminal (75), column driver LE terminal (76), column driver GND terminal (77) and 16 column driver output terminals; the column driver output terminal of the first display content column driver UR1 is connected to the 16 first display content cathode lines of the LED matrix (10), the column driver output terminal of the third display content column driver UG1 is connected to the 16 third display content cathode lines of the LED matrix (10), and the column driver output terminal of the second display content column driver UB1 is connected to the 16 second display content cathode lines of the LED matrix (10); The ICND2018 row driver IC (6) has a built-in dual voltage switching array with a voltage switching speed of less than 500ns and a single-channel output current of greater than or equal to 500mA. It also has built-in overcurrent protection circuit and overtemperature protection circuit.

3. The energy-saving LED display screen with reverse common cathode according to claim 2, characterized in that: The ICND1065L16 channel constant current sink column driver IC (7) has a built-in 14-bit PWM grayscale controller, constant current output accuracy error is less than ±3%, output leakage current is less than 1μA, and channel turn-off time is less than 100ns.

4. The energy-saving LED display screen with reverse common cathode according to claim 2, characterized in that: It also includes a power supply module, which contains a VCC_R power supply, a VCC_GB power supply and a 5V auxiliary power supply. Both the VCC_R power supply and the VCC_GB power supply adopt a two-stage power supply architecture of switching power supply plus linear regulator, and the output voltage ripple is less than 50mV.

5. The energy-saving LED display screen with reverse common cathode according to claim 4, characterized in that: The grounding terminal of the VCC_R power supply and the grounding terminal of the VCC_GB power supply share a common ground at a single point at the output terminal of the power module.

6. The energy-saving LED display screen with reverse common cathode according to claim 2, characterized in that: The common anode LED matrix (10) uses SMDTOP three-in-one common anode lamp beads. The common anode of each lamp bead is connected to the corresponding row line. The first display content cathode, the third display content cathode, and the second display content cathode are respectively connected to the first display content cathode line, the third display content cathode line, and the second display content cathode line of the corresponding column.

7. The energy-saving LED display screen with reverse common cathode according to claim 2, characterized in that: The control module (9) uses an STM32F407 microcontroller, and the clock module (8) outputs a 20MHz system clock signal to the control module (9), the row drive module, and the column drive module.

8. The energy-saving LED display screen with reverse common cathode according to claim 2, characterized in that: The R_EXT pin of the ICND1065L16 channel constant current sink column driver IC (7) is connected to an external 1.2kΩ resistor to set the global constant current output value to 25mA; It also includes a voltage regulator circuit and a protection circuit for stabilizing the display voltage; The voltage regulator circuit includes an input-stage multi-stage voltage regulation and filtering unit, a horizontal drive output spike suppression unit, and a dual-power supply isolation voltage regulator unit. The input stage multi-stage voltage regulation and filtering unit is respectively set at the input terminals of VCC_R power supply, VCC_GB power supply and 5V auxiliary power supply. The input stage of each power supply is connected in series with a self-resetting fuse, a π-type LC filter circuit and a low dropout linear regulator pre-filter capacitor. The π-type LC filter circuit uses a 10μH power inductor combined with a 100μF electrolytic capacitor and a 0.1μF ceramic capacitor to further suppress the output voltage ripple of each stage of the power supply to below 20mV. The row drive output peak suppression unit is set between the eight row drive outputs (68) of each ICND2018 row drive IC (6) and the row lines of the LED matrix (10). Each row drive output is connected in series with a 1Ω high-precision current limiting resistor, and then connected in parallel with a 0.1μF high-frequency ceramic capacitor and a bidirectional TVS tube with a breakdown voltage of 4.5V. This is used to suppress the voltage overshoot and current spike generated during the anode voltage switching process and control the voltage overshoot amplitude to within 3%. The dual-power supply isolation voltage regulator unit is located between the output terminals of the VCC_R power supply and the VCC_GB power supply. It uses a 0Ω ferrite bead to achieve high-frequency isolation at a single point common ground. At the same time, a three-stage filter array consisting of a 1000μF low ESR electrolytic capacitor, a 10μF tantalum capacitor, and a 0.01μF ceramic capacitor is connected in parallel at the output terminals of the two power supplies to eliminate voltage drops and crosstalk during dual-power supply switching. The protection circuit includes a power input abnormality protection unit, an anode voltage switching timing protection unit, an output channel independent short circuit protection unit, and a power-on / off timing protection unit. The power input abnormality protection unit includes a reverse connection protection diode, an input overvoltage detection chip, and an input undervoltage detection chip. The reverse connection protection diode is connected in series to the positive input terminal of each power supply. The sampling terminals of the input overvoltage detection chip and the input undervoltage detection chip are respectively connected to the output terminals of the VCC_R power supply, the VCC_GB power supply, and the 5V auxiliary power supply. The overvoltage threshold of the VCC_R power supply is set to 3.0V and the undervoltage threshold is set to 2.4V. The overvoltage threshold of the VCC_GB power supply is set to 4.0V and the undervoltage threshold is set to 3.4V. When the input voltage is detected to exceed the threshold range, the output of the corresponding power supply is immediately cut off, and the encoded abnormal signal is sent to the control module (9). The anode voltage switching timing protection unit is integrated into the timer module of the control module (9). The time interval between column drive shutdown and anode voltage switching is precisely controlled by the hardware timer. After all column drive output terminals are completely shut down (shutdown time ≤ 100ns), a voltage switching command is sent to the ICND2018 row driver IC (6). The minimum time interval is set to 200ns to completely avoid pixel color mixing and current surge of the driver IC during the voltage switching process. The independent short-circuit protection unit for the output channel is set on each row line and each cathode line. Each line is connected in series with a 10mΩ high-precision current sampling resistor. The two ends of the sampling resistor are connected to the input of a high-speed comparator with a response time of ≤50ns. The output of the high-speed comparator is connected to the external interrupt pin of the control module (9). When the channel current is detected to exceed 300mA, the high-speed comparator immediately triggers an interrupt. The control module (9) shuts down the corresponding row channel and column channel within 1μs and locks the fault state until manual reset.

9. The energy-saving LED display screen with reverse common cathode according to claim 2, characterized in that: The ICND1065L16-channel constant current sink column driver IC (7) has a built-in time-division conduction control unit, which supports 16 outputs to be conducted in 4 groups in sequence. It also includes a housing (4), a rotating bracket (2) and a base (3). The control module (9), clock module (8), row drive module, column drive module and power module are all integrated on a circuit board (5) inside the housing (4). The common anode LED matrix (10) is installed on the front of the housing (4). The bottom of the housing (4) is rotatably connected to the base (3) through the rotating bracket (2). It also includes peripheral circuitry for the display, which includes signal input interface circuitry, non-volatile storage circuitry, multi-point temperature monitoring and protection circuitry, multi-screen cascade communication interface circuitry, ambient light automatic brightness adjustment circuitry, and fault indication and alarm circuitry. The signal input interface circuit integrates an HDMI 1.4 interface, a VGA interface, a USB 2.0 interface, and an LVDS differential interface. Each interface has a built-in ESD electrostatic protection diode with an electrostatic protection level of not less than ±8kV contact discharge and ±15kV air discharge. The output terminals of all interfaces are connected to the corresponding video input and data pins of the control module (9) to receive display data, control commands, and firmware upgrade data from external video sources. The non-volatile storage circuit uses a serial Flash chip with an SPI interface. The CS, CLK, MOSI, and MISO pins of the chip are connected to the corresponding pins of the SPI bus of the control module (9). The storage capacity is not less than 16MB and is used to store system firmware, LED grayscale calibration data, brightness parameter configuration table and user-defined display mode. The data is not less than 10 years after power failure and the number of erase / write cycles is not less than 100,000. The multi-point temperature monitoring and protection circuit includes three NTC thermistors and a 12-bit high-precision temperature acquisition chip. The three NTC thermistors are respectively mounted on the center of the back of the LED matrix (10), the surface of the heat sink of the row driving module and the surface of the heat sink of the column driving module. The analog input terminal of the temperature acquisition chip is connected to each NTC thermistor, and the digital output terminal is connected to the I2C bus pin of the control module (9). The temperature of key parts of the screen is collected in real time. When the temperature of any monitoring point exceeds the preset threshold, the control module (9) automatically performs stepped brightness reduction protection or emergency shutdown protection. The multi-screen cascaded communication interface circuit includes an RS485 interface and a CAN bus interface. The RS485 interface has a built-in opto-isolator and surge protection circuit. The CAN bus interface conforms to the ISO11898-2 standard. Both are connected to the corresponding communication pins of the control module (9). It supports a maximum of 256 screens cascaded and networked, with a communication distance of not less than 1200 meters. It is compatible with Modbus-RTU and CANopen standard communication protocols. The ambient light automatic brightness adjustment circuit includes a silicon photocell photosensitive sensor and a signal conditioning circuit. The photosensitive sensor is installed on the non-display area of ​​the front of the housing (4). The signal conditioning circuit converts the current signal output by the photosensitive sensor into a voltage signal of 0~3.3V and inputs it into the ADC pin of the control module (9). The control module (9) linearly adjusts the overall output brightness of the LED matrix (10) in the range of 0~100% according to the ambient light intensity collected in real time. The fault indication alarm circuit includes a red fault LED indicator and an active buzzer, which are respectively connected to two GPIO pins of the control module (9). When the system detects abnormal power supply, driver IC failure, temperature over-limit or communication interruption, the red fault LED indicator flashes at different frequencies to indicate the fault type. At the same time, the active buzzer emits intermittent alarm sounds and sends the corresponding fault code to the host computer through the multi-screen cascaded communication interface.

10. A reverse common cathode energy-saving LED display driving method, applied to the system described in any one of claims 1-9, characterized in that, Includes the following steps: S31. Controller synchronously sends instructions. After the system powers on, the control module (STM32F407 microcontroller) first completes its own GPIO, SPI, and timer initialization, and then sends initialization instructions to the clock module, row driver module, and column driver module. The clock module outputs a 20MHz high-precision global synchronization clock signal to all modules to ensure that the timing deviation between row driver and column driver is less than 10ns. The power supply module outputs stable VCC_R (2.7V±0.1V), VCC_GB (3.7V±0.1V), and 5V auxiliary power, with output voltage ripple less than 50mV. S32. All column driver ICs are turned off. The control module simultaneously outputs a low-level turn-off signal to the column driver ROW terminals of the first display content column driver UR1, the third display content column driver UG1, and the second display content column driver UB1. All column driver output terminals are turned off within 100ns to avoid current spikes and pixel crosstalk during subsequent anode voltage switching. S33, ICND2018 latches row data. The control module serially inputs the row address code of the Nth row (N=0~63) and the first display content display instruction (0x01) to the eight cascaded ICND2018 row driver ICs, and outputs latch pulses to the row driver RCLK terminals of all row driver ICs. After the ICND2018 latches the data, only the row channel of the Nth row is selected, and the other row channels remain high-impedance off. S34, UR1 latches the grayscale data of the first display content in the Nth row. The control module serially inputs the 14-bit grayscale data of the first display content of 16 pixels in the Nth row to the column driver SDI_1 terminal of the first display content column driver UR1, and simultaneously inputs all-black grayscale data (0x0000) to the third display content column driver UG1 and the second display content column driver UB1. Then, it synchronously outputs latching pulses to the column driver LE terminals of the three column driver ICs to complete the grayscale data latching. S35. Only UR1 outputs. ICND2018 displays the first display content according to the latched first display content display instruction. It quickly switches the row line voltage of the Nth row from a high impedance state to 2.6~2.8VVCC_R through the built-in dual voltage switching array. The voltage switching process is completed within 500ns. After the row line voltage stabilizes, it enters the first display content display time slot. S36. When the first display content time slot ends, all column driver outputs are turned off. The control module only outputs a high-level enable signal to the column driver ROW terminal of the first display content column driver UR1. The third display content column driver UG1 and the second display content column driver UB1 remain off. UR1 outputs a constant current of 25mA Sink current in a 4-group time-conduction mode based on the latched grayscale data of the first display content, and lights up the corresponding pixel of the first display content in the Nth row; the time slot duration of the first display content is dynamically adjusted according to the grayscale level, with a maximum duration of 125μs. S37. The controller synchronously sends the instruction again to shut down all column drivers again. When the first display content display time slot ends, the control module immediately outputs a low-level shutdown signal to all three ICND1065L16 channel constant current Sink column driver ICs. All column driver outputs are shut down within 100ns to prepare for anode voltage switching. S38 and ICND2018 switch the row line voltage of the selected row to VCC_GB. The control module sends the second display content and third display content display command (0x02) to the ICND2018 row driver IC. ICND2018 quickly switches the row line voltage of the Nth row from 2.6~2.8VVCC_R to 3.6~3.8VVCC_GB through a dual voltage switching array. The voltage switching process is completed within 500ns. After the row line voltage stabilizes, the second display content and third display content display time slot is entered. S39 and UG1 / UB1 respectively latch the grayscale data of the third display content and the second display content. The control module serially inputs the 14-bit grayscale data of the Nth row and 16th pixel of the third display content to the column driver SDI_2 terminal of the third display content column driver UG1, and serially inputs the 14-bit grayscale data of the Nth row and 16th pixel of the second display content to the column driver SDI_3 terminal of the second display content column driver UB1. At the same time, it inputs all-black grayscale data (0x0000) to the first display content column driver UR1. Then, it synchronously outputs latching pulses to the column driver LE terminals of the three column driver ICs to complete the latching of the grayscale data of the second and third display contents. S310, Only UG1 / UB1 outputs, the control module simultaneously outputs a high-level enable signal to the column driver ROW terminal of the third display content column driver UG1 and the second display content column driver UB1, while the first display content column driver UR1 remains off; UG1 and UB1 respectively output a 25mA constant current sink current in a 4-group time-conduction mode according to the latched grayscale data, lighting up the corresponding third and second display content pixels in the Nth row; the time slot duration of the second and third display content is equal to the time slot duration of the first display content, with a maximum duration of 125μs; S311. When the second and third display content time slots end, all column driver outputs are turned off. When the second and third display content display time slots end, the control module outputs a low-level turn-off signal to all ICND1065L16 channel constant current Sink column driver ICs, and all column driver outputs are turned off; at the same time, a reset pulse is output to ICND2018 row driver IC, and the row channel of the Nth row is reset to the high-impedance turn-off state, completing the full scan of the Nth row; S312, proceed to the next line scan, repeat steps S32 to S311, and complete the scanning and display of lines N+1 to 63 in sequence; when all 64 lines are scanned, proceed to the next frame display cycle, with a frame refresh rate of 60Hz to ensure no visual flicker for the human eye; through this linkage driving method, precise color-separated power supply for the first display content, the second display content, and the third display content LEDs can be achieved while being fully compatible with existing common anode LEDs.

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