A method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. The method comprises the following steps: providing a semiconductor substrate, a first trench is formed in the semiconductor substrate, a field oxide layer is formed on the side wall and the bottom wall of the first trench, so that a space outside the surface of the field oxide layer in the first trench forms a second trench, and the first conductive material is filled in the second trench. The field oxide layer of the side wall of the first trench is removed to a first set depth to form a third trench. A barrier layer is formed on the bottom wall of the third trench, a gate oxide layer is formed on the side wall of the third trench, at least two separated gates are formed in the space outside the surface of the gate oxide layer in the third trench, the barrier layer is removed, and the gap between the separated gates is filled. Then, the space between the bottom of the separated gate and the upper surface of the field oxide layer forms an air layer. Due to the introduction of the air layer, the gate leakage capacitance and the gate-source capacitance are reduced, the switching loss and the conduction loss are reduced, and the opening rate of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, specifically to a method for manufacturing a semiconductor device. This application also relates to a semiconductor device. This application further relates to another method for manufacturing a semiconductor device. Background Technology

[0002] A shielded-gate metal-oxide-semiconductor field-effect transistor (SGT MOSFET) introduces a shielded gate electrode, separate from the gate and connected to the source, into the structure of a traditional trench MOSFET. SGT MOSFETs are available in left-right and top-bottom configurations. Compared to the top-bottom configuration, the left-right configuration exhibits larger parasitic capacitances between the source, drain, and gate, thus increasing switching and conduction losses and limiting the device's turn-on speed.

[0003] Therefore, how to reduce the parasitic capacitance of a device to improve its turn-on speed is a technical problem that needs to be solved. Summary of the Invention

[0004] This application provides a method for manufacturing a semiconductor device to reduce the parasitic capacitance of the device and improve the device's turn-on speed. This application also provides a semiconductor device. This application further provides another method for manufacturing a semiconductor device.

[0005] The specific plan is as follows: In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate, wherein a first trench is formed in the semiconductor substrate, and a field oxide layer is formed on the sidewalls and bottom wall of the first trench, thereby forming a second trench in the space within the first trench and outside the surface of the field oxide layer, the second trench being filled with a first conductive material; removing the field oxide layer on the sidewalls of the first trench along the depth direction of the first trench to a first predetermined depth to form a third trench; forming a barrier layer on the bottom wall of the third trench; forming a gate oxide layer on the sidewalls of the third trench; forming at least two separation gates in the space within the third trench and outside the surface of the gate oxide layer; removing the barrier layer; and filling the gaps between the separation gates.

[0006] Optionally, before removing the field oxide layer on the sidewall of the first trench along the depth direction of the first trench to a first predetermined depth to form the third trench, the method further includes: performing a chemical mechanical polishing process to remove the first conductive material and the field oxide layer on the surface of the semiconductor substrate, so as to leave a field oxide layer of a predetermined thickness on the surface of the semiconductor substrate.

[0007] Optionally, removing the field oxide layer on the sidewalls of the first trench along the depth direction of the first trench to a first predetermined depth to form a third trench includes: exposing the cell region on the semiconductor substrate by photolithography; performing dry etching and / or wet etching along the depth direction of the first trench to remove the field oxide layer on the sidewalls of the first trench in the cell region to a first predetermined depth to form a third trench.

[0008] Optionally, forming a barrier layer on the bottom wall of the third trench includes: depositing a barrier layer on the sidewalls and bottom wall of the third trench and on the surface of the semiconductor substrate; performing a high-density plasma chemical vapor deposition process to form a first sacrificial oxide layer on the bottom wall of the third trench and on the surface of the semiconductor substrate; performing a wet etching process to remove the barrier layer on the sidewalls of the third trench, while retaining the barrier layer on the bottom wall of the third trench and on the surface of the semiconductor substrate; and performing a wet etching process to remove the first sacrificial oxide layer.

[0009] Optionally, forming a gate oxide layer on the sidewall of the third trench includes: performing a thermal oxidation process to form a second sacrificial oxide layer on the sidewall of the third trench; performing wet etching to remove the second sacrificial oxide layer on the sidewall of the third trench; and performing a thermal oxidation process to form the gate oxide layer on the sidewall of the third trench.

[0010] Optionally, forming at least two separation gates in the space within the third trench and outside the gate oxide layer surface includes: depositing a second conductive material in the space outside the gate oxide layer surface on the sidewall of the third trench, on the top surface of the barrier layer on the bottom wall of the third trench, on the top surface of the first conductive material, and in other areas of the top surface of the semiconductor substrate; removing the second conductive material from the top surface of the barrier layer on the bottom wall of the third trench, the top surface of the first conductive material, and in other areas of the top surface of the semiconductor substrate, while retaining the second conductive material on the sidewall of the third trench, to form at least two separation gates, wherein a first gap region is formed between any two separation gates.

[0011] Optionally, removing the barrier layer includes performing a wet etching process to remove the barrier layer between the bottom of the separation gate and the upper surface of the field oxide layer.

[0012] Optionally, filling the gaps between the separation gates includes performing a high-temperature annealing oxidation process to form a high-temperature oxide layer in the first gap region between the separation gates and on the surface of the separation gates.

[0013] Optionally, the space between the bottom surface of the separation gate and the upper surface of the field oxygen layer constitutes a second void region.

[0014] Optionally, filling the gap between the separation gates includes: performing a filling process to fill the first gap region between the separation gates with dielectric material to form a first dielectric layer.

[0015] Optionally, the dielectric material is a low dielectric constant material with a dielectric constant lower than a preset dielectric constant.

[0016] Optionally, the semiconductor device is a shielded gate trench power device.

[0017] Optionally, the ratio between the deposition thickness of the barrier layer and the thickness of the high-temperature oxide layer is greater than or equal to 0.56.

[0018] Optionally, the barrier layer includes a nitride layer including silicon nitride (SIN), silicon oxynitride (SION), silicon hydrogen nitride (SIHN), or other non-oxidized layers that cannot react with hydrofluoric acid.

[0019] Secondly, embodiments of this application provide a semiconductor substrate in which a first trench is formed, a first conductive material is formed in the first trench, the lower part of the first conductive material and the lower part of the sidewall and the bottom wall of the first trench are isolated by a field oxide layer, a third trench is formed in the space between the upper part of the sidewall of the first trench and the upper part of the sidewall of the first conductive material, a gate oxide layer is formed on the sidewall of the third trench, at least two separation gates are formed in the space inside the third trench and outside the surface of the gate oxide layer, the area between the separation gates is filled with a target dielectric material, and at least a partial void region is formed in the space between the bottom surface of the separation gate and the upper surface of the field oxide layer.

[0020] Thirdly, embodiments of this application provide a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor structure, the semiconductor structure including at least a trench; forming a barrier layer on the bottom wall of the trench; forming a target oxide layer on the sidewall of the trench; forming at least two separate conductive structures in the space within the trench and outside the surface of the target oxide layer; removing the barrier layer; and filling the gaps between the separate conductive structures.

[0021] Compared with the prior art, this application has the following advantages: The semiconductor device manufacturing method provided in this application includes a semiconductor substrate in which a first trench is formed. A field oxide layer is formed on the sidewalls and bottom wall of the first trench, thereby forming a second trench within the first trench and outside the surface of the field oxide layer. The second trench is filled with a first conductive material as a shielding gate. The field oxide layer on the sidewalls of the first trench is removed along the depth direction of the first trench to a first predetermined depth, forming a third trench. A barrier layer is formed on the bottom wall of the third trench. This serves two purposes: firstly, as an isolation structure, it isolates the field oxide layer, preventing damage to the surface of the field oxide layer during the process of forming at least two separation gates within the third structure. Secondly, the area where the barrier layer is located serves as the area for subsequent formation of an air layer. After forming the separation gates, removing the barrier layer allows the space between the bottom surface of the separation gates and the upper surface of the field oxide layer to form an air layer. The separation gates formed in the third trench are isolated from the sidewalls of the third trench by a gate oxide layer, and a gap exists between the two separation gates. After filling the gaps between the separator gates, the air layer between the bottom surface of the separator gate and the top surface of the field oxide layer may be entirely unfilled air gaps, or it may contain partial filler. Since the areas at the bottom of the two separator gates in the air layer are unfilled, at least some areas of the air layer are unfilled, and the dielectric constant of the air layer is less than that of silicon dioxide. Using the air layer as an insulating dielectric layer isolates the separator gate from the field oxide layer, thereby isolating the separator gate from the drain region at the bottom of the semiconductor substrate. This reduces the sense of electric field in the drain region by the separator gate, thus lowering the gate-drain capacitance. Furthermore, the sidewalls of the separator gate are isolated from the upper part of the shielding gate through the gate oxide layer, and the bottom of the separator gate is isolated from the field oxide layer through the air layer. This isolates the bottom of the separator gate from the shielding gate, thereby increasing the blocking of the electric field lines between the separator gate and the shielding gate. The control signal of the separator gate is less likely to affect the shielding gate, thus reducing the charge and discharge load required for the separator gate drive circuit, and thus lowering the gate-source capacitance. The introduction of an air layer reduces gate-drain capacitance and gate-source capacitance, thereby reducing the amount of charge required to turn the device on and off, increasing the rate at which the drive circuit changes the gate voltage, thus shortening the switching time, reducing switching losses and conduction losses, and improving the device's turn-on rate. Attached Figure Description

[0022] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device provided in an embodiment of this application.

[0023] Figure 2 This is a schematic diagram of an example of forming a first trench on an epitaxial layer of a semiconductor substrate, provided in an embodiment of this application.

[0024] Figure 3 This is a schematic diagram of an example of the formation of a field oxygen layer in a first trench and a second trench provided in an embodiment of this application.

[0025] Figure 4 This is a schematic diagram of an example of filling a second trench with a first conductive material, provided in an embodiment of this application.

[0026] Figure 5 This is a schematic diagram of an example of removing the first conductive material and part of the field oxide layer from the surface of a semiconductor substrate, as provided in an embodiment of this application.

[0027] Figure 6 This is a schematic diagram of an example of forming a third trench within a first trench, provided in an embodiment of this application.

[0028] Figure 7 This is a schematic diagram of an example of forming a barrier layer on the surface of a third trench and a semiconductor substrate, as provided in an embodiment of this application.

[0029] Figure 8 This is a schematic diagram of an example of forming a first sacrificial oxide layer on the bottom wall of the third trench and the surface of the semiconductor substrate, as provided in the embodiments of this application.

[0030] Figure 9 This is a schematic diagram of an example of removing the barrier layer on the sidewall of the third trench according to an embodiment of this application.

[0031] Figure 10 This is a schematic diagram of an example of removing the first sacrificial oxide layer provided in the embodiments of this application.

[0032] Figure 11 This is a schematic diagram of an example of forming a gate oxide layer on the sidewall of the third trench, as provided in an embodiment of this application.

[0033] Figure 12 This is a schematic diagram of an example of forming a second conductive material on the bottom wall, side wall, and semiconductor substrate surface of a third trench, as provided in an embodiment of this application.

[0034] Figure 13 This is a schematic diagram of an example of forming at least two separation gates on the sidewall of the third trench, as provided in an embodiment of this application.

[0035] Figure 14 This is a schematic diagram of an example of removing the barrier layer of the bottom wall of the third trench according to an embodiment of this application.

[0036] Figure 15 This is a schematic diagram of the first example of filling the gap between the separation grids provided in the embodiments of this application.

[0037] Figure 16 This is a schematic diagram of a second example of filling the gaps between the separation grids provided in the embodiments of this application.

[0038] Figure 17This is a schematic diagram of an example of a shielding trench structure connecting electrodes provided in an embodiment of this application.

[0039] In the attached figures, the following labels are used: 01-Semiconductor substrate; 02-Epipolar layer; 03-First trench; 04-First oxide layer; 05-Second trench; 06-First conductive material; 07-Photoresist layer; 08-Third trench; 09-Barrier layer; 10-First sacrificial oxide layer; 11-Gate oxide layer; 12-Second conductive material; 12-1-First separation gate; 12-2-Second separation gate; 12-3-First void region; 13-Second void region; 14-High-temperature oxide layer; 15-First dielectric layer; 16-Cell region; 17-Termination region. Detailed Implementation

[0040] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0041] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0042] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0043] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0044] To facilitate understanding of the various embodiments of this application, the application background of the embodiments will be explained.

[0045] A shielded-gate metal-oxide-semiconductor field-effect transistor (SGT MOSFET) introduces a shielded gate electrode, separate from the gate and connected to the source, into the structure of a traditional trench MOSFET. SGT MOSFETs are available in left-right and top-bottom configurations. Compared to the top-bottom configuration, the left-right configuration exhibits larger parasitic capacitances between the source, drain, and gate, thus increasing switching and conduction losses and limiting the device's turn-on speed.

[0046] To address the aforementioned technical problems, this application provides a method for manufacturing a semiconductor device, which aims to reduce the parasitic capacitance of the device to improve the device's turn-on speed.

[0047] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0048] First Embodiment Figure 1 A flowchart of a semiconductor device manufacturing method provided in this application embodiment includes the following steps S101 to S107.

[0049] Step S101: Provide a semiconductor substrate, in which a first trench is formed, and a field oxide layer is formed on the sidewalls and bottom wall of the first trench, thereby forming a second trench in the space inside the first trench and outside the surface of the field oxide layer, and the second trench is filled with a first conductive material. Step S102: Remove the field oxygen layer on the sidewall of the first trench along the depth direction of the first trench to a first set depth to form a third trench; Step S103: Form a barrier layer on the bottom wall of the third trench; Step S104: Form a gate oxide layer on the sidewall of the third trench; Step S105: At least two separation gates are formed in the space within the third trench and outside the surface of the gate oxide layer; Step S106: Remove the barrier layer; Step S107: Fill the gaps between the separation gates.

[0050] Among them, the semiconductor device can be a shielded gate trench type power device.

[0051] Shielded trench power devices can be classified into several types according to the following methods: The first classification, based on the structure of the shielding gate, is divided into two types: top-bottom structure and left-right structure. In a top-bottom structure, the shielding gate is located at the bottom of the trench, directly below the gate. In a left-right structure, the shielding gate and gate are arranged side-by-side within the trench. The second classification, based on the semiconductor material, is divided into silicon-based shielding gate trench power devices and silicon carbide shielding gate trench power devices. The third classification, based on the type of charge carriers in the conductive channel and the polarity of the device's operating voltage, is divided into N-type shielding gate trench power devices (where the charge carrier type is electrons and a positive voltage is applied to the gate) and P-type shielding gate trench power devices (where the charge carrier type is holes and a negative voltage is applied to the gate).

[0052] This application uses a shielded grid trench type power device with a left-right structure as an example for illustration.

[0053] like Figures 2-16 The diagram shown is a structural schematic of a semiconductor device manufacturing method provided in the first embodiment of this application. The following is in conjunction with... Figures 2-16 The manufacturing method will be described in detail.

[0054] Step S101: Provide a semiconductor substrate in which a first trench is formed, and a field oxide layer is formed on the sidewalls and bottom wall of the first trench, thereby forming a second trench in the space inside the first trench and outside the surface of the field oxide layer, and the second trench is filled with a first conductive material.

[0055] like Figure 2 As shown, an epitaxial layer 02 is formed on a semiconductor substrate 01, and a first trench 03 is formed on the epitaxial layer 02.

[0056] Generally, in semiconductor manufacturing, a semiconductor substrate is the base used to form semiconductor devices. Semiconductor substrate materials include, but are not limited to, pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The material of the semiconductor substrate can be selected according to actual needs during the fabrication process. Specifically, in this embodiment, silicon is used as the material for manufacturing the substrate, and semiconductor substrate 01 is provided.

[0057] An epitaxial layer 02 is grown on the semiconductor substrate 01; a second dielectric layer is formed on the top surface of the epitaxial layer 02; a trench pattern is formed in the second dielectric layer by photolithography; using the second dielectric layer with the trench pattern as a hard mask, the epitaxial layer not covered by the second dielectric layer is etched to form a first trench 03 in the epitaxial layer 02.

[0058] An epitaxial layer 02 is grown on the semiconductor substrate 01. Generally, the epitaxial layer 02 is a thin layer of material deposited on the substrate 01 by an epitaxial growth process. The material used for the epitaxial layer 02 can be the same as or different from the material used for the semiconductor substrate 01. Epitaxial growth techniques can include chemical vapor deposition (CVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and vapor phase epitaxy (VPE). Specifically, in this embodiment, CVD is used to grow the epitaxial layer 02.

[0059] A second dielectric layer (not shown in the figure) is formed on the top surface of the epitaxial layer 02. The material of the second dielectric layer needs to have high corrosion resistance, thermal stability, and etching selectivity, and may include silicon oxide, silicon nitride, etc. In this embodiment, silicon oxide is used as an example for the second dielectric layer. The silicon oxide can be formed by thermal oxidation or deposition, which will not be elaborated here. The formed second dielectric layer serves as a hard mask for the subsequent step of forming the first trench 03.

[0060] After forming the second dielectric layer, a trench pattern for forming the first trench 03 is defined using photolithography. Then, the trench pattern is transferred to the second dielectric layer through etching, and the etching process continues to form the first trench 03. Trench etching methods include deep reactive ion etching, wet etching, plasma etching, and reactive ion etching. The number of trenches can be arranged according to the functional requirements of the actual semiconductor device. In this embodiment, forming two first trenches 03 is used as an example for illustration.

[0061] After forming the first trench 03, the second dielectric layer retained on the top surface of the epitaxial layer is removed.

[0062] In other processes, it is also possible to skip forming the second dielectric layer and instead use photoresist directly as a mask layer to form the subsequent first trench 03. After forming the first trench 03, the photoresist is removed.

[0063] After that, as Figure 3 As shown, a field oxygen layer 04 is formed on the sidewall and bottom wall of the first trench 03 by thermal oxidation and / or deposition processes, thereby forming a second trench 05 inside the first trench 03.

[0064] Specifically, a field oxide layer 04 is formed on the sidewalls and bottom wall of the first trench 03 and on the surface of the semiconductor substrate 01.

[0065] The field oxygen layer 04 can be a single type of oxide film. Other processes can also be used to form the field oxygen layer 04, including: dry oxidation, wet oxidation, hydrogen-oxygen synthesis oxidation, alternating dry-wet-dry oxidation, plasma oxidation, etc.

[0066] Preferably, the field oxide layer 04 uses a single type of oxide film layer, that is, the field oxide layer 04 is formed using a single process method. Specifically, in this embodiment, the field oxide layer 04 is a silicon oxide layer formed by performing a thermal oxidation process. In other embodiments, the field oxide layer 04 may also be a composite film layer formed by combining thermal oxidation and deposition processes.

[0067] In this embodiment, the thickness of the field oxide layer 04 is 4000~15000 Å. After forming the field oxide layer 04 of this thickness in the first trench, a second trench 05 can be formed in the space within the first trench 03 and outside the surface of the field oxide layer 04.

[0068] After that, as Figures 4-5 As shown, the second trench 05 is filled with the first conductive material 06, specifically including the following steps: The first conductive material 06 is deposited in other areas of the second trench 05 and the surface of the semiconductor substrate 01, such that the second trench 05 is filled with the first conductive material 06. The first conductive material 06 and the second conductive material 12 filled in the third trench can be the same conductive material or different conductive materials. Therefore, both the first conductive material 06 and the second conductive material 12 can be polycrystalline silicon, or other conductive materials used as gates, such as metals (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)).

[0069] Subsequently, a chemical mechanical polishing process is performed to remove the first conductive material and the field oxide layer on the surface of the semiconductor substrate 01, leaving a field oxide layer 04 of a predetermined thickness on the surface of the semiconductor substrate 01. The retained field oxide layer 04 serves as a hard mask in the subsequent formation of the third trench 08. Here, the predetermined thickness refers to the field oxide layer 04 of a predetermined thickness grown upward from the top surface of the epitaxial layer 02 of the semiconductor substrate 01.

[0070] Step S102: Remove the field oxygen layer on the sidewall of the first trench along the depth direction of the first trench to a first set depth to form a third trench.

[0071] like Figure 6 and Figure 15 As shown, step S102 specifically includes the following processes: Cellular regions 16 on the semiconductor substrate are exposed by photolithography. The cellular regions 16 are regions formed by an array of first trenches 03 including a shielding gate and a control gate. The shielding gate is formed by filling the second trench with the first conductive material 06, and the control gate is formed by a separation gate formed in the third trench. Dry etching and / or wet etching are performed along the depth direction of the first trench to remove the field oxide layer 04 on the sidewalls of the first trench 03 of the cellular region to a first set depth, forming the third trench 08.

[0072] like Figure 5 As shown, after retaining a field oxide layer 04 of a set thickness on the surface of the epitaxial layer 02, in Figure 6 and Figure 15 In this embodiment, a photoresist layer 07 covers the terminal region 17 on the semiconductor substrate, and the pattern of the field oxide layer to be etched is defined in the cell region 16. Then, the field oxide layer is etched along the depth direction of the first trench to a first predetermined depth to form a third trench 08. In this embodiment, the first predetermined depth is the sum of the deposition thickness of the field oxide layer 04 and the deposition thickness of the barrier layer 09. This ensures the space required to form the separation gate and the second gap region between the bottom of the separation gate and the field oxide layer. The first predetermined depth refers to the depth of the bottom of the sidewall of the third trench from the top surface of the epitaxial layer of the semiconductor substrate. In this application, unless otherwise specified, the predetermined depth is the dimension extending from the top surface of the epitaxial layer into the interior of the semiconductor substrate. Other predetermined depths appearing in the following description are defined in this way. Of course, all predetermined depths can also be described using other reference points.

[0073] like Figure 15 As shown, the terminal trench of the terminal region 17 is disposed around the cell region 16 to form a protective ring, which is used to protect the electric field generated by the cell region 16 from reaching the physical edge of the chip and ensure that it is effectively smoothed and absorbed by the terminal region 17. The control gate and shielding gate in the cell region 16 need to be brought out to the outside of the chip for electrical connection.

[0074] Specifically, cell region 16 is a region formed by multiple repeating cell grooves. Figure 15Only one region formed by a cell trench is shown. A cell trench refers to a first trench 03 including a shielding gate and a control gate. Specifically, the cell trench includes: a first trench 03, a field oxide layer 04 formed within the first trench; a second trench 05, a first conductive material 06 filled within the second trench as a shielding gate; a third trench 08, a gate oxide layer 11 within the third trench, and separation gates (e.g., a first separation gate 12-1 and a second separation gate 12-2) formed in the space outside the surface of the gate oxide layer 11; the shielding gate and the separation gates are isolated by the gate oxide layer 11; and a semiconductor body region and a semiconductor heavily doped source region (not shown in the figure) located outside the third trench. Two third trenches are formed on either side of the shielding gate within the first trench, constituting at least two separation gates, with a first gap region 12-3 formed between the two separation gates. Figure 15 The first side-by-side arrangement shown in the figure), or other arrangement methods (the second side-by-side arrangement method is not shown in the figure).

[0075] In step S102, the field oxygen layer is etched to a first predetermined depth along the depth direction of the first trench. This can be done using wet etching alone, dry etching alone, or a combination of wet and dry etching.

[0076] Dry etching refers to reactive ion etching, using fluorine-containing gases (such as CF4, CHF3, and C4F8) as the etching source. In a vacuum chamber, the reactive gas is ionized to form plasma. The active ions / free radicals in the plasma react with the material surface through physical sputtering or chemical reactions, generating volatile products that are then removed, thereby achieving selective material removal in micro- and nano-fabrication techniques.

[0077] Wet etching is a process that selectively removes the field oxide layer without damaging the substrate or other materials using a chemical solution. Typically, hydrofluoric acid (HF) is used as the wet etching solution. HF effectively reacts with and dissolves the field oxide layer. In this process, HF converts silicon dioxide into soluble fluorosilicic acid (H₂SiF₆). After the etching process is complete, the semiconductor substrate is cleaned to remove the fluorosilicic acid solution remaining from the reaction.

[0078] Step S103: Form a barrier layer on the bottom wall of the third trench.

[0079] like Figures 7-10 As shown, a barrier layer is formed on the bottom wall of the third trench 08, specifically including the following steps: A barrier layer 09 (e.g., ...) is deposited on the sidewalls and bottom wall of the third trench 08, and on the surface of the semiconductor substrate 01 (i.e., the top surface of the epitaxial layer 02). Figure 7(As shown); A high-density plasma chemical vapor deposition process is performed to form a first sacrificial oxide layer 10 on the bottom wall of the third trench 08 and on the surface of the semiconductor substrate 01 (as shown). Figure 8 (As shown); Perform a wet etching process to remove the barrier layer 09 on the sidewall of the third trench 08, retaining the barrier layer 09 on the bottom wall of the third trench 08 and the surface of the semiconductor substrate 01 (as shown). Figure 9 As shown); perform a wet etching process to remove the first sacrificial oxide layer 10 (as shown). Figure 10 (As shown).

[0080] First, a barrier layer 09 is deposited on the sidewalls and bottom wall of the third trench 08, and on the surface of the semiconductor substrate 01 (i.e., the top surface of the epitaxial layer 02). This is to ensure that the bottom wall of the third trench 08 is fully covered with the barrier layer. Then, the barrier layer 09 on the two sidewalls of the third trench 08 is removed to allow for the formation of the gate oxide layer 11 on the sidewalls of the third trench 08 in subsequent steps. Retaining the barrier layer on the bottom wall of the third trench 08 serves two purposes: firstly, it acts as an isolation structure, isolating the field oxide layer and preventing damage to the field oxide layer surface from residual material from the wet etching process during the formation of at least two separate gates within the third structure; secondly, the area containing the barrier layer serves as the area for subsequent formation of the air layer (i.e.,...). Figure 15 In the second void region 13), after the separation grid is formed, the barrier layer is removed, so that the space between the bottom surface of the separation grid and the upper surface of the field oxygen layer constitutes an air layer.

[0081] The barrier layer 09 includes a nitride layer including silicon nitride (SIN), silicon oxynitride (SION), silicon hydride nitride (SIHN), or other non-oxidized layers that cannot react with hydrofluoric acid. The ratio between the deposition thickness of the barrier layer 09 and the thickness of the high-temperature oxide layer is greater than or equal to 0.56. The deposition thickness of the barrier layer 09 is 300~1000 angstroms (Å). Because the barrier layer 09 formed on the bottom wall of the third trench 08 is for the subsequent formation of an air layer, and after forming at least two separation gates in the third trench and removing the barrier layer, a high-temperature oxide layer will be formed on the two separation gates. Of the thickness of the high-temperature oxide layer, 44% of the thickness is obtained by forming inside the separation gate (e.g., polycrystalline silicon material), and 56% of the thickness extends outside the polycrystalline silicon. Therefore, the high-temperature oxide layer occupies part of the thickness of the second void region 13. In order for the second void region 13 to contain a part of the thickness of the air layer, the thickness of the barrier layer here needs to be greater than 0.56 times the thickness of the high-temperature oxide layer.

[0082] It should be noted that the main function of the first sacrificial oxide layer 10 formed here is to act as a hard mask or protective layer to protect the bottom wall of the third trench 08 and the barrier layer 09 on the surface of the semiconductor substrate 01. Then, by performing a wet etching process, only the barrier layer on the sidewall of the third trench 08 can be removed.

[0083] The high-density plasma chemical vapor deposition (HDP) process here involves simultaneous deposition and physical sputtering (etching) processes. While a first sacrificial oxide film is deposited using reactive gases (e.g., silane and oxygen), a high-density inert gas (e.g., argon (Ar) or helium (He)) is introduced for physical sputtering.

[0084] Here, the HDP process is performed, and the thickness of the first sacrificial oxide layer 10 formed on the bottom wall of the third trench 08 and on the surface of the semiconductor substrate 01 is a first preset thickness, which is 200 angstroms (Å) to 500 angstroms (Å). On one hand, the heating temperature is typically 200°C to 600°C, which allows for the formation of a higher quality oxide layer at lower temperatures. For semiconductor substrates with already fine structures, this reduces the thermal budget and prevents deformation or impurity diffusion of the underlying structure. On the other hand, even if the aspect ratio of the third trench is high, a dense sacrificial oxide layer can still be formed at the edge of the bottom wall of the third trench (near the corner), improving the protection effect of the bottom wall barrier layer near the corner of the third trench.

[0085] The physical sputtering process here involves high-energy particles physically bombarding the wafer surface like "sandpaper." Due to the conservation of momentum, the semiconductor substrate surface and the bottom wall of the third trench are horizontal surfaces, and the bombardment angle they receive is relatively positive. The deposition rate is greater than the sputtering rate, so the first sacrificial oxide layer is retained and grown. However, the ion bombardment received by the sidewalls of the third trench has a specific angular effect, or the sputtering effect is stronger than the deposition effect, resulting in the removal of material on the sidewalls, or even the inability to deposit material at all. Therefore, performing a high-density plasma chemical vapor deposition process can create a highly directional coverage effect. Specifically, the bottom wall of the third trench 08 and the semiconductor substrate surface are covered with a first sacrificial oxide layer of a first predetermined thickness (e.g., 200~500 Å), while the sidewalls of the third trench 08 cannot form a first sacrificial oxide layer, or the thickness of the first sacrificial oxide layer formed on the sidewalls of the third trench 08 is very small and negligible.

[0086] Therefore, by performing the HDP process, the barrier layer on the bottom wall of the third trench 08 and the surface of the semiconductor substrate 01 is protected, while the barrier layer on the sidewalls of the third trench 08 is exposed. This allows for high-precision patterning and avoids complex mask lithography steps. Subsequently, a wet etching process is performed, which removes only the barrier layer on the sidewalls of the third trench 08. The barrier layer 09 includes a nitride layer comprising any one of silicon nitride (SIN), silicon oxynitride (SION), or silicon hydrogen nitride (SIHN), or other non-oxide layers that cannot react with hydrofluoric acid.

[0087] The wet etching solution used here is hot phosphoric acid (H3PO4). Typically, the phosphoric acid is heated to 150°C–180°C. As a catalyst, phosphoric acid promotes the hydrolysis of the nitride in the barrier layer with water, generating silicon dioxide and ammonia, thereby removing the barrier layer on the sidewall of the third trench 08. The etching rate of hot phosphoric acid for nitrides is 500–100 Å / min, while the etching rate for the first sacrificial oxide layer (silicon dioxide, SiO2) is 2–10 Å / min, and the etching rate for the epitaxial layer (single-crystal silicon, Si) of the semiconductor substrate is less than 1 Å / min. Therefore, during the removal of the barrier layer on the sidewall of the third trench 08 using hot phosphoric acid, the impact on the semiconductor substrate and the first sacrificial oxide layer on the bottom wall of the third trench is minimal, and may not even cause damage to the semiconductor substrate or the bottom wall of the third trench. Therefore, the stop time for the wet etching process on the barrier layer on the sidewall of the third trench can be determined by the change in the etching rate.

[0088] In this embodiment, a wet etching process is used to remove the barrier layer on the sidewall of the third trench 08. The content of the wet etching solution used is 1.3 to 1.5 times the content of the standard wet etching solution required for the deposition thickness of the barrier layer, so as to ensure that the barrier layer on the sidewall of the third trench 08 can be completely removed by the wet etching solution.

[0089] During the removal of the barrier layer on the sidewall of the third trench 08, residual wet etching solution and metal ions remain on the first sacrificial oxide layer on the bottom wall of the third trench. Therefore, it is necessary to remove the first sacrificial oxide layer to avoid these residues between the gate and the semiconductor substrate formed subsequently, which could lead to leakage or breakdown of the semiconductor device.

[0090] Therefore, a wet etching process is used to remove the bottom wall of the third trench 08 and the first sacrificial oxide layer 10 on the surface of the semiconductor substrate 01 (i.e., the top surface of the epitaxial layer 02). When the first sacrificial oxide layer 10 is removed using hydrofluoric acid, the aforementioned impurities (wet etching solution and metal ions) formed by the etching process are removed together with the first sacrificial oxide layer 10, exposing the barrier layer.

[0091] In this embodiment, a wet etching process is used to remove the first sacrificial oxide layer 10. The content of the wet etching solution used is 1.3 to 1.5 times the content of the standard wet etching solution required for the deposition thickness of the first sacrificial oxide layer 10, so as to ensure that the first sacrificial oxide layer 10 can be completely removed by the wet etching solution.

[0092] Step S104: Form a gate oxide layer on the sidewall of the third trench.

[0093] like Figure 11 As shown, a gate oxide layer is formed on the sidewall of the third trench 08, specifically including the following steps: A thermal oxidation process is performed to form a second sacrificial oxide layer (not shown in the figure) on the sidewall of the third trench 08; a wet etching process is performed to remove the second sacrificial oxide layer on the sidewall of the third trench 08; and a thermal oxidation process is performed to form the gate oxide layer 11 on the sidewall of the third trench 08.

[0094] During the wet etching process in step S103 to remove the barrier layer on the sidewall of the third trench 08, the single-crystal silicon surface of the sidewall of the third trench after the barrier layer is removed will be chemically eroded by the wet etching solution (e.g., hot phosphoric acid), causing damage to the single-crystal silicon lattice on the sidewall surface. If a gate oxide layer is grown directly on this sidewall surface, it will cause an increase in the interface state density, affecting device performance, such as causing leakage current and threshold voltage drift in semiconductor devices. Therefore, a thermal oxidation process is first performed to form a second sacrificial oxide layer (not shown in the figure) on the sidewall of the third trench 08. This can be achieved by growing a thin layer of silicon dioxide (SiO2) (e.g., 5~20 nanometers (nm)) by introducing oxygen or water vapor at a high temperature (900-1000°C). Damaged silicon atoms, residual metal ions, organic matter, or particles formed by wet etching of the barrier layer on the sidewall of the third trench 08 can be encapsulated in the sacrificial oxide layer. Then, during the wet etching process, when the second sacrificial oxide layer (not shown in the figure) is removed using hydrofluoric acid, the aforementioned impurities formed by the etching and the second sacrificial oxide layer are removed together, exposing an atomically smooth and defect-free silicon surface to avoid the aforementioned impurities affecting the quality of the subsequently formed gate oxide layer. Furthermore, during the formation of the second sacrificial oxide layer on the sidewall of the third trench 08, the bottom corner of the third trench can be rounded to achieve a rounded shape.

[0095] Then, when the sidewall of the third trench 08 is an atomically smooth, defect-free silicon surface, a thermal oxidation process is performed to form a high-quality, extremely thin gate oxide layer 11 on this sidewall. Specifically, dry oxidation or wet oxidation is performed at a temperature of 900℃~1200℃ to form a silicon dioxide layer on the sidewall of the third trench 08. Dry oxidation refers to introducing high-purity oxygen to react chemically with the silicon substrate to form a silicon dioxide layer. Wet oxidation refers to introducing water vapor to react chemically with the silicon substrate to form a silicon dioxide layer. Alternating dry and wet oxidation methods can also be used to form the gate oxide layer. The gate oxide layer is the core dielectric layer of the semiconductor device. As an insulating layer between the gate and the trench in the SGT MOS transistor structure, it controls the source and drain currents by inducing channel carriers through an electric field when a gate voltage is applied.

[0096] In this embodiment, the gate oxide layer is formed on the sidewall of the third trench 08 using a thermal oxidation process, rather than a composite layer or a combination of deposition and annealing processes. The reasons are as follows: The thermal oxidation process requires monocrystalline silicon, and the sidewall of the third trench 08 is an epitaxial layer of the semiconductor substrate, which is made of monocrystalline silicon. The bottom wall of the sidewall of the third trench 08 and the surface of the semiconductor substrate 01 are covered by a barrier layer, which is a nitride layer and cannot undergo thermal oxidation. Therefore, by performing the thermal oxidation process, a gate oxide layer with a thickness of 200~500 angstroms (Å) can be formed only on the sidewall of the third trench 08.

[0097] However, if a composite layer approach is used, or a combination of deposition and annealing processes is employed, a gate oxide layer will be formed on the sidewalls of the third trench 08, as well as on the bottom wall of the third trench 08 and the surface of the barrier layer on the semiconductor substrate 01. On one hand, the silicon dioxide layer formed by deposition has poor interface quality and numerous defects. In contrast, thermal oxidation can form an atomically smooth, chemically bonded, and perfectly formed interface with fewer defects. On the other hand, the composite layer refers to an oxide-nitride-oxide (ONO) layer, which is typically used for isolation beneath the gate, not as a gate oxide layer. Furthermore, the process for forming the composite layer is complex, and the ONO layer structure contains multiple interfaces. Each interface can introduce defects and charge traps, resulting in an overall interface state density higher than that of the thermally oxidized layer within the unit cell, negatively impacting device performance.

[0098] On the other hand, in this embodiment, only the gate oxide layer needs to be formed on the sidewall of the third trench 08. Therefore, an etching process is also required to remove the gate oxide layer on the bottom wall of the third trench 08 and the barrier layer surface of the semiconductor substrate 01. During the removal process, part of the gate oxide layer on the sidewall of the third trench 08 will be removed, resulting in a thinner gate oxide layer and affecting the performance of the semiconductor device formed subsequently.

[0099] Therefore, in this embodiment of the application, a gate oxide layer is formed on the sidewall of the third trench 08 by a thermal oxidation process.

[0100] Step S105: At least two separation gates are formed in the space within the third trench and outside the surface of the gate oxide layer 11.

[0101] like Figures 12 to 13 As shown, at least two separation gates (e.g., a first separation sub-gate 12-1 and a second separation sub-gate 12-2) are formed in the space within the third trench 08 and outside the surface of the gate oxide layer 11, specifically including the following steps: A second conductive material 12 is deposited in the space outside the gate oxide layer 11 on the sidewall of the third trench 08, on the top surface of the barrier layer 09 on the bottom wall of the third trench 08, on the top surface of the first conductive material 06, and in other areas on the top surface of the semiconductor substrate 01. The second conductive material 12 is removed from the top surface of the barrier layer 09 on the bottom wall of the third trench 08, the top surface of the first conductive material 06, and in other areas on the top surface of the semiconductor substrate 01, while the second conductive material 12 on the sidewall of the third trench 08 is retained, forming at least two separation gates, wherein a first gap region 12-3 is formed between any two separation gates.

[0102] like Figure 12 As shown, the second conductive material deposited on the sidewalls (e.g., the first sidewall 08-1 and the second sidewall 08-2) within the third trench 08 is isolated from the sidewalls within the third trench 08 by a gate oxide layer 11. The second conductive material deposited on the bottom wall within the third trench 08 is isolated from the bottom wall within the third trench 08 by a barrier layer 09. The deposition thickness of the second conductive material 12 is less than a second preset thickness, which is half the difference between the field oxide layer 04 and the gate oxide layer 11.

[0103] It should be noted that the deposition thickness of the second conductive material 12 is set to be less than the second preset thickness so that after the second conductive material is deposited on the sidewall and bottom wall of the third trench, there are still other gap areas between the second conductive materials on the two sidewalls of the third trench, so that the etching process can be performed through the first gap area in the subsequent process to remove the barrier layer 09 on the bottom wall of the third trench 08.

[0104] Specifically, the second conductive material 12 is first removed from the bottom wall of the third trench 08, the top surface of the first conductive material 06, and other areas of the top surface of the semiconductor substrate 01, while retaining the second conductive material on the two sidewalls of the third trench 08, forming at least two separation gates, such as... Figure 12The first separation gate 12-1 and the second separation gate 12-2 are in the middle, and a first gap region 12-3 is formed between the first separation gate 12-1 and the second separation gate 12-2.

[0105] Step S106: Remove the barrier layer.

[0106] Among them, such as Figure 14 As shown, a wet etching process is performed to remove the barrier layer 09 between the bottom of the separation gate and the upper surface of the field oxide layer 04. After removing the barrier layer 09, the space between the bottom surface of the separation gate and the upper surface of the field oxide layer 04 forms a second void region 13, which serves as an insulating material to isolate the separation gate from the field oxide layer, and to isolate the separation gate from the shielding gate. In this embodiment, a wet etching process is used to remove the barrier layer on the bottom wall of the third trench 08. The content of the wet etching solution used is 1.3 to 1.5 times the standard wet etching solution content required for the deposition thickness of the barrier layer, to ensure that the barrier layer on the bottom wall of the third trench 08 can be completely removed by the wet etching solution.

[0107] Step S107: Fill the gaps between the separation gates.

[0108] The filling of the gaps between the separation gates includes: filling the region between the separation gates with a target dielectric material, wherein the target dielectric material is a high-temperature oxidizing material (forming as shown in the figure). Figure 15 The high-temperature oxide layer 14 shown) or low dielectric constant material (formed as shown) Figure 16 The first dielectric layer is specifically described through the following two implementation methods: The first method is as follows: Figure 15 As shown, a high-temperature annealing oxidation process is performed to form a high-temperature oxide layer 14 in the first gap region 12-3 between the separation gates and on the surface of the separation gates. The separation gates can be polycrystalline silicon. The high-temperature annealing oxidation process refers to a process combining thermal oxidation and high-temperature annealing, or a high-temperature heat treatment performed in an oxidizing atmosphere. Specifically, the semiconductor device is placed in a high-temperature furnace tube, and an oxidizing gas (such as oxygen or water vapor) is introduced. Growth proceeds bidirectionally inwards and outwards, starting from the top surface, bottom surface, and sidewall surface of the separation gate. For example, if the separation gate is made of polycrystalline silicon, oxygen diffuses into the polycrystalline silicon interior of the separation gate and reacts chemically with the polycrystalline silicon, resulting in the simultaneous growth of a high-temperature oxide layer inside and outside the silicon. Typically, 44% of the high-temperature oxide layer thickness is obtained by growth into the polycrystalline silicon, and 56% of the high-temperature oxide layer thickness extends outwards from the polycrystalline silicon. After the high-temperature oxide layer is formed, the surface of the high-temperature oxide layer of the separation gate is also subjected to rounding treatment and sacrificial oxidation treatment to remove defects and residual impurities on the surface of the high-temperature oxide layer and obtain a smooth high-temperature oxide layer surface.

[0109] like Figure 15 As shown, the high-temperature oxide layer 14 covers the first void region 12-3 and the surfaces of the two separation gates. Therefore, after forming the high-temperature oxide layer 14, on the one hand, the second void region 13 is an air layer without filling material, which acts as an insulating dielectric layer, isolating the separation gate from the field oxide layer. This isolates the separation gate from the drain region at the bottom of the semiconductor substrate, reducing the separation gate's perception of the electric field in the drain region, thereby reducing the gate-drain capacitance. Furthermore, the sidewalls of the separation gate are isolated from the upper part of the shielding gate through the gate oxide layer, and the bottom of the separation gate is isolated from the field oxide layer through an air layer. This isolates the bottom of the separation gate from the shielding gate, thereby increasing the blocking of the electric field lines between the separation gate and the shielding gate. The control signal of the separation gate is less likely to affect the shielding gate, thus reducing the load that the separation gate drive circuit needs to charge and discharge, thereby reducing the gate-source capacitance. Because the introduction of the second void region 13 reduces the gate-drain capacitance and gate-source capacitance, the amount of charge required to turn the drive device on and off can be reduced, increasing the rate at which the drive circuit changes the gate voltage, thereby shortening the switching time, reducing switching losses and conduction losses, and improving the device's turn-on rate. On the other hand, during the process of forming a high-temperature oxide layer 14 on the two separate gate surfaces, the gate oxide layer on the sidewall of the third trench 08 and the high-temperature oxide layer formed on the adjacent separate gate surface are superimposed, which can increase the oxide layer thickness at the corner of the sidewall in the third trench 08, thereby adjusting the gate-source capacitance, reducing the risk of gate-source leakage, reducing the dynamic loss of semiconductor devices, and enhancing the stability and reliability of semiconductor devices.

[0110] The second method is as follows: Figure 16 As shown, a filling process is performed to fill the first gap region 12-3 between the separation gates with dielectric material to form a first dielectric layer 15. The dielectric material is a low-dielectric-constant material with a dielectric constant lower than a preset dielectric constant. Here, the preset dielectric constant is 3.9, and the field oxide layer is made of silicon dioxide with a dielectric constant of 3.9. During the filling of the first gap region 12-3 with the low-dielectric-constant material with a dielectric constant lower than 3.9, at least a portion of the second gap region 13 is filled with this low-dielectric-constant material, while the region at the bottom of the two separation gates is not filled with this low-dielectric-constant material.

[0111] Therefore, the second gap region 13 is an air layer with some unfilled areas. As an insulating dielectric layer, it isolates the bottom surface of the separation gate from the field oxygen layer, as well as the sidewall of the separation gate from the shielding gate, reducing the gate-drain capacitance and gate-source capacitance. This reduces the amount of charge required to turn the driving device on and off, increases the rate at which the driving circuit changes the gate voltage, thereby shortening the switching time, reducing switching losses and conduction losses, and improving the device's turn-on rate.

[0112] Next, the fabrication of the body region, source region, insulating layer, contact holes, and source, drain, and gate electrodes of the semiconductor device is completed, ultimately completing the fabrication of the SGT MOSFET. Among these, such as... Figure 17 As shown, the terminal region 17 is a trench structure containing only a shielding gate, which is connected to the source S. In the cell region 16, the first trench 03 contains a shielding gate (i.e., the first conductive material 06 filled in the second trench), which is connected to the source S. Two third trenches 08 are located on the left and right sides of the shielding gate. Each third trench 08 contains at least two separation gates. The separation gate closest to the sidewall of the first trench 03 (e.g., the first separation gate 12-1) is connected to the gate level G, forming a control gate. The separation gate closest to the source level (e.g., the second separation gate 12-2) serves as an adjustment electrode. The adjustment electrodes can be set to float in different regions of the die according to a certain ratio, connected to the source level, and connected to the gate, thereby adjusting the gate charge, gate resistance, and source resistance, and thus adjusting the switching loss and conduction loss to improve the switching efficiency of the device. Since the above manufacturing process can be implemented using conventional manufacturing processes in the art, it will not be described in detail here.

[0113] Second Embodiment A second embodiment of this application provides a semiconductor device, comprising: a semiconductor substrate, in which a first trench is formed, a first conductive material is formed in the first trench, the lower part of the first conductive material and the lower part of the sidewall and the bottom wall in the first trench are isolated by a field oxide layer, a third trench is formed in the space between the upper part of the sidewall in the first trench and the upper part of the sidewall of the first conductive material, a gate oxide layer is formed on the sidewall of the third trench, at least two separation gates are formed in the space in the third trench and outside the surface of the gate oxide layer, the region between the separation gates is filled with a target dielectric material, and at least a partial void region is formed in the space between the bottom surface of the separation gate and the upper surface of the field oxide layer.

[0114] The target dielectric material includes high-temperature oxidizing materials or low dielectric constant materials.

[0115] Third Embodiment The third embodiment of this application provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor structure, the semiconductor structure including at least a trench; forming a barrier layer on the bottom wall of the trench; forming a target oxide layer on the side wall of the trench; forming at least two separate conductive structures in the space within the trench and outside the surface of the target oxide layer; removing the barrier layer; and filling the gaps between the separate conductive structures.

[0116] At least two separate conductive structures are formed within the trench, with a gap between them. The dielectric constant of the gap is lower than that of the conductive structures. This allows for the use of the low-dielectric-constant dielectric material in the gap between the separate conductive structures within the trench to achieve specific electrical isolation and performance balance.

[0117] For example, filling the gaps between the separated conductive structures with a low dielectric constant, or directly using air gaps as the filler for the separated conductive structures, can reduce parasitic capacitance and decrease the amount of charge required for the device during switching, thereby significantly improving switching speed and reducing switching losses.

[0118] For example, in high-voltage power devices, the electric field distribution deep within deep trenches is complex, forming at least two separate conductive structures. The low-dielectric-constant gaps between these structures can act as effective electric field buffer layers. Because the electric field strength at the dielectric interface is inversely proportional to the dielectric constant, the low-dielectric-constant region can withstand a higher voltage drop. Therefore, the gaps between the separate conductive structures help to remove the high electric field from the sensitive oxide layer region, preventing the oxide layer from breaking down under high voltage, thereby improving the device's breakdown voltage and reliability.

[0119] The isolated conductive structure is formed by a conductive material, which can be polycrystalline silicon or other conductive materials, such as metals (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)).

[0120] After removing the barrier layer and filling the gaps between the separated conductive structures, an air layer can be formed at the bottom of the separated conductive structure. This air layer can be completely unfilled or partially filled with material. Both methods of obtaining the air layer can be used to isolate the separated conductive structure in a semiconductor device from other structures located at the bottom of the separated conductive structure.

[0121] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, in which a first trench is formed, and a field oxide layer is formed on the sidewalls and bottom wall of the first trench, thereby forming a second trench in the space inside the first trench and outside the surface of the field oxide layer, and the second trench is filled with a first conductive material. Remove the field oxygen layer on the sidewall of the first trench along the depth direction of the first trench to a first set depth to form a third trench; A barrier layer is formed on the bottom wall of the third trench; A gate oxide layer is formed on the sidewall of the third trench; At least two separation gates are formed in the space within the third trench and outside the surface of the gate oxide layer; Remove the barrier layer; Fill the gaps between the separation gates.

2. The method according to claim 1, characterized in that, The step of removing the field oxygen layer from the sidewall of the first trench along the depth direction of the first trench to a first predetermined depth to form a third trench includes: The cellular regions on the semiconductor substrate are exposed by photolithography. Dry etching and / or wet etching are performed along the depth direction of the first trench to remove the field oxide layer on the sidewall of the first trench in the cell region to a first set depth, forming a third trench.

3. The method according to claim 1, characterized in that, The formation of a barrier layer on the bottom wall of the third trench includes: A barrier layer is deposited on the sidewalls and bottom wall of the third trench and on the surface of the semiconductor substrate; A high-density plasma chemical vapor deposition process is performed to form a first sacrificial oxide layer on the bottom wall of the third trench and on the surface of the semiconductor substrate; Perform a wet etching process to remove the barrier layer on the sidewall of the third trench, while retaining the bottom wall of the third trench and the barrier layer on the surface of the semiconductor substrate. Perform a wet etching process to remove the first sacrificial oxide layer.

4. The method according to claim 1, characterized in that, The space within the third trench and outside the gate oxide layer surface forms at least two separation gates, including: A second conductive material is deposited in the space outside the gate oxide layer surface on the sidewall of the third trench, on the top surface of the barrier layer on the bottom wall of the third trench, on the top surface of the first conductive material, and in other areas on the top surface of the semiconductor substrate. Remove the second conductive material from the top surface of the barrier layer, the top surface of the first conductive material, and other areas of the top surface of the semiconductor substrate on the bottom wall of the third trench, while retaining the second conductive material on the sidewall of the third trench, to form at least two separation gates, wherein a first gap region is formed between any two separation gates.

5. The method according to claim 1, characterized in that, The removal of the blocking layer includes: A wet etching process is performed to remove the barrier layer between the bottom of the separation gate and the upper surface of the field oxide layer.

6. The method according to claim 1, characterized in that, The filling of the gaps between the separation gates includes: A high-temperature annealing oxidation process is performed to form a high-temperature oxide layer in the first gap region between the separation gates and on the surface of the separation gates.

7. The method according to claim 6, characterized in that, The space between the bottom surface of the separation gate and the upper surface of the field oxygen layer constitutes a second void region.

8. The method according to claim 1, characterized in that, The filling of the gaps between the separation gates includes: A filling process is performed to fill the first gap region between the separation gates with dielectric material to form a first dielectric layer.

9. The method according to claim 8, characterized in that, The dielectric material is a low dielectric constant material with a dielectric constant lower than a preset dielectric constant.

10. The method according to claim 1, characterized in that, The semiconductor device is a shielded gate trench type power device.

11. A semiconductor device, characterized in that, include: A semiconductor substrate has a first trench formed therein, a first conductive material formed therein, the lower part of the first conductive material and the lower part of the sidewall and the bottom wall of the first trench being isolated by a field oxide layer, a third trench being formed in the space between the upper part of the sidewall of the first trench and the upper part of the sidewall of the first conductive material, a gate oxide layer being formed on the sidewall of the third trench, at least two separation gates being formed in the space within the third trench and outside the surface of the gate oxide layer, the region between the separation gates being filled with a target dielectric material, and at least a partial void region being formed in the space between the bottom surface of the separation gate and the upper surface of the field oxide layer.

12. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor structure is provided, the semiconductor structure including at least one trench; A barrier layer is formed on the bottom wall of the trench; A target oxide layer is formed on the sidewall of the trench; At least two separate conductive structures are formed in the space within the trench and outside the surface of the target oxide layer; Remove the barrier layer; Fill the gaps between the separated conductive structures.

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