Peak current control circuit of flyback converter and flyback converter

Abstract

The utility model provides a flyback converter control circuit and the flyback converter, including a reference signal generating circuit, including a plurality of capacitors, controlling the charging time period of each capacitor in the plurality of capacitors according to the switching period to obtain a reference signal, the reference signal being used for controlling the magnitude of the peak current flowing through the main power tube; the comparator is used for comparing the reference signal with a current sampling signal representing the current of the main power tube so as to control the turn-off moment of the main power tube; wherein when the switching period is larger than a first threshold value and smaller than a second threshold value, the reference signal has at least two change stages, the switching period in the first change stage is larger than the switching period in the second change stage, and the change rates of the reference signal are different in different change stages. According to the utility model, the peak current of the flyback converter can be flexibly adjusted so as to meet application requirements.

Description

Technical Field

[0001] The utility model relates to the field of lighting, and particularly relates to a peak current control circuit of a flyback converter and the flyback converter. Background Art

[0002] In the current peak current control method of a flyback converter, the peak current is usually controlled according to the switching period Tsw / switching frequency Fsw. Figure 1 Fig. shows a common flyback converter, which includes a main power transistor Q1, a rectifier diode Q2, and a transformer T1. The main power transistor Q1 is connected to the primary winding Np of the transformer T1, and the rectifier diode Q2 is connected to the secondary winding Ns of the transformer T1. Figure 2 (a) shows a curve diagram of the reference signal VCS_REF of the peak current on the main power transistor Q1 changing with the switching period Tsw. In Figure 2 (a), when Tsw < T1, the reference signal VCS_REF reaches the maximum value VCS_MAX; when T1 < Tsw < T2, the reference signal VCS_REF decreases at a first change rate as the switching period Tsw increases; when Tsw > T2, the reference signal VCS_REF remains at the minimum value VCS_MIN. Figure 2 (b) shows a curve diagram of the relationship between the reference signal VCS_REF and the switching frequency Fsw (1 / Tsw), which corresponds to Figure 2 (a) and will not be elaborated further here.

[0003] Based on Figure 2 the shown peak current control method, the working waveform diagram of the flyback converter shown in Figure 3 is obtained. In Figure 3 , Vgs is the gate drive signal of the main power transistor Q1 of the flyback converter, Vsw is the drain voltage signal of the rectifier diode Q2 of the flyback converter, Ip is the primary excitation current, Is is the secondary freewheeling current, VCS_REF is the reference signal for controlling the peak value of Ip, and VCS is the current sampling signal on the main power transistor Q1. After the main power transistor Q1 is turned off and the secondary rectifier diode Q2 is turned on, the reference signal VCS_REF gradually decreases. When the main power transistor Q1 is turned on, the current sampling signal VCS gradually increases. When the current sampling signal VCS reaches the reference signal VCS_REF (i.e., the current on the main power transistor Q1 reaches the peak current), the main power transistor Q1 is turned off, and the reference signal VCS_REF stops decreasing and returns to the initial value.

[0004] For the above peak current control scheme, in the PD-20W (12V / 1.67A-9V / 2.23A-5V / 3A) fast charging scheme, when the output voltage is low (such as 90V) or low voltage (5V / 3A), the system works in BCM mode or DCM mode. At this time, the switching frequency is low. According to the above peak current control method, the peak current I on the main power tube Q1 is PK As the frequency decreases, it can reach 20-30kHz, according to Pin=1 / 2*I PK ^2*Fsw may result in the output power not being able to meet the requirements; in applications with high input voltage (such as 230Vac) and high output voltage (such as 12V), the maximum power point is considered to be about 1.2 times the rated power point (such as 12V / 1.67A), and combined with Figure 2 The relationship curve between VCS_REF and Fsw is shown. It can be seen that the switching frequency under rated load is significantly lower than the maximum switching frequency, which makes the operating frequency of the magnetic core low and the volume of the magnetic core cannot be significantly reduced.

[0005] The reason why the above application has some shortcomings is that when the switching frequency Fsw decreases, the current sampling signal VCS (i.e., the current on the main power tube Q1) will also decrease, and the current sampling signal VCS and the switching current Fsw are one-to-one corresponding. There will not be a phenomenon that the reference signal VCS_REF decreases and the switching frequency Fsw remains unchanged; there will not be a phenomenon that when the reference signal VCS_REF is close to the maximum value VCS_MAX, the switching frequency is significantly lower than the maximum switching frequency Fsw_max, or even about to reach the minimum switching frequency Fsw_min. Summary of the invention

[0006] The utility model aims to provide a flyback converter and a control method thereof, which can flexibly control the peak current on the main power tube, so that the system can meet the output power demand at low frequency and improve the working efficiency at high voltage input.

[0007] The utility model also provides a peak current control circuit of a flyback converter, the flyback converter comprises a main power tube, a rectifier tube and a transformer, the main power tube is connected to the primary winding of the transformer, the rectifier tube is connected to the secondary winding of the transformer, and comprises:

[0008] A reference signal generating circuit, comprising a plurality of capacitors, controlling a charging period of each of the plurality of capacitors according to a switching cycle to obtain a reference signal;

[0009] A comparator, which compares the reference signal with a current sampling signal representing the current of the main power tube to control the shutdown moment of the main power tube;

[0010] When the switching period is greater than a first threshold and less than a second threshold, the reference signal has at least two change phases, and the switching period in the first change phase is greater than the switching period in the second change phase.

[0011] Optionally, in different change phases, the change rate of the reference signal is different.

[0012] Optionally, in the first change phase, the reference signal decreases as the switching period increases.

[0013] Optionally, in the first change phase, the reference signal increases as the switching period increases.

[0014] Optionally, in the second change phase, the reference signal decreases as the switching period increases.

[0015] Optionally, the first change phase is further divided into a plurality of decline phases, and in different decline phases, the change rate of the peak current is different as the switching cycle changes.

[0016] Optionally, the second change phase is further divided into a plurality of rising phases, and in different rising phases, the change rate of the peak current is different as the switching cycle changes.

[0017] Optionally, the reference signal generating circuit includes:

[0018] A first reference voltage generating circuit, generating a first reference voltage according to a switching cycle of the main power tube;

[0019] A first voltage generating circuit includes a plurality of first capacitors, and controls a charging period of each of the plurality of first capacitors according to the switching cycle to generate a first voltage;

[0020] an operational amplifier, performing operational amplification on the first reference voltage and the first voltage to obtain the reference signal;

[0021] When the switching period is greater than a first threshold and less than a second threshold, the first voltage has a plurality of rising stages, and the change rate of the first voltage is different in each rising stage.

[0022] Optionally, the first reference voltage generating circuit includes a plurality of second capacitors, and controls a charging period of each of the plurality of second capacitors according to the switching cycle to generate the first reference voltage;

[0023] Among them, when the switching period is greater than the first threshold and less than the third threshold, the reference voltage has multiple rising stages, and the change rate of the first reference voltage is different in each rising stage; when the switching period is greater than the third threshold, the first voltage has multiple rising stages, and the change rate of the first voltage is different in each rising stage.

[0024] Optionally, a clamping circuit is included to receive the reference signal, and when the reference signal is greater than a maximum reference voltage, the reference signal is clamped at the maximum reference voltage; when the reference signal is less than a minimum reference voltage, the reference signal is clamped at the minimum reference voltage.

[0025] The present invention also provides a flyback converter, comprising a main power tube, a rectifier tube and a transformer, wherein the main power tube is connected to the primary winding of the transformer, the rectifier tube is connected to the secondary winding of the transformer, and further comprising:

[0026] A primary side controller, connected to the control end of the main power tube, used to control the switch state of the main power tube, including any one of the peak current control circuits described above;

[0027] The secondary side controller is connected to the control end of the rectifier tube and is used to control the switching state of the rectifier tube.

[0028] Compared with the prior art, the utility model has the following advantages: when the switching cycle is greater than the first threshold cycle and less than the second threshold cycle, the utility model can flexibly adjust the peak current on the main power tube, so that the peak current increases or decreases with the increase of the switching cycle to meet the application requirements; when the input frequency is low, the peak current can be increased to make the system meet the output power requirements; when the input and output frequency are high, the utilization rate of the transformer core can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a conventional flyback converter schematic;

[0030] Figure 2 A graph showing a reference signal of an existing primary inductor current and a switching period / switching frequency;

[0031] Figure 3 is a control waveform diagram of an existing flyback converter;

[0032] Figure 4 A graph showing the first reference signal and the switching period / switching frequency of the utility model;

[0033] Figure 5 Based on Figure 4 The obtained peak current control circuit schematic of the flyback converter;

[0034] Figure 6 For Figure 5 The peak current control circuit schematic diagram of the flyback converter obtained by further expansion;

[0035] Figure 7 A curve diagram of a reference signal of a second primary inductor current and a switching period / switching frequency of the utility model;

[0036] Figure 8 according to Figure 7 The obtained peak current control circuit schematic of the flyback converter;

[0037] Fig. 9 A curve diagram of a reference signal of a primary inductor current and a switching period / switching frequency of the third type of the utility model;

[0038] Fig.10 Based on Fig. 9 The obtained peak current control circuit schematic of the flyback converter. DETAILED DESCRIPTION

[0039] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitution, modification, equivalent method and scheme made on the spirit and change stage of the present invention.

[0040] In order to enable the public to have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, and those skilled in the art can fully understand the present invention without these detailed descriptions.

[0041] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the accompanying drawings are all simplified and in non-precise proportions to facilitate and clearly illustrate the purpose of the embodiments of the present invention.

[0042] like Figure 1As shown in the figure, a schematic diagram of a conventional flyback converter is illustrated, including a transformer T1, a main power transistor Q1, a rectifier diode Q2, a primary controller 01, and a secondary controller 02. The main power transistor Q1 is connected to the primary winding Np of the transformer T1, and the rectifier diode Q2 is connected to the secondary winding Ns of the transformer T1. The primary controller 01 receives the current sampling signal VCS on the main power transistor Q1 and communicates with the secondary side through the transformer T1 or other isolation devices (such as opto-isolation, capacitor isolation, etc.) to control the switching state of the main power transistor Q1. The secondary controller 02 is used to control the switching state of the rectifier diode Q2 according to the node voltage Vsw and the output voltage Vout. The AC input voltage VAC is rectified to obtain the input voltage Vin, and the flyback converter converts the input voltage Vin into the output voltage Vout by controlling the switching states of the main power transistor Q1 and the rectifier diode Q2. The present invention designs a control strategy for controlling the peak current on the main power transistor Q1 of the flyback converter. Specifically, a reference signal VREF for the current on the main power transistor is designed according to the switching period Tsw. When the current sampling signal VCS reaches the reference signal VREF, the main power transistor Q1 is controlled to turn off. The design of the reference signal VREF is described and explained below.

[0043] As Figure 4 shown, a graph of the first reference signal of the present invention versus the switching period / switching frequency is illustrated. Figure 4 (a) is the relationship curve between the reference signal VCS_REF and the switching period Tsw. Figure 4 (b) is the relationship curve between the reference signal and the corresponding switching frequency fsw (1 / Tsw). Taking Figure 4 (a) as an example for explanation, when Tsw < T1, the reference signal VCS_REF is set at the maximum value VCS_MAX; when Tsw > T2, the reference signal VCS_REF is set at the minimum value VCS_MIN; when T1 < Tsw < T2, it generally corresponds to a load between light load and heavy load. The reference signal VCS_REF has two changing stages with the switching period Tsw, corresponding to the two stages of T1 - T3 and T3 - T2. The changing rates of the reference signal VCS_REF in different stages with the switching period Tsw are different. In the T1 - T3 stage, the reference signal VCS_REF is set to decrease slowly with the increase of the switching period Tsw, corresponding to a changing rate of the reference signal VCS_REF less than the first changing rate. In the T3 - T2 stage, the reference signal VCS_REF is set to decrease rapidly with the increase of the switching period, corresponding to a changing rate of the reference signal VCS_REF greater than the first changing rate.

[0044] As Figure 5 shown, it illustrates according to Figure 4The obtained peak current control circuit schematic of the flyback converter includes a reference signal generating circuit 01, a comparator 02, and a drive circuit 03. The reference signal generating circuit 01 is used to generate a reference signal VCS_REF of the current of the main power tube Q1 according to the switching cycle Tsw. The comparator 02 compares the reference signal VCS_REF with the current sampling signal VCS representing the current of the main power tube Q1 to generate a control signal Vtr. The control signal Vtr generates a drive signal DRV to control the turn-off moment of the main power tube Q1 through the drive circuit 03. When the current sampling signal VCS reaches the reference signal VCS_REF, the control signal Vtr controls the main power tube Q1 to turn off. The reference signal generated by the reference signal generating circuit 01 is as follows: Figure 4 As shown, the reference signal generating circuit 01 specifically includes a first reference voltage generating circuit 101, a first voltage generating circuit 102, an error amplifier 103 and a clamping circuit 104. The first reference voltage generating circuit 101 sets a first reference voltage VREF1 according to a switching period Tsw, the first voltage generating circuit 102 generates a first voltage VC1 according to the switching period Tsw, and the operational amplifier 103 performs error amplification on the first reference voltage VREF1 and the first voltage VC1 to generate a reference signal VCS_REF; the clamping circuit 104 is connected to the output end of the operational amplifier 103, and is used to set the reference signal VCS_REF at the maximum reference voltage VCS_max when the reference signal VCS_REF output by the operational amplifier 103 is greater than the set maximum reference voltage VCS_max, and is used to set the reference signal VCS_REF at the minimum reference voltage VCS_min when the reference signal VCS_REF output by the operational amplifier 103 is less than the set minimum reference voltage VCS_min.

[0045] Among them, the first voltage generation circuit 102 includes a reference current source Iref, a switch S0, a switch S1, two first capacitors C0 and C1, and a switch signal generation circuit 1021. The switch S0 and the capacitor C0 are connected in parallel. The switch S1 and the capacitor C1 are connected in series and then connected in parallel with the capacitor C0. The reference current source Iref is used to charge the capacitors C0 and C1. The switch signal generation circuit 1021 is used to generate switch control signals tr0 and tr1 according to the switch period Tsw to control the on-off states of the switches S0 and S1 respectively, and further control the charging time periods of the capacitors C0 and C1. Specifically, when Tsw < T1, the switch control signals tr0 and tr1 control the switch S0 to turn on and the switch S1 to turn off respectively. The first voltage VC1 is zero, and the reference signal VCS_REF is set at the maximum reference voltage VCS_max. When T1 < Tsw < T3, the switch control signals tr0 and tr1 control the switches S0 and S1 to turn off respectively. The reference current source Iref charges the capacitor C0, and the generated first voltage VC1 rises at a first rate of change, and the reference signal VCS_REF drops at a corresponding rate of change. When Tsw > T3, the switch control signals tr0 and tr1 control the switch S0 to turn off and the switch S1 to turn on respectively. The reference current source Iref charges the capacitors C0 and C1 simultaneously, and the generated first voltage VC1 rises at a second rate of change, and the reference signal VCS_REF drops at a corresponding other rate of change. When Tsw > T2, the generated first voltage VC1 continues to rise, and the obtained reference signal VCS_REF is clamped at the minimum reference voltage VCS_min. In the medium and high frequency stage when T1 < Tsw < T3, by controlling the relatively small rate of change of the first voltage VC1, the reference signal VCS_REF is made close to the maximum reference voltage VCS_max to meet the output power requirement. As the switch period Tsw further increases, in the medium and low frequency stage when Tsw > T3, by controlling the relatively large rate of change of the first voltage VC1, the reference signal VCS_REF is made to drop rapidly, so that the reference signal VCS_REF quickly approaches the minimum reference voltage VCS_min to meet the power consumption and output power requirements.

[0046] As Figure 6 shown, it schematically shows the peak current control circuit schematic diagram of the flyback converter further expanded from Figure 5 which. The same parts as Figure 5 will not be elaborated again. The same as Figure 5The differences are as follows: The first voltage generation circuit 102 includes a plurality of first capacitors C0, C1, C2, C3,......, Cn and corresponding switches S0, S1, S2, S3,......, Sn, where n is an integer greater than or equal to 1. As shown in the figure, each switch is connected to a corresponding capacitor. When Tsw < T1, switch S0 is turned on and the first voltage VC1 is zero; when Tsw > T1, switch S0 is turned off and capacitor C0 is charged. At the same time, according to application requirements, switches S1, S2, S3,......, Sn can be sequentially turned on in stages. That is, as the switching period Tsw increases, the number of turned-on switches increases sequentially in stages, and the number of charged capacitors increases sequentially. The reference current source Iref charges capacitors C0, C1, C2, C3,......, Cn sequentially in stages to obtain a first voltage VC1 that increases sequentially in stages. The change rate of the first voltage VC1 in each stage is different, and the finally obtained reference signal VCS_REF also changes sequentially in multiple stages, and the change rate in each stage is also different. As the switching period Tsw increases, when the reference signal VCS_REF drops to the minimum reference voltage VCS_min, the reference signal VCS_REF is clamped at the minimum reference voltage VCS_min. In this embodiment, it can be assumed that the capacitance values of the capacitors are equal. After Tsw > T1, as the switching period Tsw increases, the number of charged capacitors increases stage by stage, and the change rate of the first voltage VC1 gradually decreases; however, in other embodiments, the capacitance values can also be set to be different, and a capacitor can be charged sequentially in stages so that the change rates of the first voltage VC1 and the corresponding reference signal VCS_REF in different stages are different; optionally, the change rates of the first voltage VC1 and the corresponding reference signal VCS_REF can be set to increase, decrease, or remain unchanged in a certain intermediate stage. The present invention can flexibly adjust the peak current on the main power transistor Q1 according to application requirements so that the output power can meet the requirements at different frequency stages.

[0047] As Figure 7 shown, it schematically shows the curve diagram of the reference signal of the second primary-side inductor current and the switching period / switching frequency of the present utility model. Figure 7 (a) is the relationship curve between the reference signal VCS_REF and the switching period Tsw. Figure 7 (b) is the relationship curve between the reference signal and the corresponding switching frequency fsw (1 / Tsw). Figure 7Taking (a) as an example, when the switching period Tsw < T1, the reference signal VCS_REF is set to a certain value less than the maximum value VCS_MAX; when the switching period Tsw > T2, the reference signal VCS_REF is set to the minimum value VCS_MIN; when T1 < Tsw < T2, it generally corresponds to the load being between light load and heavy load. The reference signal VCS_REF has two change stages with the switching period Tsw, corresponding to the two stages of T1 - T3 and T3 - T2. The change rate of the reference signal VCS_REF with the switching period Tsw is different in different stages. In the T1 - T3 stage, the reference signal VCS_REF is set to increase with the increase of the switching period Tsw, and in the T3 - T2 stage, the reference signal VCS_REF is set to gradually decrease with the increase of the switching period Tsw. In this embodiment, under the rated load in the T1 - T3 stage, as the switching frequency decreases, the reference signal VCS_REF can be increased to meet the output requirements. This embodiment is different from Figure 4 the illustrated embodiment in that in Figure 7 the T1 - T3 stage of (a), the reference signal VCS_REF can increase with the increase of the switching period Tsw; according to Figure 4 and Figure 7 it can be seen that the present invention can flexibly adjust the relationship between the reference signal VCS_REF and the switching period Tsw according to requirements to meet the output requirements, that is, during T1 < Tsw < T2, according to the application requirements, the reference signal VCS_REF can be flexibly adjusted in stages, which can make the change rate of the reference signal VCS_REF different in different stages and also make the change trend of the reference signal VCS_REF different.

[0048] As Figure 8 shown, it illustrates the schematic diagram of the peak current control circuit of the flyback converter obtained according to Figure 7 This schematic diagram is the same as Figure 5The same parts are not repeated here. In the schematic diagram, the reference signal generating circuit 01 includes a first reference voltage generating circuit 101, a first voltage generating circuit 102, a switching signal generating circuit 105, an operational amplifier 103 and a clamping circuit 104. The first reference voltage generating circuit 101 sets a first reference voltage VREF1 according to a switching period Tsw, the first voltage generating circuit 102 generates a first voltage VC1 according to a switching period Tsw, and the operational amplifier 103 performs error amplification on the first reference voltage VREF1 and the first voltage VC1 to generate a reference signal VCS_REF; the clamping circuit 104 is connected to the output end of the operational amplifier 103, and is used to set the reference signal VCS_REF at the maximum reference voltage VCS_max when the reference signal VCS_REF output by the operational amplifier 103 is greater than the set maximum reference voltage VCS_max, and is used to set the reference signal VCS_REF at the minimum reference voltage VCS_min when the reference signal VCS_REF output by the operational amplifier 103 is less than the set minimum reference voltage VCS_min. Wherein,

[0049] The first reference voltage generation circuit 101 includes a preset current source Iset, a second capacitor CV1, a switch SV1, a switch SV0, an operational amplifier 1011, and a preset voltage source Vset. The preset current source Iset, the second capacitor CV1, and the switch SV1 are connected in series and then grounded. The non-inverting input terminal of the operational amplifier 1011 is connected to the high potential terminal of the capacitor CV1, and the inverting input terminal is grounded. The switch SV0 is connected to the output terminal of the operational amplifier 1011. The negative terminal of the preset voltage source Vset is connected to the output terminal of the operational amplifier 1011, and the positive terminal outputs the first reference voltage VREF1. The first voltage generation circuit 102 includes a reference current source Iref and a switch S0 and a first capacitor C0 connected in parallel. The reference current source Iref is used to charge the capacitor C0. The switch signal generation circuit 105 is used to generate switch control signals tp0, tp1, and tr0 to control the switch states of the switches SV0, SV1, and S0 respectively. Specifically, when Tsw < T1, the switch control signals tp0, tp1, and tr0 control the switch SV0 to turn on, the switch SV1 to turn off, and the switch S0 to turn on respectively. The output voltage of the preset voltage source Vset is the first reference voltage VREF1 generated by the first reference voltage generation circuit 101. The first voltage VC1 generated by the first voltage generation circuit 102 is zero, and the reference signal VCS_REF maintains a value corresponding to VREF1. When T1 < Tsw < T3, the switch control signals tp0, tp1, and tr0 control the switch SV0 to turn off, the switch SV1 to turn on, and the switch S0 to turn on respectively. The preset current source Iset charges the capacitor CV1, and the voltage VS1 generated on the capacitor CV1 rises at a certain rate of change. The first reference voltage VREF1 is obtained based on the difference between the reference voltage source Vset and the voltage VS1 on the capacitor CV1, and the first reference voltage VREF1 rises at a corresponding rate of change. The first voltage VC1 continues to be zero, and the reference signal VCS_REF also rises at a corresponding rate of change. When Tsw > T3, the switch control signals tp0, tp1, and tr0 control the switch SV0 to turn off, the switch SV1 to turn off, and the switch S0 to turn off respectively. The reference current source Iref charges the capacitor C0, and the generated first voltage VC1 rises at a certain rate of change. The reference signal VCS_REF drops at a corresponding rate of change. When Tsw > T2, the generated first voltage VC1 continues to rise, and the obtained reference signal VCS_REF is clamped at the minimum reference voltage VCS_min.

[0050] As Fig. 9 shown, it schematically shows the curve graph of the reference signal of the primary inductor current and the switching period / switching frequency of the third embodiment of the present invention. The same parts as Figure 7 are not described again. For Fig. 9Taking (a) as an example, when the switching period Tsw satisfies T1 < Tsw < T2, the reference signal VCS_REF is divided into multiple changing stages, including multiple rising stages and multiple falling stages respectively. Specifically, in the T1 - T3 stage, the switching period Tsw is divided into multiple stages. Correspondingly, the reference signal VCS_REF has multiple rising stages with different changing rates. For example, in the period from T1 to Td1, the reference signal VCS_REF rises at the first changing rate; in the period from Td1 to Td2, the reference signal VCS_REF rises at the second changing rate; there are also multiple similar rising stages of the reference signal VCS_REF between Td2 and T3. In the T3 - T2 stage, the switching period Tsw is divided into multiple stages. Correspondingly, the reference signal VCS_REF has multiple falling stages with different changing rates. For example, in the period from T3 to Ts1, the reference signal VCS_REF falls at the first changing rate; in the period from Ts1 to Ts2, the reference signal VCS_REF rises at the second changing rate; there are also multiple similar rising stages of the reference signal VCS_REF between Ts2 and T2. The number of the multiple rising stages and multiple falling stages set for the reference signal VCS_REF of the present invention is not limited and can be flexibly set according to application requirements.

[0051] As Fig.10 shown, it is the schematic diagram of the peak current control circuit of the flyback converter obtained according to Fig. 9 . Referring to the schematic diagram set in Figure 8 , the same parts will not be described again. On the basis of Figure 8 , the first reference voltage generation circuit 101 and the first voltage generation circuit 102 are further expanded respectively. The first reference voltage generation circuit 101 includes n (n is an integer greater than or equal to 1) second capacitors CV1, CV2,..., CVn, and the corresponding n switches SV1, SV2,..., SVn, which are respectively connected in series with the corresponding capacitors to form n series circuits, and each series circuit is connected in parallel. The first voltage generation circuit 102 refers to Figure 6Description of the first voltage generation circuit 102. When the switching period Tsw is greater than T1, the n switching control signals tp1, tp2, ..., tpn generated by the switching signal generation circuit 105 according to the switching period Tsw can control the n switches SV1, SV2, ..., SVn to turn on in sequence, so as to control the number of charging capacitors to increase in sequence, and further make the first reference voltage VREF1 have n rising stages with different change rates, and the reference signal VCS_REF have n rising stages with different change rates. When the switching period Tsw is greater than T2, the switching control signal tr0 generated by the switching signal generation circuit 105 according to the switching period Tsw controls the switch S0 to remain off, and at the same time generates n switching control signals tr1, tr2, ..., trn to control the n switches S1, S2, ..., Sn to turn on in sequence, so as to control the number of charging capacitors in the first voltage generation circuit 102 to increase in sequence, and further make the first voltage VC1 have n rising stages with different change rates, and the reference signal VCS_REF have n rising stages with different change rates. In this embodiment, the number of capacitors in the first reference voltage generation circuit 101 and the first voltage generation circuit 102 can be set as needed, or the number of charging capacitors can be controlled as needed to control the number of change stages of the reference signal VCS_REF, or the capacitance values of each capacitor can be set as needed to set the change rate of the change stages of the reference signal VCS_REF.

[0052] According to the above introduction, when the switching period Tsw satisfies T1 < Tsw < T2, the reference signal VCS_REF can be divided into several change stages according to the total number of capacitors charged in the first reference voltage generation circuit 101 and the first voltage generation circuit 102. For example Figure 5 In [example], there are 2 capacitors C0 and C1 in the first voltage generation circuit 102, and the reference signal VCS_REF has 2 falling stages (T1 - T3, T3 - T2). Figure 8 In [example], there are 2 capacitors C0 and CV1 in the first reference voltage generation circuit 101 and the first voltage generation circuit 102, and the reference signal VCS_REF has 2 transformation stages, namely 1 rising stage (T1 - T3) and 1 falling stage (T3 - T2). However, the present invention is not limited to the adjustment method of the reference signal VCS_REF introduced above, and the present invention is also not limited to the capacitance values of each capacitor, nor to the way of charging each capacitor combination (for example, only one capacitor is charged in each change stage of the reference signal VCS_REF, but the sizes of each capacitor are different). In practical applications, it can be flexibly adjusted according to requirements.

[0053] Although the embodiments are described and illustrated separately above, some common technologies are involved. It is the opinion of ordinary technicians in this field that the embodiments can be replaced and integrated. If the content is not clearly recorded in one of the embodiments, reference can be made to another recorded embodiment.

[0054] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A peak current control circuit of a flyback converter, the flyback converter comprising a main power tube, a rectifier tube and a transformer, the main power tube is connected to the primary winding of the transformer, the rectifier tube is connected to the secondary winding of the transformer, characterized in that: include, A reference signal generating circuit, comprising a plurality of capacitors, controlling a charging period of each of the plurality of capacitors according to a switching cycle to obtain a reference signal; A comparator, which compares the reference signal with a current sampling signal representing the current of the main power tube to control the shutdown moment of the main power tube; When the switching period is greater than a first threshold and less than a second threshold, the reference signal has at least two change phases, and the switching period in the first change phase is greater than the switching period in the second change phase.

2. The peak current control circuit according to claim 1, characterized in that: In different change phases, the change rate of the reference signal is different.

3. The peak current control circuit according to claim 2, characterized in that: In the first change phase, the reference signal decreases as the switching period increases.

4. The peak current control circuit according to claim 2, characterized in that: In the first change phase, the reference signal increases as the switching period increases.

5. The peak current control circuit according to claim 2, characterized in that: In the second change phase, the reference signal decreases as the switching period increases.

6. The peak current control circuit according to claim 3, characterized in that: The first change phase is further divided into a plurality of decline phases. In different decline phases, the change rate of the peak current is different as the switching cycle changes.

7. The peak current control circuit according to claim 4, characterized in that: The second change phase is further divided into a plurality of rising phases. In different rising phases, the change rate of the peak current is different as the switching cycle changes.

8. The peak current control circuit according to claim 2, characterized in that: The reference signal generating circuit comprises: A first reference voltage generating circuit, generating a first reference voltage according to a switching cycle of the main power tube; A first voltage generating circuit, comprising a plurality of first capacitors, controlling a charging period of each of the plurality of first capacitors according to the switching cycle to generate a first voltage; an operational amplifier, performing operational amplification on the first reference voltage and the first voltage to obtain the reference signal; When the switching period is greater than a first threshold and less than a second threshold, the first voltage has a plurality of rising stages, and the change rate of the first voltage is different in each rising stage.

9. The peak current control circuit according to claim 8, characterized in that: The first reference voltage generating circuit comprises a plurality of second capacitors, and the charging period of each of the plurality of second capacitors is controlled according to the switching cycle to generate the first reference voltage; Among them, when the switching period is greater than the first threshold and less than the third threshold, the reference voltage has multiple rising stages, and the change rate of the first reference voltage is different in each rising stage; when the switching period is greater than the third threshold, the first voltage has multiple rising stages, and the change rate of the first voltage is different in each rising stage.

10. The peak current control circuit according to claim 2, characterized in that: Also includes a clamping circuit, receiving the reference signal, and when the reference signal is greater than the maximum reference voltage, clamping the reference signal at the maximum reference voltage; When the reference signal is less than a minimum reference voltage, the reference signal is clamped at the minimum reference voltage.

11. A flyback converter, comprising a main power tube, a rectifier tube and a transformer, wherein the main power tube is connected to a primary winding of the transformer, the rectifier tube is connected to a secondary winding of the transformer, and further comprising: A primary side controller, connected to the control end of the main power tube, used to control the switch state of the main power tube, comprising the peak current control circuit according to any one of claims 1 to 10; The secondary side controller is connected to the control end of the rectifier tube and is used to control the switching state of the rectifier tube.

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