Quantum chip test circuit, layout structure, quantum chip and quantum computer
By introducing signal reflection ports and directional couplers into the quantum chip test line, combined with vector network analyzer, the problem of sharp increase in the number of ports in the existing technology is solved, the effect of reducing the number of ports is achieved, and the difficulty of chip layout is reduced.
Patent Information
- Application Number
- CN202420358006.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-27
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-02-27
AI Technical Summary
When the number of qubits of existing superconducting quantum chips increases, the number of ports required increases sharply, resulting in huge pressure on chip design and layout, making it difficult to effectively reduce the number of ports.
By introducing signal reflection ports into the quantum chip test line, combining directional couplers and vector network analyzers, one end of the read bus provides signal transmission and reflection functions, reducing the number of external connection ports.
During the quantum chip testing process, this solution only needs to use one port of the read bus, which significantly reduces the number of ports required during the measurement process and reduces the difficulty of layout of superconducting quantum chips.
Smart Images
Figure CN222483381U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of quantum chips, in particular to a quantum chip test circuit, a layout structure, a quantum chip and a quantum computer. Background Art
[0002] The current test circuit of superconducting quantum chips is basically: one bit is configured with an X control line, a Z control line, and a read resonant cavity, and multiple read resonant cavities are inductively coupled or capacitively coupled to the same read bus. Each read bus is equipped with two ports, corresponding to the signal input end and the signal output end respectively.
[0003] As the number of quantum bits increases, the number of control lines and read buses for quantum bits gradually increases, and the corresponding number of external connection ports also increases dramatically. Under limited chip processing and packaging processing conditions, the design and layout of quantum chips are under tremendous pressure.
[0004] Therefore, reducing the number of ports required for quantum chip testing is an urgent problem to be solved. Utility Model Content
[0005] The purpose of the utility model is to provide a quantum chip test circuit, a layout structure, a quantum chip and a quantum computer to solve the deficiencies in the prior art, and it can reduce the number of ports required in quantum chip testing.
[0006] The solution of this application example is implemented through the following contents.
[0007] In a first aspect, an example of the present application proposes a quantum chip test circuit, comprising a read bus and a quantum processor connected by coupling, wherein the read bus comprises a signal transmission port provided by one end and a signal reflection port provided by the other end;
[0008] The signal transmission port is used to input a read input signal for performing a read operation on a quantum bit unit in the quantum processor;
[0009] The signal reflection port is used to reflect the read output signal fed back by the quantum bit unit in the quantum processor to the signal transmission port, and the signal transmission port is also used to output the read output signal.
[0010] According to some examples of the present application, the signal reflection port is open to ground.
[0011] According to some examples of the present application, the signal reflection port is short-circuited to ground.
[0012] According to some examples of the present application, the quantum chip test circuit further includes:
[0013] A directional coupler having an input port, a through port, a coupled port, and an isolated port;
[0014] The input port is used to input the read input signal;
[0015] The through port is used to output the read output signal;
[0016] The coupling port is connected to the signal transmission port and is used to input the read input signal input from the input port to the signal transmission port. The coupling port is also used to transmit the read output signal output from the signal transmission port to the through port.
[0017] According to some examples of the present application, the quantum chip test circuit further includes a vector network analyzer;
[0018] The vector network analyzer comprises:
[0019] An output end, connected to the signal transmission port, for generating the read input signal;
[0020] The input end is connected to the signal transmission port and is used to obtain the test result according to the read output signal.
[0021] According to some examples of the present application, the quantum processor includes a plurality of the qubit units, each of the qubit units includes a qubit and a resonant cavity coupled thereto, and each of the qubits is coupled to the read bus via the resonant cavity.
[0022] According to some examples of the present application, the coupling mode between the read bus and the quantum processor is capacitive coupling or inductive coupling.
[0023] In a second aspect, the examples of the present application propose a layout structure including the quantum chip test circuit described in the first aspect.
[0024] In a third aspect, an example of the present application proposes a quantum chip, comprising: the quantum chip test circuit described in the first aspect, wherein the quantum chip test circuit is made using the layout structure described in the second aspect.
[0025] In a fourth aspect, an example of the present application proposes a quantum computer, comprising the quantum chip described in the third aspect.
[0026] In the quantum chip test circuit of the aforementioned example in the present application, the signal transmission port provided at one end of the read bus can realize two functions: reading input signals to the quantum bit unit of the quantum processor and reading output signals fed back by the output quantum bit unit. Therefore, in the process of measuring the quantum chip, for each read bus, only one port of the read bus needs to be used, which greatly reduces the number of ports required in the measurement process and reduces the difficulty of superconducting quantum chip layout.
[0027] A layout structure, a quantum chip and a quantum computer provided by the utility model have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] For a clearer explanation, the following briefly introduces the drawings required for the description.
[0029] Figure 1 This is a block diagram of the quantum chip test circuit structure in an example of this application;
[0030] Figure 2 This is a block diagram of the quantum chip test circuit structure in another example of this application;
[0031] Figure 3 This is a transmission curve diagram of the output signal of the quantum bit test circuit in an example of this application.
[0032] Reference numerals:
[0033] Read bus 100; signal transmission port 110; signal reflection port 120; quantum processor 200; quantum bit unit 210; quantum bit 211; resonant cavity 212; directional coupler 300; input port 310; through port 320; coupling port 330; isolation port 340. DETAILED DESCRIPTION
[0034] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limitations on the present application.
[0035] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.
[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0037] In the prior art, the quantum state of a qubit in a superconducting quantum chip is usually inferred by measuring the state of a resonant cavity coupled to the qubit. As long as there is a suitable coupling strength between the (read) resonant cavity and the corresponding qubit, the quantum state of the qubit can be read in engineering by detecting (reading) the operating frequency of the resonant cavity.
[0038] The current test circuit of the superconducting quantum chip is basically: one bit is configured with an X control line, a Z control line, and a read resonant cavity, and multiple read resonant cavities are inductively coupled or capacitively coupled to the same read bus. Each read bus is provided with two ports, corresponding to the signal input end and the signal output end respectively. In the superconducting quantum chip test process, for each read bus, the test signal is input to the signal input end of the read bus. When the frequency of the test signal is the same as the operating frequency of the resonant cavity coupled to the read bus, the test signal will be coupled into the resonant cavity to produce resonance, resulting in insertion loss, and cannot be transmitted to the signal output end. When the frequency of the test signal is different from the operating frequency of the resonant cavity coupled to the read bus, the test signal cannot be coupled into the resonant cavity and will be transmitted to the signal output end. The signal strength at the signal output end is detected to determine the test signal frequency corresponding to the insertion loss, and the operating frequency of the resonant cavity can be determined, and then the quantum state of the quantum bit is read. Therefore, in the existing test technology, for each read bus, two ports, namely the signal input end and the signal output end, are required. As the number of qubits increases, the number of qubit read buses gradually increases, and the corresponding number of external connection ports also increases dramatically. Under limited chip processing and packaging processing conditions, the design and layout of quantum chips are under tremendous pressure.
[0039] Based on this, Figure 1As shown, in one embodiment of the utility model, a quantum chip test circuit is provided, including a read bus 100 and a quantum processor 200 connected by coupling, the read bus 100 includes a signal transmission port 110 provided by one end and a signal reflection port 120 provided by the other end; the signal transmission port 110 is used to input a read input signal for performing a read operation on a quantum bit unit 210 in the quantum processor 200; the signal reflection port 120 is used to reflect the read output signal fed back by the quantum bit unit 210 in the quantum processor 200 to the signal transmission port 110, and the signal transmission port 110 is also used to output the read output signal.
[0040] Among them, the read input signal is a frequency sweep signal. The quantum bits in the quantum processor 200 need to receive XY signals and Z signals to enter the working state. Therefore, the quantum processor 200 also needs to be coupled with the XY control line and the Z control line, or the XYZ control line. The present application does not specifically limit the type of XY signal and Z signal control line coupled to the quantum processor, which can be selected according to actual needs. The quantum processor may include only one quantum bit unit or multiple quantum bit units, which is not specifically limited in the present application.
[0041] Specifically, the read input signal enters the read bus 100 from the signal transmission port 110. When the frequency of the read input signal is the same as the operating frequency of the resonant cavity coupled to the read bus 100, the read input signal will be coupled into the resonant cavity to produce resonance and insertion loss. At this time, the read output signal intensity transmitted to the signal reflection port 120 is low; when the frequency of the read input signal is different from the operating frequency of the resonant cavity coupled to the read bus 100, the read input signal cannot be coupled into the resonant cavity. At this time, the read output signal intensity transmitted to the signal reflection port 120 is high. The signal reflection port 120 reflects all the received read output signals to the signal transmission port 110. Therefore, it is only necessary to detect the read output signal intensity curve information received by the signal reflection port 120 to determine the operating frequency of the resonant cavity, and then determine the quantum state of the quantum bit.
[0042] In the quantum chip test circuit provided by the present application, the signal reflection port 120 is set so that the signal transmission port 110 has the functions of inputting the read input signal and outputting the read output signal fed back by the quantum bit unit 210. Then, in the process of testing the quantum chip, only one of the ports is used for each read bus 100. Compared with the prior art, for each read bus 100, two ports of the read bus 100 are required. The quantum chip test circuit provided by the present application greatly reduces the number of ports required in the measurement process, reduces the difficulty of layout of the superconducting quantum chip, and can be applied to quantum chips with a large number of quantum bits.
[0043] In one embodiment of the present application, the signal reflection port 120 of the read bus 100 is open to the ground.
[0044] In one embodiment of the present application, the signal reflection port 120 of the read bus 100 is short-circuited to the ground.
[0045] Specifically, when the read output signal fed back by the qubit unit 210 is transmitted to the signal reflection port 120 on the read bus 100, it will be completely reflected to the signal transmission port 110. Since in a lossless transmission line, when the terminal is short-circuited or open-circuited, the electromagnetic wave reaching the terminal of the transmission line cannot be absorbed and will be completely reflected out, therefore, in the embodiment of the present application, the signal reflection port 120 is set to be open-circuited or short-circuited to the ground, so as to achieve the effect of reflecting all the read output signals to the signal transmission port 110, so as to ensure that the signal transmission port 110 has the functions of inputting the read input signal and outputting the read output signal fed back by the qubit unit 210.
[0046] In one embodiment of the present application, Figure 2 As shown, the quantum chip test circuit also includes:
[0047] Directional coupler 300 having an input port 310, a through port 320, a coupled port 330 and an isolated port 340;
[0048] The input port 310 is used to input a read input signal;
[0049] The through port 320 is used to output the read output signal;
[0050] The coupling port 330 is connected to the signal transmission port 110 and is used to input the read input signal input from the input port 310 to the signal transmission port 110 . The coupling port 330 is also used to transmit the read output signal output from the signal transmission port 110 to the through port 320 .
[0051] The isolation port 340 is also connected to a resistor with a preset resistance value, and the preset resistance value may be 50Ω.
[0052] Specifically, the read input signal is input to the directional coupler 300 from the input port 310 of the directional coupler 300, and then input to the signal transmission port 110 of the read bus 100 from the coupling port 330 of the directional coupler 300. In the above transmission process, according to the characteristics of the directional coupler 300, when the read input signal is transmitted to the signal transmission port 110, it is equivalent to passing through an attenuator, which can attenuate the thermal noise of the upper temperature layer of the refrigerator.
[0053] In one embodiment of the present application, the input port 310 of the directional coupler 300 is used to input a read input signal; the through port 320 is used to output a read output signal; the isolation port 340 is connected to the signal transmission port 110, and is used to input the read input signal input by the input port 310 to the signal transmission port 110, and the isolation port 340 is also used to transmit the read output signal output by the signal transmission port 110 to the through port 320.
[0054] Specifically, it is only necessary to determine that the input port 310 of the directional coupler 300 inputs the read input signal and the through port 320 outputs the read output signal, and the isolation port 340 or the coupling port 330 can be optionally connected to the signal transmission port 110 of the read bus 100. Similar to the connection between the coupling port 330 and the signal transmission port 110, after the read input signal is input from the input port 310 to the directional coupler 300, it is then input from the isolation port 340 of the directional coupler 300 to the signal transmission port 110 of the read bus 100. According to the characteristics of the directional coupler 300, when the read input signal is transmitted to the signal transmission port 110, it is equivalent to passing through an attenuator, which can attenuate the thermal noise of the upper temperature layer of the refrigerator.
[0055] In one embodiment of the present application, the quantum chip test circuit further includes a vector network analyzer;
[0056] Vector Network Analyzer includes:
[0057] An output terminal connected to the signal transmission port 110 and used to generate a read input signal;
[0058] The input end is connected to the signal transmission port 110 and is used to obtain the test result according to the read output signal.
[0059] Furthermore, the vector network analyzer can also be connected to the directional coupler 300: the output end of the vector network analyzer is connected to the input port 310 of the directional coupler 300, for generating a read input signal, and inputting the read input signal into the directional coupler 300; the input end of the vector network analyzer is connected to the through port 320 of the directional coupler 300, for receiving the read output signal fed back by the quantum bit unit 210, and obtaining the test result according to the read output signal.
[0060] Based on the above-mentioned embodiment of the quantum chip test circuit, the working principle of the quantum chip test circuit is as follows: the quantum chip test circuit obtains a test signal (i.e., a read input signal) from the signal transmission port 110 of the read bus 100. When the test signal is transmitted to the resonant cavity 212 of the quantum bit unit 210 coupled to the read bus 100, if the frequency of the test signal is the same as the operating frequency of the resonant cavity 212 at this time, the test signal will be coupled into the resonant cavity 212 to form resonance, and the insertion loss is large, and the signal transmitted to the signal reflection port 120 (i.e., the read output signal) has a low intensity; if the frequency of the test signal is different from the operating frequency of the resonant cavity 212, the test signal will not be able to enter the resonant cavity 212, and the signal transmitted to the signal reflection port 120 (i.e., the read output signal) has a high intensity. Based on this, the operating frequency corresponding to the resonant cavity 212 can be determined by the read output signal curve graph output by the signal transmission port 110, so as to determine the quantum state of the quantum bit 211 according to the operating frequency of the resonant cavity 212. In one embodiment of the present application, the curve graph of the read output signal output by the signal transmission port 110 is as follows: Figure 3 As shown, the horizontal axis represents the frequency of the read output signal, the vertical axis represents the intensity of the read output signal, and the frequencies corresponding to the six troughs represent the operating frequencies of the six resonant cavities 212. Based on the quantum chip test circuit described in the present application, for each read bus 100, only one port is needed, which effectively reduces the pressure of chip design layout.
[0061] In one embodiment of the present application, the quantum processor 200 includes a plurality of qubit units 210 , each qubit unit 210 includes a qubit 211 and a resonant cavity 212 coupled thereto, and each qubit 211 is coupled to the read bus 100 via the resonant cavity 212 .
[0062] Specifically, the quantum chip may include multiple read buses 100, and for each read bus 100, there may be multiple qubit units 210 coupled thereto. The qubit 211 in each qubit unit 210 is coupled to the read bus 100 through the resonant cavity 212 coupled thereto.
[0063] In one embodiment of the present application, the coupling mode between the read bus 100 and the quantum processor 200 is capacitive coupling or inductive coupling.
[0064] It should be noted that the present application does not specifically limit the coupling method between the read bus 100 and the quantum processor 200, and it can be set according to actual needs.
[0065] In one embodiment of the present application, the utility model provides a layout structure including the above-mentioned quantum chip test circuit.
[0066] In one embodiment of the present application, the utility model provides a quantum chip, including: the above-mentioned quantum chip test circuit, wherein the quantum chip test circuit is made using the above-mentioned layout structure.
[0067] In one embodiment of the present application, the utility model provides a quantum computer, including the above-mentioned quantum chip.
[0068] Regarding the technical effects of the layout structure, quantum chip and quantum computer described in the above embodiments, reference can be made to other embodiments of this specification for comparative explanation and no further details will be given here.
[0069] In the description of this specification, the description with reference to the terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.
[0070] The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, may make any equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which shall be deemed as the content of the technical solution of the present invention and still fall within the protection scope of the present invention.
Claims
1. A quantum chip test circuit, characterized in that: comprising a read bus and a quantum processor connected by coupling, the read bus comprising a signal transmission port provided by one end and a signal reflection port provided by the other end; The signal transmission port is used to input a read input signal for performing a read operation on a quantum bit unit in the quantum processor; The signal reflection port is used to reflect the read output signal fed back by the quantum bit unit in the quantum processor to the signal transmission port, and the signal transmission port is also used to output the read output signal.
2. The quantum chip test circuit according to claim 1, characterized in that: The signal reflection port is open to the ground.
3. The quantum chip test circuit according to claim 1, characterized in that: The signal reflection port is short-circuited to ground.
4. The quantum chip test circuit according to claim 1, characterized in that: The quantum chip test circuit also includes: A directional coupler having an input port, a through port, a coupled port, and an isolated port; The input port is used to input the read input signal; The through port is used to output the read output signal; The coupling port is connected to the signal transmission port and is used to input the read input signal input from the input port to the signal transmission port. The coupling port is also used to transmit the read output signal output from the signal transmission port to the through port.
5. The quantum chip test circuit according to claim 1, characterized in that: The quantum chip test circuit also includes a vector network analyzer; The vector network analyzer comprises: An output end, connected to the signal transmission port, for generating the read input signal; The input end is connected to the signal transmission port and is used to obtain the test result according to the read output signal.
6. The quantum chip test circuit according to claim 1, characterized in that: The quantum processor includes a plurality of the quantum bit units, each of the quantum bit units includes a quantum bit and a resonant cavity coupled thereto, and each of the quantum bits is coupled to the read bus via the resonant cavity.
7. The quantum chip test circuit according to claim 1, characterized in that: The coupling mode between the read bus and the quantum processor is capacitive coupling or inductive coupling.
8. A layout structure, characterized in that: include: A quantum chip test circuit as described in any one of claims 1 to 7.
9. A quantum chip, characterized in that: include: The quantum chip test circuit according to any one of claims 1 to 7, wherein the quantum chip test circuit is made using the layout structure according to claim 8.
10. A quantum computer, characterized in that: Comprising the quantum chip as described in claim 9.