Rapid turn-off protection circuit

Abstract

The utility model discloses a rapid turn-off protection circuit which is characterized in that one end of a sixth resistor, a grid electrode of a second MOS tube and a grid electrode of a third MOS tube are all connected with an enabling end, the other end of the sixth resistor and source electrodes of the first MOS tube, the second MOS tube and the third MOS tube are all grounded, the grid electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, and the grid electrode of the third MOS tube is connected with the enabling end. The drain electrode of the first MOS tube is sequentially connected with the first resistor and the second resistor and then connected with the first pin of the first power MOS tube, the first pin of the first power MOS tube is further connected with the first pin of the second power MOS tube, the fourth pin of the first power MOS tube is connected with the fourth pin of the second power MOS tube, the drain electrode of the third MOS tube is connected with the fourth pin of the second power MOS tube through the fifth resistor, and the drain electrode of the third MOS tube is connected with the fourth pin of the second power MOS tube. The base electrode of the first triode is connected between the first resistor and the second resistor, the collector electrode is connected with the fourth pin of the first power MOS tube, and the emitter electrode is connected with the first pin of the first power MOS tube. According to the utility model, the problem that the MOSFET tube is burnt out due to slow turn-off response caused by the influence of the junction capacitance of the MOSFET tube can be effectively solved.

Description

Technical Field

[0001] The utility model relates to the field of circuits, in particular to a fast shut-off protection circuit. Background Art

[0002] With the rapid development of mobile power fast charging technology, its charging power has jumped from the original 5W to the current 240W fast charging. Based on the PD3.1 protocol, the adapter charges the mobile power, and there are more options for charging voltage during communication handshake, such as 28V, 36V, and 48V. Of course, this must be connected to a cable carrying a PD3.1 chip to succeed.

[0003] Nowadays, there are many adapters equipped with PD3.1 protocol on the market. Adapters usually have many output ports. When one of the TYPE-C ports is a high-power output, the adapter will usually downshift when connected to other ports, and the voltage will return to 20V. If the adapter is re-shifted at this time, during the process of re-shifting from 20V to PD3.1 high voltage, due to the inconsistency of PD3.1 protocol processing among various manufacturers, some may directly cause the MOSFET tube inside the mobile power supply to burn out. In order to solve this problem, the utility model proposes a fast shutdown protection circuit. Utility Model Content

[0004] In order to solve the above problems, the purpose of the utility model is to provide a fast shutdown protection circuit, which can effectively solve the problem of slow shutdown response of MOSFET tube due to the influence of its own junction capacitance and thus burn out the MOSFET tube, thereby ensuring the safety of the load circuit.

[0005] Based on this, the utility model provides a fast shutdown protection circuit, the circuit comprising:

[0006] One end of the sixth resistor, the gate of the second MOS tube and the gate of the third MOS tube are all connected to the enable end, the other end of the sixth resistor, the first MOS tube, the second MOS tube and the source of the third MOS tube are all grounded, the gate of the first MOS tube is connected to the drain of the second MOS tube, the drain of the first MOS tube is connected to the first pin of the first power MOS tube after being connected to the first resistor and the second resistor in sequence, the first pin of the first power MOS tube is also connected to the first pin of the second power MOS tube, the fourth pin of the first power MOS tube is connected to the fourth pin of the second power MOS tube, the drain of the second MOS tube is connected to the voltage VDD through the fourth resistor, the drain of the third MOS tube is connected to the fourth pin of the second power MOS tube through the fifth resistor, the base of the first triode is connected between the first resistor and the second resistor, the collector of the first triode is connected to the fourth pin of the first power MOS tube, the emitter of the first triode is connected to the first pin of the first power MOS tube, and the third resistor is also connected between the first pin and the fourth pin of the second power MOS tube.

[0007] The first pin of the first power MOS tube is connected to the cathode of the voltage-stabilizing diode, and the fourth pin of the first power MOS tube is connected to the anode of the voltage-stabilizing diode.

[0008] The first pin of the second power MOS tube is connected to one end of the first capacitor, and the fourth pin of the second power MOS tube is connected to the other end of the first capacitor.

[0009] Among them, the models of the first power MOS tube and the second power MOS tube are both LT4485FL-Y.

[0010] Wherein, the first transistor is a PNP transistor.

[0011] Wherein, the first MOS transistor, the second MOS transistor and the third MOS transistor are all N-channel enhancement type field effect transistors.

[0012] Wherein, the first MOS tube, the second MOS tube and the third MOS tube are respectively connected in parallel with a voltage stabilizing diode.

[0013] The utility model has the following advantages:

[0014] 1. The response time is fast, and the MOSFET tube can be turned off quickly, so that the MOSFET tube will not be turned off when there is still current, which will cause damage to the MOSFET tube;

[0015] 2. Relying on hardware control circuit, it has good stability and higher reliability;

[0016] 3. The circuit is simple, which has more cost advantages, can effectively improve product competitiveness and greatly reduce market risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a circuit diagram of a fast shutdown protection circuit provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0020] Figure 1 : is a circuit diagram of a fast shutdown protection circuit provided by an embodiment of the utility model, the circuit comprising:

[0021] One end of the sixth resistor R6, the gate of the second MOS transistor M2, and the gate of the third MOS transistor M3 are all connected to the enable terminal EN, the other end of the sixth resistor R6, the source of the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are all grounded, the gate of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, the drain of the first MOS transistor M1 is connected to the first resistor R1 and the second resistor R2 in sequence, and then connected to the first pin of the first power MOS transistor Q1, the first pin of the first power MOS transistor Q1 is also connected to the first pin of the second power MOS transistor Q2, and the fourth pin of the first power MOS transistor Q1 is connected to the first pin of the second power MOS transistor Q2. The fourth pin of the second power MOS tube Q2 is connected, the drain of the second MOS tube M2 is connected to the voltage VDD through the fourth resistor R4, the drain of the third MOS tube M3 is connected to the fourth pin of the second power MOS tube Q2 through the fifth resistor R5, the base of the first triode T1 is connected between the first resistor R1 and the second resistor R2, the collector of the first triode T1 is connected to the fourth pin of the first power MOS tube Q1, the emitter of the first triode T1 is connected to the first pin of the first power MOS tube Q1, and a third resistor R3 is further connected between the first pin and the fourth pin of the second power MOS tube Q2.

[0022] The first pin of the first power MOS transistor Q1 is connected to the cathode of the voltage stabilizing diode ZD1 , and the fourth pin of the first power MOS transistor Q1 is connected to the anode of the voltage stabilizing diode ZD1 .

[0023] The first pin of the second power MOS tube Q2 is connected to one end of the first capacitor C1, and the fourth pin of the second power MOS tube Q2 is connected to the other end of the first capacitor C1.

[0024] The first power MOS tube Q1 and the second power MOS tube Q2 are both of the model LT4485FL-Y. The first power MOS tube Q1 and the second power MOS tube Q2 are both P-channel enhancement type power MOSFETs.

[0025] Wherein, the first transistor T1 is a PNP transistor.

[0026] The first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 are all N-channel enhancement type field effect transistors.

[0027] The first MOS transistor M1 , the second MOS transistor M2 , and the third MOS transistor M3 are respectively connected in parallel with a voltage stabilizing diode.

[0028] The function of the sixth resistor R6 is to stabilize the G electrode level of the second MOS tube M2 and the third MOS tube M3. Because one end of the sixth resistor R6 is connected to the signal input end of the MCU, and the other end is connected to the G electrode of the second MOS tube M2 and the third MOS tube M3, when the MCU pin does not have the pull-down resistor R6, the MCU pin is suspended and it is easy to cause a sudden high level to turn on the second MOS tube M2 and the third MOS tube M3. Therefore, a pull-down resistor is generally connected to the GS electrode of the second MOS tube M2 and the third MOS tube M3.

[0029] The fourth resistor R4 is mainly used to prevent short circuit. When the second MOS tube M2 is turned on, VDD3V3 is pulled to ground through the fourth resistor R4 to prevent direct short circuit. In addition, when the first MOS tube M1 is turned on, it can be used as a current limiting resistor for the G pole of the first MOS tube M1.

[0030] When the input voltage of the third resistor R3 is very high, it divides the voltage with the fifth resistor R5 so that the VGS voltage between the first power MOS transistor Q1 and the second power MOS transistor Q2 does not exceed the specification limit.

[0031] Circuit principle analysis:

[0032] 1. Static analysis of Q1 / Q2 on state:

[0033] From the right side, when EN is at a high level, the third MOS tube M3 will be turned on, and the D pole is directly connected to GND. VOUT and VBUS are the same no matter which side is input. Assuming VBUS is used as input and VOUT is used as output, the voltage will pass through the body diode of Q2, and through the voltage division of the third resistor R3 and the fifth resistor R5, the VGS of the first power MOS tube Q1 and the second power MOS tube Q2 will reach the turn-on voltage, and the MOSFET tube will be turned on. From the left side, when EN is at a high level, the second MOS tube M2 will be turned on, and the D pole is directly connected to GND. The G pole voltage of the first MOS tube M1 is 0V, so the first MOS tube is in a closed state, the first resistor R1 and the second resistor R2 are in a suspended state, and the first transistor T1 is in a closed state.

[0034] 2. Static analysis of Q1 / Q2 closed state:

[0035] From the right side, when EN is low, the third MOS tube M3 will be closed, the third resistor R3 and the fifth resistor R5 are in a suspended state, VOUT and VBUS are the same no matter which side is input, assuming that VBUS is used as input and VOUT is used as output, the voltage will pass through the body diode of the second power MOS tube Q2, and since the third resistor R3 and the fifth resistor R5 are in a suspended state, the VGS voltage difference between the first power MOS tube Q1 and the second power MOS tube Q2 is 0V, and the MOSFET tube is in a closed state. From the left side, when EN is low, the second MOS tube M2 is in a closed state, and the first MOS tube M1 is in an open state through the pull-up resistor, that is, the fourth resistor R4, and the D pole is directly connected to GND. The first resistor R1 and the second resistor R2 make the first transistor T1 in an open state through voltage division. When the first transistor T1 is turned on, the VGS voltage of the first power MOS tube Q1 and the second power MOS tube Q2 will instantly become 0V, thereby achieving the effect of fast shutdown of the first power MOS tube Q1 and the second power MOS tube Q2.

[0036] 3. Dynamic analysis of Q1 / Q2 opening status:

[0037] From the right side, when the EN level changes from low to high, the third MOS tube M3 will be turned on, and the D pole will be directly connected to GND. VOUT and VBUS are the same no matter which side they are input from. Assuming that VBUS is used as input and VOUT is used as output, the voltage will pass through the body diode of the second power MOS tube Q2, and through the voltage division of the third resistor R3 and the fifth resistor R5. When the third MOS tube M3 is turned on, the G pole voltage of the first power MOS tube Q1 and the second power MOS tube Q2 will slowly decrease from the VBUS voltage to the voltage division value of the third resistor R3 and the fifth resistor R5. When the VGS voltage difference reaches the turn-on voltage of the first power MOS tube Q1 and the second power MOS tube Q2, the MOSFET tube will be turned on. At the same time, the junction capacitance of the first capacitor C1, the first power MOS tube Q1 and the second power MOS tube Q2 will start to charge immediately after the third MOS tube M3 is turned on. In order to prevent the VGS voltage difference between the first power MOS tube Q1 and the second power MOS tube Q2 from being greater than its specification value, a voltage regulator diode ZD1 is added here to clamp the VGS voltage of the first power MOS tube Q1 and the second power MOS tube Q2 within the specification value. From the left, when the EN level changes from low to high, the second MOS tube M2 will be turned on, and the G pole voltage of the first MOS tube M1 will drop from 3.3V to 0V, so the first MOS tube M1 will change from the on state to the off state, the first resistor R1 and the second resistor R2 will become suspended, and the first transistor T1 will become off.

[0038] 4. Dynamic analysis of Q1 / Q2 closed state:

[0039] From the right side, when the EN level changes from high to low, the third MOS tube M3 will be turned off, the third resistor R3 and the fifth resistor R5 will be in a suspended state, VOUT and VBUS are the same no matter which side they are input from. Assuming that VBUS is used as input and VOUT is used as output, the VBUS voltage will pass through the body diode of the second power MOS tube Q2. Since the third resistor R3 and the fifth resistor R5 will become suspended, the G pole voltage of the first power MOS tube Q1 and the second power MOS tube Q2 will become consistent with the VBUS voltage, the VGS voltage difference will become 0V, and the MOSFET tube will become closed. From the left side, when the EN level changes from high to low, the second MOS tube M2 will be turned off, and the G pole voltage of the first MOS tube M1 will rise from 0V to 3.3V, so the first MOS tube M1 will change from off to on, and the first transistor T1 will be turned on through the voltage division of the first resistor R1 and the second resistor R2. When the first transistor T1 is turned on, the VGS voltage of the first power MOS tube Q1 and the second power MOS tube Q2 will instantly become 0V, thereby achieving the effect of fast shutdown of the first power MOS tube Q1 and the second power MOS tube Q2. At the same time, the VBUS input voltage will also charge the junction capacitance of the first capacitor C1, the first power MOS tube Q1 and the second power MOS tube Q2. Due to the voltage regulator ZD1, the VGS voltage of the first power MOS tube Q1 and the second power MOS tube Q2 is always clamped within the specification value.

[0040] The utility model has the following advantages:

[0041] 1. The response time is fast, and the MOSFET tube can be turned off quickly, so that the MOSFET tube will not be turned off when there is still current, which will cause damage to the MOSFET tube;

[0042] 2. Relying on hardware control circuit, it has good stability and higher reliability;

[0043] 3. The circuit is simple, which has more cost advantages, can effectively improve product competitiveness and greatly reduce market risks.

[0044] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principle of the present invention. These improvements and substitutions should also be regarded as the protection scope of the present invention.

Claims

1. A fast shutdown protection circuit, characterized in that: include: One end of the sixth resistor, the gate of the second MOS tube and the gate of the third MOS tube are all connected to the enable end, the other end of the sixth resistor, the first MOS tube, the second MOS tube and the source of the third MOS tube are all grounded, the gate of the first MOS tube is connected to the drain of the second MOS tube, the drain of the first MOS tube is connected to the first pin of the first power MOS tube after being connected to the first resistor and the second resistor in sequence, the first pin of the first power MOS tube is also connected to the first pin of the second power MOS tube, the fourth pin of the first power MOS tube is connected to the fourth pin of the second power MOS tube, the drain of the second MOS tube is connected to the voltage VDD through the fourth resistor, the drain of the third MOS tube is connected to the fourth pin of the second power MOS tube through the fifth resistor, the base of the first triode is connected between the first resistor and the second resistor, the collector of the first triode is connected to the fourth pin of the first power MOS tube, the emitter of the first triode is connected to the first pin of the first power MOS tube, and the third resistor is also connected between the first pin and the fourth pin of the second power MOS tube.

2. The fast shutdown protection circuit according to claim 1, characterized in that: The first pin of the first power MOS tube is connected to the cathode of the voltage-stabilizing diode, and the fourth pin of the first power MOS tube is connected to the anode of the voltage-stabilizing diode.

3. The fast shutdown protection circuit according to claim 1, characterized in that: The first pin of the second power MOS tube is connected to one end of the first capacitor, and the fourth pin of the second power MOS tube is connected to the other end of the first capacitor.

4. The fast shutdown protection circuit according to claim 1, characterized in that: The models of the first power MOS tube and the second power MOS tube are both LT4485FL-Y.

5. The fast shutdown protection circuit according to claim 1, characterized in that: The first transistor is a PNP transistor.

6. The fast shutdown protection circuit according to claim 1, characterized in that: The first MOS transistor, the second MOS transistor and the third MOS transistor are all N-channel enhancement type field effect transistors.

7. The fast shutdown protection circuit according to claim 6, characterized in that: The first MOS tube, the second MOS tube and the third MOS tube are respectively connected in parallel with a voltage stabilizing diode.

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