Control system for aviation device

Abstract

The utility model discloses a control system for an aviation device, and belongs to the technical field of aviation weapon control. The control system comprises a power supply control module, an SOC module, a configuration Flash, an EMMC memory, a crystal oscillator, a JTAG, a peripheral component and an external connector. An ARM processor and an FPGA are integrated in the SOC module, and a hard core processor is arranged in the ARM processor and used for executing software tasks. A soft core microprocessor and IP cores are arranged in the FPGA, the IP cores are connected with peripheral components correspondingly controlled by the IP cores one by one, and under the support of the IP cores and the peripheral components corresponding to the IP cores, transceiving control over the interfaces is achieved; the configuration Flash is used for storing a configuration file and serial loading software of the SOC module; the EMMC memory is used for storing software and data; the crystal oscillator is used for providing a clock required by the work of the SOC module; and the JTAG is used for downloading the configuration file of the SOC module to the configuration Flash. The control system provided by the utility model has strong electromagnetic compatibility, can be used in a complex electromagnetic environment, and improves the operation speed and the product reliability through the optimization of the SOC module.

Description

Technical Field

[0001] The utility model relates to the technical field of aviation weapon control, in particular to a control system for aviation devices. Background Art

[0002] With the rapid development of my country's economy, microelectronics technology, computer technology and automation technology have also developed rapidly, and their application scope has become wider and wider; and aviation weapon launch technology, as a modern military product, plays a decisive role in modern wars and maintaining national stability and peace. Therefore, it is necessary to apply microelectronics technology, computer technology and automation control technology to modern aviation weapon launch.

[0003] In the prior art, the control system of the aviation device adopts the following Figure 1 In the embedded control system, all protocol chips, transformers, transmitters, transceivers, converters, etc. are connected separately, the overall integration is relatively low, the volume is relatively large, and it cannot meet the requirements of miniaturization. In addition, the reliability and electromagnetic compatibility of the existing control system overlap, and the purchase of imported components is restricted. It is fundamentally unable to meet the needs of modern warfare.

[0004] The utility model patent with publication number CN 216748463 U discloses a control system for aviation devices, including FPGA, power supply control module, program memory, configuration device, clock circuit, CPLD, JTAG1, JTAG2, peripheral components and external connectors; the control system integrates the 1553B (BC) protocol chip, 1553B (RT) protocol chip, 4 ARINC429 protocol chips, two CAN bus protocol chips and single-chip microcomputer in the existing launcher control system into the FPGA, with high integration. The final control system is small in size and light in weight, which can well meet the miniaturization requirements of modern warfare. However, there are still areas that need to be optimized when the control system is used: (1) The main frequency of the control system is 100MHz, and the operation speed is slow. It cannot meet the demand for large amount of calculations well, and the operation speed needs to be optimized to improve; (2) The electromagnetic compatibility of the control system is not enough, and it cannot meet the electromagnetic compatibility requirements in harsh environments; (3) The core of the control system is FPGA, and the configuration time after startup is long, which cannot meet the requirements of fast startup. (4) The control system cannot meet the requirements of storing large amounts of data. Summary of the invention

[0005] In view of the above-mentioned problems, the utility model aims to provide a control system for aviation equipment. Through the integrated setting of ARM processor and FPGA, the system has both soft processing and hard-core processing functions, thereby improving the performance and reliability of the product and increasing the computing speed; through the new EMC design, the electromagnetic compatibility of the product is enhanced to meet the use in complex environmental conditions.

[0006] In order to achieve the above purpose, the technical solution adopted by the utility model is as follows:

[0007] A control system for an aviation device, comprising a power supply control module, peripheral components and external connectors, and also comprising a SOC module, a configuration Flash and an EMMC memory;

[0008] The SOC module integrates an ARM processor and FPGA. The ARM processor has a built-in hard-core processor for executing software tasks; the FPGA has a built-in IP core, which is connected one by one with the peripheral components it controls. With the support of each IP core and its corresponding peripheral components, the receiving and sending control of each interface is realized.

[0009] Configuration Flash is connected to the SOC module to store the configuration files of the SOC module and serial loading software;

[0010] The EMMC memory is connected to the SOC module and is used to store software and data;

[0011] The peripheral components correspond to the external connectors one by one to realize external connection, and the peripheral components are connected to the SOC module.

[0012] Furthermore, the control system also includes a crystal oscillator and JTAG. The crystal oscillator is connected to the SOC module to provide the clock required for the SOC module to work; the JTAG is connected to the SOC module to download the configuration file of the SOC module to the configuration Flash.

[0013] Further, the peripheral components include a BC transceiver transformer, an RT transceiver transformer, a 429 transceiver, a CAN transceiver, a 422 transceiver, an AD converter, a DA converter and a 485 transceiver;

[0014] The BC transceiver transformer and IP core work together to implement the 1553B bus BC protocol;

[0015] The RT transceiver transformer and IP core work together to implement the 1553B bus RT protocol;

[0016] The 429 transceiver and IP core work together to realize the sending and receiving functions of the ARINC429 bus;

[0017] CAN transceiver and IP core work together to realize CAN bus function;

[0018] The 422 transceiver cooperates with the IP core to realize the RS422 bus sending and receiving functions;

[0019] The AD converter and IP core work together to realize the analog quantity acquisition function;

[0020] The DA converter and IP core work together to realize the analog output function;

[0021] The 485 transceiver cooperates with the IP core to realize the RS485 bus sending and receiving functions.

[0022] Furthermore, the FPGA embeds a Microblaze processor soft core, a 1553B BC controller IP core, a 1553B RT controller IP core, an ARINC429 controller IP core, a CAN bus controller IP core, an RS422 controller IP core, an RS485 controller IP core, an AD controller IP core, a DA controller IP core and serial loader software.

[0023] Furthermore, GPIO, SPI, UART, PWM, INT and LVDS are directly connected between the SOC module and the external connector.

[0024] Furthermore, the power supply control module includes a 15V reference voltage source and a 5V power supply module. The 15V reference voltage source is connected to the AD converter and the DA converter; the 5V power supply module is connected to the SOC module and other peripheral components.

[0025] The beneficial effect of the utility model is that compared with the prior art, the improvement of the utility model is that:

[0026] 1. The aviation device control system of the utility model adopts a new EMC design, with magnetic bead filtering added to the power input and RC filtering added to the clock signal, which enhances the electromagnetic compatibility of the product and meets the requirements for use in complex environmental conditions. The number of PCB design layers is reduced from 20 to 14.

[0027] 2. The aviation device control system of the utility model adopts SOC, integrating ARM processor and FPGA, so that the system has the characteristics of high main frequency, flexible configuration and numerous interfaces. Soft processing and hard-core processing work together to improve the performance, compatibility and reliability of the product, and increase the main frequency and improve the computing speed.

[0028] 3. The aviation device control system of the utility model adds an RS485 transceiver, which is connected to an external connector via an RS485 bus, enriching the product interface and satisfying that the product can be connected to a specific 485 bus.

[0029] 4. The aviation device control system of the utility model reduces the communication protocol chip circuit, thereby correspondingly reducing the number of devices, the number of wirings and the complexity of circuit layout. It has the advantages of high integration, small size and light weight, and can well adapt to the miniaturization requirements of modern warfare. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a diagram of the existing aviation device control system.

[0031] Figure 2 The utility model is a block diagram of a control system for an aviation device.

[0032] Figure 3 This is the circuit diagram of the 1553B RT isolation transceiver of the utility model.

[0033] Figure 4 This is the circuit diagram of the 1553B BC isolation transceiver of the utility model.

[0034] Figure 5 This is the first CAN transceiver circuit diagram of the utility model.

[0035] Figure 6 This is the circuit diagram of the second CAN transceiver of the utility model.

[0036] Figure 7 This is the circuit diagram of the first 422 transceiver of the utility model.

[0037] Figure 8 This is the circuit diagram of the second 422 transceiver of the utility model.

[0038] Fig. 9 This is the circuit diagram of the first 429 transmitter of the utility model.

[0039] Fig.10 This is the circuit diagram of the third 429 transmitter of the utility model.

[0040] Fig.11 This is the circuit diagram of the second 429 transmitter of the utility model.

[0041] Fig.12 This is the circuit diagram of the fourth 429 transmitter of the utility model.

[0042] Fig.13 This is the circuit diagram of the 429 receiver of the utility model.

[0043] Fig.14 This is the AD converter circuit diagram of the utility model.

[0044] Fig.15 This is the circuit diagram of the DA converter of the utility model.

[0045] Fig.16 This is the reference voltage source circuit diagram of the utility model.

[0046] Fig.17 This is the circuit diagram of the FPGA configuration pins of the utility model.

[0047] Fig.18 This is the FPGA JTAG circuit diagram of the utility model.

[0048] Fig.19 This is the crystal oscillator circuit diagram of the utility model.

[0049] Fig. 20 This is the circuit diagram of the FPGA IO pins of the utility model.

[0050] Fig.21 This is the circuit diagram of the FPGA GND pin of the utility model.

[0051] Fig. 22 This is the circuit diagram of the FPGA power supply pin of the utility model.

[0052] Fig.23 This is the circuit diagram of the filter capacitor of the utility model.

[0053] Fig.24 This is a circuit diagram of an external connector 1 of the utility model.

[0054] Fig.25 This is a circuit diagram of the external connector 2 of the utility model.

[0055] Fig.26 This is the CPLD JTAG circuit diagram of the utility model.

[0056] Fig. 27 This is the CPLD circuit diagram of the utility model.

[0057] Fig.28 This is the circuit diagram of the FPGA configuration chip of the utility model.

[0058] Fig.29 This is the FLASH circuit diagram of the utility model.

[0059] Fig.30 This is the circuit diagram of the FPGA power supply module of the utility model.

[0060] Fig.31 This is the circuit diagram of the CPLD and interface transceiver power supply module of the utility model.

[0061] Fig.32 This is the 485 circuit diagram of the utility model. DETAILED DESCRIPTION

[0062] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0063] Refer to the attached Figure 2 A control system for an aviation device shown includes a power supply control module, a SOC module, a configuration Flash, an EMMC memory, a crystal oscillator, a JTAG, peripheral components and external connectors.

[0064] Specifically, the SOC module is the core device of the entire control system, with built-in ARM processor and FPGA. The ARM processor has a built-in hard-core processor for executing software tasks; the FPGA has a built-in soft-core microprocessor and IP core, and the IP core is connected one by one with the peripheral components it controls. With the support of each IP core and its corresponding peripheral components, the receiving and sending control of each interface is realized;

[0065] Configuration Flash is connected to the SOC module to store the configuration files of the SOC module and serial loading software;

[0066] The EMMC memory is connected to the SOC module and is used to store software and data;

[0067] The crystal oscillator is connected to the SOC module to provide the clock required for the SOC module to work;

[0068] JTAG connects to the SOC module and is used to download the configuration file of the SOC module to the configuration Flash

[0069] Peripheral components correspond one-to-one with external connectors to achieve external connection, and the peripheral components are used in conjunction with the IP core built into the SOC module.

[0070] More specifically, the peripheral components include a BC transceiver transformer, an RT transceiver transformer, a 429 transceiver, a CAN transceiver, a 422 transceiver, an AD converter, a DA converter, and a 485 transceiver;

[0071] The BC transceiver transformer and IP core work together to implement the 1553B bus BC protocol;

[0072] The RT transceiver transformer and IP core work together to implement the 1553B bus RT protocol;

[0073] The 429 transceiver and IP core work together to realize the sending and receiving functions of the ARINC429 bus;

[0074] CAN transceiver and IP core work together to realize CAN bus function;

[0075] The 422 transceiver cooperates with the IP core to realize the RS422 bus sending and receiving functions;

[0076] The AD converter and IP core work together to realize the analog quantity acquisition function;

[0077] The DA converter and IP core work together to realize the analog output function;

[0078] The 485 transceiver cooperates with the IP core to realize the RS485 bus sending and receiving functions.

[0079] Correspondingly, the external connector provides the connection of the external interface and power supply of BC, RT, 429, CAN, 422, AD, DA, 485 output. Transformers, transceivers, etc. play the role of level conversion and coupling, and their function is to make various communication signals more stable within the level range they meet, and complete the signal reception and transmission with stronger anti-interference. The 485 transceiver and the external connector are connected through the RS485 bus to meet the product's connection with a specific 485 bus.

[0080] Furthermore, the power supply control module includes a 15V reference voltage source and a 5V power supply module. The 15V reference voltage source is connected to an AD converter and a DA converter; the 5V power supply module is connected to the SOC module and other peripheral components.

[0081] Furthermore, the built-in FPGA in the SOC module uses Verilog and VHDL languages ​​to implement interface control logic, and is embedded with Microblaze processor soft core, 1553B BC controller IP core, 1553B RT controller IP core, ARINC429 controller IP core, CAN bus controller IP core, RS422 controller IP core, RS485 controller IP core, AD controller IP core, DA controller IP core and serial loader software, mainly realizing the following functions:

[0082] a) Equipped with 2 1553B bus communications, 1 BC and 1 RT;

[0083] b) 32-bit RTC clock with 1553B bus system;

[0084] c) It has 429 bus transmission channels, adjustable baud rate, and a transmission buffer of 256 words;

[0085] d) It has a 429 bus receiving channel, adjustable baud rate, and a receiving buffer of 256 words;

[0086] e) It has RS422 communication interface, the baud rate is 115200bps, and the receiving and sending buffer is 16 words;

[0087] f) It has CAN2.0B bus communication interface, adjustable baud rate, 1K byte sending buffer and 1K byte receiving buffer;

[0088] g) It has a 485 bus receiving channel, with adjustable baud rate and a receiving buffer of 256 words;

[0089] h) Equipped with 1-way AD controller, using IIC bus protocol communication;

[0090] i) Equipped with 1-way DA controller, using parallel bus protocol communication;

[0091] j) It has the function of loading software through serial port.

[0092] In addition, GPIO, SPI, UART, PWM, INT and LVDS are also connected between the SOC module and the external connector in the utility model. These signals are directly drawn from the SOC without passing through the driver chip and are directly connected to the external connector.

[0093] Further, the circuit diagram of each component in the control system of the aviation device of the utility model is as shown in the attached Figure 3-32 As shown, Figure 3 The circuit diagram of 1553B RT isolation transceiver is shown below. Figure 4 This is the 1553B BC isolation transceiver circuit diagram. Figure 5 This is the circuit diagram of the first CAN transceiver. Figure 6 This is the circuit diagram of the second CAN transceiver. Figure 7 This is the circuit diagram of the first 422 transceiver. Figure 8 This is the circuit diagram of the second 422 transceiver. Fig. 9 This is the circuit diagram of the first 429 transmitter. Fig.10 This is the circuit diagram of the second 429 transmitter. Fig.11 This is the circuit diagram of the third 429 transmitter. Fig.12 This is the circuit diagram of the fourth 429 transmitter. Fig.13 This is the circuit diagram of the 429 receiver. Fig.14 This is the AD converter circuit diagram. Fig.15 This is the DA converter circuit diagram. Fig.16 is the reference voltage source circuit diagram, Fig.17 FPGA configuration pin circuit diagram, Fig.18 This is the FPGA JTAG circuit diagram. Fig.19 This is the crystal oscillator circuit diagram. Fig. 20 This is the FPGA IO pin circuit diagram. Fig.21 This is the FPGA GND pin circuit diagram. Fig. 22 Circuit diagram of the FPGA power supply pins. Fig.23 is the filter capacitor circuit diagram, Fig.24 For the circuit diagram of external connector 1, Fig.25 For the circuit diagram of external connector 2, Fig.26 This is the CPLD JTAG circuit diagram. Fig. 27 This is the CPLD circuit diagram. Fig.28 Configure the chip circuit diagram for FPGA, Fig.29 This is the FLASH circuit diagram. Fig.30 Circuit diagram of FPGA power supply module. Fig.31 Circuit diagram of the power supply module for CPLD and interface transceiver. Fig.32 This is the 485 circuit diagram.

[0094] The working principle of the utility model is as follows: First, after the control system is powered on by external +5V and ±15V, the FPGA in the SOC module starts to read data from the configuration device and configure. After the configuration is completed, the SOC module starts the pre-programmed serial loader.

[0095] Finally, after the serial loader is started, it detects whether a new application needs to be burned within the specified time. If the handshake with the host computer is successful within the specified time, the application is updated, that is, the new application is received from the specified CAN bus and written into the EMMC memory; if the handshake with the host computer is unsuccessful within the specified time, the application in the EMMC memory is loaded into the SOC module space after the specified time and its operation is started.

[0096] After the application is running, all peripheral components work together under the control of the application to complete the application task.

[0097] The above shows and describes the basic principle, main features and advantages of the utility model. Those skilled in the art should understand that the utility model is not limited by the above embodiments. The above embodiments and descriptions are only for explaining the principle of the utility model. Without departing from the spirit and scope of the utility model, the utility model may have various changes and improvements, which fall within the scope of the utility model to be protected. The scope of protection of the utility model is defined by the attached claims and their equivalents.

Claims

1. A control system for an aviation device, comprising a power supply control module, peripheral components and external connectors, characterized in that: It also includes SOC module, configuration Flash and EMMC memory; The SOC module integrates an ARM processor and FPGA. The ARM processor has a built-in hard-core processor for executing software tasks; the FPGA has a built-in IP core, which is connected one by one with the peripheral components it controls. With the support of each IP core and its corresponding peripheral components, the receiving and sending control of each interface is realized. The configuration Flash is connected to the SOC module to store the configuration files of the SOC module and the serial loading software; The EMMC memory is connected to the SOC module and is used to store software and data; The peripheral components correspond to the external connectors one by one to realize external connection, and the peripheral components are connected to the SOC module.

2. A control system for an aviation device according to claim 1, characterized in that: The control system also includes a crystal oscillator and JTAG. The crystal oscillator is connected to the SOC module to provide the clock required for the SOC module to work; the JTAG is connected to the SOC module to download the configuration file of the SOC module to the configuration Flash.

3. A control system for an aviation device according to claim 2, characterized in that: The peripheral components include BC transceiver transformer, RT transceiver transformer, 429 transceiver, CAN transceiver, 422 transceiver, AD converter, DA converter and 485 transceiver; The BC transceiver transformer and IP core work together to implement the 1553B bus BC protocol; The RT transceiver transformer and IP core work together to implement the 1553B bus RT protocol; The 429 transceiver and IP core work together to realize the sending and receiving functions of the ARINC429 bus; CAN transceiver and IP core cooperate to implement CAN bus protocol; The 422 transceiver cooperates with the IP core to realize the RS422 bus sending and receiving functions; The AD converter and IP core work together to realize the analog quantity acquisition function; The DA converter and IP core work together to realize the analog output function; The 485 transceiver cooperates with the IP core to realize the RS485 bus sending and receiving functions.

4. A control system for an aviation device according to claim 3, characterized in that: The FPGA is embedded with Microblaze processor soft core, 1553B BC controller IP core, 1553B RT controller IP core, ARINC429 controller IP core, CAN bus controller IP core, RS422 controller IP core, RS485 controller IP core, AD controller IP core, DA controller IP core and serial loader software.

5. A control system for an aviation device according to claim 4, characterized in that: GPIO, SPI, UART, PWM, INT and LVDS are also directly connected between the SOC module and the external plug-in components.

6. A control system for an aviation device according to claim 5, characterized in that: The power supply control module includes a 15V reference voltage source and a 5V power supply module. The 15V reference voltage source is connected to an AD converter and a DA converter; the 5V power supply module is connected to a SOC module and other peripheral components.

Images