Communication data processing mainboard

Abstract

The utility model relates to the technical field of communication data processing, in particular to a communication data processing mainboard, which comprises an Intel-to-strong D processor, the Intel to strong D processor is provided with four 10-gigabit optical ports; each 10-gigabit optical port is connected with a corresponding communication device and is used for transmitting communication data to the communication device or receiving the communication data sent by the communication device, compared with the prior art, by adopting the Intel-to-strong D processor, abundant hardware resources are provided, so that the processor can directly lead out four 10-gigabit optical ports without switching, and the communication data can be transmitted to the communication device through the 10-gigabit optical ports. The communication data processing bandwidth is improved to 40Gbps from 16-20Gbps of a traditional double-10-gigabit optical port mainboard, and the data processing density and the data throughput are greatly improved.

Description

Technical Field

[0001] The utility model relates to the technical field of communication data processing, in particular to a communication data processing mainboard. Background Art

[0002] With the rapid development of new communication technologies such as 5G in recent years, the data processing density and data throughput required for communication data processing have increased significantly.

[0003] At present, traditional communication data processing motherboards have problems of low data processing density and low data throughput. Traditional communication data processing motherboards are no longer able to meet the basic data processing requirements in today's communication field.

[0004] The above contents are only used to assist in understanding the technical solution of the present utility model and do not constitute an admission that the above contents are prior art. Utility Model Content

[0005] The main purpose of the utility model is to provide a communication data processing mainboard, aiming to solve the technical problems of low data processing density and low data throughput in the conventional communication data processing mainboard in the prior art.

[0006] To achieve the above-mentioned purpose, the utility model provides a communication data processing motherboard, the communication data processing motherboard comprising: an Intel Xeon D processor;

[0007] The Intel Xeon D processor is provided with 4 10G optical ports;

[0008] Each of the 10 Gigabit optical ports is connected to a corresponding communication device and is used to transmit communication data to the communication device or receive communication data sent by the communication device.

[0009] Optionally, the communication data processing mainboard further comprises: a backplane connector network interface;

[0010] The backplane connector network interface is connected to the Intel Xeon D processor;

[0011] The backplane connector network interface is used to meet different interface requirements of the communication data processing machine.

[0012] Optionally, the communication data processing mainboard further includes: a baseboard management controller chip;

[0013] The baseboard management controller chip is provided with 1 display interface, 2 universal asynchronous receiver / transmitter interfaces and 3 pulse width modulation interfaces;

[0014] The baseboard management controller chip is connected to the Intel Xeon D processor;

[0015] The display interface is used to provide the operator with visual information related to operation and maintenance during out-of-band management;

[0016] The universal asynchronous receiver / transmitter interface is used to connect input and output devices during out-of-band management;

[0017] The pulse width modulation interface is used to forward the pulse width modulation signal to the intelligent fan on the mainboard and the intelligent fan on the communication data processing chassis.

[0018] Optionally, the Intel Xeon D processor is further provided with 4 memory interfaces through a memory channel;

[0019] The memory interface is used to provide dual-channel memory for the Intel Xeon D processor.

[0020] Optionally, the Intel Xeon D processor is further provided with a serial advanced technology attachment interface;

[0021] The serial advanced technology attachment device interface is used to connect a hard disk.

[0022] Optionally, the Intel Xeon D processor is further provided with 4 universal serial bus interfaces;

[0023] Among them, two of the USB interfaces are 3.0 interfaces, and two of the USB interfaces are 2.0 interfaces;

[0024] The universal serial bus interface is used to connect external storage devices or human-computer interaction devices with different transmission rates.

[0025] Optionally, the Intel Xeon D processor is further provided with three M.2 interfaces;

[0026] The M.2 interface is used to connect a hard disk.

[0027] Optionally, the Intel Xeon D processor is further provided with two network card chips;

[0028] The network card chip is provided with two local area network interfaces;

[0029] The LAN network interface is used for network communication in the LAN.

[0030] Optionally, the Intel Xeon D processor is further provided with a general input / output interface and a general input / output interface derived from a general input / output controller;

[0031] The universal input / output interface is used to connect hardware for data interaction and hardware control;

[0032] The universal input / output interface derived from the universal input / output controller is used to connect an LED lamp, wherein the LED lamp is used to intuitively reflect the working status of the communication data processing mainboard.

[0033] Optionally, the Intel Xeon D processor is also provided with a -48V power supply interface;

[0034] The -48V power supply interface is used to connect to the -48V power supply of the communication data processing machine.

[0035] The utility model proposes a communication data processing motherboard, which includes: an Intel Xeon D processor; the Intel Xeon D processor is provided with 4 10 Gigabit optical ports; each of the 10 Gigabit optical ports is connected to a corresponding communication device and is used to transmit communication data to the communication device or receive communication data sent by the communication device. Compared with the prior art, the utility model adopts the Intel Xeon D processor to provide rich hardware resources, thereby realizing that the processor directly leads to 4 10 Gigabit optical ports without switching, and the communication data processing bandwidth is increased from 16 to 20 Gbps of a traditional dual 10 Gigabit optical port motherboard to 40 Gbps, thereby greatly improving data processing density and data throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0037] Figure 1 A schematic diagram of the structure of a first embodiment of a communication data processing mainboard proposed in an embodiment of the utility model;

[0038] Figure 2 This is a structural schematic diagram of a second embodiment of a communication data processing mainboard proposed in an embodiment of the utility model.

[0039] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0042] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0043] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0044] Reference Figure 1 , Figure 1 A schematic diagram of the structure of a first embodiment of a communication data processing mainboard proposed in an embodiment of the utility model;

[0045] based on Figure 1 , a first embodiment of a communication data processing mainboard of the utility model is proposed.

[0046] In this embodiment, the communication data processing mainboard includes: an Intel Xeon D processor;

[0047] The Intel Xeon D processor is provided with 4 10G optical ports;

[0048] Each of the 10 Gigabit optical ports is connected to a corresponding communication device and is used to transmit communication data to the communication device or receive communication data sent by the communication device.

[0049] It should be noted that the above-mentioned Intel Xeon D processor can provide sufficient hardware resources to realize 4 10 Gigabit optical ports, and has a variety of special optimization technologies that are effective for large-scale data processing, and the data processing performance is significantly higher than similar products. Specifically, the 10 Gigabit optical port refers to a network interface that can be inserted into a small hot-swappable optical transceiver module to realize the mutual conversion of optical and electrical signals, and can transmit network data through optical fibers connected to the module. A single 10 Gigabit optical port can provide an upper limit of 10 Gbps transmission rate when performing network data transmission, that is, the 4 10 Gigabit optical ports of the motherboard can provide a total upper limit of 40 Gbps transmission rate when performing network data transmission. Compared with traditional 100M, 1 Gigabit network ports or single or dual 10 Gigabit optical ports, the network data transmission rate of 40 Gigabit optical ports has increased significantly, and the communication data throughput has increased significantly accordingly.

[0050] The present embodiment proposes a communication data processing motherboard, which includes: an Intel Xeon D processor; the Intel Xeon D processor is provided with four 10 Gigabit optical ports; each of the 10 Gigabit optical ports is connected to a corresponding communication device, and is used to transmit communication data to the communication device or receive communication data sent by the communication device. Compared with the prior art, the present embodiment adopts the Intel Xeon D processor to provide rich hardware resources, thereby enabling the processor to directly lead out four 10 Gigabit optical ports without switching, thereby increasing the communication data processing bandwidth from 16 to 20 Gbps of a traditional dual 10 Gigabit optical port motherboard to 40 Gbps, greatly improving data processing density and data throughput.

[0051] Reference Figure 2 , Figure 2 This is a structural schematic diagram of a second embodiment of a communication data processing mainboard proposed in an embodiment of the utility model.

[0052] like Figure 2 As shown, the communication data processing mainboard also includes: a backplane connector network interface;

[0053] The backplane connector network interface is connected to the Intel Xeon D processor;

[0054] The backplane connector network interface is used to meet different interface requirements of the communication data processing machine.

[0055] It should be noted that the communication data processing mainboard is provided with a backplane connector network interface connected to the processor, and the 10G optical port and the backplane connector network interface can be switched through simple hardware changes to meet the different interface requirements of the communication data processing machine.

[0056] Furthermore, the communication data processing mainboard further comprises: a baseboard management controller chip;

[0057] The baseboard management controller chip is provided with 1 display interface, 2 universal asynchronous receiver / transmitter interfaces and 3 pulse width modulation interfaces;

[0058] The baseboard management controller chip is connected to the Intel Xeon D processor;

[0059] The display interface is used to provide the operator with visual information related to operation and maintenance during out-of-band management;

[0060] The universal asynchronous receiver / transmitter interface is used to connect input and output devices during out-of-band management;

[0061] The pulse width modulation interface is used to forward the pulse width modulation signal to the intelligent fan on the mainboard and the intelligent fan on the communication data processing chassis.

[0062] It should be noted that the baseboard management controller chip can be a baseboard management controller chip produced by ASPEED, and the Intel Xeon D processor and the baseboard management controller chip can be connected through a high-speed serial computer expansion bus standard interface, a low pin count bus interface and a universal serial bus interface.

[0063] The display interface may be a video graphics array video interface, which may provide an operator with visual information related to operation and maintenance during out-of-band management.

[0064] The universal asynchronous receiver-transmitter interface is connected to two serial port conversion chips, and the serial port conversion chip is provided with two serial ports, which can be connected to input and output devices during out-of-band management.

[0065] The number of the pulse width modulation interfaces is 3, and the pulse width modulation interfaces are connected to 3 intelligent fan interfaces. The intelligent fan interfaces are used to forward pulse width modulation signals to the intelligent fans on the above-mentioned mainboard and the intelligent fans on the communication data processing chassis.

[0066] Specifically, the smart fan refers to a fan that can transmit rotation speed information to a communication data processing mainboard and can also receive a pulse width modulation signal sent by the communication data mainboard to control the rotation speed.

[0067] The baseboard management controller chip is used for out-of-band management of the communication data processing mainboard.

[0068] Specifically, out-of-band management refers to a remote monitoring and management mode that uses a dedicated management interface and is not affected by the operating system and hardware failures of the communication data processing motherboard. Compared with traditional in-band management, out-of-band management is not affected by the failure of the communication data processing motherboard itself, and can be remotely monitored and managed on a large scale without affecting the performance of the communication data processing motherboard, which greatly facilitates the management of the communication data processing center.

[0069] Furthermore, the Intel Xeon D processor is also provided with 4 memory interfaces through the memory channel;

[0070] The memory interface is used to provide dual-channel memory for the Intel Xeon D processor.

[0071] It should be noted that the memory may be a fourth generation double data rate synchronous dynamic random access memory. Dual channel memory is a memory control and management technology that can theoretically double the memory bandwidth and improve processor performance. Two sets of dual channel memory take into account both memory capacity and bandwidth, which can make the processor data processing capability of the communication data processing motherboard compatible with the greatly improved data throughput.

[0072] Furthermore, the Intel Xeon D processor is also provided with a serial advanced technology attachment interface;

[0073] The serial advanced technology attachment device interface is used to connect a hard disk.

[0074] Furthermore, the Intel Xeon D processor is also provided with 4 universal serial bus interfaces;

[0075] Among them, two of the USB interfaces are 3.0 interfaces, and two of the USB interfaces are 2.0 interfaces;

[0076] The universal serial bus interface is used to connect external storage devices or human-computer interaction devices with different transmission rates.

[0077] It should be noted that the Universal Serial Bus 3.0 interface can provide a maximum theoretical data transmission rate of 5Gbps, and can be connected to devices such as large-capacity removable storage devices that require a higher transmission rate. The Universal Serial Bus 2.0 interface can provide a maximum theoretical data transmission rate of 480Mbps, and can be connected to human-computer interaction devices such as keyboards and mice that require a lower transmission rate.

[0078] Furthermore, the Intel Xeon D processor is also provided with three M.2 interfaces;

[0079] The M.2 interface is used to connect a hard disk.

[0080] It should be noted that the M.2 interface can be an M.2KEY-M interface, which can provide a high-speed serial computer expansion bus standard interface signal connection, support non-volatile memory standard protocol, and provide high-speed hard disk data transmission capabilities that are superior to serial advanced technology attachment interface solid-state hard disks. The interface supports the high-speed serial computer expansion bus standard 4.0 protocol, and can provide a sequential read speed of more than 7000MB / s when connected to a specific high-speed serial computer expansion bus standard 4.0 hard disk, which is compatible with the data processing capabilities of Intel Xeon D processors. If a 4TB hard disk is used, a total of 12TB of high-speed hard disk capacity can be provided, which fully meets the data storage requirements of communication data processing.

[0081] Furthermore, the Intel Xeon D processor is also provided with two network card chips;

[0082] The network card chip is provided with two local area network interfaces;

[0083] The LAN network interface is used for network communication in the LAN.

[0084] Furthermore, the Intel Xeon D processor is also provided with a general purpose input / output interface and a general purpose input / output interface derived from a general purpose input / output controller;

[0085] The universal input / output interface is used to connect hardware for data interaction and hardware control;

[0086] The universal input / output interface derived from the universal input / output controller is used to connect an LED lamp, wherein the LED lamp is used to intuitively reflect the working status of the communication data processing mainboard.

[0087] It should be noted that the universal input / output interface can provide 8 independent universal input / output pins, which can be configured as input or output respectively.

[0088] It should be noted that the LED lights include a 10G optical port operation status indicator light, a mainboard self-check status indicator light, a mainboard power indicator light, and a hard disk indicator light. The LED lights can intuitively reflect the working status of the communication data processing mainboard.

[0089] Furthermore, the Intel Xeon D processor is also provided with a -48V power supply interface;

[0090] The -48V power supply interface is used to connect to the -48V power supply of the communication data processing machine.

[0091] It should be noted that the mainboard has a -48V power supply interface, which can meet the special voltage requirements of the communication industry. The interface can be directly connected to the -48V power supply of the communication data processing machine without additional conversion.

[0092] Specifically, the more common power supply voltages for electronic devices are 220V, 24V, 12V, etc. However, in the early stages of the development of the communications industry, direct current was used. Considering the electrochemical corrosion of telephone lines, negative voltage power supply was adopted, and the -48V power supply is still used today. Traditional motherboards do not consider this power supply method and cannot be directly used for communication data processing machines, but the communication data processing motherboard described above can do the job.

[0093] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A communication data processing mainboard, characterized in that: The communication data processing mainboard includes: an Intel Xeon D processor; The Intel Xeon D processor is provided with 4 10G optical ports; Each of the 10 Gigabit optical ports is connected to a corresponding communication device and is used to transmit communication data to the communication device or receive communication data sent by the communication device; The communication data processing mainboard also includes: a baseboard management controller chip; The baseboard management controller chip is provided with 1 display interface, 2 universal asynchronous receiver / transmitter interfaces and 3 pulse width modulation interfaces; The baseboard management controller chip is connected to the Intel Xeon D processor; The display interface is used to provide the operator with visual information related to operation and maintenance during out-of-band management; The universal asynchronous receiver / transmitter interface is used to connect input and output devices during out-of-band management; The pulse width modulation interface is used to forward the pulse width modulation signal to the intelligent fan on the communication data processing mainboard and the intelligent fan on the communication data processing chassis.

2. The communication data processing mainboard according to claim 1, characterized in that: The communication data processing mainboard also includes: a backplane connector network interface; The backplane connector network interface is connected to the Intel Xeon D processor; The backplane connector network interface is used to meet different interface requirements of the communication data processing machine.

3. The communication data processing mainboard according to claim 1, characterized in that: The Intel Xeon D processor is also provided with four memory interfaces through a memory channel; The memory interface is used to provide dual-channel memory for the Intel Xeon D processor.

4. The communication data processing mainboard according to claim 1, characterized in that: The Intel Xeon D processor is also provided with a serial advanced technology attachment interface; The serial advanced technology attachment device interface is used to connect a hard disk.

5. The communication data processing mainboard according to claim 1, characterized in that: The Intel Xeon D processor is also provided with 4 universal serial bus interfaces; Among them, two of the USB interfaces are 3.0 interfaces, and two of the USB interfaces are 2.0 interfaces; The universal serial bus interface is used to connect external storage devices or human-computer interaction devices with different transmission rates.

6. The communication data processing mainboard according to claim 1, characterized in that: The Intel Xeon D processor is also provided with three M.2 interfaces; The M.2 interface is used to connect a hard disk.

7. The communication data processing mainboard according to claim 1, characterized in that: The Intel Xeon D processor is also provided with two network card chips; The network card chip is provided with two local area network interfaces; The LAN network interface is used for network communication in the LAN.

8. The communication data processing mainboard according to claim 1, characterized in that: The Intel Xeon D processor is also provided with a general purpose input / output interface and a general purpose input / output interface derived from a general purpose input / output controller; The universal input / output interface is used to connect hardware for data interaction and hardware control; The universal input / output interface derived from the universal input / output controller is used to connect an LED lamp, wherein the LED lamp is used to intuitively reflect the working status of the communication data processing mainboard.

9. The communication data processing mainboard according to claim 1, characterized in that: The Intel Xeon D processor is also provided with a -48V power supply interface; The -48V power supply interface is used to connect to the -48V power supply of the communication data processing machine.

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