Light emitting diode

Abstract

The utility model discloses a light emitting diode. The light emitting diode comprises a substrate; the epitaxial layer comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially formed on one surface of the substrate; the edge of the epitaxial layer is provided with a step structure exposing the first semiconductor layer; a transparent conductive layer on a surface of the second semiconductor layer; the transparent conductive layer is provided with a plurality of through holes exposing the second semiconductor layer; a metal layer on the surface of the transparent conductive layer, at least for ohmic contact with the second semiconductor layer and for current expansion; the metal layer covers the side walls and the bottoms of the plurality of through holes and is electrically connected with the second semiconductor layer in the plurality of through holes; the metal layer exposes the edge part of the transparent conductive layer; the electrode layer comprises a first electrode and a second electrode; the first electrode is located at the bottom of the step structure and electrically connected with the first semiconductor layer; the second electrode is located on the surface of the metal layer and electrically connected with the metal layer. The light-emitting diode provided by the utility model has the advantages of low working voltage and high ESD (Electro-Static Discharge) performance.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a light emitting diode (LED). Background Art

[0002] Light-emitting diodes are light-emitting devices that convert electrical energy into light energy. They have the characteristics of low energy consumption, small size, long life, good stability, fast response, and stable wavelength. They are now widely used in lighting, home appliances, display screens, indicator lights, and other fields.

[0003] At present, the size of the regular LED is constantly shrinking to increase the output of a single wafer and reduce costs. At the same time, the ESD (Electro-Static discharge) level, voltage, and brightness of the LED have become huge challenges to meet market demand. The epitaxial technology is constantly being optimized, which has improved the light efficiency of the LED to a certain extent. Therefore, the low voltage and high ESD performance of regular small-size LEDs has become one of the technical difficulties. The ESD capability of the LED is closely related to its leakage value and overall reliability. Often, a high ESD level is accompanied by an improvement in both optical and electrical characteristics. Utility Model Content

[0004] In view of this, the present application provides a light emitting diode, the scheme is as follows:

[0005] A light emitting diode, comprising:

[0006] substrate;

[0007] The epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially formed on a surface of a substrate; an edge of the epitaxial layer has a step structure exposing the first semiconductor layer;

[0008] A transparent conductive layer located on the surface of the second semiconductor layer; the transparent conductive layer has a plurality of through holes exposing the second semiconductor layer;

[0009] A metal layer located on the surface of the transparent conductive layer is used at least for ohmic contact with the second semiconductor layer and for current expansion; the metal layer covers the sidewalls and bottoms of the plurality of through holes and is electrically connected to the second semiconductor layer at the plurality of through holes; the metal layer exposes an edge portion of the transparent conductive layer;

[0010] The electrode layer includes a first electrode and a second electrode; the first electrode is located at the bottom of the step structure and is electrically connected to the first semiconductor layer; the second electrode is located on the surface of the metal layer and is electrically connected to the metal layer.

[0011] Optionally, in the above light-emitting diode, the first semiconductor layer has a first thickness;

[0012] The bottom of the step structure extends into the first semiconductor layer, and a portion of the first semiconductor layer below the step structure has a second thickness that is less than or equal to one third of the first thickness.

[0013] Optionally, in the above-mentioned light-emitting diode, the shape of the through hole includes at least one of a circle, an ellipse and a polygon.

[0014] Optionally, in the above-mentioned light-emitting diode, the plurality of through holes include a first through hole and a plurality of second through holes arranged around the first through hole, and the area of ​​the first through hole is larger than the area of ​​the second through holes;

[0015] The second electrode is arranged opposite to the first through hole.

[0016] Optionally, in the above-mentioned light-emitting diodes, the second through holes are all the same;

[0017] Alternatively, at least two second through holes are different.

[0018] Optionally, in the above-mentioned light-emitting diode, the transparent conductive layer is an ITO film;

[0019] And / or, the metal layer includes at least one metal film.

[0020] Optionally, in the above-mentioned light-emitting diode, at least one layer of metal film includes at least one of Ag film, Ti film, TiW film, Cr film, NiAu film and NiAg film.

[0021] Optionally, in the above-mentioned light-emitting diode, the side wall inclination angle of the step structure ranges from 5° to 50°.

[0022] Optionally, in the above-mentioned light-emitting diode, a buffer layer is provided on the surface of the substrate, and the epitaxial layer is formed on the surface of the buffer layer.

[0023] Optionally, in the above light-emitting diode, the maximum width of the through hole in a plane parallel to the substrate is 6 μm to 20 μm.

[0024] Optionally, in the above light-emitting diode, the spacing between adjacent through holes is not less than 5 μm.

[0025] Optionally, in the above-mentioned light-emitting diode, the transparent conductive layer includes: a first region and a second region surrounding the first region, and the plurality of through holes are located in the first region;

[0026] The metal layer is located above the first area and does not overlap with the second area. The metal layer has a hollow area, and the hollow area does not overlap with the through hole.

[0027] Optionally, in the above-mentioned light-emitting diode, the area of ​​the plurality of through holes accounts for no less than 70% of the area of ​​the transparent conductive layer.

[0028] Optionally, in the above-mentioned light-emitting diode, the thickness of the transparent conductive layer is in the range of 50 nm to 150 nm;

[0029] The thickness of the metal layer ranges from 1 nm to 10 nm.

[0030] Optionally, in the above-mentioned light emitting diode, it also includes:

[0031] The passivation protection layer covers the surface of the metal layer, the surface of the transparent conductive layer, the surface of the epitaxial layer, and the sidewall and bottom of the step structure, and exposes at least a portion of the first electrode and the second electrode.

[0032] From the above description, it can be seen that in the light-emitting diode provided by the technical solution of the present application, a metal layer is arranged on the surface of a transparent conductive layer having a plurality of through holes, and the metal layer can be electrically contacted with the second semiconductor layer based on the plurality of through holes in the transparent conductive layer. Through the metal layer, not only can ohmic contact with the second semiconductor layer be achieved, thereby reducing the contact resistance and thus reducing the operating voltage of the light-emitting diode, but also current expansion can be achieved through the metal layer, so that the light-emitting diode has a more uniform current distribution, avoiding current accumulation under the second electrode, thereby improving the light extraction efficiency of the light-emitting diode, and based on the low resistance property of the metal material, static electricity can be quickly released, thereby avoiding static electricity damage caused by static electricity accumulation and improving the ESD performance of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0034] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0035] Figure 1 A top view of a transparent conductive layer in a light-emitting diode provided in an embodiment of the present application;

[0036] Figure 2 For light emitting diodes Figure 1 Cross-sectional view along the A-A' direction;

[0037] Figure 3 A schematic diagram of a layout of a step structure in an epitaxial layer provided in an embodiment of the present application;

[0038] Figure 4 A top view of a metal layer in a light-emitting diode provided in an embodiment of the present application;

[0039] Figure 5-Figure 10 A product structure diagram of a light emitting diode in different preparation process steps provided in an embodiment of the present application.

[0040] Reference numerals:

[0041] 100-substrate; 101-epitaxial layer; 102-electrode layer; 103-transparent conductive layer; 1031-first region; 1032-second region; 104-metal layer; 105-passivation protective layer; 11-buffer layer; 12-first semiconductor layer; 13-light-emitting layer; 14-second semiconductor layer; 15-step structure; 16-through hole; 161-first through hole; 162-second through hole; 17-first electrode; 18-second electrode; 19-hollow region. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0043] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0044] refer to Figure 1 and Figure 2 As shown, Figure 1 A top view of a transparent conductive layer in a light emitting diode provided in an embodiment of the present application, Figure 2 For light emitting diodes Figure 1 In the cross-sectional view along the A-A' direction, the light-emitting diode provided in the embodiment of the application includes:

[0045] Substrate 100;

[0046] The epitaxial layer 101 includes a first semiconductor layer 12, a light emitting layer 13, and a second semiconductor layer 14, which are sequentially formed on a surface of the substrate 100; the edge of the epitaxial layer 101 has a step structure 15 exposing the first semiconductor layer 12;

[0047] A transparent conductive layer 103 is located on the surface of the second semiconductor layer 14; the transparent conductive layer 103 has a plurality of through holes 16 exposing the second semiconductor layer 14;

[0048] A metal layer 104 is located on the surface of the transparent conductive layer 103, and the metal layer 104 is at least used for ohmic contact with the second semiconductor layer 14 and for current expansion; the metal layer 104 covers the sidewalls and bottoms of the plurality of through holes 16, and is electrically connected to the second semiconductor layer 14 at the plurality of through holes 16; the metal layer 104 exposes the edge portion of the transparent conductive layer 103;

[0049] The electrode layer 102 includes a first electrode 17 and a second electrode 18 . The first electrode 17 is located at the bottom of the step structure 15 and is electrically connected to the first semiconductor layer 12 . The second electrode 18 is located on the surface of the metal layer 104 and is electrically connected to the metal layer 104 .

[0050] In order to facilitate the illustration of the graphic structure of the transparent conductive layer 103, Figure 1 The top view only shows the substrate 100 and the transparent conductive layer 103 thereon. The other film structures in the light emitting diode can be referred to as Figure 2 Cross-sectional view shown.

[0051] In the light-emitting diode provided in the embodiment of the present application, a metal layer 104 is arranged on the surface of a transparent conductive layer 103 having a plurality of through holes 16. The metal layer 104 can be electrically contacted with the second semiconductor layer 14 based on the plurality of through holes 16 in the transparent conductive layer 103. The metal layer 104 can not only achieve ohmic contact with the second semiconductor layer 14 to reduce the contact resistance, thereby reducing the operating voltage of the light-emitting diode, but also achieve current expansion through the metal layer 104, so that the light-emitting diode has a more uniform current distribution, avoids current accumulation under the second electrode 18, and improves the light extraction efficiency of the light-emitting diode. Based on the low resistance property of the metal material, static electricity can be quickly released to avoid static electricity damage caused by static electricity accumulation, thereby improving the ESD performance of the light-emitting diode.

[0052] In the embodiment of the present application, the thickness of the transparent conductive layer 103 and the metal layer 104 can be set based on product design requirements. For example, the thickness of the transparent conductive layer 103 can be set to be in the range of 50nm to 150nm; the thickness of the metal layer 104 can be set to be in the range of 1nm to 10nm.

[0053] In the light-emitting diode, the light-emitting layer 13 is a multi-quantum well layer (MQW). One of the first semiconductor layer 12 and the second semiconductor layer 14 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. The present application does not limit this. For example, the first semiconductor layer 12 can be an N-type semiconductor layer, and the second semiconductor layer 14 can be a P-type semiconductor layer. Among them, the P-type semiconductor layer can be P-type GaN or other P-type doped semiconductor materials, and the N-type semiconductor layer can be N-type GaN or other N-type doped semiconductor materials.

[0054] In the embodiment of the present application, the LED is a front-mounted structure, and the light generated by the LED is emitted from the side close to the electrode layer 102. The metal layer 104 exposes the edge portion of the transparent conductive layer 103 so that the light generated by the LED can at least be emitted through the edge portion.

[0055] In order to achieve electrical connection between the first electrode 17 and the first semiconductor layer 12 at the bottom of the step structure 15, the depth of the step structure 15 in the epitaxial layer 101 is set to be no less than the sum of the thicknesses of the second semiconductor layer 14 and the light-emitting layer 13, so that the bottom of the step structure 15 can be located in the first semiconductor layer 12 and the first semiconductor layer 12 is exposed.

[0056] Optionally, in the embodiment of the present application, the first semiconductor layer 12 has a first thickness, the bottom of the step structure 15 is arranged to extend into the first semiconductor layer 12, and the portion of the first semiconductor layer 12 located below the step structure 15 has a second thickness, and the second thickness is less than or equal to one-third of the first thickness, that is, the depth of the step structure 15 extending into the first semiconductor layer 12 is not less than two-thirds of the thickness of the first semiconductor layer 12. The inventor has found that the etching depth of the step structure 15 in the first semiconductor layer 12 will affect the operating voltage of the light-emitting diode. When the step structure 15 extends into the first semiconductor layer 12 to a depth not less than two-thirds of the thickness of the first semiconductor layer 12, the operating voltage of the light-emitting diode can be effectively reduced.

[0057] The step structure 15 may extend into the first semiconductor layer 12 to a depth of 1 μm to 3 μm, so as to effectively reduce the operating voltage of the light emitting diode.

[0058] In the embodiment of the present application, the shape of the through hole 16 in the transparent conductive layer 103 can be at least one of a circle, an ellipse and a polygon, that is, the vertical projection of the through hole 16 in the transparent conductive layer 103 on the plane where the substrate 100 is located can be at least one of a circle, an ellipse and a polygon, and is not limited to Figure 1 In the embodiment shown, all through holes 16 are circular.

[0059] For the epitaxial layer 101 provided with the step structure 15, the area of ​​the transparent conductive layer 103 to be provided is determined. Based on the determined transparent conductive layer 103, in order to make all the through holes 16 in the transparent conductive layer 103 have a larger area ratio relative to the transparent conductive layer 103, the through holes 16 are not limited to a single shape and a single size. Any number of through holes 16 and the shape and size of each through hole 16 can be arranged based on the transparent conductive layer 103, and the embodiments of the present application do not limit this.

[0060] Optionally, the area of ​​the plurality of through holes 16 in the transparent conductive layer 103 is not less than 70% of the area of ​​the transparent conductive layer 103. Assuming that the area of ​​the area surrounded by the periphery of the transparent conductive layer 103 is S1, and the area of ​​all through holes 16 in the transparent conductive layer 103 is S2, then At this time, a larger contact area can be provided between the metal layer 104 and the second semiconductor layer 14, thereby significantly reducing the contact resistance, effectively reducing the operating voltage of the light-emitting diode, and achieving a better current spreading effect.

[0061] like Figure 1 As shown, the plurality of through holes 16 in the transparent conductive layer 103 may include a first through hole 161 and a plurality of second through holes 162 arranged around the first through hole 161, and the area of ​​the first through hole 161 is larger than the area of ​​the second through hole 162; the second electrode 18 is arranged opposite to the first through hole 161. In this way, the second electrode 18 can achieve good electrical contact with the metal layer 104 above the first through hole 161, thereby reducing the contact resistance. In addition, the through holes 16 can be arranged as much as possible based on space requirements through a plurality of smaller second through holes 162 around the first through hole 161, thereby effectively increasing the area ratio of the through holes 16.

[0062] In the embodiment of the present application, all the second through holes 162 may be arranged to be the same, so as to facilitate the preparation of the through holes 16 in the transparent conductive layer 103 .

[0063] In the embodiment of the present application, at least two different second through holes 162 may be provided so that a larger number of second through holes 162 are arranged in the transparent conductive layer 103 around the first through hole 161 , so that the through hole 16 in the transparent conductive layer 103 has a larger area occupancy.

[0064] It should be noted that the two through holes 16 being the same means that the geometric figures of the vertical projections of the two through holes 16 on the plane where the substrate 100 is located are congruent, and the two through holes 16 being different means that the geometric figures of the vertical projections of the two through holes 16 on the plane where the substrate 100 is located are not congruent.

[0065] In one implementation of the embodiment of the present application, the maximum width of the through hole 16 on the plane parallel to the substrate 100 is 6 μm to 20 μm. If the through hole 16 is a circular hole, the radius of the circular hole is 3 μm to 10 μm, and the diameter is 6 μm to 20 μm, so that the area ratio of the through hole 16 in the transparent conductive layer 103 can be increased based on the through hole 16 of a smaller size.

[0066] Optionally, the spacing between adjacent through holes 16 is set to be no less than 5 μm. In the light-emitting diode, the through holes 16 are generally formed in the transparent conductive layer 103 by a wet etching process, and the spacing between two adjacent through holes 16 is set to be no less than 5 μm, so that the spacing of the through holes 16 is adapted to the etching accuracy of the wet etching process, so that the spacing between the two through holes 16 has a safe distance, and the connection between the two through holes 16 is avoided due to process errors.

[0067] In the embodiment of the present application, the transparent conductive layer 103 may be an ITO (indium tin oxide) film, or may be other transparent conductive oxide films (such as IZO films, etc.), and the embodiment of the present application does not limit the implementation of the transparent conductive layer 103. For a small-size face-mounted light-emitting diode, the current density is relatively small, so that the current cannot effectively extend to the peripheral area of ​​the light-emitting diode. By providing a metal layer 104 on its surface, the contact resistance can be reduced and the current extension effect can be improved.

[0068] Based on any of the above embodiments, the metal layer 104 includes at least one metal film. The metal film may be a metal single substance film or an alloy film. Optionally, the metal film includes at least one of an Ag film, a Ti film, a TiW film, a Cr film, a NiAu film, and a NiAg film. Based on at least one metal film as the metal layer 104, based on the low resistance characteristics of the metal material, not only can a good ohmic contact effect be formed with the second semiconductor layer 14 below in the longitudinal direction, but also a good current spreading effect can be achieved in the lateral direction.

[0069] Optionally, a buffer layer 11 is provided on the surface of the substrate 100, and the epitaxial layer 101 is formed on the surface of the buffer layer 11. The buffer layer 11 can effectively adjust the stress generated by lattice mismatch or thermal mismatch between the substrate 100 and the epitaxial layer 101 to ensure the lattice quality of the epitaxial layer 101 formed on the substrate 100.

[0070] Based on the light-emitting diode provided in any of the above embodiments, the light-emitting diode of the embodiment of the present application may further include: a passivation protection layer 105, the passivation protection layer 105 covers the surface of the metal layer 104, the surface of the transparent conductive layer 103, the surface of the epitaxial layer 101, and the sidewall and bottom of the step structure 15, and exposes at least part of the first electrode 17 and the second electrode 18. The reliability of the light-emitting diode can be improved by the passivation protection layer 105.

[0071] refer to Figure 3 As shown, Figure 3 A schematic diagram of the layout of a step structure in an epitaxial layer provided in an embodiment of the present application, wherein the sidewall inclination angle β of the step structure 15 is in the range of 5° to 50°. The sidewall inclination angle β of the step structure 15 is set in the range of 5° to 50°, so that the sidewall of the step structure 15 has a large slope, thereby preventing the film layer located above the epitaxial layer 101 and covering the sidewall of the step structure 15 from breaking, such as preventing the passivation protection layer 105 from breaking.

[0072] The value range of the side wall inclination angle β of the step structure 15 can be set based on needs. In other embodiments, the side wall of the step structure 15 can be set to be perpendicular or approximately perpendicular to the plane where the substrate 100 is located. In this case, β is equal to or approximately equal to 90°. This method does not require the formation of a side wall of the step structure 15 with a large slope, and can reduce the difficulty of the preparation process of the step structure 15.

[0073] refer to Figure 4 As shown, Figure 4 This is a top view of a metal layer in a light-emitting diode provided in an embodiment of the present application. To facilitate illustration of the graphic structure of the transparent conductive layer 103 and the metal layer 104, Figure 4 The top view only shows the substrate 100 and the transparent conductive layer 103 and the metal layer 104 thereon. The other film layer structures in the light emitting diode can be referred to. Figure 2 Cross-sectional view shown.

[0074] Combination Figure 1 and Figure 4As shown, based on any of the above embodiments, the transparent conductive layer 103 includes: a first region 1031 and a second region 1032 surrounding the first region 1031, and a plurality of through holes 16 are located in the first region 1031; the metal layer 104 is located above the first region 1031 and does not overlap with the second region 1032, and the metal layer 104 has a hollow region 19, and the hollow region 19 does not overlap with the through hole 16. Among them, the second region 1032 is the edge portion of the transparent conductive layer 103 exposed by the metal layer 104. In this embodiment, by providing the hollow region 19 on the metal layer 104 that does not overlap with the through hole 16, the light generated by the light emitting diode can be emitted not only from the second region 1032, but also from the hollow region 19 that is not blocked by the metal layer 104, thereby improving the brightness.

[0075] exist Figure 4 In the illustrated embodiment, the hollow region 19 may be an etched hole formed in the metal layer 104. In other embodiments, the metal layer 104 may be a metal grid structure, and the hollow region 19 may be a grid unit in the metal grid structure.

[0076] In other embodiments, the metal layer 104 may be configured as a metal film that covers the entire surface of the first region 1031 . In this case, there is no need to configure the hollow region 19 on the metal layer 104 .

[0077] In order to more clearly introduce the product structure of the light emitting diode provided in the embodiment of the present application, the following is respectively combined with Figure 2 The schematic diagram of the product structure of the light-emitting diode with a normal structure in each process step is shown to further illustrate the product structure and preparation process of the light-emitting diode provided in the embodiment of the present application.

[0078] refer to Figure 5-Figure 10 As shown, Figure 5-Figure 10 A product structure diagram of a light-emitting diode in different preparation process steps provided in an embodiment of the present application, the preparation method of the light-emitting diode includes:

[0079] Step S101: Figure 5 As shown, an epitaxial layer 101 is formed on one side surface of a substrate 100 .

[0080] An epitaxial layer 101 may be formed on one side surface of the substrate 100 by an epitaxial growth process. The substrate 100 includes but is not limited to a sapphire substrate, a Si substrate, and a SiC substrate. The substrate 100 may be a mirror substrate or a PSS patterned substrate. Optionally, a patterned sapphire substrate is selected in the embodiment of the present application. The epitaxial growth process includes but is not limited to a hydride vapor deposition process (HVPE), a metal organic chemical vapor deposition (MOCVD), a molecular beam epitaxy process (MBE), and the like.

[0081] In the embodiment of the present application, MOCVD can be used to deposit the epitaxial layer 101, and the thickness of the epitaxial layer 101 ranges from 500μm to 800μm. The epitaxial layer 101 includes an N-type GaN layer (first semiconductor layer 12), a multi-quantum well layer MQW (light-emitting layer 13), and a P-type GaN layer (second semiconductor layer 14) formed in sequence. The thickness of the N-type GaN layer ranges from 1000nm to 5000nm, which is a semiconductor material with electrons as the majority carriers, and Si is used as a doping element; the multi-quantum well layer MQW provides a radiation recombination site for electrons and holes, which can improve the luminous efficiency; the thickness of the P-type GaN layer ranges from 100nm to 500nm, which is a semiconductor material with holes as the majority carriers, and Mg is selected as a doping element, but is not limited to this.

[0082] Optionally, the surface of the substrate 100 used to form the epitaxial layer 101 has a buffer layer 11 , and the thickness of the buffer layer 11 is in the range of 100 nm to 500 nm, which can effectively regulate the stress generated by lattice mismatch or thermal mismatch between the sapphire substrate and the epitaxial layer 101 .

[0083] Step S102: Figure 6 As shown, a stepped structure 15 is formed in the epitaxial layer 101 .

[0084] Photolithography and ICP dry etching processes may be used to form a step structure 15 at the edge region of the epitaxial layer 101 to expose a portion of the first semiconductor layer 12 .

[0085] In an embodiment of the present application, a patterned photoresist layer can be formed on the P-type GaN layer, and the photoresist layer is used as a mask to etch the epitaxial layer 101 through an ICP dry etching process, sequentially penetrating the P-type GaN layer and the multi-quantum well layer MQW, so that part of the N-type GaN layer is exposed, and then the photoresist layer is removed. In order to reduce the operating voltage, the step structure 15 can be extended into the N-type GaN layer. The etching depth can be 1.45μm. The side wall inclination angle of the step structure 15 can be 5° to 50°, such as 40°. For the convenience of illustration, the side wall of the step structure 15 is illustrated in the embodiment of the present application as being perpendicular or approximately perpendicular to the plane of the substrate 100.

[0086] Step S103: Figure 7 As shown, a patterned transparent conductive layer 103 is formed on the surface of the P-type GaN layer.

[0087] First, a layer of ITO film can be prepared on the surface of the P-type GaN layer by a deposition process as the transparent conductive layer 103. Specifically, a layer of ITO film with a thickness of 100 nm can be prepared by an electron beam evaporation process, and the ITO film can be annealed in a N2 gas environment and a temperature environment of 500° C., so that the ITO film forms a good ohmic contact with the underlying P-type GaN layer, thereby reducing the contact resistance.

[0088] Then, a patterned photoresist layer is formed on the surface of the ITO film, and the ITO film is etched using the photoresist layer as a mask to form a plurality of through holes 16 in the ITO film. Specifically, a first through hole 161 with a larger area is formed in the region corresponding to the second electrode 18, and a plurality of second through holes 162 with smaller areas are formed around the first through hole 161.

[0089] Optionally, in the embodiment of the present application, the surface of the transparent conductive layer 103 may be a roughened surface to improve light extraction efficiency.

[0090] Finally, the photoresist layer on the surface of the ITO film is removed.

[0091] The shape of the through hole 16 on the substrate 100 includes but is not limited to a circle, an ellipse and a polygon. The through hole 16 can be a single graphic structure or a combination of multiple different graphic structures to improve the light extraction efficiency of the light emitting diode.

[0092] The through holes 16 of the required pattern structure and size can be set in the transparent conductive layer 103 according to the size of the light-emitting diode. For small-sized light-emitting diodes, if circular through holes 16 are used, the radius of the through holes 16 can be set to be 3μm to 10μm. Since the through holes 16 in the transparent conductive layer 103 are formed by a wet etching process, the process control capability is weak. In order to ensure a safe distance, the distance between adjacent through holes 16 is set to be no less than 5μm. In order to improve the light extraction efficiency of the light-emitting diode, the area of ​​all through holes 16 in the transparent conductive layer 103 accounts for no less than 70%.

[0093] Step S104: Figure 8 As shown, a metal layer 104 is deposited on the surface of the transparent conductive layer 103 to reduce contact resistance and improve current spreading effect.

[0094] A photoresist layer pattern can be formed on the epitaxial layer 101 and the transparent conductive layer 103, and a Cr film-Ti film can be sequentially deposited on the epitaxial layer 101 and the transparent conductive layer 103 by an ion beam evaporation process as a metal layer 104. The thickness of the metal layer 104 can be 3nm. As mentioned above, the metal layer 104 includes at least one metal film, and the metal film includes but is not limited to an Ag film, a Ti film, a TiW film, a Cr film, a NiAu film, and a NiAg film. After the metal layer 104 is formed, the photoresist layer and the metal layer 104 on its surface are removed by a stripping process, thereby forming a metal layer 104 with a desired graphic structure.

[0095] Step S105: Fig. 9 As shown, an electrode layer 102 is prepared. The first electrode 17 and the second electrode 18 can be prepared in the corresponding regions of the N-type GaN layer and the P-type GaN layer respectively by using photolithography and evaporation processes.

[0096] The electrode layer 102 including the first electrode 17 and the second electrode 18 can be prepared by an evaporation process. The thickness of the electrode layer 102 can be 1 μm to 3 μm. The electrode layer 102 can be configured to include a Cr film, an Al film, a plurality of pairs of Ti films and Pt films stacked in sequence, and an AuTi alloy film. The thickness of the Cr film can be The thickness of the Al film can be Since the Cr film has a good ohmic contact effect with the P-type GaN layer, the Cr film formed first in the electrode layer 102 can reduce the contact resistance between the second electrode 18 and the P-type GaN. In addition, the Al film formed later has a higher reflectivity.

[0097] Among them, the thickness of the Ti film must be at least greater than that of the Al film. If the thickness of the Ti film is too thin, it will not be able to provide good protection for the Al film. The Ti in the AuTi alloy film can make the AuTi alloy film have good hardness, which can effectively prevent the light-emitting diode from falling off due to the force applied to the light-emitting diode during wire bonding. The proportion of Ti in the alloy film does not exceed 20%. If the Ti content is too high, it will affect the voltage and brightness parameters of the light-emitting diode.

[0098] In addition, since the electrode layer 102 of the light-emitting diode will produce metal hydrolysis and migration problems during the power-on process, which may easily lead to leakage problems in the light-emitting diode, the AuTi alloy film in the electrode layer 102 can block the diffusion of metal atoms in the electrode layer 102, thereby alleviating the problems of metal hydrolysis and migration in the electrode layer 102.

[0099] Step S106: Fig.10As shown, a passivation protection layer 105 is prepared. The passivation protection layer 105 can be grown on the entire surface, and openings are formed in the passivation protection layer 105 corresponding to the first electrode 17 and the second electrode 18 by photolithography and wet etching processes to expose the first electrode 17 and the second electrode 18, so as to facilitate the connection of the electrode layer 102 with an external circuit.

[0100] A 390nm thick SiO2 film can be deposited on the entire surface as a passivation protective layer 105, and then a photolithography process is used to form a photolithography pattern. Then, the passivation protective layer 105 at the positions of the first electrode 17 and the second electrode 18 is removed by a wet etching process to expose the first electrode 17 and the second electrode 18.

[0101] Finally, the formation Figure 2 The light emitting diode shown has low operating voltage and high ESD performance.

[0102] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. The implementation methods provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0103] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0104] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0105] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0106] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A light emitting diode, characterized in that: include: substrate; The epitaxial layer includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer sequentially formed on a surface of the substrate; The edge of the epitaxial layer has a step structure exposing the first semiconductor layer; a transparent conductive layer located on a surface of the second semiconductor layer; The transparent conductive layer has a plurality of through holes exposing the second semiconductor layer; A metal layer located on the surface of the transparent conductive layer, at least used for ohmic contact with the second semiconductor layer and for current spreading; The metal layer covers the sidewalls and bottoms of the plurality of through holes, and is electrically connected to the second semiconductor layer at the plurality of through holes; the metal layer exposes an edge portion of the transparent conductive layer; The electrode layer includes a first electrode and a second electrode; the first electrode is located at the bottom of the step structure and is electrically connected to the first semiconductor layer; the second electrode is located on the surface of the metal layer and is electrically connected to the metal layer.

2. The light emitting diode according to claim 1, characterized in that: The first semiconductor layer has a first thickness; The bottom of the stepped structure extends into the first semiconductor layer, and a portion of the first semiconductor layer below the stepped structure has a second thickness that is less than or equal to one third of the first thickness.

3. The light emitting diode according to claim 1, characterized in that: The shape of the through hole includes at least one of a circle, an ellipse and a polygon.

4. The light emitting diode according to claim 1, characterized in that: The plurality of through holes include a first through hole and a plurality of second through holes arranged around the first through hole, and the area of ​​the first through hole is larger than the area of ​​the second through holes; The second electrode is disposed opposite to the first through hole.

5. The light emitting diode according to claim 4, characterized in that: The second through holes are all the same; Alternatively, at least two of the second through holes are different.

6. The light emitting diode according to claim 1, characterized in that: The transparent conductive layer is an ITO film.

7. The light emitting diode according to claim 1, characterized in that: The metal layer includes at least one metal film.

8. The light emitting diode according to claim 7, characterized in that: The at least one metal film layer includes at least one of an Ag film, a Ti film, a TiW film, a Cr film, a NiAu film and a NiAg film.

9. The light emitting diode according to claim 1, characterized in that: The side wall inclination angle of the step structure ranges from 5° to 50°.

10. The light emitting diode according to claim 1, characterized in that: The substrate has a buffer layer on its surface, and the epitaxial layer is formed on the surface of the buffer layer.

11. The light emitting diode according to claim 1, characterized in that: The maximum width of the through hole on a plane parallel to the substrate is 6 μm to 20 μm.

12. The light emitting diode according to claim 1, characterized in that: The distance between adjacent through holes is not less than 5 μm.

13. The light emitting diode according to claim 1, characterized in that: The transparent conductive layer comprises: a first region and a second region surrounding the first region, and the plurality of through holes are located in the first region; The metal layer is located above the first area and does not overlap with the second area. The metal layer has a hollow area, and the hollow area does not overlap with the through hole.

14. The light emitting diode according to claim 1, characterized in that: The area of ​​the plurality of through holes accounts for no less than 70% of the area of ​​the transparent conductive layer.

15. The light emitting diode according to claim 1, characterized in that: The thickness of the transparent conductive layer is in the range of 50nm to 150nm; The thickness of the metal layer is in the range of 1 nm to 10 nm.

16. The light emitting diode according to any one of claims 1 to 15, characterized in that: Also includes: A passivation protective layer covers the surface of the metal layer, the surface of the transparent conductive layer, the surface of the epitaxial layer, and the sidewall and bottom of the step structure, and exposes at least a portion of the first electrode and the second electrode.

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