Test chip for testing optical performance of wafer-level optical waveguide and packaging structure of test chip

Abstract

The embodiment of the utility model provides a test chip for testing the optical performance of a wafer-level optical waveguide and a packaging structure thereof, and the test chip comprises a light inlet end face which enables test light to enter the test chip in a coupling manner; the waveguide is used for transmitting the test light to the transmitting end grating; the transmitting end grating is used for coupling the test light rays into the receiving end grating of the wafer to be tested, coupling the test light rays into a waveguide pattern area to be tested of the wafer to be tested through the receiving end grating of the wafer to be tested and then conducting the test light rays to the transmitting end grating of the wafer to be tested; the light passing through the to-be-tested waveguide pattern area is coupled by the transmitting end grating of the to-be-tested wafer and is incident to the receiving end grating of the test chip; and the receiving end grating couples the received light into the waveguide of the test chip and then emits the light through the end face of the light outlet, and the emitted light is used for determining optical performance parameters. The utility model also provides a packaging structure for realizing the test function of the test chip. According to the scheme, the optical performance test of the wafer-level optical waveguide is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of silicon light, and in particular to a test chip for testing the optical performance of a wafer-level optical waveguide and a packaging structure thereof. Background Art

[0002] With the development of silicon photonics technology, the requirements for the efficiency and stability of silicon photonics wafer / chip testing are becoming increasingly higher; especially in the mass production stage, the demand for testing and inspection of large-scale silicon photonics integrated chips is becoming increasingly clear.

[0003] Currently, wafers fabricated using silicon photonics processes can only be tested for film refractive index before dicing. Testing the optical performance parameters of chip waveguides, such as transmission loss and splitting ratio, requires testing after the wafer is diced. This means large-scale optical waveguide performance testing cannot be performed on silicon photonics wafers before dicing. Utility Model Content

[0004] In view of this, the present invention provides a test chip for wafer-level optical waveguide optical performance testing to solve the technical problem in the prior art of being unable to perform large-scale optical waveguide optical performance testing on silicon photonic wafers before dicing. The test chip includes:

[0005] The light inlet end face 26 is used to couple the test light into the test chip 21;

[0006] A waveguide 24 for transmitting the test light to the emission end grating 27;

[0007] The transmitting-end grating 27 is used to couple the test light into the receiving-end grating of the wafer to be tested 29, and couple the test light into the waveguide pattern area to be tested of the wafer to be tested 29 through the receiving-end grating of the wafer to be tested 29, and then transmit the test light to the transmitting-end grating of the wafer to be tested 29. The light passing through the waveguide pattern area to be tested is coupled to the receiving-end grating 28 of the test chip 21 through the transmitting-end grating of the wafer to be tested 29. The channel conditions of the waveguide 24, the transmitting-end grating 27, and the receiving-end grating 28 are consistent with the channel conditions of the wafer to be tested 29.

[0008] The receiving end grating 28 is used to couple the received light into the waveguide of the test chip 21 and then emit it through the light outlet end face 25. The emitted light is used to characterize the optical performance parameters of the waveguide graphic area to be tested.

[0009] The present invention also provides a packaging structure for a test chip used for wafer-level optical waveguide optical performance testing to address the prior art problem of being unable to perform large-scale optical waveguide optical performance testing on silicon photonic wafers before dicing. The packaging structure includes:

[0010] an adapter board 12 coupled and aligned with the pad 22 of the test chip 21 , the adapter board 12 being used to power the pad 22 ;

[0011] PCB board 13, the test chip 21 and the adapter board 12 are fixed on the PCB board 13;

[0012] A substrate 14 on which the PCB board 13 is fixed;

[0013] The optical fiber array pigtail bracket 15 is fixed to the back side of the substrate 14;

[0014] The optical fiber array 16 has its head coupled and solidified with the test chip 21, and its tail is fixed to the optical fiber array pigtail holder 15. The optical fiber array 16 is used to couple the test light into the test chip 21 through the light inlet end face 26, and emit the light emitted from the light outlet end face 25.

[0015] Compared with the prior art, the beneficial effects achieved by at least one of the above technical solutions adopted in the embodiments of this specification include at least the following: proposing to couple the test light into the test chip 21 through the light inlet end face, and then the waveguide 24 transmits the test light to the emitting end grating 27, the emitting end grating 27 couples the test light into the receiving end grating of the wafer to be tested 29, and the test light is coupled into the waveguide graphic area to be tested of the wafer to be tested 29 through the receiving end grating of the wafer to be tested 29 and then transmitted to the emitting end grating of the wafer to be tested 29, and the light passing through the waveguide graphic area to be tested is coupled to the emitting end grating of the wafer to be tested 29 through the emitting end grating of the wafer to be tested The receiving end grating 28 of the test chip 21, finally, the receiving end grating 28 couples the received light into the waveguide of the test chip 21 and then emits it through the light output end face 25, that is, the test light is coupled into the waveguide graphic area to be tested of the wafer to be tested through the test chip 21, and then the light passing through the waveguide to be tested of the wafer to be tested is emitted through the test chip 21, and then the optical performance parameters of the waveguide graphic area to be tested can be characterized based on the emitted light, so that the optical performance test of the optical waveguide can be performed on the wafer before dicing through the test chip 21, which solves the technical problem that large-scale optical performance test of the optical waveguide cannot be performed on the silicon photonic wafer before dicing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 This is a schematic structural diagram of a test chip for wafer-level optical waveguide optical performance testing provided by an embodiment of the present utility model;

[0018] Figure 2 This is a schematic diagram of a packaging structure of a test chip for wafer-level optical waveguide optical performance testing provided by an embodiment of the present utility model;

[0019] Figure 3 This is a schematic diagram of coupling between a test chip and a wafer to be tested provided by an embodiment of the present utility model;

[0020] Figure 4 This is a principle block diagram of a wafer test using the packaging structure of the test chip for wafer-level optical waveguide optical performance testing provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0022] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0023] In an embodiment of the present invention, a test chip for testing the optical performance of a wafer-level optical waveguide is provided. Figure 1 As shown, the test chip includes:

[0024] The light inlet end face 26 is used to couple the test light into the test chip 21;

[0025] A waveguide 24 for transmitting the test light to the emission end grating 27;

[0026] The transmitting-end grating 27 is used to couple the test light into the receiving-end grating of the wafer to be tested 29, and couple the test light into the waveguide pattern area to be tested of the wafer to be tested 29 through the receiving-end grating of the wafer to be tested 29, and then transmit the test light to the transmitting-end grating of the wafer to be tested 29. The light passing through the waveguide pattern area to be tested is coupled to the receiving-end grating 28 of the test chip 21 through the transmitting-end grating of the wafer to be tested 29. The channel conditions of the waveguide 24, the transmitting-end grating 27, and the receiving-end grating 28 are consistent with the channel conditions of the wafer to be tested 29.

[0027] The receiving end grating 28 is used to couple the received light into the waveguide of the test chip 21 and then emit it through the light outlet end face 25. The emitted light is used to characterize the optical performance parameters of the waveguide graphic area to be tested.

[0028] Depend on Figure 1 As shown, in the embodiment of the present invention, the test light is coupled to the waveguide graphic area to be tested of the wafer to be tested through the test chip 21, and then the light passing through the waveguide to be tested of the wafer to be tested is emitted through the test chip 21, and then the optical performance parameters of the waveguide graphic area to be tested can be characterized based on the emitted light, so that the optical performance test of the optical waveguide can be performed on the wafer before dicing through the test chip 21, which solves the technical problem that large-scale optical waveguide optical performance test cannot be performed on silicon photonic wafers before dicing.

[0029] During specific implementation, in order to achieve optical coupling between the test chip 21 and the wafer to be tested 29, the channel conditions of the waveguide 24, the transmitting end grating 27 and the receiving end grating 28 of the test chip 21 are consistent with the channel conditions of the wafer to be tested 29, for example, the number of channels is consistent, so that each channel between the grating coupler of the test chip 21 and the grating coupler of the wafer to be tested 29 is aligned one by one.

[0030] In specific implementation, in order to realize thermal modulation of the modulation area of ​​the waveguide 24, thereby controlling the on-off of each waveguide 24, and then controlling the on-off of each transmitting end grating 27 and receiving end grating 28, the test chip 21 can be used to test the performance of the waveguides and passive components on the wafer to be tested. Figure 1As shown, this embodiment proposes that the above-mentioned test chip for wafer-level optical waveguide optical performance testing further includes: a pad 22; a thermode 23, wherein the thermode 23 is arranged on the waveguide 24, and is used to realize that the thermode 23 performs thermal modulation on the modulation area of ​​the waveguide 24 when the pad 22 is energized, thereby controlling the on-off of each waveguide 24, and further controlling the on-off of each transmitting end grating 27 and the receiving end grating 28, so that the test light can be transmitted to different waveguide graphic areas to be tested on the wafer 29 to be tested (inside the wafer 29 to be tested, different waveguide graphic areas to be tested are coupled or connected with different transmitting end grating channels and receiving end grating channels, respectively) for optical performance testing.

[0031] In a specific implementation, the distance between the pad 22 and the dicing line or polishing edge can be in the range of 100 μm to 200 μm, and the pad 22 is exposed to one side through dicing and end polishing. For example, the end surface of the test chip 21 and the edges of the pads 22 on both sides are ground and polished.

[0032] During specific implementation, the grating coupler of the test chip 21 is aligned with the grating coupler of the wafer to be tested 29 (i.e., each channel of the grating at the transmitting end of the test chip 21 is aligned and coupled with each channel of the grating at the receiving end of the wafer to be tested 29, and each channel of the grating at the transmitting end of the wafer to be tested 29 is aligned and coupled with each channel of the grating at the receiving end of the test chip 21). In order to improve the coupling efficiency, the coupling distance between the test chip 21 and the wafer to be tested 29 is strictly required. During the test process, the coupling distance between the upper surface of the test chip 21 and the wafer to be tested 29 is in the range of 5μm-15μm. For example, the coupling distance requirement between the test chip 21 and the wafer to be tested 29 can be ensured by ensuring that there are no protruding structures larger than 15μm on the upper surface of the test chip 21 during the test.

[0033] In specific implementation, the test chip 21 can be manufactured using any feasible process. However, in order to ensure that the processing technology of the test chip 21 is compatible with the silicon photonics platform chip process, without the need for backhole holes or flange electrodes, and to complete the processing of the wafer to be tested and the test chip in a single tape-out, thereby reducing tape-out costs, this embodiment proposes that the test chip 21 and the wafer to be tested 29 are simultaneously processed using the same silicon photonics technology platform in the same tape-out, and the test chip 21 is obtained by dicing the wafer to be tested 29. For example, in the same tape-out, the test chip 21 can be obtained by dicing at a corner of the wafer to be tested 29, without having to fully scribe the wafer in order to perform optical performance testing on the optical waveguide of the wafer.

[0034] In specific implementation, in order to realize large-scale optical waveguide optical performance testing of silicon photonic wafers conveniently and efficiently before dicing, the utility model also proposes a packaging structure of a test chip for wafer-level optical waveguide optical performance testing, such as Figure 2 As shown, the packaging structure includes:

[0035] an adapter board 12 coupled and aligned with the pad 22 of the test chip 21 , the adapter board 12 being used to power the pad 22 ;

[0036] PCB board 13, the test chip 21 and the adapter board 12 are fixed on the PCB board 13;

[0037] A substrate 14 on which the PCB board 13 is fixed;

[0038] The optical fiber array pigtail bracket 15 is fixed (for example, by screws) to the back side of the substrate 14;

[0039] The optical fiber array 16 has its head coupled and solidified with the test chip 21, and its tail is fixed to the optical fiber array pigtail holder 15. The optical fiber array 16 is used to couple the test light into the test chip 21 through the light inlet end face 26, and emit the light emitted from the light outlet end face 25.

[0040] In a specific implementation, for example, the pads 22 of the test chip 21 can be powered through the driving / control system, the PCB board 13 and the adapter board 12, thereby achieving switching control of each channel waveguide.

[0041] In a specific implementation, the test chip 21 can be mounted on the PCB board 13 via a thermally conductive adhesive patch. For example, the thermally conductive adhesive can be any one of silicone thermally conductive adhesive, epoxy resin thermally conductive adhesive, polyurethane thermally conductive adhesive, and UV-curable thermally conductive adhesive.

[0042] In a specific implementation, the pads 22 of the test chip 21 are connected to the channels of the adapter board 12 via conductive adhesive, and the adapter board 12 is connected to the pad channels of the PCB 13 via conductive adhesive. For example, the conductive adhesive can be any one of low-temperature conductive silver adhesive, nano-conductive silver adhesive, and conductive copper adhesive; and the adapter board 12 can be any one of a quartz adapter board, a ceramic adapter board, and a silicon adapter board.

[0043] In a specific implementation, the head of the optical fiber array 16 is fixed to the end face of the test chip 21 by UV glue to achieve optical coupling with the test chip 21, and the tail of the optical fiber array 16 is fixed to the optical fiber array pigtail holder 15 by UV glue. For example, the UV glue can be any one of high-refractive-index and low-thermal-expansion acrylic UV glue, polyurethane UV glue, and epoxy resin UV glue.

[0044] During specific implementation, the specific form and shape of the optical fiber array pigtail bracket 15 are not specifically limited in this application, and it only needs to be able to fix and support the optical fiber array 16 and the substrate 14.

[0045] In specific implementation, in order to further ensure the coupling distance requirement between the upper surface of the test chip 21 and the wafer to be tested 29, as shown in FIG. Figure 2 As shown, it is proposed that the upper surface of the adapter plate 12, the upper surface of the PCB board 13, and the head of the optical fiber array 16 are all lower than the upper surface of the test chip 21, that is, they do not protrude from the upper surface of the test chip 21, as shown in FIG. Figure 3 As shown, when the upper surface of the test chip 21 is coupled with the wafer 29 to be tested, the coupling distance can be ensured to be as small as possible, within the range of 5 μm-15 μm.

[0046] When implementing it specifically, Figure 4 As shown, the process of testing a wafer using the packaging structure of the test chip for wafer-level optical waveguide optical performance testing can be achieved by the following method:

[0047] The switch control of each channel waveguide of the test chip 21 is realized by the drive / control system-PCB board 13-adapter board 12. The test light emitted by the laser is coupled into the test chip 21 through the optical fiber array 16 and the light inlet end face 26. It reaches the transmitting end grating 27 of the test chip 21 through the control of each channel waveguide 24 of the test chip 21. It is coupled to the receiving end grating of the wafer 29 to be tested through the transmitting end grating 27 of the test chip 21. It is then coupled into the waveguide graphic area to be tested on the wafer 29 to be tested through the receiving end grating of the wafer 29 to be tested. The light from the waveguide is transmitted to the emitting end grating of the wafer to be tested 29, and then coupled to the receiving end grating 28 of the test chip 21 through the emitting end grating of the wafer to be tested 29, coupled into the waveguide of the test chip 21 through the receiving end grating 28 of the test chip 21, and coupled into the optical fiber array 16 through the waveguide of the test chip 21 through the light outlet end face 25, and then emitted through the optical fiber array 16 and received by the detector. By comparing the light data received by the detector with the test light, key optical performance parameters such as transmission loss and splitting ratio of the waveguide graphic area to be tested on the wafer to be tested 29 can be obtained.

[0048] The embodiments of the present utility model achieve the following technical effects: the test light is coupled into the waveguide graphic area to be tested of the wafer to be tested through the test chip 21, and the light passing through the waveguide to be tested of the wafer to be tested is then emitted through the test chip 21, and the optical performance parameters of the waveguide graphic area to be tested can be characterized based on the emitted light. This allows the test chip 21 to be used to test the optical performance of the optical waveguide of the wafer before dicing, solving the technical problem of being unable to perform large-scale optical waveguide optical performance testing on silicon photonics wafers before dicing.

[0049] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of the present invention can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, optionally, they can be implemented using program codes executable by the computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the embodiments of the present invention are not limited to any specific combination of hardware and software.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A test chip for wafer-level optical waveguide optical performance testing, characterized in that: include: A light inlet end face (26) for coupling test light into the test chip (21); a waveguide (24) for transmitting the test light to the emission end grating (27); The transmitting end grating (27) is used to couple the test light into the receiving end grating of the wafer to be tested (29), and couple the test light into the waveguide graphic area to be tested of the wafer to be tested (29) through the receiving end grating of the wafer to be tested (29) and then transmit it to the transmitting end grating of the wafer to be tested (29), and the light passing through the waveguide graphic area to be tested is coupled to the receiving end grating (28) of the test chip (21) through the transmitting end grating of the wafer to be tested (29), wherein the channel conditions of the waveguide (24), the transmitting end grating (27) and the receiving end grating (28) are consistent with the channel conditions of the wafer to be tested (29); The receiving end grating (28) is used to couple the received light into the waveguide of the test chip (21) and then emit it through the light outlet end face (25). The emitted light is used to characterize the optical performance parameters of the waveguide graphic area to be tested.

2. The test chip for wafer-level optical waveguide optical performance testing according to claim 1, wherein: Also includes: pad (22); A thermocouple (23) is provided on the waveguide (24) and is used for enabling the thermocouple (23) to perform thermal modulation on the modulation area of ​​the waveguide (24) when the pad (22) is powered, so as to control the on / off of each waveguide (24), and further control the on / off of each transmitting end grating (27) and the receiving end grating (28), so as to conduct the test light to different waveguide pattern areas to be tested on the wafer (29) to perform optical performance testing.

3. The test chip for wafer-level optical waveguide optical performance testing according to claim 2, wherein: The distance between the pad (22) and the dicing road or the polishing edge ranges from 100 μm to 200 μm.

4. The test chip for wafer-level optical waveguide optical performance testing according to any one of claims 1 to 3, characterized in that: The grating coupler of the test chip (21) is aligned with the grating coupler of the wafer to be tested (29). During the test process, the coupling spacing between the upper surface of the test chip (21) and the wafer to be tested (29) is in the range of 5 μm to 15 μm.

5. The test chip for wafer-level optical waveguide optical performance testing according to any one of claims 1 to 3, characterized in that: The test chip (21) and the wafer to be tested (29) are processed simultaneously in one tape-out through the same silicon photonics technology platform, and the test chip (21) is obtained by dicing the wafer to be tested (29).

6. A packaging structure of a test chip for wafer-level optical waveguide optical performance testing according to any one of claims 1 to 5, characterized in that: include: an adapter plate (12) coupled and aligned with the pad (22) of the test chip (21), the adapter plate (12) being used to power the pad (22); A PCB board (13), on which the test chip (21) and the adapter board (12) are fixed; A substrate (14), the PCB board (13) being fixed on the substrate (14); An optical fiber array pigtail bracket (15) is fixed to the back side of the substrate (14); An optical fiber array (16) is provided. The head of the optical fiber array (16) is coupled and solidified with the test chip (21). The tail of the optical fiber array (16) is fixed to the optical fiber array pigtail bracket (15). The optical fiber array (16) is used to couple the test light into the test chip (21) through the light inlet end face (26) and emit the light emitted from the light outlet end face (25).

7. The packaging structure according to claim 6, wherein: The test chip (21) is placed on the PCB board (13) via a thermally conductive adhesive patch.

8. The packaging structure according to claim 6, wherein: The pads (22) of the test chip (21) are connected to the channels of the adapter board (12) via conductive glue, and the adapter board (12) is connected to the pads of the PCB board (13) via conductive glue.

9. The packaging structure according to claim 6, wherein: The head of the optical fiber array (16) is fixed on the end face of the test chip (21) by UV glue to achieve optical coupling with the test chip (21), and the tail of the optical fiber array (16) is fixed on the optical fiber array pigtail bracket (15) by UV glue.

10. The packaging structure according to claim 6, wherein: The upper surface of the adapter plate (12), the upper surface of the PCB board (13), and the head of the optical fiber array (16) are all lower than the upper surface of the test chip (21).

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