Chip cavity packaging structure

Abstract

This application provides a chip cavity packaging structure, relating to the field of semiconductor technology. The chip cavity packaging structure includes a substrate, a chip, a film layer, and a molding compound. The chip is mounted on the substrate, and the chip and substrate are electrically connected. The film layer covers the chip, and the film layer forms a sealed cavity between the chip and the substrate. The molding compound encapsulates the chip and the film layer; a groove is formed on the molding compound, and metal pillars are placed within the groove. The vertical isolation structure formed by the metal pillars has excellent blocking effect on vertically propagating sound waves, preventing signal interference between chips, and also has good heat dissipation characteristics.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a chip cavity packaging structure. Background Technology

[0002] With the rapid development of the semiconductor industry, surface acoustic wave (SAW) filters are widely used in receiver front-ends, duplexers, and receiver filters. SAW filter chips typically use lithium tantalate or lithium niobate materials. Utilizing the piezoelectric properties of these materials, input and output transducers convert the input electromagnetic signal into mechanical energy. After processing, the mechanical energy is then converted back into an electrical signal, thus filtering out unwanted signals and noise and improving reception quality.

[0003] Traditional electronic devices integrate different types of filter chips to receive and transmit different sound wave signals. Adjacent sound wave signals are prone to generating resonance waves or noise, thus causing signal interference. Utility Model Content

[0004] The purpose of this invention is to provide a chip cavity packaging structure that can effectively prevent signal interference between chips and make signal transmission more stable.

[0005] This utility model provides a chip cavity packaging structure, including:

[0006] substrate;

[0007] A chip, which is mounted on the substrate and electrically connected to the substrate;

[0008] A film layer that covers the chip and forms a sealed cavity between the chip and the substrate;

[0009] A molding compound, which encapsulates the chip and the film layer; the molding compound has a groove, and a metal pillar is provided in the groove.

[0010] In an optional embodiment, a metal layer is provided at the bottom of the groove, and the metal pillar is connected to the metal layer.

[0011] In an alternative embodiment, the height of the metal column is less than or flush with the depth of the groove.

[0012] In an optional embodiment, the groove is filled with an adhesive layer that completely or partially fills the groove.

[0013] In an optional embodiment, the substrate is provided with a plurality of the chips; the molding compound is provided with a plurality of the grooves; the grooves are correspondingly disposed in the intervals between adjacent chips.

[0014] In an optional embodiment, a bridging wire is also included, one end of which is connected to a metal post in one of the grooves, and the other end is connected to a metal post in the other groove.

[0015] In an optional implementation, the multiple bridge-connecting wires are arranged in parallel or staggered configurations.

[0016] In an optional embodiment, the bridging wire protrudes from the surface of the encapsulation.

[0017] In an optional embodiment, the bottom of the groove is higher than the film layer.

[0018] In an optional embodiment, the substrate is provided with a solder resist layer.

[0019] The chip cavity packaging structure provided in this embodiment of the utility model has the following advantages:

[0020] The chip cavity packaging structure provided in this embodiment of the utility model can effectively reflect and absorb sound waves propagating between chips by setting metal pillars. In particular, the vertical isolation structure formed by the metal pillars has an excellent blocking effect on vertically propagating sound waves, which can prevent signal interference between chips and has good heat dissipation characteristics. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 A schematic diagram of a first type of chip cavity packaging structure provided in an embodiment of this utility model;

[0023] Figure 2 This is a schematic diagram of a second structure of the chip cavity packaging structure provided in an embodiment of the present utility model;

[0024] Figure 3 This is one of the process diagrams of the chip cavity packaging structure provided in the embodiments of this utility model;

[0025] Figure 4 The second schematic diagram of the manufacturing process of the chip cavity packaging structure provided in this embodiment of the present utility model.

[0026] Icons: 100-Chip cavity package structure; 110-Substrate; 111-Pad; 112-Solder resist layer; 120-Chip; 121-Bump; 130-Film layer; 131-Sealed cavity; 140-Molded body; 141-Groove; 151-Metal layer; 152-Metal pillar; 153-Adhesive layer; 154-Bridging wire bonding. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0029] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0030] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this utility model is in use. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0032] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0033] The following detailed description, in conjunction with the accompanying drawings, outlines some embodiments of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0034] This utility model provides a chip cavity packaging structure that is suitable for surface acoustic wave filters and other packaging devices that require the formation of a working cavity.

[0035] Please combine Figure 1 The chip cavity packaging structure 100 includes a substrate 110, a chip 120, a film layer 130, and a molding compound 140. The chip 120 is mounted on the substrate 110, and the chip 120 and the substrate 110 are electrically connected. The film layer 130 covers the chip 120 and forms a sealed cavity 131 between the chip 120 and the substrate 110. The molding compound 140 encapsulates the chip 120 and the film layer 130; a groove 141 is formed on the molding compound 140, and a metal pillar 152 is provided within the groove 141. The vertical isolation structure formed by the metal pillar 152 has excellent blocking effect on vertically propagating sound waves, preventing signal interference between the chips 120. Furthermore, the groove 141 and the metal pillar 152 also help improve heat dissipation performance, giving the packaging structure good heat dissipation characteristics.

[0036] A solder resist layer 112 and pads 111 are provided on the substrate 110. The solder resist layer 112 covers the surface of the substrate 110 and has openings to avoid the pads 111. The chip 120 may be a flip chip 120, including but not limited to a filter chip 120 or a gyroscope. The chip 120 is mounted by flip-chip bonding, and the bumps 121 on the chip 120 are soldered to the pads 111 to achieve electrical connection. A film layer 130 covers the chip 120 and seals the gap between the chip 120 and the substrate 110 to form a cavity. The multiple chips 120 on the substrate 110 may be chips 120 of different types and sizes.

[0037] Optionally, a metal layer 151 is provided at the bottom of the groove 141, and a metal pillar 152 is connected to the metal layer 151. In this embodiment, the metal pillar 152 is formed by vertical wire bonding. The metal layer 151 can serve as a seed layer for vertical wire bonding, improving the structural reliability of the metal pillar 152. The metal pillar 152 and the metal layer 151 can work together to block clutter and can block the propagation of clutter from different directions, thus enhancing the signal interference prevention capability.

[0038] Optionally, the height of the metal column 152 is lower than or flush with the depth of the groove 141. This makes the structure more compact, occupies less volume, and the metal column 152 does not occupy additional space in the height direction.

[0039] Of course, in some other embodiments, the height of the metal post 152 may also be greater than the depth of the groove 141, that is, the metal post 152 protrudes from the surface of the encapsulation body 140, which is not specifically limited here.

[0040] Optionally, multiple metal pillars 152 can be arranged in an array to increase the isolation effect.

[0041] Optionally, the groove 141 is filled with an adhesive layer 153, which completely or partially fills the groove 141. By providing the adhesive layer 153, the metal column 152 can be better fixed, and heat dissipation can also be improved.

[0042] It is worth noting that the adhesive layer 153 can completely fill the groove 141, or the thickness of the adhesive layer 153 can be less than the depth of the groove 141. In some embodiments, the adhesive layer 153 and the metal layer 151 can be stacked in an adhesive manner, that is, multiple layers of metal layer 151 and multiple layers of adhesive layer 153 are provided in the groove 141, and the multiple layers of metal layer 151 and multiple layers of adhesive layer 153 are alternately arranged. In this way, the multiple layers of metal layer 151 and multiple metal pillars 152 are arranged in a cross pattern, which has a better effect on blocking clutter.

[0043] The adhesive layer 153 can be made of conductive or non-conductive adhesive. Optionally, the adhesive layer 153 can be made of a thermally conductive but non-conductive material, which can meet both insulation and heat dissipation requirements.

[0044] Optionally, the substrate 110 has multiple chips 120; the molding compound 140 has multiple grooves 141; the grooves 141 are correspondingly disposed in the intervals between adjacent chips 120. This arrangement can better isolate noise signals between chips 120 and prevent signal interference between chips 120.

[0045] Of course, the number, shape, and distribution of the grooves 141 can be flexibly set according to actual needs. For example, the shape of the grooves 141 is not limited to rectangles; it can be circles or polygons, etc. No specific limitations are made here.

[0046] Please combine Figure 2 Optionally, the chip cavity package structure 100 further includes a bridging wire 154, one end of which is connected to a metal post 152 in one of the recesses 141, and the other end is connected to a metal post 152 in another recess 141. The number of bridging wires 154 can be one or more.

[0047] This embodiment includes multiple bridging wires 154. These bridging wires 154 are arranged in parallel or staggered configurations. Since the bridging wires 154 are metal wires, their use enhances noise isolation performance, better prevents signal interference, and improves heat dissipation. Optionally, the bridging wires 154 can be made of gold or copper wires of different diameters to accommodate the isolation requirements of signals at different frequencies.

[0048] Optionally, the bridging wires 154 protrude from the surface of the molding compound 140. Multiple bridging wires 154 are distributed crisscrossingly on the surface of the molding compound 140 to form a grid, which can further isolate surface noise and improve heat dissipation performance.

[0049] It should be noted that the grooves 141 are correspondingly located between adjacent chips 120, and the multiple metal pillars 152 can form an isolation wall, effectively preventing acoustic interference between different chips 120. Especially when the operating frequencies of the chips 120 are different, this isolation structure can significantly reduce resonance and noise generation. In addition, the grid-like bridging wires 154 on the surface of the molded package 140 can further block surface noise, forming a more complex acoustic wave reflection path, resulting in better isolation and improved reception quality of the packaged device.

[0050] Optionally, the bottom of the groove 141 is higher than the film layer 130. This arrangement prevents damage to the chip 120 during groove cutting and prevents damage to the film layer 130, which could lead to a decrease in the sealing performance of the sealing cavity 131 at the bottom of the chip 120. In this embodiment, it can ensure that the sealing cavity 131 at the bottom of the chip 120 has good sealing performance and is not contaminated by the molding compound 140 or other impurities, thereby improving the working performance of the sealing cavity 131.

[0051] Please combine Figure 3 and Figure 4 The chip cavity packaging structure 100 provided in this embodiment of the present invention has the following general manufacturing process:

[0052] Step S1: Provide a substrate 110 with pads 111 and a solder resist layer 112. The substrate 110 is preferably an organic substrate 110, such as a BT resin substrate 110 or an ABF thin film substrate 110, or it can be a silicon-based, germanium-based, or ceramic substrate 110. The solder resist layer 112 is a green paint layer.

[0053] Step S2: The chip 120 is mounted onto the substrate 110 by flip-chip bonding, and the bumps 121 of the chip 120 are soldered to the pads 111 of the substrate 110.

[0054] Step S3: Vacuum coating is applied to chip 120, and a sealed cavity 131 is formed at the bottom of chip 120 through film layer 130.

[0055] Step S4: Perform a molding process to form a molded body 140 that encapsulates the chip 120 and the film layer 130.

[0056] Step S5: Laser grooving is used to form grooves 141 on the molding compound 140. Other methods such as etching or electron beam grooving can also be used, which are not specifically limited here.

[0057] Step S6: Deposit a metal layer 151 at the bottom of the groove 141 as a seed layer. The metal layer 151 can be formed by electroplating, chemical plating, or sputtering processes. The metal layer 151 includes, but is not limited to, a copper layer.

[0058] Step S7: Form metal pillars 152 on the metal layer 151 using a vertical wire bonding process. The metal pillars 152 can be arranged in an array. The metal pillars 152 can be made of copper wire, gold wire, or alloy wire, etc., without specific limitations.

[0059] Step S8: Fill the groove 141 with an adhesive layer 153. The adhesive layer 153 can be a conductive or non-conductive material. The adhesive layer 153 can be filled into the groove 141 by a dispensing process.

[0060] Step S9: A bridging wire 154 is formed between the metal pillars 152 in different grooves 141. This step may be omitted in some embodiments.

[0061] Step S10: Finally, the wafer is separated into individual products through a dicing process.

[0062] In summary, the chip cavity packaging structure 100 provided by this utility model embodiment has the following beneficial effects, including:

[0063] The chip cavity packaging structure 100 provided in this embodiment of the invention, by setting metal pillars 152, can effectively reflect and absorb sound waves propagating between chips 120. In particular, the vertical isolation structure formed by the metal pillars 152 has an excellent blocking effect on vertically propagating sound waves. The metal pillars 152 and the metal layer 151 together constitute an acoustic wave isolation structure, which can effectively block the sound waves generated by the chip 120 during operation from propagating to the surroundings, reducing interference to neighboring chips 120. The setting of the bridging wire 154 can further block surface noise and improve reception quality. At the same time, the metal pillars 152, the metal layer 151, and the bridging wire 154 provide additional heat dissipation paths, which is beneficial to the heat dissipation of the chip 120 and improves the heat dissipation performance.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of this utility model.

Claims

1. A chip cavity packaging structure, characterized in that, include: substrate; A chip, which is mounted on the substrate and electrically connected to the substrate; A film layer that covers the chip and forms a sealed cavity between the chip and the substrate; A molding compound, which encapsulates the chip and the film layer; the molding compound has a groove, and a metal pillar is provided in the groove.

2. The chip cavity packaging structure according to claim 1, characterized in that, The bottom of the groove is provided with a metal layer, and the metal pillar is connected to the metal layer.

3. The chip cavity packaging structure according to claim 2, characterized in that, The height of the metal column is less than or flush with the depth of the groove.

4. The chip cavity packaging structure according to claim 1, characterized in that, The groove is filled with an adhesive layer, which either completely or partially fills the groove.

5. The chip cavity packaging structure according to claim 1, characterized in that, The substrate has a plurality of chips; the molding compound has a plurality of grooves; the grooves are correspondingly arranged in the intervals between adjacent chips.

6. The chip cavity packaging structure according to claim 1, characterized in that, It also includes a bridging wire, one end of which is connected to a metal post in one of the grooves, and the other end of which is connected to a metal post in the other groove.

7. The chip cavity packaging structure according to claim 6, characterized in that, Multiple bridge connecting wires are arranged in parallel or staggered configurations.

8. The chip cavity packaging structure according to claim 6, characterized in that, The bridge-connecting wire protrudes from the surface of the encapsulated body.

9. The chip cavity packaging structure according to claim 1, characterized in that, The bottom of the groove is higher than the membrane layer.

10. The chip cavity packaging structure according to any one of claims 1 to 9, characterized in that, The substrate has a solder resist layer.

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