Chip package structure
By setting buffer trenches and filling them with material on the packaging substrate, the problem of chip stress concentration in flip chip ball grid array packaging is solved, the stability and reliability of the packaging structure are improved, and miniaturization and high performance of the packaging are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING X RING TECHNOLOGY CO LTD
- Filing Date
- 2025-05-09
- Publication Date
- 2026-06-23
Smart Images
Figure CN224402110U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a chip packaging structure. Background Technology
[0002] Flip Chip Ball Grid Array (FCBGA) is a mainstream technology for high-end chip packaging. Its package cover (Lid) plays an important role in protecting the chip, providing support, and assisting in heat dissipation. Summary of the Invention
[0003] To address the above problems, this application provides a chip packaging structure, including:
[0004] A packaging substrate has opposing first and second surfaces, the first surface including a chip mounting region and a stress buffer surrounding the chip mounting region;
[0005] The chip is located within the chip mounting area;
[0006] At least one of the chip mounting area and the stress buffer zone has at least one buffer trench, which extends from the first surface toward the second surface and at least partially penetrates the packaging substrate.
[0007] In one embodiment, the buffer trench extends from the first surface to the second surface and penetrates the packaging substrate.
[0008] In one embodiment, the depth of the buffer trench is 30%-90% of the thickness of the packaging substrate.
[0009] In one embodiment, the plurality of said buffer trenches are connected; or
[0010] The buffer trenches are arranged at intervals.
[0011] In one embodiment, the stress buffer includes four trapezoidal sub-regions, the upper bases of which are connected end to end and surround the boundary of the chip mounting area. Adjacent trapezoidal sub-regions share a common side connection, and at least one buffer groove is formed in each trapezoidal sub-region.
[0012] In one embodiment, the buffer groove includes a first sub-buffer groove and a second sub-buffer groove. The extension direction of the first sub-buffer groove is parallel to the upper base of the trapezoidal sub-region in which it is located, and the extension direction of the second sub-buffer groove is perpendicular to the common side.
[0013] Each trapezoidal sub-region shall have at least one of the first sub-buffer slots; and / or
[0014] Each trapezoidal sub-region is provided with a portion of the second sub-buffer slot.
[0015] In one embodiment, when the buffer trench is formed in the chip mounting area, the orthographic projection of the buffer trench on the packaging substrate at least partially overlaps with the orthographic projection of the chip on the packaging substrate.
[0016] In one embodiment, the chip packaging structure further includes a filler layer, the surface of the chip is provided with a plurality of interconnects, the chip is connected to the packaging substrate through the interconnects, and the filler layer fills the space between the chip and the packaging substrate and encapsulates the interconnects.
[0017] In one embodiment, the cross-section of the buffer groove is any one of a rectangle, a regular trapezoid, an inverted trapezoid, a semicircle, a semi-ellipse, a triangle, a sector, or an irregular shape.
[0018] In one embodiment, the buffer groove is filled with any one of silicone material, polymer material, rubber material, or composite material.
[0019] In one embodiment, the chip packaging structure further includes a first packaging cover, and the first surface further includes a connection area arranged around the stress buffer.
[0020] The first encapsulation cover is located within the connection area, and the side of the first encapsulation cover closest to the encapsulation substrate is bonded to the first surface.
[0021] In one embodiment, the chip packaging structure further includes a second packaging cover, which is at least partially bonded to the chip, and the orthographic projection of the chip on the packaging substrate falls within the orthographic projection of the second packaging cover on the packaging substrate.
[0022] In one embodiment, the first encapsulation cover and the second encapsulation cover are an integral structure.
[0023] The technical solutions provided by the embodiments of this application may include the following beneficial effects:
[0024] As described in the above embodiments, the chip packaging structure of this application includes a packaging substrate and a chip. A first surface of the packaging substrate has a chip mounting area and a stress buffer surrounding it. The chip is located within the chip mounting area. At least one region in the chip mounting area and the stress buffer has at least one buffer trench, which extends from the first surface to the second surface and at least partially penetrates the packaging substrate. By providing buffer trenches on the packaging substrate, this application can effectively reduce stress concentration on the chip, thereby reducing the stress impact on the chip during package cover mounting and improving the reliability and stability of the packaging structure.
[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the description are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a schematic diagram of the chip packaging structure provided in one embodiment of this application from a single perspective.
[0028] Figure 2 This is another schematic diagram of the chip packaging structure provided in one embodiment of this application from one viewpoint.
[0029] Figure 3 This is another schematic diagram of the chip packaging structure provided in one embodiment of this application from one perspective.
[0030] Figure 4 This is another schematic diagram of the chip packaging structure provided in one embodiment of this application from a different perspective.
[0031] Figure 5 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0032] Figure 6 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0033] Figure 7 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0034] Figure 8 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0035] Figure 9 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0036] Figure 10 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0037] Figure 11 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0038] Figure 12 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0039] Figure 13 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0040] Figure 14 This is a schematic diagram of the structure of the packaging substrate provided in one embodiment of this application from a certain perspective.
[0041] Figure 15 This is a block diagram of an electronic device provided in one embodiment of this application.
[0042] Figure label:
[0043] 10. Packaging substrate; 10a. First surface; 10b. Second surface; 100. Chip mounting area; 200. Stress buffer zone; 300. Connection area; 2001. First trapezoidal sub-region; 2002. Second trapezoidal sub-region; 2003. Third trapezoidal sub-region; 2004. Fourth trapezoidal sub-region; 101. Buffer trench; 1010. First sub-buffer trench; 1011. Second sub-buffer trench.
[0044] 20. Chip; 21. Interconnect; 30. Filler layer; 40. First package cover; 50. Second package cover; 60. Ball grid array ball.
[0045] a. First side; b. Second side; c. Third side; d. Fourth side. Detailed Implementation
[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. Various modifications, variations, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but can be changed as will become apparent upon understanding this disclosure, except for operations that must be performed in a particular order. Furthermore, descriptions of features known in the art may be omitted for clarity and brevity. The modes described in the following exemplary embodiments do not represent all modes consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.
[0047] Flip chip (FC) technology is a mainstream advanced packaging technology. This technology involves growing bumps on the front side of the chip, then flipping the chip over so that the bumps are flip-bonded to the substrate (FC bond) for interconnection. Compared to traditional wire bonding, FC technology offers more I / O interfaces and better electrical and thermal performance, thus enjoying widespread market application. Currently, common flip chip packaging methods include FCCSP (Flip Chip Scale Package) and FCBGA (Flip Chip Ball Grid Array). FCCSP is generally used in products with small-sized bare chips, while FCBGA is generally used in products with large-sized bare chips.
[0048] As described in the background section, in FCBGA (Flip Chip Ball Grid Array Package), the chip is typically thicker, and a lid is installed around the substrate to reduce compressive stress (Cop) and warpage of the package unit. However, in order to minimize package size, the ratio of chip area to substrate area is constantly increasing, resulting in the lid being too close to the chip. This causes the chip to be subjected to greater stress, making it prone to die cracks or molding compound cracks (UF cracks). The stress risk at the chip package interface (CPI) also increases accordingly.
[0049] In related technologies, methods to reduce chip stress often involve reducing chip thickness or decreasing the ratio of chip area to substrate area. However, these methods have limitations and struggle to minimize package size. Once the package size increases, issues like cop (compressive stress) and warpage become more prominent, and the risk of chip stress cannot be minimized. Therefore, there is an urgent need for a packaging solution that can fundamentally reduce chip stress through structural innovation without increasing package size.
[0050] Based on this, this application provides a chip packaging structure, referring to... Figure 1 and Figure 5 The package includes a packaging substrate 10, a chip 20, and a filler layer 30. The packaging substrate 10 has opposing first surfaces 10a and second surfaces 10b. The first surface 10a includes a chip mounting region 100 and a stress buffer 200 surrounding the chip mounting region 100.
[0051] Chip 20 is located within chip mounting area 100, and a plurality of interconnects 21 are disposed on the side of chip 20 closest to package substrate 10. Chip 20 is connected to the first surface 10a of package substrate 10 through the plurality of interconnects 21. Filler layer 30 fills the space between chip 20 and package substrate 10 and encapsulates the plurality of interconnects 21.
[0052] Specifically, this application does not limit the structure of the packaging substrate 10, as long as it can transmit the signal from the first surface 10a to the second surface 10b.
[0053] Specifically, this application does not limit the number of chips connected on the packaging substrate 10. For example, refer to... Figures 1-4 A chip 20 is disposed on the packaging substrate 10.
[0054] Specifically, this application does not limit the structure of chip 20. Chip 20 can be a bare chip (die) or a packaged chip obtained by packaging a bare chip.
[0055] It is understandable that the bare chip is obtained by dicing the wafer. The wafers obtained from the wafer fab without interconnects 21 (bumping) are diced and diced through standard wafer thinning (backside grinding, BG), laser groove sintering (LG), and die sawing (DS) processes to form bare chips.
[0056] Furthermore, when multiple chips 20 are connected on the packaging substrate 10, all of the multiple chips 20 may be bare chips; all of the multiple chips 20 may be packaged chips; or some of the multiple chips 20 may be bare chips and some may be packaged chips. This application does not impose any restrictions on this.
[0057] Specifically, the interconnect 21 can be a structure made of metal solder, such as a solder ball, bump, copper pillar, or controlled collapse chip connection bump (C4bump). This application does not limit the shape or material of the interconnect 21.
[0058] Specifically, the filler layer 30 can be configured as a filler adhesive. The filler adhesive material can be epoxy resin, silicone, polyimide, polyurethane, low-temperature curing materials, and nanocomposite materials, etc. The filler layer 30 encapsulating multiple interconnects 21 can be understood as the filler adhesive completely filling the gaps between the interconnects 21 and the chip 20 and the packaging substrate 10, forming a gapless protective layer.
[0059] Furthermore, the curing degree of the filler layer 30 near the chip 20 is greater than that near the packaging substrate 10, in order to balance stress absorption and interfacial adhesion. For example, the curing degree of the filler layer 30 near the chip 20 is greater than 95%, and the curing degree on the substrate side is 80-90%.
[0060] Furthermore, the filling method can be capillary filling, molding bottom filling, non-conductive film filling, non-conductive adhesive filling, etc. The specific method should be selected according to the actual needs, which will not be elaborated here.
[0061] This application provides a buffer trench 101 in at least one region of the chip mounting area 100 and the stress buffer zone 200. The buffer trench 101 extends from the first surface 10a of the packaging substrate 10 towards the second surface 10b and at least partially penetrates the packaging substrate 10. This effectively disperses the stress generated during the chip 20 packaging process, reduces the risk of stress concentration in the chip 20, and decreases the probability of die cracks and molding compound cracks in the chip 20. Simultaneously, this design helps alleviate package warpage, improves the stability and reliability of the package structure, optimizes package size, and achieves miniaturization and high performance of the chip 20 package.
[0062] In some embodiments, the buffer trench 101 may be left unfilled or filled with stress-reducing material. For example, the buffer trench 101 may be filled with one of the following: silicone, polymer, rubber, or composite material. Preferably, the buffer trench 101 is filled with silicone or epoxy resin. Filling the buffer trench 101 with material can effectively buffer the stress during the chip 20 packaging process, reduce the risk of chip 20 cracking and molding compound cracking, and improve the stability and reliability of the packaging structure. At the same time, these materials can also provide a certain degree of elastic support, further optimizing the mechanical properties of the package and ensuring the safety and durability of the chip during use.
[0063] In one embodiment, the buffer trench 101 can be designed as a straight line, a polygonal line, or a curve, and this application does not limit the specific shape of the buffer trench 101. Different shape designs can adapt to diverse packaging structures and stress distribution requirements. For example, straight trenches are suitable for regular layouts, while polygonal or curved trenches can be optimized for specific stress concentration areas. This flexibility makes the packaging design more adaptable, can more effectively alleviate chip stress, and improve the reliability and performance of the packaging.
[0064] In some implementations, refer to Figure 3 The buffer trench 101 extends from the first surface 10a to the second surface 10b and penetrates the packaging substrate 10. It is worth noting that this penetration means the buffer trench 101 completely penetrates the packaging substrate 10. This configuration, where the buffer trench 101 completely penetrates the packaging substrate 10, provides a larger buffer space for thermal expansion and contraction within the package, reducing internal stress caused by differences in thermal expansion coefficients. This design significantly improves the performance and durability of the package without significantly increasing its size, meeting the miniaturization and high reliability requirements of high-end chip packaging.
[0065] In some implementations, reference continues. Figure 3 When a plurality of buffer trenches 101 that completely penetrate the packaging substrate 10 are formed on the packaging substrate 10, these buffer trenches 101 are arranged at intervals to form discontinuous slots. This design ensures that each buffer trench 101 exists independently and is not connected to each other. This layout helps to disperse stress at multiple points, avoiding the formation of continuous stress transmission paths, thereby more effectively alleviating stress during the chip 20 packaging process. In addition, the discontinuous buffer trenches 101 can also prevent the structural integrity of the packaging substrate 10 from being excessively weakened, avoiding potential substrate strength reduction or debris falling problems that may be caused by trench connectivity, thereby ensuring the reliability and stability of the packaging. This discontinuous buffer trench 101 design optimizes the stress dispersion effect while taking into account the integrity and mechanical performance of the packaging structure.
[0066] In some implementations, refer to Figure 2 The depth of the buffer trench 101 is 30%-90% of the thickness of the packaging substrate 10. The direction from the first surface 10a to the second surface 10b of the packaging substrate 10 within the buffer trench 101 can be understood as the thickness direction of the packaging substrate 10. Therefore, the extension length of the buffer trench 101 is the depth of the buffer trench 101 in the packaging substrate 10.
[0067] In this embodiment, the buffer trench 101 penetrates a portion of the packaging substrate 10, and its depth is 30%-90% of the thickness of the packaging substrate 10, effectively buffering stress. The buffer trench 101 extends along the thickness direction of the packaging substrate 10, forming an effective stress buffer zone 200, allowing stress during the packaging process to be released or alleviated at the trench, thereby reducing stress concentration on the chip 20 and decreasing the risk of die cracks and molding compound cracks (UF cracks). Simultaneously, since the buffer trench 101 only partially penetrates the packaging substrate 10, sufficient remaining thickness is retained, ensuring the structural integrity and mechanical strength of the substrate. The trench opening will not cause a significant decrease in the mechanical properties of the substrate, thus ensuring the reliability and stability of the packaging. Furthermore, this arrangement helps optimize the heat conduction path inside the package, promoting more efficient heat dissipation from the chip and avoiding the impact of overheating on chip performance and lifespan.
[0068] In some embodiments, when the buffer trench 101 penetrates a portion of the packaging substrate 10, multiple buffer trenches 101 are interconnected. This can also be understood as the buffer trenches 101 being formed by continuous grooving. Continuous grooving is a simple and easy-to-prepare process, which helps to reduce the production cost of chip packaging structures.
[0069] It is worth noting that when the buffer trench 101 completely penetrates the packaging substrate 10, it cannot be continuously slotted. Only when the buffer trench 101 penetrates part of the packaging substrate 10 can there be a continuous slotting scheme.
[0070] In some embodiments, when the buffer trench 101 penetrates a portion of the packaging substrate 10, multiple buffer trenches 101 are arranged at intervals. This can also be understood as each buffer trench 101 being a separate groove, discontinuous with other buffer trenches 101. Discontinuous buffer trenches 101 can effectively reduce the impact of the buffer trenches 101 on the rigidity of the packaging substrate 10.
[0071] Specifically, when the buffer trench 101 adopts a continuous slot design, its specific shape is not limited and can be rectangular, circular, polygonal, or other shapes. Furthermore, the buffer trench 101 located in the chip mounting area 100 and the buffer trench 101 located in the stress buffer zone 200 can have the same or different shapes. This flexibility allows the packaging structure to be optimized and adjusted according to the actual stress distribution and chip layout. For example, the buffer trench 101 in the chip mounting area 100 can be designed with a specific shape based on the chip shape and stress concentration areas, while the buffer trench 101 in the stress buffer zone 200 can be adjusted according to the overall mechanical requirements of the package. This design not only more effectively disperses and buffers stress but also improves the adaptability and reliability of the package, ensuring the stability and durability of the chip under various operating conditions.
[0072] In one embodiment, refer to Figure 11 A continuous buffer trench 101 is formed within the chip mounting area 100, and the buffer trench 101 is rectangular.
[0073] In one embodiment, refer to Figure 12 A continuous buffer groove 101 is formed within the stress buffer zone 200, and the buffer groove 101 is rectangular.
[0074] In one embodiment, refer to Figure 13 The continuous buffer trench 101 is simultaneously formed in the chip mounting area 100 and the stress buffer area 200. The buffer trench 101 in the chip mounting area 100 and the buffer trench 101 in the stress buffer area 200 have the same shape and are both rectangular.
[0075] In one embodiment, refer to Figure 14 The continuous buffer trench 101 is simultaneously formed in the chip mounting area 100 and the stress buffer area 200. The buffer trench 101 in the chip mounting area 100 and the buffer trench 101 in the stress buffer area 200 have different shapes. One of the buffer trenches 101 is rectangular and the other is circular.
[0076] In some embodiments, when the buffer trenches 101 employ a discontinuous slotting design, the spacing pattern between the buffer trenches 101 is unrestricted. The pattern formed by the spacing of the buffer trenches 101 located in the chip mounting area 100 can be the same as or different from the pattern formed by the spacing of the buffer trenches 101 located in the stress buffer area 200. This flexible arrangement allows the package design to be customized according to the specific layout and stress distribution of the chip. For example, the spacing of the buffer trenches 101 in the chip mounting area 100 can be optimized according to the shape and pin distribution of the chip, while the stress buffer area 200 can be adjusted according to the overall mechanical requirements of the package. Such a design not only enhances the adaptability of the package structure to different stress conditions but also improves the reliability and stability of the package, ensuring that the chip maintains good performance and durability under various operating conditions.
[0077] In one embodiment, the stress buffer 200 includes four trapezoidal sub-regions. The upper bases of the four trapezoidal sub-regions are connected end to end and surround the boundary of the chip mounting area 100. Adjacent trapezoidal sub-regions share side connections, and at least one buffer groove 101 is formed in each trapezoidal sub-region.
[0078] This configuration allows the stress buffer 200 to effectively disperse and alleviate stress from the chip mounting area 100, while enhancing the stability and reliability of the package structure through the specific layout of the trapezoidal sub-regions and the arrangement of the buffer trench 101.
[0079] Specifically, refer to Figure 7 and Figure 10 The buffer groove 101 includes a first sub-buffer groove 1010 and a second sub-buffer groove 1011. The extension direction of the first sub-buffer groove 101 is parallel to the upper bottom of the trapezoidal sub-region in which it is located, and the extension direction of the second sub-buffer groove 1011 is perpendicular to the common side.
[0080] Specifically, refer to Figures 5 to 10 The four trapezoidal sub-regions include a first trapezoidal sub-region 2001, a second trapezoidal sub-region 2002, a third trapezoidal sub-region 2003, and a fourth trapezoidal sub-region 2004. Each trapezoidal sub-region has at least one first sub-buffer groove 1010 to enhance the stress dispersion effect. Meanwhile, referring to... Figure 6 or Figure 7 A second sub-buffer slot 1011 is provided on the common side.
[0081] Specifically, the first trapezoidal sub-region 2001 and the second trapezoidal sub-region 2002 share a first side a, the second trapezoidal sub-region 2002 and the third trapezoidal sub-region 2003 share a second side b, the third trapezoidal sub-region 2003 and the fourth trapezoidal sub-region 2004 share a third side c, and the fourth trapezoidal sub-region 2004 and the first trapezoidal sub-region 2001 share a fourth side d. A second sub-buffered groove 1011 is formed at each of these shared sides.
[0082] Furthermore, when the second sub-buffer trench 1011 is located in two adjacent trapezoidal sub-regions, their areas are equal to ensure the uniformity and symmetry of stress distribution. This design can effectively disperse stress, reduce the risk of chip stress concentration, and improve the stability and reliability of the packaging structure.
[0083] In one embodiment, refer to Figure 7 Each trapezoidal sub-region is provided with a first sub-buffered groove 1010, and each trapezoidal sub-region and the side shared by the two adjacent trapezoidal sub-regions are provided with a second sub-buffered groove 1011.
[0084] In some embodiments, the length of the first sub-buffer trench 1010 is 50%-80% of the length of the upper base of the corresponding trapezoidal sub-region. The length of the second sub-buffer trench 1011 is 30%-60% of the length of the common side of the corresponding trapezoidal sub-region. This arrangement can optimize the buffering effect, ensure uniform stress distribution, improve the stability and reliability of the packaging structure, and reduce the risk of chip stress concentration.
[0085] In some embodiments, the first sub-buffer trench 1010 and the second sub-buffer trench 1011 are staggered within the trapezoidal sub-region, and the depth ratio of the first sub-buffer trench 1010 to the second sub-buffer trench 1011 is 1:1.2-1.5. By optimizing the layout and depth ratio of the buffer trenches, stress can be more effectively dispersed and absorbed, reducing stress concentration, thereby improving the stability and reliability of the packaging structure and reducing the risk of chip cracking.
[0086] In some embodiments, when a buffer trench 101 is provided in the chip mounting area 100, the orthographic projection of the buffer trench 101 on the packaging substrate 10 at least partially overlaps with the orthographic projection of the chip 20 on the packaging substrate 10.
[0087] This application sets the buffer trench 101 in the chip mounting area 100 to have its orthographic projection on the packaging substrate 10 at least partially overlap with the orthographic projection of the chip 20. This can directly buffer the stress on the chip 20, effectively reduce the risk of cracking, optimize the utilization of packaging space, and improve structural stability.
[0088] In some embodiments, the cross-section of the buffer trench 101 is any one of a rectangle, a regular trapezoid, an inverted trapezoid, a semicircle, a semi-ellipse, a triangle, a sector, or an irregular shape. Different shapes are suitable for diverse stress distributions and packaging structure requirements, enabling more precise buffering and dispersion of stress, reducing the risk of stress concentration in the chip 20, and improving the reliability and stability of the package.
[0089] In some implementations, refer to Figure 4 The chip packaging structure also includes a first packaging cover 40.
[0090] Specifically, the first package cover 40 can also be understood as a heat dissipation cover. It is used to protect the chip 20 from physical damage, provide mechanical support, and assist in heat dissipation.
[0091] Furthermore, the material of the first package cover 40 can be a metal (such as copper or aluminum) or a plastic with high thermal conductivity to ensure good thermal conductivity. The first package cover 40 reduces the heat dissipation pressure on the heat sink and lowers the operating temperature of the chip 20 by conducting and dissipating the heat generated by the chip 20, thereby improving the performance and reliability of the chip.
[0092] The first encapsulation cap 40 is mounted within the connection area 300 of the encapsulation substrate 10, which is located around the stress buffer zone 200. The side of the first encapsulation cap 40 closest to the encapsulation substrate 10 is bonded to the first surface 10a of the encapsulation substrate 10 to ensure good thermal contact and mechanical stability.
[0093] Furthermore, the material connecting the first package cover 40 and the package substrate 10 can be any one of epoxy resin adhesive, thermally conductive silicone, thermally conductive grease, thermally conductive tape, and silver paste. Selecting a suitable adhesive material requires comprehensive consideration of factors such as heat dissipation requirements, mechanical strength, cost, and manufacturing processes to ensure the effective installation of the first package cover 40 and the reliable operation of the chip.
[0094] In some implementations, refer to Figures 1 to 3 The chip packaging structure also includes a second packaging cover 50, which is at least partially bonded to the chip 20, and the orthographic projection of the chip 20 onto the packaging substrate 10 falls within the orthographic projection of the second packaging cover 50 onto the packaging substrate 10. This arrangement ensures that critical areas of the chip 20 are effectively protected from corrosion and interference by external physical and chemical factors. It also enhances the overall stability of the chip 20 packaging, reduces the risk of displacement of the chip 20 during packaging and use, improves reliability, and optimizes packaging performance to ensure stable operation of the chip 20 in various environments.
[0095] Furthermore, the adhesive material between the second encapsulation cover 50 and the chip 20 is the same as the adhesive material used between the encapsulation substrate 10 and the first encapsulation cover 40. Any one of epoxy resin adhesive, thermally conductive silicone, thermally conductive grease, thermally conductive tape, and silver paste can be used.
[0096] Furthermore, the first encapsulation cover 40 and the second encapsulation cover 50 are an integral structure.
[0097] In some implementations, refer to Figures 1 to 4 A plurality of ball grid array balls 60 are arranged on the second surface 10b (bottom surface) of the packaging substrate 10. The ball grid array balls 60 are made of solder and are spherical or nearly spherical, used to electrically connect and mechanically fix the chip package structure to an external circuit board (such as a printed circuit board PCB). The ball grid array balls 60 are used to achieve efficient connection between the chip package and external circuitry, while providing good mechanical support and thermal conductivity.
[0098] This application also provides an electronic device, which includes the chip packaging structure mentioned in any of the above embodiments. The electronic device referred to herein can be a terminal device with a touch control, such as an in-vehicle display device, a television, a tablet computer, a mobile phone, or a wearable device.
[0099] Figure 15 This is a block diagram illustrating an electronic device 800 according to some embodiments of the present disclosure. For example, device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.
[0100] Reference Figure 15 The device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.
[0101] Processing component 802 typically controls the overall operation of device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.
[0102] Memory 804 is configured to store various types of data to support the operation of device 800. Examples of this data include instructions for any application or method operating on device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.
[0103] The power supply component 806 provides power to the various components of the device 800. The power supply component 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power to the device 800.
[0104] Multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
[0105] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.
[0106] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.
[0107] Sensor assembly 814 includes one or more sensors for providing status assessments of various aspects of device 800. For example, sensor assembly 814 may detect the on / off state of device 800, the relative positioning of components such as the display and keypad of device 800, changes in the position of device 800 or a component of device 800, the presence or absence of user contact with device 800, the orientation or acceleration / deceleration of device 800, and temperature changes of device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.
[0108] Communication component 816 is configured to facilitate wired or wireless communication between device 800 and other devices. Device 800 can access wireless networks based on communication standards, such as WiFi, 3G, 4G, 5G, other communication standards, or combinations thereof. In some embodiments of this disclosure, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In some embodiments of this disclosure, communication component 816 further includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
[0109] In some embodiments of this disclosure, the apparatus 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.
[0110] In the above detailed description, reference has been made to the accompanying drawings, which illustrate specific aspects of how this disclosure can be practiced. In this regard, terms indicating direction or positional relationship, such as “thickness,” “upper,” “lower,” “top,” “bottom,” “inner,” and “outer,” can be used with reference to the orientation of the described figures. Since components of the described device can be positioned in several different orientations, these directional terms are for illustrative purposes and not for limitation. It should be understood that other aspects can be utilized and structural or logical changes can be made without departing from the concept of this disclosure. Therefore, the following detailed description should not be considered limiting.
[0111] It should be understood that, unless otherwise specifically indicated, features of various embodiments of this disclosure described herein can be combined with each other. As used herein, the term “and / or” includes any one of the relevant listed items and any combination of any two or more; similarly, “at least one of…” includes any one of the relevant listed items and any combination of any two or more.
[0112] It should be understood that, unless otherwise expressly specified and limited, the terms "joining," "attaching," "installing," "connecting," "linking," "fixing," etc., used in the embodiments of this disclosure should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms herein based on the specific circumstances.
[0113] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited to these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section. Furthermore, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include at least one of that feature. In the description herein, “a plurality” means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
Claims
1. A chip package structure, characterized by, include: A packaging substrate has opposing first and second surfaces, the first surface including a chip mounting region and a stress buffer surrounding the chip mounting region; The chip is located within the chip mounting area; At least one of the chip mounting area and the stress buffer zone has at least one buffer trench, which extends from the first surface toward the second surface and at least partially penetrates the packaging substrate.
2. The chip package structure of claim 1, wherein, The buffer trench extends from the first surface to the second surface and penetrates the packaging substrate.
3. The chip package structure of claim 1, wherein, The depth of the buffer trench is 30%-90% of the thickness of the packaging substrate.
4. The chip package structure of claim 3, wherein, Multiple buffer trenches are connected; or The buffer trenches are arranged at intervals.
5. The chip package structure of claim 1, wherein, The stress buffer zone includes four trapezoidal sub-regions. The top bases of the four trapezoidal sub-regions are connected end to end and surround to form the boundary of the chip mounting area. Adjacent trapezoidal sub-regions share a common side connection, and at least one buffer groove is formed in each trapezoidal sub-region.
6. The chip package structure of claim 5, wherein, The buffer groove includes a first sub-buffer groove and a second sub-buffer groove. The extension direction of the first sub-buffer groove is parallel to the upper base of the trapezoidal sub-region it is located in, and the extension direction of the second sub-buffer groove is perpendicular to the common side. Each trapezoidal sub-region shall have at least one of the first sub-buffer slots; and / or Each trapezoidal sub-region is provided with a portion of the second sub-buffer slot.
7. The chip package structure of claim 1, wherein, When the buffer trench is formed in the chip mounting area, the orthographic projection of the buffer trench on the packaging substrate at least partially overlaps with the orthographic projection of the chip on the packaging substrate.
8. The chip package structure of any one of claims 1-7, wherein, The chip packaging structure further includes a filler layer. The surface of the chip is provided with a plurality of interconnects. The chip is connected to the packaging substrate through the interconnects. The filler layer fills the space between the chip and the packaging substrate and encapsulates the interconnects.
9. The chip package structure of any one of claims 1-7, wherein, The cross-section of the buffer groove is any one of the following shapes: rectangular, trapezoidal, inverted trapezoidal, semi-circular, semi-elliptical, triangular, fan-shaped, or irregular.
10. The chip package structure of any one of claims 1-7, wherein, The buffer groove is filled with any one of the following materials: silicone, polymer, rubber, or composite material.
11. The chip packaging structure according to any one of claims 1-7, characterized in that, The chip packaging structure further includes a first packaging cover, and the first surface further includes a connection area, which is arranged around the stress buffer. The first encapsulation cover is located within the connection area, and the side of the first encapsulation cover closest to the encapsulation substrate is bonded to the first surface.
12. The chip package structure of claim 11, wherein, The chip packaging structure further includes a second packaging cover, which is at least partially bonded to the chip, and the orthographic projection of the chip on the packaging substrate falls within the orthographic projection of the second packaging cover on the packaging substrate.
13. The chip package structure of claim 12, wherein, The first and second encapsulation covers are an integral structure.