A general-purpose digital signal processing system

Abstract

The utility model discloses a general type digital signal processing system, in the system, audio frequency ADC chip, audio frequency ADC chip's input end is connected with standard audio interface electricity, and audio frequency ADC chip's output end is connected with FPGA chip's first input electricity, and the input of high -speed ADC chip is connected with radio frequency input interface electricity, and the output of high -speed ADC chip is connected with FPGA chip's second input electricity, and the output of FPGA chip is connected with high -speed DAC chip's input electricity, and the output of high -speed DAC chip is connected with radio frequency output interface electricity. The utility model improves signal processing's quality and reliability.

Description

Technical Field

[0001] This utility model relates to the field of digital communication, specifically a general-purpose digital signal processing system. Background Technology

[0002] In wireless communication systems, digital signal processing units (DSPs) are key devices for signal modulation, demodulation, and digitization. Traditional DSPs often suffer from problems such as large size, high power consumption, and poor anti-interference capabilities, making it difficult to meet the miniaturization and high reliability requirements of modern communication systems.

[0003] Currently, there are digital signal processing solutions on the market that combine FPGAs with ADC and DAC chips. These solutions achieve signal sampling, quantization, encoding, and modulation through digital processing technology, thus addressing some of the shortcomings of traditional analog circuits. These solutions employ an "AD-FPGA-DA" architecture, enabling the conversion of baseband signals into radio frequency signals and achieving flexible signal processing capabilities.

[0004] However, existing digital signal processing units mainly rely on imported chips, which not only leads to high costs but, more importantly, poses supply chain security risks. A chip supply disruption would severely impact the stable operation of the communication system. Furthermore, existing solutions have shortcomings in electromagnetic compatibility design, making them susceptible to external electromagnetic interference, which can affect the quality and reliability of signal processing. Utility Model Content

[0005] In order to address the problems and shortcomings of the existing technology, the purpose of this utility model is to provide a general-purpose digital signal processing system to improve the quality and reliability of signal processing.

[0006] To achieve the above objectives, in a first aspect, this application provides a general-purpose digital signal processing system, which includes:

[0007] The audio ADC chip has its input terminal electrically connected to a standard audio interface and its output terminal electrically connected to the first input terminal of the FPGA chip.

[0008] The input terminal of the high-speed ADC chip is electrically connected to the RF input interface, and the output terminal of the high-speed ADC chip is electrically connected to the second input terminal of the FPGA chip.

[0009] The FPGA chip's output is electrically connected to the input of the high-speed DAC chip.

[0010] The high-speed DAC chip has its output terminal electrically connected to the RF output interface.

[0011] In the above embodiments, by electrically connecting the input terminal of the audio ADC chip to a standard audio interface and the output terminal of the audio ADC chip to the first input terminal of the FPGA chip, the audio signal can be accurately converted into a digital signal and input into the FPGA chip for processing. By electrically connecting the input terminal of the high-speed ADC chip to the RF input interface and the output terminal of the high-speed ADC chip to the second input terminal of the FPGA chip, high-speed digital sampling and transmission of the RF signal is achieved. After receiving the digitized audio and RF signals, the FPGA chip can perform flexible digital signal processing. The processed digital signal is transmitted through the output terminal of the FPGA chip to the input terminal of the high-speed DAC chip, converted into an analog signal by the high-speed DAC chip, and output from the RF output interface. This structural design allows the system to process audio and RF signals simultaneously. The programmability of the FPGA chip enables the flexibility and multifunctionality of signal processing, and the use of high-speed ADC and DAC chips improves the real-time performance and accuracy of RF signal processing.

[0012] In conjunction with some embodiments of the first aspect, in some embodiments, the FPGA chip is a JFM7K325T chip in an FCBGA900 package.

[0013] In the above embodiments, the JFM7K325T chip in an FCBGA900 package is used as the FPGA chip. This chip adopts advanced FCBGA900 packaging technology, which has high package density and a large number of pins, and can meet the input and output requirements of complex digital signal processing. At the same time, the FCBGA package has good heat dissipation performance, which is conducive to the stable operation of the chip at high speed. The JFM7K325T chip has abundant programmable logic resources and hardware multiplier resources, supports high-speed serial transceivers, and has strong clock management capabilities. These characteristics enable the system to have powerful computing and data processing capabilities when performing digital signal processing, enabling the implementation of complex signal processing algorithms, while ensuring high-speed and reliable data transmission, thereby improving the overall system performance and processing efficiency.

[0014] In conjunction with some embodiments of the first aspect, in some embodiments, the high-speed ADC chip adopts a QFN-packaged BLAD16D125 type 16-bit / 125MSPS high-speed dual-channel analog-to-digital converter.

[0015] In the above embodiments, the BLAD16D125 16-bit / 125MSPS high-speed dual-channel analog-to-digital converter in QFN package is used as the high-speed ADC chip. This chip adopts the QFN package form, which has the characteristics of small package size, good heat dissipation performance and low parasitic inductance, which is conducive to improving signal integrity. The 16-bit resolution enables the analog-to-digital conversion to have high quantization accuracy, which can more accurately reproduce the detailed features of analog signals. The 125MSPS sampling rate meets the sampling requirements of radio frequency signals. The dual-channel design increases the parallelism of signal acquisition, enabling the system to acquire two radio frequency signals simultaneously. The reasonable configuration of these performance indicators makes the system have good accuracy and bandwidth characteristics in the process of radio frequency signal acquisition and conversion.

[0016] In conjunction with some embodiments of the first aspect, in some embodiments, the high-speed DAC chip adopts a QFN-packaged BL1031 type 16-bit / 250MSPS high-speed dual-channel digital-to-analog converter.

[0017] In the above embodiments, the BL1031 16-bit / 250MSPS high-speed dual-channel digital-to-analog converter in QFN package is used as the high-speed DAC chip. The QFN package of this chip has the characteristics of short pins and small parasitic parameters, which is beneficial to the transmission quality of high-speed signals. The 16-bit conversion accuracy ensures the quantization accuracy when converting digital signals to analog signals, the 250MSPS conversion rate meets the bandwidth requirements of RF signal reconstruction, and the sampling rate design, which is higher than that of ADC, provides sufficient margin for signal reconstruction. The dual-channel structure supports simultaneous output of I / Q signals. These performance characteristics enable the system to maintain high signal fidelity and bandwidth during the conversion of digital signals to analog signals, meeting the performance requirements of RF signal output.

[0018] In conjunction with some embodiments of the first aspect, in some embodiments, the audio ADC chip uses an ES7243 analog-to-digital converter in a QFN package.

[0019] In the above embodiments, the technical solution of using the ES7243 analog-to-digital converter in a QFN package as the audio ADC chip leverages the large heat dissipation area and low thermal resistance of the QFN package to improve heat dissipation efficiency during audio signal acquisition and reduce the impact of chip operating temperature on sampling accuracy. The ES7243 ADC features low power consumption and a high signal-to-noise ratio, enabling higher quality digital signal output during audio signal sampling. The miniaturization of the QFN package reduces board space, shortens signal transmission distance, and minimizes signal loss and interference during transmission. This solution solves the heat generation and signal quality degradation problems of traditional audio ADC chips during high-precision sampling, improving the reliability and stability of the system during audio signal processing.

[0020] In conjunction with some embodiments of the first aspect, in some embodiments, the FPGA chip integrates a signal processing circuit, which includes an automatic gain control module, an orthogonal transformation module, and a sampling rate transformation module. The output terminal of the automatic gain control module is electrically connected to the input terminal of the orthogonal transformation module, and the output terminal of the orthogonal transformation module is electrically connected to the input terminal of the sampling rate transformation module.

[0021] In the above embodiments, a pipelined signal processing operation is achieved by integrating an automatic gain control (AGC) module, a quadrature transform (QT) module, and a sampling rate conversion (SRC) module within an FPGA chip and cascading them in the order of AGC, QT, and SRC. The AGC module dynamically adjusts the signal amplitude to keep the signal within its optimal dynamic range, preventing signal distortion and saturation. The AGC-controlled signal is then processed by the QT module, which accurately extracts the signal's amplitude and phase information. The SRC module resamples the processed signal to adapt the output signal to the sampling rate requirements of different application scenarios. This processing chain design avoids the signal loss and interference problems associated with discrete component implementations, improving the real-time performance and accuracy of signal processing.

[0022] In conjunction with some embodiments of the first aspect, in some embodiments, the output terminal of the quadrature transformation module further includes an I-channel signal output terminal and a Q-channel signal output terminal, which are electrically connected to the input terminals of two sampling rate transformation modules, respectively.

[0023] In the above embodiments, by setting I-channel and Q-channel signal output terminals at the output end of the quadrature transformation module and connecting them respectively to two sampling rate conversion modules, the system can process in-phase and quadrature component signals separately. Independent processing of the I-channel and Q-channel signals reduces mutual interference between signals and improves the accuracy of signal separation. Since the two signals are processed by sampling rate conversion separately, different sampling rates can be used for the I-channel and Q-channel signals according to actual needs, increasing the flexibility of the system in signal processing. This scheme overcomes the problem of traditional single-channel processing methods failing to accurately restore the characteristics of complex signals and improves the system's ability to process complex modulated signals.

[0024] In conjunction with some embodiments of the first aspect, in some embodiments, a signal selection switch circuit is provided between the first input terminal and the second input terminal of the FPGA chip, and the control terminal of the signal selection switch circuit is electrically connected to the control output terminal of the FPGA chip.

[0025] In the above embodiments, by setting a signal selection switch circuit between the first and second input terminals of the FPGA chip, and controlling the switch circuit with the control output terminal of the FPGA chip, the system can flexibly switch the input signals of the audio ADC and the high-speed ADC according to actual needs. The signal selection switch circuit enables the system to dynamically select signal channels, processing audio or radio frequency signals as needed, avoiding waste of signal processing resources. The FPGA-controlled switch circuit enables real-time switching of signal channels, reducing signal interruption time during switching. This solution solves the problem of inflexibility in traditional fixed-channel configurations, improving the system's signal processing efficiency and resource utilization.

[0026] In conjunction with some embodiments of the first aspect, in some embodiments, the input terminal of the standard audio interface is provided with a programmable gain amplifier circuit, and the gain control terminal of the programmable gain amplifier circuit is electrically connected to the gain control output terminal of the FPGA chip.

[0027] In the above embodiments, by setting a programmable gain amplifier circuit at the input of the standard audio interface and controlling the gain of the amplifier circuit with the gain control output of the FPGA chip, the system can dynamically adjust the front-end gain according to the amplitude characteristics of the input audio signal. The programmable gain amplifier circuit expands the system's adaptability to input signal amplitude and enhances its ability to process weak signals. The FPGA-controlled gain adjustment allows for precise gain setting, ensuring that the signal is processed within the optimal dynamic range. This solution solves the problem that traditional fixed-gain amplification methods are difficult to adapt to different signal strengths, improving the system's processing quality for various audio signals.

[0028] In conjunction with some embodiments of the first aspect, in some embodiments, a protection circuit is provided in parallel at the output terminal of the radio frequency output interface. The protection circuit includes a transient suppression diode and a radio frequency bypass capacitor. The cathode of the transient suppression diode is electrically connected to the radio frequency output interface, and the anode of the transient suppression diode is grounded.

[0029] In the above embodiments, by connecting a protection circuit including a transient suppression diode and an RF bypass capacitor in parallel at the output terminal of the RF output interface, and with the cathode of the transient suppression diode electrically connected to the RF output interface and the anode grounded, a complete protection mechanism is formed during RF signal output. The transient suppression diode can effectively suppress external interference and high-voltage spikes generated by electrostatic discharge, preventing these interference signals from damaging the internal circuitry. The RF bypass capacitor provides a low-impedance path for high-frequency interference signals, reducing the impact of interference signals on the output RF signal. This solution solves the problem of the RF output circuit being susceptible to damage from external interference and improves the reliability of the system in complex electromagnetic environments.

[0030] The general-purpose digital signal processing system provided in this application embodiment has at least the following technical effects or advantages:

[0031] 1. This application provides a general-purpose digital signal processing system. By electrically connecting the input terminal of an audio ADC chip to a standard audio interface and the output terminal of the audio ADC chip to the first input terminal of an FPGA chip, audio signals can be accurately converted into digital signals and input into the FPGA chip for processing. By electrically connecting the input terminal of a high-speed ADC chip to a radio frequency (RF) input interface and the output terminal of the high-speed ADC chip to the second input terminal of the FPGA chip, high-speed digital sampling and transmission of RF signals are achieved. After receiving the digitized audio and RF signals, the FPGA chip can perform flexible digital signal processing. The processed digital signal is transmitted to the input terminal of a high-speed DAC chip through the output terminal of the FPGA chip. After being converted into an analog signal by the high-speed DAC chip, it is output from the RF output interface. This structural design allows the system to process audio and RF signals simultaneously. The programmability of the FPGA chip enables the flexibility and multifunctionality of signal processing, and the use of high-speed ADC and DAC chips improves the real-time performance and accuracy of RF signal processing.

[0032] 2. This application provides a general-purpose digital signal processing system. By setting I-channel and Q-channel signal output terminals at the output end of the quadrature converter module and connecting them to two sampling rate conversion modules respectively, the system can process in-phase and quadrature component signals separately. Independent processing of the I-channel and Q-channel signals reduces mutual interference between signals and improves the accuracy of signal separation. Since the two signals are processed by sampling rate conversion separately, different sampling rates can be used for the I-channel and Q-channel signals according to actual needs, increasing the system's flexibility in signal processing. This scheme overcomes the problem of traditional single-channel processing methods failing to accurately restore the characteristics of complex signals and improves the system's ability to process complex modulated signals.

[0033] 3. This application provides a general-purpose digital signal processing system. By connecting a protection circuit including a transient suppression diode and an RF bypass capacitor in parallel at the output terminal of the RF output interface, and with the cathode of the transient suppression diode electrically connected to the RF output interface and the anode grounded, a complete protection mechanism is formed during RF signal output. The transient suppression diode effectively suppresses external interference and high-voltage spikes generated by electrostatic discharge, preventing these interference signals from damaging the internal circuitry. The RF bypass capacitor provides a low-impedance path for high-frequency interference signals, reducing the impact of interference signals on the output RF signal. This solution solves the problem of the RF output circuit being susceptible to damage from external interference and improves the system's reliability in complex electromagnetic environments. Attached Figure Description

[0034] Figure 1 This is a module connection diagram of an embodiment of the present utility model.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1. Standard audio interface; 2. Programmable gain amplifier circuit; 3. Audio ADC chip (ES7243); 4. RF input interface; 5. High-speed ADC chip (BLAD16D125); 6. Signal selection switch circuit; 7. FPGA chip (JFM7K325T); 8. High-speed DAC chip (BL1031); 9. RF output interface; 10. Protection circuit; 701. Automatic gain control module; 702. Quadrature converter module; 703. Sampling rate conversion module; 101. Transient diode; 102. RF bypass capacitor. Detailed Implementation

[0037] The terminology used in the following embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to include the plural expressions as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this application refers to any or all possible combinations including one or more of the listed items.

[0038] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0039] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0040] This utility model embodiment provides a general-purpose digital signal processing system, such as... Figure 1 As shown, Figure 1 This is a module connection diagram of an embodiment of the present utility model, including:

[0041] Audio ADC chip 3, the input terminal of audio ADC chip 3 is electrically connected to standard audio interface 1, and the output terminal of audio ADC chip 3 is electrically connected to the first input terminal of FPGA chip 7;

[0042] The input terminal of the high-speed ADC chip 5 is electrically connected to the RF input interface 4, and the output terminal of the high-speed ADC chip 5 is electrically connected to the second input terminal of the FPGA chip 7.

[0043] FPGA chip 7, the output of FPGA chip 7 is electrically connected to the input of high-speed DAC chip 8;

[0044] The high-speed DAC chip 8 is electrically connected to the RF output interface 9.

[0045] FPGA chip 7 uses the JFM7K325T chip in an FCBGA900 package.

[0046] The high-speed ADC chip 5 is a QFN packaged BLAD16D125 16-bit / 125MSPS high-speed dual-channel analog-to-digital converter.

[0047] The high-speed DAC chip 8 uses the BL1031 type 16-bit / 250MSPS high-speed dual-channel digital-to-analog converter in QFN package.

[0048] The audio ADC chip uses the ES7243 analog-to-digital converter in a QFN package.

[0049] The FPGA chip 3 integrates a signal processing circuit (not shown in the figure). The signal processing circuit includes an automatic gain control module 701, an orthogonal transformation module 702, and a sampling rate transformation module 703. The output terminal of the automatic gain control module 701 is electrically connected to the input terminal of the orthogonal transformation module 702, and the output terminal of the orthogonal transformation module 702 is electrically connected to the input terminal of the sampling rate transformation module 703.

[0050] The output terminals of the quadrature conversion module 702 also include an I-channel signal output terminal and a Q-channel signal output terminal, which are electrically connected to the input terminals of the two sampling rate conversion modules 703, respectively.

[0051] A signal selection switch circuit 6 is provided between the first input terminal and the second input terminal of the FPGA chip 7. The control terminal of the signal selection switch circuit 6 is electrically connected to the control output terminal of the FPGA chip 7.

[0052] The input terminal of the standard audio interface 1 is equipped with a programmable gain amplifier circuit 2, and the gain control terminal of the programmable gain amplifier circuit 2 is electrically connected to the gain control output terminal of the FPGA chip 7.

[0053] A protection circuit 10 is connected in parallel to the output terminal of the RF output interface 9. The protection circuit 10 includes a transient suppression diode 101 and an RF bypass capacitor 102. The cathode of the transient suppression diode 101 is electrically connected to the RF output interface 9, and the anode of the transient suppression diode 101 is grounded.

[0054] To facilitate understanding of this utility model, the workflow of this general-purpose digital signal processing system is described below:

[0055] External audio signals are sent to audio ADC chip 3 through standard audio interface 1. Audio ADC chip 3 converts analog audio signals into digital signals and sends them to FPGA chip 7 for signal processing. The processed signal is sent by FPGA chip 7 to high-speed DAC chip 8. High-speed DAC chip 8 then converts the digital signal into an analog signal and sends it out through radio frequency interface 9.

[0056] In the above embodiments, by electrically connecting the input terminal of the audio ADC chip to a standard audio interface and the output terminal of the audio ADC chip to the first input terminal of the FPGA chip, the audio signal can be accurately converted into a digital signal and input into the FPGA chip for processing. By electrically connecting the input terminal of the high-speed ADC chip to the RF input interface and the output terminal of the high-speed ADC chip to the second input terminal of the FPGA chip, high-speed digital sampling and transmission of the RF signal is achieved. After receiving the digitized audio and RF signals, the FPGA chip can perform flexible digital signal processing. The processed digital signal is transmitted through the output terminal of the FPGA chip to the input terminal of the high-speed DAC chip, converted into an analog signal by the high-speed DAC chip, and output from the RF output interface. This structural design allows the system to process audio and RF signals simultaneously. The programmable nature of the FPGA chip enables flexibility and multifunctionality in signal processing, and the use of high-speed ADC and DAC chips improves the real-time performance and accuracy of RF signal processing.

Claims

1. A general-purpose digital signal processing system, characterized by, include: An audio ADC chip, wherein the input terminal of the audio ADC chip is electrically connected to a standard audio interface, and the output terminal of the audio ADC chip is electrically connected to the first input terminal of an FPGA chip; The input terminal of the high-speed ADC chip is electrically connected to the radio frequency input interface, and the output terminal of the high-speed ADC chip is electrically connected to the second input terminal of the FPGA chip. The FPGA chip has its output terminal electrically connected to the input terminal of the high-speed DAC chip. The high-speed DAC chip has its output terminal electrically connected to the radio frequency output interface.

2. The general-purpose digital signal processing system according to claim 1, characterized in that, The FPGA chip is a JFM7K325T chip in an FCBGA900 package.

3. The general-purpose digital signal processing system according to claim 1, characterized in that, The high-speed ADC chip is a QFN-packaged BLAD16D125 type 16-bit / 125MSPS high-speed dual-channel analog-to-digital converter.

4. A general-purpose digital signal processing system according to claim 1, characterized in that, The high-speed DAC chip is a QFN-packaged BL1031 type 16-bit / 250MSPS high-speed dual-channel digital-to-analog converter.

5. A general-purpose digital signal processing system according to claim 1, characterized in that, The audio ADC chip is an ES7243 analog-to-digital converter in a QFN package.

6. A general-purpose digital signal processing system according to claim 1, characterized in that, The FPGA chip integrates a signal processing circuit, which includes an automatic gain control module, an orthogonal transformation module, and a sampling rate transformation module. The output of the automatic gain control module is electrically connected to the input of the orthogonal transformation module, and the output of the orthogonal transformation module is electrically connected to the input of the sampling rate transformation module.

7. A general-purpose digital signal processing system according to claim 6, characterized in that, The output of the quadrature transformation module also includes an I-channel signal output terminal and a Q-channel signal output terminal, which are electrically connected to the input terminals of the two sampling rate transformation modules, respectively.

8. A general-purpose digital signal processing system according to claim 1, characterized in that, A signal selection switch circuit is provided between the first input terminal and the second input terminal of the FPGA chip, and the control terminal of the signal selection switch circuit is electrically connected to the control output terminal of the FPGA chip.

9. A general-purpose digital signal processing system according to claim 1, characterized in that, The input terminal of the standard audio interface is equipped with a programmable gain amplifier circuit, and the gain control terminal of the programmable gain amplifier circuit is electrically connected to the gain control output terminal of the FPGA chip.

10. A general-purpose digital signal processing system according to claim 1, characterized in that, A protection circuit is connected in parallel at the output terminal of the radio frequency output interface. The protection circuit includes a transient suppression diode and a radio frequency bypass capacitor. The cathode of the transient suppression diode is electrically connected to the radio frequency output interface, and the anode of the transient suppression diode is grounded.

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