CODER SPEED MONITORING DEVICE

Abstract

A speed monitoring device comprises a second MCU (4b) that outputs a second count value (C2) which is cleared by a Z-phase signal. The second MCU (4b) comprises: a phase counter (6b) that counts an A-phase signal and a B-phase signal and outputs the count result as the base count value (Cb); a first acquisition circuit (7b) that buffers the base count value (Cb) at one acquisition period (Ts) and outputs the buffered value as the position count value (Cp); a second acquisition circuit (7c) that buffers the base count value (Cb) at an active edge of the Z-phase signal and outputs the buffered value as the reference count value (Cz); and a second counter calculation unit (9) that calculates the second count value (C2) based on the position count value (Cp) and the reference count value (Cz).

Description

[0001] This application claims priority over Japanese patent application No. 2023-182433, which was filed on October 24, 2023. TECHNICAL AREA

[0002] This document describes a speed monitoring device that uses an encoder which outputs a signal with a phase difference corresponding to a rotation angle. BACKGROUND

[0003] International standards require a speed monitoring function for machine tool spindles. For example, ISO 23125 requires that speed monitoring for lathe spindles be implemented in safety category 3.

[0004] Generally, speed detectors used for machine tool spindles are classified into types such as a magnetic encoder (hereinafter simply referred to as an "encoder"), which can output cosine and sine signals with a wavenumber N per revolution and a phase difference of 90 degrees, according to the angle of rotation. These signals are commonly referred to as A-phase signals and B-phase signals.

[0005] When this encoder is used to perform speed monitoring, it is common practice to reference the counts of a phase difference counter, which performs a quadruple pulse count based on the phase difference between the A and B phase signals and uses the value difference between speed monitoring periods. That is, a safety controller performing the speed monitoring samples the counts of the phase difference counter for each monitoring cycle T and calculates a monitoring speed V, defined as V = (P(n) - P(n-1)) / (T×4×N), where P(n) represents the current count and P(n-1) represents the previous count. Therefore, to ensure accuracy when performing speed monitoring using the phase difference counter, the single-revolution wavenumber N set for the phase difference counter must be equal to the actual single-revolution wavenumber N of the encoder.The sampling of the phase difference counter by the safety controller can be carried out, for example, in a safety communication where the reliability of the communication data is guaranteed by protocol.

[0006] To implement speed monitoring using this encoder in safety category 3, it is further necessary to use two phase difference counters with different elements to compare the calculated speeds (i.e., differences in pulse count) and perform cross-monitoring. The encoder is also typically accompanied by a marker signal, called the Z-phase signal, which outputs one pulse per revolution to identify the position within a revolution. Furthermore, one of the phase difference counters can be a sub-single-revolution counter, which is reset by the Z-phase signal, and the other can be a multi-revolution counter, which increments and decrements the Z-phase signal.

[0007] Furthermore, calculations are performed to obtain a rotational speed based on a phase difference counter that uses the Z-phase signal and combines the sub-single-revolution counter and the multi-revolution counter, and a rotational speed based on a phase difference counter that does not use the Z-phase signal. The two resulting rotational speed values ​​are then compared to confirm whether the encoder's single-revolution wavenumber is correct.

[0008] Non-patent document 1 discloses an exemplary counter that uses the Z-phase signal. The counter disclosed in non-patent document 1 is a microcontroller unit (hereinafter referred to as "MCU") that has the function of clearing the sub-single-turn counter on a rising edge of the Z-phase signal and incrementing and decrementing the multi-turn counter depending on whether the counter is immediately counting up or down within a single turn.

[0009] Furthermore, patent document 1 discloses a method for realizing the counter clearing of the sub-single-revolution counter and the counting up and down of the multi-revolution counter based on a logical level of the Z-phase signal instead of on the edge of the Z-phase signal and the rising or falling edge of the A-phase signal and the B-phase signal. COUNTERPOINTS

[0010] JP2009-153335 A, NON-PATENT DOCUMENT: “32-Bit Microcontroller FM0+ Family Peripheral Manual Timer Part,” Cypress Semiconductor Corporation, September 9, 2020

[0011] According to a counter implemented in a general-purpose MCU disclosed in the non-patent document, if only the Z-phase signal oscillates without being accompanied by changes in the A-phase and B-phase signals—for example, if the Z-phase signal oscillates at an angle where the edge changes—accurate speed monitoring is not possible because the multi-revolution counter repeatedly counts up or down. For example, if, as in Fig. As shown in Figure 3, if the oscillation of less than 1 count persists near the edge of the Z-phase signal after the forward rotation, the multi-rotation counter repeatedly increments on each rising edge of the Z-phase signal.

[0012] Furthermore, if the Z-phase signal has a wide pulse width, an error of an amount corresponding to the pulse width count will occur in the speed monitoring when the direction of rotation is reversed. For example, this shows Fig. 4 An exemplary timing diagram of the Z-phase signal, which is passed on after the change from forward rotation to reverse rotation. In the example of Fig. 4. There is a deviation, corresponding to 6 counts, between a Z-phase rising edge during the forward rotation (see (a) in Fig. 4) and a Z-phase rising edge during the reverse rotation (see (b) in Fig. 4) Therefore, on the first Z-phase rise edge after a change in the direction of rotation, a discrepancy equivalent to 6 counts can occur between the phase difference counter using the Z-phase signal and the phase difference counter not using the Z-phase signal. These factors cause a discrepancy in the difference of the count value compared to the phase difference counter not using the Z-phase signal, and therefore the safety controller may falsely detect an anomaly in a speed monitoring interface.

[0013] Furthermore, according to the counter circuit described in Patent Document 1, it is possible to use the Z-phase signal to accurately design the multi-revolution and sub-single-revolution counters. However, such a counter circuit is not implemented in a general-purpose MCU. Therefore, to use a general-purpose MCU to implement a counter comparable to the one described in Patent Document 1, it is necessary to add a complex logic circuit outside the MCU, resulting in higher costs and a higher probability of one dangerous failure per hour (PFHD). It should be noted that the frequencies of the A-phase and B-phase signals can exceed 100 kHz, and it is difficult to simply replace the MCU's software processing with processing comparable to that of the counter circuit described in Patent Document 1. SUMMARY

[0014] A speed monitoring device disclosed in this document is a speed monitoring device for monitoring the rotational speed of an object and is characterized in that it comprises: an encoder that outputs an A-phase signal with N pulses per revolution, a B-phase signal that is phase-shifted by 90 degrees with respect to the A-phase signal, and a Z-phase signal with 1 pulse per revolution; a first unit that is configured to output a first count value by quadruple phase counting based on the A-phase signal and the B-phase signal; a second unit that is configured to calculate a second count value from a sub-single-revolution count value obtained from the Z-phase signal by clearing the count value obtained by quadruple phase counting based on the A-phase signal and the B-phase signal, and a multi-revolution count value.which is obtained by counting up or down the Z-phase signal according to the direction of rotation; and a safety controller that calculates a first monitoring speed based on the change in the first count value, calculates a second monitoring speed based on the change in the second count value, and determines whether a speed anomaly is present based on a comparison between the first and second monitoring speeds. The second unit comprises: a phase count counter that performs a quadruple phase count of the A-phase signal and the B-phase signal and outputs the count result as the base count value; a first sensing circuit that updates the base count value at a sensing period, which is a value obtained by dividing a speed monitoring period by a positive integer.a second acquisition circuit that buffers the base count on an active edge of the Z-phase signal and outputs the buffered value as the reference count; and a second counter calculation unit designed to calculate the second count based on the position count and the reference count. The second counter calculation unit calculates a reference count correction value, which corresponds to a difference between the base count and the reference count at a reference position of the Z-phase signal, based on a current value of the reference count, a previous value of the reference count, and a previous value of the reference count correction value; it calculates a reference count estimate by adding the reference count correction value to the reference count.It counts the multi-revolution count up or down based on a magnitude relationship between a current position count value, a previous position count value, and the reference count estimate, and calculates a difference value between the position count and the reference count estimate as the sub-single-revolution count.

[0015] According to the technique disclosed in this document, it is possible to construct a phase difference counter based on the Z-phase signal using a general-purpose MCU, and it is possible to implement a speed monitoring system that includes confirmation of the agreement between a single-revolution wavenumber setting value in the speed monitoring system and an actual single-revolution wavenumber of the encoder in a cost-effective manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments of the present disclosure are described with reference to the following figures; they show: Fig. 1 a block diagram representing a speed monitoring device; Fig. 2 a flowchart illustrating an exemplary calculation method for a multi-revolution counter and a single-revolution counter; Fig. 3 a time diagram representing a problem of a conventional multi-revolution counter; Fig. 4 a time diagram representing a problem of a conventional phase difference counter; Fig. 5 a time diagram of counter operations in the speed monitoring device, which is in Fig. 1 is shown. DETAILED DESCRIPTION

[0017] When duplexing a phase difference counter with different elements, variations in signal delay time or similar factors can lead to deviations in the specified change time between the count values. Therefore, it is necessary to allow a deviation in the difference between the count values ​​of duplex counters within a range that does not adversely affect speed monitoring. If the phase difference counter's counting method is 1x, the permissible deviation is 1 count or less, which is the minimum resolution; i.e., 1 wavenumber or less. Even in a case where the phase difference counter's counting method is 4x, a deviation in the difference between the count values ​​of 1 wavenumber or less (i.e., 4 counts or less) is permitted in the duplex counter if the permissible deviation is set to a value whose resolution is comparable to that of the 1x counting method.Therefore, a phase difference counter to be mounted on a general-purpose MCU is designed to perform calculations based on a position count value sampled in each speed monitoring period and a reference count value sampled on an active edge of the Z-phase signal, as a phase difference counter that combines a multi-revolution counter with a single-revolution counter, using a Z-phase signal whose error with a phase difference counter that does not use the Z-phase signal is less than 4 counts (less than 1 wavenumber) in the difference, which corresponds to the speed monitoring period, due to software processing.

[0018] A speed monitoring device is described with reference to Fig. 1 and Fig. 2 described. Fig. Figure 1 is a block diagram showing an example configuration of the speed monitoring device. Fig. Figure 2 is a flowchart showing an exemplary calculation method for a multi-revolution counter and a single-revolution counter using the speed monitoring device.

[0019] One coder of Fig. According to the rotation angle of an object (not shown), component 1 outputs an A-phase signal with wavenumber N per rotation, a B-phase signal with a phase difference of 90 degrees relative to the A-phase signal, and a Z-phase signal with one pulse per rotation. The Z-phase signal is a signal with an active level at a predefined reference position, which is defined as only one position per rotation. The A-phase signal is level-converted and pulsed by a pulse-width modulation circuit 2a and input as an A-phase pulse signal to a first MCU 4a and a second MCU 4b. Similarly, the B-phase signal is level-converted and pulsed by a pulse-width modulation circuit 2b and input as a B-phase pulse signal to the first MCU 4a and the second MCU 4b. Furthermore, the Z-phase signal is level-converted and pulsed by a pulsing circuit 2c and entered as a Z-phase pulse signal into the second MCU 4b.The first MCU 4a is a microcontroller unit comprising a phase counting counter 6a, a sensing circuit 7a, and a first counter calculation unit 8, which serve as peripheral equipment. Similarly, the second MCU 4b is a microcontroller unit comprising a phase counting counter 6b, first and second sensing circuits 7b and 7c, and a second counter calculation unit 9. Each of the phase counting counters 6a and 6b has phase counting capability. Each of the sensing circuits 7a, 7b, and 7c acquires a counter value based on at least two external signals. These microcontroller units are available in a wide variety of products on the market.The first MCU 4a generates an initial count value C1, which is not reset by the Z-phase pulse signal, for the count obtained by phase counting the A-phase and B-phase pulse signals, and outputs the generated initial count value C1 to a safety controller 10 in each speed monitoring period. The second MCU 4b obtains from the count value obtained by phase counting the A-phase and B-phase pulse signals (hereinafter referred to as the "base count value Cb") a single-revolution count value Cs, which is reset by the Z-phase pulse signal, and a multi-revolution count value Cm, which counts the Z-phase pulse signal. Furthermore, the second MCU 4b outputs the single-revolution count value Cs and the multi-revolution count value Cm as a second count value C2 to the safety controller 10 in each speed monitoring period.The second count value C2 can be converted into a count value of the same format as the first count value C1 using the wavenumber N per revolution. The wavenumber N per revolution is set and stored in the safety controller 10. For example, a safety communication protocol, which takes measures against transmission errors, is used to output the first count value C1 and the second count value C2 from the first MCU 4a and the second MCU 4b to the safety controller 10.

[0020] A first speed monitoring unit 11 of the safety controller 10 performs speed monitoring using a change ΔC1 of the first count value C1 at each speed monitoring period T and a single-revolution count setting N' of the encoder 1, which is preset in the safety controller 10, where a first monitoring speed V1 is calculated as V1 = ΔC1 / N'. The single-revolution count setting N' is a count value of the phase count when the encoder 1 completes a full revolution. In the case of a 4x phase count, the single-revolution count setting N' is given using the number of waves N per revolution as N' = 4×N.

[0021] Similarly, a second speed monitoring unit 12 of the safety controller 10 performs speed monitoring using a change amount ΔC2 of the second count value C2 at each speed monitoring period T and the preset single-revolution count setting value N' of the encoder 1, where a second monitoring speed V2 is calculated as V2 = ΔC2 / N'. The second count value C2 is converted into a count value of the same format as in the case where the counter reset by the Z-phase signal is not performed and is used for the calculation of ΔC2. This conversion is performed by applying the multi-revolution count value Cm and the single-revolution count value Cs to the following formula (1). C2=(Cm+F)×N'+Cs

[0022] F takes the value 0 if the single-revolution count value Cs is 0 or positive, and the value 1 if it is negative. The first speed monitoring unit 11 and the second speed monitoring unit 12 exchange the change amount ΔC1 of the first count value C1 and the change amount ΔC2 of the second count value C2. If |ΔC1-ΔC2| is greater than or equal to a predefined anomaly detection threshold, they detect an anomaly in a speed monitoring interface. The anomaly detection threshold can be set, for example, to 4 counts; that is, a count value corresponding to 1 wavenumber. This makes it possible to detect an anomaly if the single-revolution wavenumber N of encoder 1 does not match the single-revolution wavenumber setting value N'.

[0023] The phase count counter 6a of the first MCU 4a is a counting circuit that performs quadruple phase counting using the A-phase pulse signal and the B-phase pulse signal. The A-phase pulse signal and the B-phase pulse signal can be subjected to noise removal by noise filters 5a and 5b before being input to the phase count counter 6a. The acquisition circuit 7a detects an active edge of an acquisition time setpoint signal output by an acquisition time setpoint generator 3 described below and temporarily stores the count value of the phase count counter 6a. The acquisition time setpoint signal can be subjected to noise removal by a noise filter 5c before being input to the acquisition circuit 7a.

[0024] The first counter processing unit 8 performs a predetermined interrupt operation each time the acquisition circuit 7a temporarily stores the count value. As an interrupt operation, the first counter processing unit 8 aligns the count value temporarily stored by the acquisition circuit 7a with a bit width M' of the first count value C1 required by the safety controller 10, and outputs the aligned value as the first count value C1 in each speed monitoring period to the safety controller 10.

[0025] Bit width matching is achieved through software processing. If M ≥ M', the first counter calculation unit 8 extracts a lower M' bit from the bit width M of the phase counting counter 6a. Furthermore, if M < M', the first counter calculation unit 8 detects an overflow or underflow based on a change in the count value buffered by the sensing circuit 7a and increments an (M'-M)-bit extended counter by +1 in case of overflow and decrements it by -1 in case of underflow. Although not shown, the first counter calculation unit 8 is a microcomputer comprising various memories, a computing device (i.e., a processor), and the like, necessary to perform the software processing.

[0026] The phase counter 6b of the second MCU 4b is a counting circuit that performs quadruple phase counting using the A-phase pulse signal and the B-phase pulse signal. The A-phase pulse signal and the B-phase pulse signal can undergo noise removal by noise filters 5d and 5e before being input to the phase counter 6b. The first acquisition circuit 7b detects an active edge of the acquisition time target signal output by the acquisition time target generator 3 and temporarily stores the count value of the phase counter 6b. The acquisition time target signal can undergo noise removal by a noise filter 5f before being input to the first acquisition circuit 7b. The second acquisition circuit 7c detects an active edge of the Z-phase pulse signal and stores the count value of the phase counter 6b.The Z-phase pulse signal can be subjected to noise removal by a noise filter 5g before being fed into the second acquisition circuit 7c.

[0027] The second counter processing unit 9 performs interrupt processing each time the first acquisition circuit 7b buffers the count value. As interrupt processing, the second counter processing unit 9 performs the software processing described below, based on a position count value Cp buffered by the first acquisition circuit 7b and a reference count value Cz buffered by the second acquisition circuit 7c, to calculate the single-revolution count value Cs and the multi-revolution count value Cm. The second counter processing unit 9 then outputs the single-revolution count value Cs and the multi-revolution count value Cm as the second count value C2 to the safety controller 10 in each speed monitoring period. Although not shown, the second counter processing unit 9 is a microcomputer that incorporates various memories, a computing device (i.e., a computer), and a computer.a processor) and the like, which are necessary to perform software processing.

[0028] The acquisition time setpoint generation unit 3 is a circuit that generates and outputs the acquisition time setpoint signal, which specifies an acquisition period Ts. The acquisition period Ts is a value that satisfies Ts = T / INT for the speed monitoring period T (where INT is a positive integer). The acquisition period Ts is a value preset to be shorter than the period of the Z-phase signal when the encoder 1 is rotating at maximum speed. Although the acquisition time setpoint generation unit 3 in Fig. Although MCU 1 is depicted as an independent component of the first MCU 4a and the second MCU 4b, it is not necessarily an independent component. For example, the first MCU 4a or the second MCU 4b may be configured to output the acquisition time preset signal.

[0029] The following is an example of processing carried out by the second counter calculation unit 9, with reference to a flowchart of Fig. 2 described. The processing of the in Fig. The flowchart shown in Figure 2 is started at each intermediate count storage by the first acquisition circuit 7b (i.e., at each acquisition period Ts), as described above. In the following description, Cp(n) represents a current value of the position count value Cp obtained through intermediate storage, and Cp(n-1) represents a previous value. Other parameters are designated in the same way.

[0030] In step S901, the position count Cp(n) from the first acquisition circuit 7b and a reference count Cz(n) from the second acquisition circuit 7c are obtained by zero expansion. Furthermore, previous values ​​of the position count Cp(n) and the reference count Cz(n) are retrieved from memory as previous position count Cp(n-1) and previous reference count Cz(n-1) by zero expansion. The processing then proceeds to step S902.

[0031] Step S902 is a correction process to eliminate discontinuities in Cp(n), Cz(n), Cp(n-1), and Cz(n-1) caused by overflow or underflow of phase counter 6b in step S903 and subsequent processing. Specifically, a corrected position count Cp'(n), a corrected previous position count Cp'(n-1), a corrected reference count Cz'(n), and a corrected previous reference count Cz'(n-1) are calculated using the following formulas. The processing then proceeds to step S903. Cp'(n)=Cp(n)+f×f1×2M Cp'(n−1)=Cp(n−1)+f×f2×2M Cz'(n)=Cz(n)+f×f3×2M Cz'(n−1)=Cz(n−1)+f×f4×2M

[0032] Here, M represents a bit width of the phase-counting counter 6b, and f is a marker specifying the implementation of the correction processing. At least one of the count values ​​Cp(n), Cz(n), Cp(n-1), and Cz(n-1) described above is used in the determination. If the count value used in the determination is not greater than a lower threshold or not less than an upper threshold, f is 1; otherwise, it is 0. Regarding the thresholds, the bit width M can be used to set the lower threshold to 2M / 4 and the upper threshold to 2M×3 / 4. If Cp(n) is less than or equal to a determination value, f1 is 1; if Cp(n) is greater than the determination value, f1 is 0. Similarly, f2 is 1 if Cp(n-1) is less than or equal to the determination value and 0 if Cp(n-1) is greater than the determination value.If Cz(n) is less than or equal to the target value, f3 is 1 and then, if Cz(n) is greater than the target value, it is 0. If Cz(n-1) is less than or equal to the target value, f4 is 1 and then, if Cz(n-1) is greater than the target value, it is 0. When using the bit width M, the target value can be set to, for example, 2(M-1). The procedure described above for setting the lower threshold, the upper threshold, and the target value is only an example and can be modified as needed.

[0033] Step S903 is a processing step that uses a Z-phase-crossing marker to determine whether the multi-revolution count value Cm has been incremented or decremented once. If the Z-phase-crossing marker is OFF, processing continues with step S904. If it is ON, processing continues with step S911. The Z-phase-crossing marker is turned off during the initialization processing (not shown).

[0034] Steps S904 through S910 are operations performed if the multi-revolution count value Cm has never been incremented or decremented. Here, the multi-revolution count value Cm is incremented or decremented when the reference position is deemed to have been traversed by the Z-phase signal. The reference position of the Z-phase signal is determined based on the logic levels of the A-phase pulse signal, the B-phase pulse signal, and the Z-phase pulse signal. For example, the reference position of the Z-phase signal is a position where, when the Z-phase pulse signal is an active high signal, the A-phase pulse signal is at a low level, the B-phase pulse signal is at a low level, and the Z-phase pulse signal is at a high level.

[0035] Step S904 is used to obtain a status from the second acquisition circuit 7c, indicating whether the buffer operation of the phase counter 6b has been performed once in response to the rising edge of the Z-phase pulse signal. If the buffer operation has been performed, processing continues with step S905. If not, processing continues with step S910.

[0036] Steps S905 and S907 are operations to determine whether the reference position has been traversed by the Z-phase signal. In this example, the reference position is considered traversed if, after the detection of the active edge of the Z-phase signal, there is a significant advance of more than two counts. Therefore, if the relationship Cp'(n) > Cz'(n) + 2 ≥ Cp'(n-1) is satisfied, the reference position is determined to have been traversed in the forward direction of rotation. As described above, the reference count Cz is a value obtained by buffering the base count Cb at the time the active edge of the Z-phase signal was detected. Accordingly, Cz'(n) is the base count Cb at the time the active edge of the Z-phase signal was last detected.

[0037] If step S905 returns YES, processing proceeds to step S906, where the reference count correction value Zc(n) is set to +2 and the over-rotation count value Cm is set to +1. If step S905 returns NO, processing proceeds to step S907, where, if the relationship Cp'(n) < Cz'(n) - 2 ≤ Cp'(n-1) is satisfied, it is determined that the reference position has been traversed in the reverse direction of rotation. Processing then proceeds to step S908, where the reference count correction value Zc(n) is set to -2 and the over-rotation count value Cm is set to -1. Step S909 is a joint processing step performed after steps S906 and S907, when the reference position is considered to have been traversed by the Z-phase signal.In step S909, the Z-phase crossing marker is switched on and a reference count estimate Czc is set to a value obtained by adding the reference count Cz'(n) and the reference count correction value Zc(n).

[0038] The reference count correction value Zc(n) is a correction value used to correct a difference between the base count Cb at the active edge of the Z-phase pulse signal (i.e., reference count Cz) and the base count Cb at a true Z-phase reference position. Furthermore, the reference count estimate Czc is the base count Cb at an estimated Z-phase reference position. As described above, the true Z-phase reference position is determined based on the logic levels of the A-phase pulse signal, the B-phase pulse signal, and the Z-phase pulse signal. If, for example, the Z-phase pulse signal is an active H-signal, then the true Z-phase reference position is, for example, a position where the A-phase pulse signal is at a L level, the B-phase pulse signal is at a L level, and the Z-phase pulse signal is at a H level.

[0039] Step S910 is a process to clear the reference count correction value Zc(n), the reference count estimate value Czc, and the Z-phase crossing marker, assuming that the reference position has never been traversed by the Z-phase signal.

[0040] Steps S911 to S920 are processes executed after it is assumed that the reference position has been traversed at least once by the Z-phase signal. Steps S911 to S915 are processes for updating the reference count correction value Zc(n). Specifically, if the relationship Cz'(n) - Cz'(n-1) > 6 is satisfied, it is determined that the active edge of the Z-phase signal has been traversed in the forward direction of rotation, and Zc(n) = +2 is set. If the relationship Cz'(n) - Cz'(n-1) < -6 is satisfied, it is determined that the active edge of the Z-phase signal has been traversed in the reverse direction of rotation, and Zc(n) = -2 is set. In other cases, it is determined whether the direction of rotation has changed and whether the active edge of the Z-phase signal has been passed, and Zc(n) = Zc(n-1) - Cz'(n) + Cz'(n-1) is determined.

[0041] Here, Zc(n-1) is the previous value of the reference count correction value Zc(n), and the value stored in memory is retrieved. Furthermore, the reference value "6" used in the determination is the maximum value of the difference between the base count value Cb at the active edge of the Z-phase pulse signal and the base count value Cb at a non-active edge of the Z-phase pulse signal. In other words, the reference value "6" is a count value that corresponds to the maximum pulse width of the Z-phase pulse signal. If the maximum width of the Z-phase pulse signal exceeds a value corresponding to 6 counts, there are multiple reference positions based on the logic levels of the A-phase pulse signal, the B-phase pulse signal, and the Z-phase pulse signal, independent of any phase relationship between the A-phase pulse signal, the B-phase pulse signal, and the Z-phase pulse signal.Therefore, the maximum width of the Z-phase pulse signal is always the value that corresponds to 6 counts or less.

[0042] Step S916 is used to set the reference count estimate Czc to a value obtained by adding the reference count Cz'(n) and the reference count correction value Zc(n), and then processing proceeds to S917.

[0043] Steps S917 to S920 are processes for incrementing or decrementing the multi-revolution count value Cm. Specifically, if the relationship Cp'(n) ≥ Czc > Cp'(n-1) is satisfied, it is determined that the reference position in the forward rotation direction has been traversed by the Z-phase signal, and the multi-revolution count value Cm is incremented. If the relationship Cp'(n) < Czc ≤ Cp'(n-1) is satisfied, the multi-revolution count value Cm is decremented.

[0044] Step S921 is a process for calculating the single-turn count value Cs, where the single-turn count value is set to a value obtained by subtracting Czc from Cp'(n).

[0045] Step S922 is used to store the position count value Cp(n), the reference count value Cz(n) and the reference count correction value Zc(n) as previous values ​​in memory, so that these values ​​can be referenced when the next processing is started.

[0046] As described above, the safety controller 10 determines whether a speed anomaly exists based on the difference between the change ΔC1 of the first count value C1 and the change ΔC2 of the second count value C2; ​​i.e., |ΔC1 - ΔC2|. If the base count value Cb at the true Z-phase reference position is a "true reference count value Cz*", the difference |ΔC1 - ΔC2| is equal to a value obtained by adding the change ΔCz = |Czc - Cz*| between the reference count estimate Czc and the true reference count value Cz* and a difference ±1 between the count values ​​detected by the detection circuit 7a and the first detection circuit 7b. The difference in the measured value occurs, for example, due to a difference in the delay time between internal signals of the first MCU 4a and the second MCU 4b.

[0047] The error ΔCz is determined as a function of the reference count correction value Zc(n) and the pulse width of the Z-phase pulse signal. That is, the difference between the base count Cb at the time the active edge of the Z-phase pulse signal was traversed in the forward direction of rotation (i.e., reference count Cz) and the base count Cb at the true Z-phase reference position (i.e., the true reference count Cz*) is set to w1, and the difference between the reference count Cz at the time it was traversed in the reverse direction and the true reference count Cz* is set to -w2. In this case, the error ΔCz at the time when the active edge of the Z-phase pulse signal was traversed in the forward direction of rotation is w1 - 2. Furthermore, the error ΔCz at the time when the active edge of the Z-phase pulse signal was traversed in the reverse direction of rotation is -w2 + 2.Accordingly, if w = w1 + w2, the change in ΔCz is at most |w - 4|, as shown in formula 2. |Amount of change in ΔCz|=|(w1−2)−(−w2+2)|=|w−4|

[0048] Here, w = w1 + w2 is a value obtained by converting the pulse width at the active level of the Z-phase pulse signal into the count value of the phase counter 6b. As described above, the maximum value of w is 6. Given that logical level ranges of the A-phase pulse signal and the B-phase pulse signal are included, the minimum value of w is 2, where the active level of the Z-phase pulse signal is the true Z-phase reference position. Accordingly, according to formula (2), the change in ΔCz during the speed monitoring period Ts is in a range of ±2. Thus, the difference between ΔC1, the change in the first count value C1, and ΔC2, the change in the second count value C2, is in a range of ±3.

[0049] As a result, the design of the second counter calculation unit 9 is such that it corresponds to the one described above and in Fig. By performing the processing shown in Figure 2, it is possible to reduce the difference between ΔC1 (the change in the first count value C1) and ΔC2 (the change in the second count value C2) during the speed monitoring period Ts to 4 or fewer counts, which is less than the equivalent of one shaft number. Thus, the safety controller 10 can perform speed monitoring without falsely detecting an anomaly in the speed monitoring interface.

[0050] For example, Fig. 5. An exemplary time diagram showing the exemplary sweep of the Z-phase signal in the sequence of [1] Forward rotation direction, two or more times (not shown) [2] Forward direction of rotation (between (a) and (b) in Fig. 5) [3] Reverse direction of rotation (between (c) and (d) in Fig. 5) [4] Reverse direction of rotation (between (e) and (f) in Fig. 5) shows when the wavenumber N = 25 and the Z-phase signal pulse width corresponds to 6 counts.

[0051] In Fig. 5. To make the timing diagram easier to understand, the correction processing (0 extension in step S901 and step S902) takes into account the overflow and underflow in the flowchart of Fig. 2 omitted. The Z-phase signal passing through [2] is a Z-phase signal that passes through as the forward rotation continues, and the reference count correction value Zc is obtained by processing step S912 in Fig. 2 held at +2. Therefore, no error occurs in the count difference. The Z-phase signal passing through in [3] is a first Z-phase signal that passes through after the transition from forward rotation to reverse rotation, and the reference count correction value Zc is obtained by processing step S915 in Fig. 2 is corrected by an amount equal to the pulse width of the Z-phase signal. Therefore, the reference count estimate Czc is the same value as that at the time the Z-phase signal passes through in the immediately preceding forward rotation direction ([2]). Therefore, no error occurs in the count difference. The Z-phase signal passing through in [4] is a second Z-phase signal that passes through after the transition from forward rotation to reverse rotation, and the reference count correction value is obtained by processing step S914 in Fig. 2 set to -2. At this point, the difference in the phase count counter between (e) and (f) is in Fig. 5 -4. On the other hand, the count value difference after converting the single-revolution count value Cs and the multi-revolution count value Cm using formula (1) -6. As a result, an error of -2 occurs. In Fig.5 corresponds to the pulse width of the Z-phase signal 6 counts, which agrees with the calculation result using formula (2). REFERENCE MARK LIST 1 Coder 2a, 2b, 2c Pulsing circuit 3 Recording time specifications - generation unit 4a first MCU 4b second MCU 5a, 5b, 5c, 5d, 5e, 5f, 5g noise filter 6a, 6b Phase counting counter 7a Detection circuit 7b first detection circuit 7c second detection circuit 8 first meter calculation unit 9 second counter calculation unit 10 security controllers 11 first speed monitoring unit 12 second speed monitoring unit QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-182433

[0001] JP 2009-153335 A

[0010]

Claims

[1] A speed monitoring device for monitoring the speed of an object, comprising: an encoder that outputs an A-phase signal with N pulses per revolution, a B-phase signal 90 degrees out of phase with the A-phase signal, and a Z-phase signal with 1 pulse per revolution; a first unit configured to output a first count value by quadruple-phase counting based on the A-phase signal and the B-phase signal; a second unit configured to calculate a second count value consisting of a sub-single-revolution count value obtained by counter-clearing the count value obtained by the quadruple-phase count based on the A-phase signal and the B-phase signal by the Z-phase signal and a multi-revolution count value obtained by counting up or down the Z-phase signal according to the rotation direction; and a safety controller that calculates a first monitoring speed based on a change amount of the first count value, calculates a second monitoring speed based on a change amount of the second count value, and determines whether a speed abnormality exists based on a comparison result between the first monitoring speed and the second monitoring speed, where the second unit includes: a phase count counter that performs quadruple phase counting of the A-phase signal and the B-phase signal and outputs the counting result as a base count value; a first detection circuit that latches the base count value at a detection period, which is a value obtained by dividing a speed monitoring period by a positive integer, and outputs the latched value as a position count value; a second detection circuit that latches the base count value at an active edge of the Z-phase signal and outputs the latched value as a reference count value; and a second counter calculation unit configured to calculate the second count value based on the position count value and the reference count value, wherein the second counter calculation unit calculates a reference count correction value corresponding to a difference between the base count value and the reference count value at a reference position of the Z-phase signal based on a current value of the reference count value, a previous value of the reference count value, and a previous value of the reference count correction value, calculates a reference count estimate by adding the reference count correction value to the reference count value, increments or decrements the multi-revolution count based on a magnitude relationship between a current position count value, a previous position count value, and the reference count estimate, and a difference value between the position count value and the reference count estimate value is calculated as the sub-single-revolution count. [2] The rotation speed monitoring device according to claim 1, wherein the second counter calculation unit calculates a difference value between the current value of the reference count value and the previous value of the reference count value while taking overflow and underflow into account, sets the reference count correction value to +2 when the difference value exceeds a count value corresponding to a pulse width of the Z-phase signal, sets the reference count correction value to -2 when the difference value falls below the inverse of the count value corresponding to the pulse width of the Z-phase signal, and otherwise sets the reference count correction value to a value obtained by subtracting a difference value between the current value of the reference count value and the previous value of the reference count value from the previous value of the reference count correction value. [3] The rotational speed monitoring device according to claim 1 or 2, wherein the second counter calculation unit, after obtaining an initial value of the reference count value, sets the reference count correction value and the over-revolution count value to 0, respectively, until either a first condition or a second condition is satisfied, sets the reference count correction value to +2 and sets the over-revolution count value to +1 when the first condition is satisfied, and sets the reference count correction value to -2 and sets the over-revolution count value to -1 when the second condition is satisfied, and further, when the reference count value is Cz(n), the current value of the position count value is Cp(n), and the previous value of the position count value is Cp(n-1), and the values after the correction processing for eliminating discontinuities of Cz(n), Cp(n), and Cp(n-1) are Cz'(n), Cp'(n), and Cp'(n-1), respectively. are,the first condition is Cp'(n) > Cz'(n) + 2 ≥ Cp'(n-1) and the second condition is Cp'(n) < Cz'(n) - 2 ≤ Cp'(n-1).

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