Switching power converter with adaptive power factor correction

Abstract

A blocking converter control device (105) comprising: an error signal generator (615) configured to generate an error signal (Verror) proportional to a difference between a reference signal (Vref) and a feedback signal (Vsense); a ramp generator (610) configured to cyclically generate a ramp signal (630); a comparator (605) configured to trip a circuit breaker in response to the ramp signal (630) matching the fault signal (Verror); and a ramp slope control circuit (625) configured to control a ramp slope for the ramp signal (630) such that the ramp slope has a substantially sinusoidal peak period for each cycle of an input voltage (Vin), and such that the ramp slope is kept constant during a remaining part of each cycle of the input voltage (Vin).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Patent Application No. 14 / 752,700, filed June 26, 2015, which is incorporated herein by reference in its entirety. TECHNICAL AREA

[0002] This application relates to switching power converters and, in particular, to a switching power converter with adaptive power factor correction. BACKGROUND

[0003] The power factor of a system relates to its efficiency, as it is a ratio of the system's real power to its apparent power. For example, a nonlinear load, such as an electric motor, presents a significant amount of inductance to an AC mains supply. Therefore, upon start-up, the input current must ramp from zero, while the AC voltage across the load continues to cycle with the AC mains supply voltage. The voltage and current into the load are thus out of phase with each other. A worst-case scenario with respect to power delivery occurs when the voltage and current are orthogonal (90° out of phase), so that power delivery is completely reactive, with no real power delivery.However, apparent power is the product of voltage and current (no phase dependence), so such a device would continue to consume apparent power even though the power factor would be zero. In contrast, a purely resistive load would produce no reactive power component, or reactive power component, so the real and apparent power are equal, producing an optimal power factor of unity. As the reactive power component increases, the power factor drops from unity to zero.

[0004] The power factor is therefore an important parameter for a switching power converter, such as a flyback or flyback converter, since its transformer necessarily presents a non-linear load to the AC mains supply. It is therefore common to implement power factor correction in a flyback power converter. For example, a diode bridge and a capacitor can be used to provide a rectified input voltage for a flyback power converter. Despite the rectification, the input voltage still has a sinusoidal profile for relatively small (and therefore inexpensive) input capacitors. To achieve a high power factor, the peak current through the primary winding in the flyback converter's transformer should also have a similar sinusoidal profile. This peak current through the primary winding is proportional to a product of the input voltage and the on-time (t on) for the corresponding switching cycle in the flyback converter. The on-time is proportional to the ratio of the peak primary winding current to the input voltage. If the amplitude of the peak primary winding current is tied to the input voltage (as it should be for a high power factor), it is easy to see that a constant on-time achieves a high power factor.

[0005] However, the resulting constant on-time causes unwanted ripple in the flyback converter's output voltage. In this regard, it can be shown that the output power of a flyback converter is proportional to a square of a product of the input voltage and the on-time. Since the input voltage varies sinusoidally, the output power (and thus the output voltage) also varies sinusoidally for constant-on-time power factor correction. The flyback converter must then use a relatively large output capacitor on the secondary side of the transformer to filter the output ripple, which increases the cost. To achieve high power factor correction while still providing a tightly regulated output voltage, it is therefore common to use a multi-stage approach, such as processing the output voltage from the flyback converter through a DC-DC switching power converter.However, such multi-stage approaches are expensive in terms of additional components and increased control complexity. It is therefore more economical to use a single-stage flyback converter architecture. However, such users then have only the choice between a better power factor with a poorly regulated output voltage or a tightly regulated output voltage with a reduced power factor.

[0006] US 2013 / 0 077 370 A1 shows an AC to DC power supply device and a power control structure and method therefor.The provided method includes: causing an AC-to-DC converter in the AC-to-DC power supply device to convert an AC input voltage in response to a drive signal to produce a DC output voltage; sampling a rectified voltage with respect to the AC input voltage to provide a sample signal; providing an output feedback signal with respect to an output of the AC-to-DC converter; multiplying the sample signal by the output feedback signal to provide a product signal; performing signal modulation on the product signal to produce the drive signal to control switching of a main power switch in the AC-to-DC converter; and performing an amplitude limiting process on the sample signal or the product signal.

[0007] CN 102 332 814 A discloses a power factor correction control circuit for reducing EMI (electromagnetic interference) including an inductive current threshold, wherein, when an inductive current is less than the inductive current threshold, a peak value of the inductive current is controlled to vary along with an input voltage; and when the inductive current reaches the inductive current threshold, the inductive current is limited to the inductive current threshold.

[0008] US 2005 / 0 219 871 A1 discloses a power factor corrector with a PWM switch for switching a mains current generated from a mains voltage to charge a boost capacitor and thereby generate an output voltage, a device and a method for piecewise on-time modulation, which comprise comparing a voltage dependent on the mains voltage with a voltage dependent on the output voltage to generate a comparison signal for determining the on-time of the PWM switch. When the mains voltage is lower than a threshold, the on-time of the PWM switch varies with the mains voltage, and when the mains voltage is higher than the threshold, the on-time of the PWM switch is constant.US 7 230 561 B2 shows a ramp generator for an analog-to-digital converter comprising an array of capacitors, each controlled by a switch responsive to one or more control signals and operable to connect / disconnect one or more of the capacitors relative to the array, and a current source operable to charge at least one of the capacitors. A method of operating a ramp generator with an array of capacitors includes resetting the ramp generator, enabling a current generator to charge at least one capacitor in the switched capacitor array, and controlling the state of one or more switches, the switches operable to connect and disconnect one or more of the capacitors relative to the array. The output of the ramp generator has a plurality of programmable breakpoints.

[0009] Consequently, there is a need in the art for single-stage flyback converters with power factor correction and reduced output voltage ripple. SUMMARY

[0010] To solve the problems described above, the present invention provides a flyback control apparatus and a switching power converter control method having the features of the respective independent claims. Aspects considered useful for understanding the invention are explained below. A flyback switching power converter control apparatus is provided with adaptive power factor correction. In this adaptive power factor correction, the control apparatus initiates a period of constant peak current control and a period of constant switch-on-time control in each cycle of the input voltage. The flyback converter rectifies an AC line voltage to generate the rectified input voltage such that it continues to maintain a rectified sinusoidal profile. The constant peak current control period may be centered around the sinusoidal peak in each cycle of the input voltage.In such embodiments, the controller would control a power switch for the flyback converter to have a constant on-time during an initial portion of each input voltage cycle and during a final portion of each input voltage cycle.

[0011] Regardless of the relative timing of the constant-on-time periods versus the constant-peak current period, the mixed use of these two modes in any input voltage significantly reduces the resulting output voltage ripple at the expense of a relatively small reduction in power factor. A suitably high power factor can thus be provided in combination with a relatively tightly regulated output voltage. These advantageous features can be better understood by considering the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows an exemplary flyback converter according to an embodiment of the disclosure. Fig. Figure 2 shows an exemplary constant peak current control feedback circuit with adaptive power factor correction for the control device of Fig. 1. Fig. Figure 3 shows another exemplary constant peak current control feedback circuit with adaptive power factor correction for the control device of Fig. 1. Fig. Figure 4 shows a clamped or limited signal waveform for the feedback circuits of Fig. 2 and Fig. 3. Fig. Figure 5 shows the clamped signal waveforms for the feedback circuits of Fig. 2 and Fig. 3 under a light load condition, a heavy load condition and an overload condition. Fig. Figure 6 shows an exemplary constant-on-time control feedback circuit with adaptive power factor correction for the control device of Fig. 1. Fig. Figure 7 shows the ramp slope waveform for two cycles of the input voltage for the feedback circuit of Fig. 6.

[0012] Embodiments of the present disclosure and their advantages are best understood by reference to the following detailed description. It should be noted that like reference numerals are used to identify like elements illustrated in one or more of the figures. DETAILED DESCRIPTION

[0013] To address the need in the art for improved power factor correction in a single-stage flyback converter with reduced output ripple, two different control modes are used over each AC mains supply cycle. During part of the AC mains supply cycle, the flyback converter uses a constant-on-time mode of operation. During a remaining portion of the AC mains supply cycle, the flyback converter uses a constant-peak current mode of operation. Using the constant-on-time mode during each AC mains supply cycle provides a high power factor but at the expense of a relatively large output voltage ripple. Conversely, using the constant-peak current mode of operation provides a tightly regulated output voltage at the expense of a reduced power factor.Mixed mode operation thus provides a beneficial compromise between the conflicting goals of reducing output voltage ripple and increasing power factor.

[0014] The result is a power factor correction that is less than that which would be achieved using a constant on-time throughout the entire AC mains supply cycle. However, this reduction can be relatively small, such as resulting in a power factor of 0.7 instead of the nearly uniform value that a strict constant on-time would provide. Such a relatively high power factor is perfectly sufficient for low-power applications, such as an LED driver. At the same time, the output voltage level is significantly improved compared to a strict constant-on-time operating mode.Advantageously, the disclosed mixed-mode controller provides the user with the ability to select or tune the relative amounts of power factor correction and reduced output voltage ripple for a given application by varying the duration in each AC mains supply cycle for the constant-on-time mode period to the constant-peak current mode period.

[0015] The mixed-mode control disclosed herein is independent of the control method conventionally used to achieve single-stage high-power factor correction using a flyback converter. For example, it is common to achieve single-stage high-power factor correction using either a constant-on-time feedback loop method or a constant-peak current feedback loop. Both control methods can be modified to practice the mixed-mode control (adaptive power factor correction) disclosed herein. Embodiments of constant-peak current control are discussed first, followed by a discussion of a constant-on-time embodiment. Peak current feedback control with adaptive power factor correction

[0016] An exemplary single-stage flyback converter 100 configured to implement adaptive power factor correction using a modified constant peak current feedback control loop is shown in Fig. 1. As explained below, the flyback converter 100 can also be modified to practice adaptive power factor correction using a modified constant-on-time feedback control loop. The flyback converter 100 is thus generic for both control methods. A controller integrated circuit 105 for the flyback converter controls the switching of a power switch, such as an NMOS transistor Q1. In alternative embodiments, the power switch can be implemented using a bipolar transistor. The controller 105 controls a gate voltage for the power switch transistor Q1 via an output terminal 5. When turned on, the power switch transistor Q1 allows a primary current to flow through a primary winding 110 of a transformer 115 in response to an input voltage Vin.A rectifier 120, comprising a diode bridge and a capacitor C1, rectifies the alternating line voltage carried on an AC mains supply 125 to provide the input voltage Vin. In some embodiments, the capacitor C1 is not an electrolytic capacitor, so it has a relatively low capacitance. The input voltage Vin thus continues to maintain a sinusoidal profile over each half of an AC mains supply cycle.

[0017] For each cycle of the power switch transistor Q1, the primary winding current increases from zero to a peak winding current value that depends on the input voltage Vin, the switch on time, and the inductance for the primary winding 110. When the power switch transistor Q1 turns off, a secondary winding current flows through a second winding 125 in the transformer 115, starting from a peak value and continuing to decrease to zero. An output capacitor C2 and a resistor R2 stabilize a resulting output voltage Vout generated by the second winding current. A diode D1 prevents the secondary winding current from flowing while the primary winding is conducting. The secondary winding current creates a reflected voltage across the primary winding 110 and also across an auxiliary winding 130 for the transformer 115.Diode D2 has a voltage drop that prevents a direct relationship between the reflected voltage and the output voltage while the secondary current is still flowing. However, when the secondary current drops to zero (the transformer reset time), there is no voltage drop across diode D2, such that the resulting reflected voltage at that time is directly related to the output voltage. By sampling the reflected voltage across auxiliary winding 130 at the transformer reset time, controller 105 can thus determine the output voltage Vout, as known in the primary-only feedback technique. For example, controller 105 may include a Vsense terminal 2 that samples the reflected voltage across auxiliary winding 130 through a voltage divider formed by a pair of resistors R3 and R4.The reflected voltage may also be rectified by a diode D12 and a capacitor C3 to form a power supply voltage VCC, which is received by the control device 105 at a power terminal 1.

[0018] The control device 105 may include a ground terminal 6 and a current sense (Isense) terminal 4, which senses the primary winding current through the voltage generated across a sense resistor Rs coupled to a source of the power switch transistor Q1. Since the input voltage Vin is proportional to a time rate of change of the primary winding current multiplied by the primary winding inductance, the control device 105 may determine the input voltage Vin indirectly via the Isense terminal voltage. However, the control device 105 may also include a Vin terminal 3 for directly sensing the input voltage Vin through one or more resistors R1.

[0019] With the rectified sinusoidal profile for the input voltage Vin, the resulting primary winding current should also have a similar profile to provide a high power factor for the flyback converter 100. Should the controller 105 implement a constant on-time for each cycle of the power switch transistor Q1, the peak primary winding current will have a similar rectified sinusoidal profile over each cycle of the input voltage Vin (and thus over each half-cycle of the AC line voltage) to provide a high power factor, but at the expense of significant output voltage ripple. The controller 105 is thus configured to practice adaptive power factor correction, utilizing both a constant-on-time mode of operation and a constant-peak current mode of operation within each cycle of the input voltage Vin.

[0020] For example, the control device 105 may include a first peak current control feedback circuit 200, as shown in Fig. 2. In the first peak current control feedback circuit 200, a comparator 205 (e.g., a differential) generates an error voltage (Verror) equal to the difference between a reference signal (e.g., a reference voltage generated by a bandgap reference circuit 210) and a feedback signal (e.g., a feedback voltage Isense, as sampled at the transformer reset time). As discussed above, the Vsense voltage has a direct relationship to the output voltage Vout for the flyback converter 100 when sampled at the transformer reset time. After filtering by a compensation filter 215, the error voltage is multiplied by a clamped version 230 of the input voltage Vin in a multiplier 220. A voltage clamp circuit 225 clamps the input voltage Vin to produce a clamped version 230, which may also be referred to as a reference signal.A resulting peak winding current command 240 from multiplier 220 is thus equal to a product of the compensated error voltage and the clamped version 230 of the input voltage Vin. A comparator 245 determines a power-off command 250 when Isense is equal to the peak winding current command 240. Referring again to FIG. Fig. 1, it is noted that Isense represents the winding current. Since the power switch transistor Q1 is turned off when Isense is equal to the peak winding current command 240, the first peak current control feedback circuit 200 controls the peak winding current in each cycle of the power switch transistor Q1.

[0021] If the input voltage is unclamped, it has a sinusoidal profile 235, showing the two sinusoidal peaks generated in the sinusoidal profile 235 for each cycle of the AC line voltage. If the multiplier 220 instead multiplies the compensated error voltage by Vin 235, a conventional constant-on-time mode of operation results using a peak current power factor correction feedback loop. In particular, note that the peak primary winding current for a given power switch cycle is proportional to a product of the peak input voltage Vin and the switch on time. The switch on time is thus proportional to a ratio of the peak primary winding current and the peak input voltage Vin.Because the peak primary winding current is tied by multiplication by the peak input voltage, such a conventional peak current power factor correction feedback loop results in a constant on-time for each power switch switching cycle. However, multiplication by the clamped input voltage 235 only produces the constant-on-time mode of operation during the portions of each input voltage cycle that are not clamped.

[0022] During the clamped portion of a cycle for the clamped input voltage 230, the peak winding current command 240 is substantially constant. However, the input voltage 235 continues to increase sinusoidally during these clamped periods. Thus, starting from an initial time for each clamped period, the on-time for successive power switch cycles becomes shorter and shorter until a minimum on-time is reached when the input voltage 235 reaches its peak. The switch on-time for successive power switch cycles then begins to increase until the end of the clamped portion in the cycle for the clamped input voltage is reached. It is thus evident that the switch on-time is inversely proportional to the input voltage 235 during each clamped portion of the clamped input voltage 230 such that the product of the input voltage 235 and the on-time is substantially constant.Since the output power for flyback converter 100 is proportional to the square of this product, the constant-peak current mode of operation significantly reduces output voltage ripple during each clamped period compared to conventional constant-on-time peak primary current control techniques. Such output voltage ripple reduction comes at the expense of a reduced power factor, since the input voltage 235 varies across the clamped portion, whereas the peak primary current is held constant. However, as discussed above, numerous applications, such as an LED driver, operate satisfactorily at lower power factors.Furthermore, the resulting power factor from the adaptive power factor correction provided by the first peak current control feedback circuit 200 is much better than what would be achieved if the primary winding current were held constant over the entire cycle of the input voltage 235.

[0023] Instead of clamping the input voltage Vin, the Isense voltage may be clamped to provide adaptive power factor correction. For example, the controller 105 may include a second peak current control feedback circuit 300, as shown in Fig. 3. A bandgap reference circuit 210, a comparator 245, a multiplier 220, a compensation filter 215, and a comparator 205 all function as discussed with respect to the first peak current control feedback circuit 200. However, it should be noted that the input voltage Vin is no longer clamped. Instead, the Isense voltage is clamped analogously by a voltage clamp circuit 315 to generate a clamped Isense voltage 305, which is received by the comparator 245. In this regard, it is common practice to clamp the Isense voltage to provide overcurrent protection. However, such conventional clamping occurs at a peak voltage level that exceeds that generated by the peak primary winding current during normal operation.In contrast, voltage clamp circuit 315 clamps the Isense voltage at a level lower than the peak Isense voltage generated by the peak primary winding current during normal operation. Furthermore, in an overcurrent condition, a flyback converter is typically reset or turned off, while controller 105 continues to cycle power switch transistor Q1 on / off despite clamping Isense voltage 310 to generate a clamped Isense voltage 305 in second peak current control feedback circuit 300. Comparing the first peak current control feedback circuit 200 with the second peak current control feedback circuit 300, it can be seen that in both embodiments, a clamp circuit is used to clamp a signal selected from a group consisting of a reference signal (e.g., clamped version 230) or an Isense signal.

[0024] Regardless of whether the adaptive feedback control is achieved using the first peak current control feedback circuit 200 or the second peak current control feedback circuit 300, the peak current control uses a clamped signal representative of the input voltage Vin. In other words, the clamped signal has a rectified sinusoidal profile in the absence of clamping that is in-phase with the input voltage Vin. Referring again to Fig. 2, the clamped version 230 of the input voltage Vin does not have to be derived directly from the input voltage Vin, but can instead be a synthesized waveform. The synthesis only needs to be synchronized with each cycle of the input voltage Vin. Similarly, the clamped Isense voltage 305 in the constant-peak current control feedback circuit 300 does not have to be derived from the Isense voltage 310, but can instead be synthesized, as long as the resulting clamped waveform is synchronized with each cycle of the input voltage Vin. Regardless of how the clamped signal (Vin or Isense) is generated, the resulting mixed operating modes in Fig. 4 for a clamped signal 400. During each clamped portion of the clamped signal 400, a period 405 of constant-peak current operation occurs. Similarly, during each unclamped portion, in which the clamped signal resumes its rectified sinusoidal profile, a period 410 of constant-on-time operation results. Referring again to the Fig. 2 and Fig. 3, voltage clamp circuit 225 and voltage clamp circuit 315 may each have their respective clamping voltage levels responsive to a clamping command such that the respective percentages are adjusted accordingly when flyback converter 100 is operating in a constant-peak current mode or a constant-on-time mode. This adjustment may be performed automatically by controller 105 in response to operating conditions or may be in response to a user command.

[0025] In embodiments where the clamp voltage level is controlled by the controller 105, the error voltage can be used to determine the load level such that the clamp level is scaled proportionally to the determined load level. The resulting clamped signal is Fig. 5. A first clamped signal 500 represents a low-load condition where the clamping voltage is reduced to a nominal value (Vnom). As the load increases, the controller 105 continues to increase the clamping voltage level until a maximum value (Vclamp) is reached, as shown for a second clamped signal 505 (a high-load condition). At this point, no further increases in the clamping voltage level can be achieved, so the feedback loop can only deliver more power by increasing the percentage of time the constant-peak current mode of operation is used, as shown for a third clamped signal 515. This provides the ability to detect an overcurrent condition, which is particularly useful for the second peak current control feedback circuit 300 because a conventional overvoltage clamp is replaced by the voltage clamp circuit 315.In this regard, the constant peak current period in each clamped signal cycle has a nominal duration (Tnom). If this duration is exceeded for the third clamped signal 515, an overload condition may be detected. Constant-on-time feedback control with adaptive power factor correction

[0026] An exemplary constant-on-time feedback circuit 600 with adaptive power correction is shown in Fig. 6. A first comparator 605, such as a differential amplifier, receives a ramp voltage (or current) signal 630 from a ramp generator 610. A second comparator 615 (which may also comprise a differential amplifier) ​​provides an error signal (Verror) to the first comparator 605 based on the difference between a reference voltage Vref and the Vsense signal. A suitable reference voltage generator, such as a bandgap reference circuit 620, may be used to provide the reference voltage Vref. When the ramp generator 610 generates the ramp voltage using a constant slope, a conventional constant-on-time control loop results. This is because the error signal Verror can be considered relatively constant over a given cycle of the input voltage Vin.Comparing a constant-slope ramp signal with the relatively static error signal Verror thus produces a constant on-time for each cycle of the power switch transistor Q1, as is conventional, to result in a high power factor at the expense of a relatively high output voltage ripple. To provide a significantly reduced voltage ripple (e.g., a 50% reduction) while still providing a relatively high power factor (such as 0.7 or greater), a slope control module 625 varies a slope for the ramp generator 610 across a constant-peak current mode of operation during each cycle of the input voltage Vin. The slope control module 625 maintains the slope constant over a remaining portion of each cycle of the input voltage Vin.A compensation filter (not shown) may be used to filter the error signal Verror to prevent the constant-on-time feedback circuit 600 from responding to the tilt modulation provided by the tilt control module 625. Alternatively, the bandwidth of the comparator 615 may be made relatively low to provide the desired compensation.

[0027] A resulting waveform for the ramp signal 630 can be as shown in Fig. 7. In each cycle of the input voltage Vin (and thus in each ramp slope cycle), the ramp slope is held constant over an initial constant on-time period and a final constant on-time period. Between these two periods, the slope has a sinusoidal peak in each ramp slope cycle. During these peak portions, the increasing ramp slope results in shorter and shorter on-times until a shortest switch on-time is reached. The switch on-times would then be increased until the ramp slope is constant again. The switch on-times during the sinusoidal peak portion of each ramp slope cycle are thus consistent with a constant-peak current mode of operation. The remaining constant slope portions of each ramp slope cycle correspond to a constant-on-time mode of operation.Regarding synchronizing the generation of the constant slope periods with the constant peak current period in each ramp slope cycle, the slope control module 625 may receive a timing command derived from the cycling of the input voltage Vin. Additionally, the controller 105 may instruct the slope control module 625 to analogously vary the relative proportions of the constant peak current portion compared to the constant on-time portions in each ramp slope period in response to changing load conditions, as described with respect to FIG. Fig. 5. The slope control module 625 may generate the changing ramp slope command, for example, using selectable resistors R. Further, the changing ramp slope may be performed in a piecewise linear manner that approximates the desired sinusoidal profile during the constant-peak current periods.

[0028] The present invention is defined by the claims. As those skilled in the art will now recognize, and depending on the particular application at hand, many modifications, substitutions, and variations may be made in and to the materials, devices, configurations, and methods of use of the devices of the present disclosure without departing from the scope thereof. In view of this, the scope of the present disclosure should not be limited to the specific embodiments illustrated and described herein, which are merely exemplary, but rather should be fully consistent with the appended claims and their functional equivalents.

Claims

[1] A flyback converter control device (105) comprising: an error signal generator (615) configured to generate an error signal (Verror) proportional to a difference between a reference signal (Vref) and a feedback signal (Vsense); a ramp generator (610) configured to cyclically generate a ramp signal (630); a comparator (605) configured to turn off a power switch in response to the ramp signal (630) corresponding to the error signal (Verror); and a ramp slope control circuit (625) configured to control a ramp slope for the ramp signal (630) such that the ramp slope has a substantially sinusoidal peak period for each cycle of an input voltage (Vin), and such that the ramp slope is maintained constant during a remaining portion of each cycle of the input voltage (Vin). [2] The flyback converter control device (105) according to claim 1, further comprising a bandgap reference circuit (620) configured to generate the reference signal (Vref) as a bandgap reference voltage. [3] The flyback converter controller (105) of claim 1, wherein the ramp slope controller (625) is further configured to control the ramp slope by selecting from a plurality of selectable resistors (R) to generate a ramp slope command. [4] The flyback converter controller (105) of claim 1, wherein the ramp slope control circuit (625) is further configured to control the ramp slope such that the substantially sinusoidal peak period is a piecewise linear period. [5] A switching power converter control method comprising: generating a ramp signal (630) that, during each cycle of a sinusoidally varying input voltage, has an initial constant ramp slope and then a substantially sinusoidal peak during a period of constant peak current and finally is constant again; Comparing the ramp signal (630) with an error signal (Verror); cyclically switching a power switch for the switching power converter on and off during each cycle of the input voltage, wherein the switching off of the power switch is in response to the ramp signal (630) corresponding to the error signal (Verror); Varying a duration of the constant peak period depending on a load level; and Detecting a peak current condition based on the duration of the constant peak period exceeding a threshold. [6] The switching power converter control method according to claim 5, further comprising generating the error signal (Verror) in response to a comparison of a reference signal (Vref) with a feedback signal (Vsense). [7] The switching power converter control method according to claim 6, further comprising generating the reference signal (Vref) as a bandgap reference voltage using a bandgap reference circuit.

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