Dynamic timing calibration system and method

Abstract

To provide a system and method for performing dynamic adaptation and correction of internal delays in devices (130, 150) connected to a common time-multiplexed bus (120).SOLUTION: In the system (100), the master device (102) compensates for inherent and unknown delays in the components and in the system by measuring actual delays using multiple read values on the bus (120), thereby allowing the devices (130, 150) to operate reliably at higher bus frequencies. Intrinsic noise and jitter are used to increase the accuracy of the measurement, thereby essentially using these uncertainties as self-dithering to increase the measurement resolution. During adaptation, the delay may be adjusted in multiple step sizes to speed up the adaptation time.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 914,351 (filed October 11, 2019), which is a continuation-in-part of U.S. Patent Application No. 16 / 455,625 (June 27, 2019), and is a continuation-in-part of U.S. Patent Application No. 17 / 068,766 (filed October 12, 2020), each of which is incorporated herein by reference in its entirety.

[0002] U.S. Patent Application No. 16 / 455,625 (filed June 27, 2019) claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 721,412 (filed August 22, 2018); U.S. Provisional Patent Application No. 62 / 791,607 (filed January 11, 2019); U.S. Provisional Patent Application No. 62 / 824,985 (filed March 27, 2019); and U.S. Provisional Patent Application No. 62 / 853,654 (filed May 28, 2019), each of which is incorporated herein by reference in its entirety.

[0003] This application is also related to U.S. Provisional Patent Application No. 62 / 895,449 (filed September 3, 2019), entitled "Dynamic Timing Calibration Systems and Methods," which is incorporated herein by reference in its entirety.

[0004] Technical Field This application relates generally to a system and method for synchronization among multiple devices attached to a common bus utilizing time multiplexing of data and clock information on the common lines. [Background technology]

[0005] background Many modern communication systems allow the transfer of data between two or more connected devices (e.g., between headphones and a host processing system) via a bus system. To conserve pin count and account for physical constraints, it is often advantageous to combine two or more signals on a common bus, allowing signal sharing between devices. When these signals are time-multiplexed, the individual devices use a common synchronization source, which is typically provided by a clock line and a start-of-frame marker to identify the start of data.

[0006] A device coupled to a bus that sends out clock and frame start information is referred to herein as a master device, and a receiver of this information is referred to herein as a slave device. The source of the clock and frame start may be another device, and / or a subcircuit may provide this information to the bus for all to use. Assuming the master device communicates information to the slave devices, it is common for data to be received from the master device by the slave devices at high speeds, since the clock and data incur equal delays within the system. However, depending on internal propagation delays in the circuits involved, as well as external delays as determined by the bus diameter and the physical parameters of the bus system, there may be significant uncertainty in the arrival time of the signal propagated from the slave device and received at the master device. While this is not an issue at low transmission rates, on high-speed links, this uncertainty results in a reduction in the size of the receiver eye opening, resulting in either degraded signal quality at higher transmission rates or complete transmission failure.

[0007] Increased manufacturing costs and silicon area, and / or Very precise circuit manufacturing, with trimming of individual components, can alleviate the problem to some extent. Despite efforts to reduce this variability from individual component delays, variability due to process, voltage, and temperature (PVT) still exists. Thus, while precision design and trimming can increase transmission speeds, PVT variations severely limit performance at higher speeds.

[0008] In view of the above, there is a continuing need in the art for a low-cost, low-power bus system that facilitates high-speed communication between connected devices. Summary of the Invention [Means for solving the problem]

[0009] overview The present disclosure discloses a bus system and method that includes an automatic adjustment procedure to allow devices to self-calibrate. The approach disclosed herein enables the production of low-cost devices through the elimination of precision trimming or precision circuitry within these devices.

[0010] In various embodiments, a method includes controlling a bus to facilitate communications between a plurality of devices, the communications synchronized based at least in part on a time-multiplexed clock and data protocol, the method further including initializing the bus to a first value using a first device; receiving a second value on the bus from a second device, the second value being different from the first value; and transmitting a response to the second device based at least in part on the second value, the response configured to control a delay of the second device to calibrate communications on the bus from the second device.

[0011] The method may further include the first device estimating a delay of the second device and adjusting the delay of the second device to cause variability in the value read by the first device. In some embodiments, the method includes reading back a second value written by the second device before the second value settles on the bus. The second value may be written multiple times by the second device, and the first device may filter the read value to reduce variability in the estimate of the current readback value on the bus. The first device may request one or more devices coupled to the bus to respond with a reply and generate a command to the device to adjust the delay based at least in part on the reply, the reply including multiple responses from each responding device. The method may include adjusting an average of values ​​read from the bus to have a probability between 0 and 1 and adjusting the delay accordingly to avoid reading back the same value.

[0012] In some embodiments, the method further includes providing a bus holder in the bus circuitry configured to suppress leakage currents that may cause an indeterminate state, the bus holder maintaining a current state of the bus when not driven.

[0013] The method further includes providing a first settling mode to obtain a correct delay position estimate using a first delay step during initial correction, and providing a final settling mode to obtain a correct delay position estimate using a first delay step during initial correction. and providing a second settling mode to obtain a more accurate delay position for settling, the second settling mode using a second delay step smaller than the first delay step and settling slower than the first settling mode, and the method may further include switching between the first settling mode and the second settling mode based on a plurality of readback values. Switching between the first settling mode and the second settling mode may further include switching to the first settling mode when there is no change in value over N readouts and switching to the second settling mode when there are one or more changes in value over N readouts. The method may further include providing a plurality of adaptation speeds for the adaptation mode and The method may include determining whether the value being read back is equal to the previous value and increasing the adaptation rate up to some upper limit, and determining whether the value being read back is different from the previous value and decreasing the adaptation rate up to some lower limit.

[0014] In various embodiments, a system includes a first device coupled to a bus, the first device configured to control the bus to synchronize communications among multiple devices based at least in part on a time-multiplexed clock and data protocol and to initialize the bus to a first value, the system further including a second device communicatively coupled to the bus, the second device configured to transmit a second value on the bus, the second value being different from the first value. The first device may be configured to read the second value from the bus and transmit a response to the second device based at least in part on the second value, the response being configured to control a delay of the second device to calibrate communications on the bus from the second device. The system may be configured to include limits on the multiple calculated delay values ​​to be aligned with actual hardware values.

[0015] In some embodiments, the first device is configured to adjust the delay of the second device so that the value being read by the first device varies between two or more values. The first device may be further configured to read the value written by the second device multiple times and perform filtering of these values; the filter is configured to reduce variability in the estimate of the current readback value on the bus. The first device may be configured to set the bus to a known value and then leave the bus undriven by disabling output drivers, after which the second device may change the state of the bus.

[0016] The bus may include circuitry including a bus holder configured to eliminate problems with leakage current that can result in an indeterminate state, the bus holder maintaining the current state of the bus when not driven.

[0017] In some embodiments, the first device is configured to write initial delay values ​​to the multiple connected devices before the multiple connected devices are configured to drive the bus, the initial delay values ​​being previous delay values ​​used from the last time the system was operational as initial values ​​for updating the other connected devices. The system may further be configured to adjust the average of values ​​read from the bus to have a probability between 0 and 1, and adjust the delays accordingly to avoid reading back the same value.

[0018] The system may be configured to include a first settling mode for use during adjustment of the delay to obtain an estimate of the correct delay position, and a second settling mode configured to determine a more accurate delay position for final adjustment of the delay, the second settling mode having a smaller delay step than the first settling mode during subsequent corrections. The system may further be configured to switch between the first and second settling modes based on a plurality of readback values.

[0019] The system may further be configured to include an adaptation mode with multiple adaptation rates, where when the read back value is the same as the previous value, the adaptation rate is incrementally increased up to some upper limit, and when the read back value is different from the previous value, the adaptation rate is decremented down to some lower limit.

[0020] BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure and their advantages can be better understood by reference to the following drawings and detailed description below. It will be appreciated that like reference numerals may be used to identify like elements shown in one or more of the drawings and the accompanying drawings. It should be understood that the drawings are for purposes of illustrating embodiments of the present disclosure, and are not intended to limit the present disclosure. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram illustrating a master device and two slave devices connected to a common bus, along with delays within the devices and on the bus itself, in accordance with one or more embodiments of the present disclosure. [Figure 2] 1 is an eye diagram of a calibrated slave device in accordance with one or more embodiments of the present disclosure. [Figure 3A] FIG. 10 is a timing diagram illustrating timing information from a slave device in accordance with one or more embodiments of the present disclosure. [Figure 3B] FIG. 10 is a timing diagram illustrating timing information from a slave device in accordance with one or more embodiments of the present disclosure. [Figure 3C] FIG. 10 is a timing diagram illustrating timing information from a slave device in accordance with one or more embodiments of the present disclosure. [Figure 3D] FIG. 10 is a timing diagram illustrating timing information from a slave device in accordance with one or more embodiments of the present disclosure. [Figure 4]FIG. 1 illustrates time slots for an exemplary time-multiplexed bus system having 16 time slots in one row, including two time slots for timing information, in accordance with one or more embodiments of the present disclosure. [Figure 5] 10A-10C illustrate a slave device writing to a master device with various delays (too small, calibrated, and too large), in accordance with one or more embodiments of the present disclosure. [Figure 6] FIG. 10 is a timing comparison diagram illustrating the variability of individual samples obtained from a slave device due to jitter and noise on the bus, in accordance with one or more embodiments of the present disclosure. [Figure 7] 10 is a flowchart illustrating exemplary programming of slave device delays using one or more commands issued to the bus by a master device, in accordance with one or more embodiments of the present disclosure. [Figure 8] FIG. 2 is a block diagram illustrating internal logic from a slave device attached to a time division multiplexed bus with embedded clock information in accordance with one or more embodiments of the present disclosure. [Figure 9] FIG. 2 is a block diagram illustrating a clock recovery circuit used to adjust the delay of one or more slave devices by correcting timing events within a row or frame, in accordance with one or more embodiments of the present disclosure. [Figure 10] FIG. 10 is a block diagram illustrating a circuit that uses analog integration of returned delay information from a master device to adjust the internal delay of a slave device in accordance with one or more embodiments of the present disclosure. [Figure 11] FIG. 10 is a block diagram illustrating a delay circuit configured to adjust the internal delay of a slave device circuit using a digital control algorithm and a digital-to-analog converter to control the delay element, in accordance with one or more embodiments of the present disclosure. [Figure 12] 1 is a flowchart illustrating a program, process, and / or algorithm configured to control internal master or slave device delay using a linear search, in accordance with one or more embodiments of the present disclosure. [Figure 13] 10 is a flowchart illustrating a program, process, and / or algorithm configured to control internal master or slave device delay using a linear search method with two step sizes, in accordance with one or more embodiments of the present disclosure. [Figure 14] 1 is a flowchart illustrating a program, process, and / or algorithm configured to control internal master or slave device delay using an adaptive two-step linear search method, in accordance with one or more embodiments of the present disclosure. [Figure 15] 1 is a flowchart illustrating a program, process, and / or algorithm configured to control internal master or slave device delay using an adaptive multi-step linear search method, in accordance with one or more embodiments of the present disclosure. [Figure 16] 13 is a modification of the algorithm of FIG. 12 to include multiple read measurements before each delay adjustment, in accordance with one or more embodiments of the present disclosure. [Figure 17] 1 is a flowchart illustrating a program, process, and / or algorithm that implements a calibration procedure in which a master or slave device self-calibrates its internal delay using multiple read / write sequences, in accordance with one or more embodiments of the present disclosure. [Figure 18] FIG. 10 is a timing diagram illustrating a master or slave device configured to read delays for both falling and rising edges by performing two reads on alternating events, in accordance with one or more embodiments of the present disclosure. [Figure 19] FIG. 1 is a block diagram illustrating a master device and two slave devices connected to a common bus, along with delays within the devices and on the bus itself, in accordance with one or more embodiments of the present disclosure. [Figure 20] FIG. 1 is a block diagram illustrating a master device and two slave devices connected to a common bus, along with delays within the devices and on the bus itself, in accordance with one or more embodiments of the present disclosure. [Figure 21]FIG. 1 is a block diagram illustrating a master device and two slave devices connected to a common bus, along with delays within the devices and on the bus itself, in accordance with one or more embodiments of the present disclosure. [Figure 22] 1 illustrates exemplary calibration timing for a bus system including a master device and two slave devices connected to a common bus, along with delays within the devices and on the bus itself, in accordance with one or more embodiments of the present disclosure. [Figure 23] 1 illustrates exemplary calibration timing for a bus system including a master device and two slave devices connected to a common bus implementing two different clock or synchronization rates, along with delays within the devices and on the bus itself, in accordance with one or more embodiments of the present disclosure. [Figure 24A] 1 is a block diagram illustrating a bus device connected to a common bus and including a write timing adjustment module, along with delays within the device and on the bus itself, in accordance with one or more embodiments of the present disclosure. [Figure 24B] 1 is a block diagram illustrating a bus device connected to a common bus and including a read timing adjustment module, along with delays within the device and on the bus itself, in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0022] Detailed Description According to various embodiments of the present disclosure, systems and methods are described for achieving synchronization among multiple devices connected to a common bus on which clock and data information is combined.

[0023] For synchronization among multiple devices connected to a bus system, one device sends out a synchronization pattern that is received and used as a time reference by other devices connected to the same bus system. The internal delays of these other devices connected to the bus may be unknown. Embodiments disclosed herein include systems and methods for calibrating the delay between the time reference and individual devices.

[0024] A method for self-calibration is described herein that allows individual devices to perform their own time adjustments based on data written by them to the bus and replicated by the device providing the time reference. In this context, the device that provides the time reference is called the master device, and the device that attempts to correct its own timing is called the slave device. In various embodiments, the procedure for performing calibration will include: (i) the master device sends out a time reference (e.g., a synchronization pattern) to which the slave devices can lock; (ii) based on that information, these slave devices may be able to read information from the master device to the slave devices, because both the synchronization pattern and any commands from the master device will incur the same delay and can therefore be received reliably.

[0025] However, the delay from the slave device to the master device is unknown until it is measured, so to facilitate high-speed bus operation and avoid bus collisions, the bus is configured to optimize the timing of the transmission of data from the slave device to the master device. In some embodiments, this problem is solved by having the slave device write a value to the master device, which will change the current value of the bus state, and the master device will write the value it read to the bus for the slave device to use as an indication of its internal delay.

[0026] The slave device may be configured to adjust its internal delay based on the value read back from the master device. For example, the read back value may approach a certain probability of 0 and 1, e.g., 50%, thereby indicating that this particular delay value will result in the release of the slave device transmitter at the optimal time, from which the master device may be able to reliably read that value from the master device one time unit later, where one time unit is defined by a time reference for the clock system.

[0027] Although the methods described herein are shown using examples on a single-ended bus system, similar methods may be applied to a differential bus, where both master and slave devices would include differential transmitter and receiver circuits.

[0028] Components of a system 100 for performing bus communications between multiple components attached to a bus 120 utilizing time-multiplexed communications with embedded clock delay adjustment of the devices will now be described with reference to Figure 1. System 100 includes at least one master device 102, which may include a port 104 for external or internal communications, a bus control unit 106, a transmitter output port 108 connected to the common bus, and a receiver input port 110 also connected to the common bus. The master device may include clock generation circuitry or an external clock source (not shown), which may be located elsewhere in the system.

[0029] The bus system may include one or more slave devices, such as slave 1 130. This device includes a receiver input port 132, a clock or timing recovery circuit 134, an optional input time adjustment circuit 136, an output transmitter port 138, an output timing adjustment circuit 140, bus control circuitry 142, and various ports for communication 144. In addition to slave 1, a similar device, slave 2 150, is shown having similar circuitry (e.g., a receiver input port 152, a clock or timing recovery circuit 154, an optional input time adjustment circuit 156, an output transmitter port 158, an output timing adjustment circuit 160, bus control circuitry 162, and various ports for communication 164), although the two devices need not be identical, and neither device need be attached to the bus. In some embodiments, multiple devices are located on the bus in addition to slaves 1 and 2. The slave devices may use, for example, a DLL (delay-locked loop) or a PLL (phase-locked loop) for synchronization to the master device synchronization information. In some cases, these subcircuits may be configured to detect any signal on the bus that interferes with the operation of the PLL and DLL circuits. A time gate (not shown) may be included to filter out random data from the bus. This time gate may be used only after the slave device has acquired a lock to the bus.

[0030] Any clock and data signals from the master device to an attached slave device will experience the same delay. Therefore, the slave device may use the clock reference as stable timing to recover any data. However, internal delays in both the master and slave devices are unknown, and there are unknown external factors, such as bus delays. Therefore, there will be significant uncertainty regarding the arrival of data in the direction from the slave device to the master device. To optimize this timing, a procedure is described for obtaining highly accurate delay calibration at low cost. This procedure does not require the addition of additional special circuitry to the system. Here, factors such as jitter and noise, which are normally considered detrimental to system operation, are used to improve the system's timing resolution, thereby enabling the master and slave devices to obtain accurate timing information even when only two voltage levels are used to transmit and receive information. While the large jitter associated with very low-power systems will result in variability in received values ​​sampled near transition points, this variability will be used constructively to improve timing estimates of the total path delay. Although it is possible to coordinate the reception of data within a master device, it may be better to coordinate the actual transmission events within one or more attached slave devices for the highest possible bandwidth. In this way, any data from a slave device can be tightly aligned for the highest possible bandwidth on the bus system.

[0031] The range of delay adjustment required depends on component tolerances, bus diameter, and internal delays, which are governed by specific technology considerations. As an example, it is currently feasible to manufacture slave device receiver circuits with a variation in the output settling point compared to the input edge of +5 nanoseconds (ns) (internal delay) and + / - 10 ns, for a total variation of -5 ns to +15 ns (static delay, jitter not included).

[0032] The master device contains its own timing reference, and in some contemplated implementations, the variation within this device may be in the range of -1 to +5 ns. For a bus diameter between 0 and 200 cm (e.g., a relatively long bus system), one would obtain a delay between 0 and 12 ns (assuming a slow propagation speed of approximately 16 cm / ns). The total variation of these factors results in a total timing variation between -6 and 32 ns. To obtain a high-speed, low-power signal transmission system, it is desirable to limit the number of clock transitions, but this increases jitter in the slave device receiver circuitry.

[0033] Due to cost and system considerations, it is desirable to properly align slave device data positions regardless of manufacturing tolerances. For the lowest possible power consumption, jitter in the receiver clock recovery circuit will increase, and it is therefore desirable to limit the bandwidth loss due to misalignment of the master and slave device data patterns. With rms jitter on the order of 0.3 to 1.5 ns (realistic values), we will have a worst-case variation of + / - 2.1 to 10.5 ns in many implementations (10 -12 factor 7 for the probability of error.

[0034] For calibration to be considered successful, in some embodiments, it is desirable for the slave device data to be aligned within 1-2 ns of an optimal value, such that this factor is a small percentage of the total error budget. This value is so small that it is impractical to program or control it by one-time factory programming. Therefore, the optimal timing is defined herein. Embodiments are described that dynamically measure and control delays within a device for control purposes.

[0035] Control of slave device delay timing can occur in the master device, in the slave device, or in another device otherwise connected to the bus or component. The advantage of the master device controlling the timing is that not all slave devices require control circuitry, and thus a single circuit can control all devices, making for a simpler system than may be possible. However, it is also possible for a slave device to control its own timing if the slave device knows what values ​​the master device has read from it.

[0036] One way this can be solved is by having the master device write back the value it reads from the slave device during the calibration phase. The advantage over previous methods is that the master device only needs to write back one bit, which allows for lower bandwidth requirements during the calibration phase. The slave device itself can be entirely responsible for the calibration and does not need to rely on any special characteristics of the control algorithm located inside the master device. Alternatively, instead of providing an absolute delay control value to the slave device, the master device can signal the slave device to adjust its internal delay (e.g., no change in delay, increase delay, or decrease delay).

[0037] Figure 2 shows an eye diagram of data transmitted by a slave device operating at a relatively high frequency (e.g., 75 MHz) and using delay adjustment accurate to within + / - 1 ns. As can be seen, this leaves + / - 4.5 ns for system-wide jitter and noise, and the data will still be readable. This is equivalent to an error probability of 10 -12 This corresponds to a root mean square (rms) jitter of 643 picoseconds (ps). Without adjustment, using earlier values ​​of the required adjustment in the range of -10 to +30 ns would result in data being scattered randomly across the eye opening.

[0038] 3A-3D illustrate an embodiment of the events involved in sampling delay information from a slave device to a master device. Looking at FIG. 3A, this illustrates the events involved in measuring system delay. First, the master device sends an LH transition to signal the start of a synchronization event. Then, the master device leaves the bus floating, after which the slave device may change the bus level. Finally, the system delay (i.e., master device → slave device → master device) is shown based on the time it takes for the bus to change again (in this example, from H level to L level). Optionally, although not shown in the figure, the master device can send a copy of the value it reads from the bus, either in the same frame or row or a later row or frame, if the slave device performs any delay adjustments on its own without any other interaction from the master device. The timing diagrams are shown from the perspective of the master device. A bus holder may be included in the system to keep the bus value constant when no devices are driving the bus. The output impedance of the bus holder may be significantly higher than the impedance of the bus (transmission line) and may be significantly higher than the output impedance of the individual output drivers. Bus holders may be located within one or more components, or may not be required at all for systems with low leakage currents and high operating frequencies.

[0039] Looking at Figure 3B, there is some uncertainty in the exact time the bus changes level after the master device leaves the bus idle. This uncertainty is primarily due to the slave This is caused by jitter from the device clock recovery circuitry. There will be some uncertainty in the exact master device timing, but this timing will be much more stable with a direct connection to the reference clock.

[0040] 3C, if a master device reads a bus value long after a slave device has changed it, the value read will always be the same. In the case shown, the master device will always read an L value or zero. This indicates that the delay value set inside the slave device is too low, as it may occupy more bandwidth than is actually needed for correct operation.

[0041] 3D, if the master device reads the bus value significantly earlier than the time when the slave device changes the bus value, it will always read the same value. In this case, the master device will always read H or 1. This indicates that the delay value was set too large, as the master device will not be able to receive any information from the slave device in this time slot.

[0042] Figure 4 shows one embodiment of a time-multiplexed system with 16 time slots in each row. Each row also uses two time slots to convey synchronization information from the master device to the slave devices. All other time slots may be used to transfer data between the master and slave devices or to allow the direction of data transfer to change. The master device will read data from the slave devices at the center of the time slot and at the edge of the time slot to obtain delay information (i.e., 1 / 2 clock cycles earlier).

[0043] Looking at the diagram, the last time slot (15) is used to predefine the bus to a low level, marking the start of the synchronization pulse. The next time slot (number 0) is used to set the bus high, and the boundary between the low-to-high transitions is used by the slave device's clock recovery circuit to ensure proper synchronization between the master and slave devices. Time slot 1 is used to set the bus to idle, allowing the bus direction to change from the master device to the slave device and write to the bus. The output level may change anywhere within time slot 1 based on internal delays within the slave device and external delays unknown to the slave device. The master device can read back the bus level at the transition between time slots 1 and 2. This read will be used for delay compensation. Finally, the bus value located in the middle of time slot 2 will be used as the return value from the slave device for the actual data transfer, because here the bus has had time to settle and this scheme allows for the maximum tolerance for jitter and noise (i.e., the sampling point is in the middle of the "data eye"). Time slots 3-14 are shown idle in the figure, but may contain actual data transfers between devices, as long as the data would not interfere with the delay measurements.

[0044] Figure 5 shows the details of the delay measurement in more detail. The first timing diagram at the top shows a slave device with its delay compensation set too low, resulting in the master device always reading back changes in bus level, even at test sampling points between time slot 1 and time slot 2. In the second timing diagram, the master device will read alternating values ​​of 0 and 1 (i.e., sometimes it will see a change in bus level, and sometimes it will not). Due to jitter and noise, the values ​​being read back will alternate randomly. Finally, the last timing diagram at the bottom of the diagram shows a slave device with its delay compensation set too long, causing it to respond too slowly to the changes required. The master device will read back alternating values ​​of 0 and 1 (i.e., sometimes it will see a change in bus level, and sometimes it will not). Finally, the last timing diagram at the bottom of the diagram shows a slave device with its delay compensation set too long, causing it to respond too slowly to the changes required. The master device will read back alternating values ​​of 1 and 0 (i.e., sometimes it will see a change in bus level, and sometimes it will not). When measuring the bus level using the MAX 16488, you will never see a change in the bus level. Finally, the actual value that will be used for communication between the slave and master devices is the same as the value tested. 1 After / 2 time slots, i.e., in the middle of time slot 2 The value sampled at

[0045] Figure 6 shows that the master device's measurement of the value written by the slave device will be modulated by noise and timing jitter. However, this variability may be used to obtain more than two levels when multiple samples are combined for more precise adjustment. Due to the requirement for very low power consumption in the slave device, timing jitter becomes significant. However, in this application, this is used to our advantage because it allows us to form an average of multiple measured values, which together provide information about the transition zone. We can not only determine whether the value is before or after the transition, but also accurately use the averaged value to adjust the delay setting to an optimal value, resulting in an average return value near 50% of either read value (50%L and 50%H) in many embodiments. If less than 50% of the returned bus values ​​show no change, it means the delay should be smaller for better signal integrity, and if they show more than 50% change, it means the delay should be set to a smaller value to optimize bus bandwidth. The master device may adjust the internal timing of the slave devices themselves, or simply write back the read values ​​and let the slave devices adjust them themselves. If the master device were to adjust its own receiver timing, the slave devices would not need any adjustments, but this scheme, while simpler, would result in less than optimal use of bandwidth because slave devices could interfere with each other unless extra bandwidth was allocated for fluctuations. Therefore, it is recommended to adjust the transmitter timing rather than the receiver timing.

[0046] 7 illustrates an example of one or more commands issued by a master device to a bus system to read and optimally compensate for slave device delays, according to one or more embodiments. Issuing commands to the bus proceeds as follows: First, the master device issues synchronization information long enough that all devices attached to the bus will acquire synchronization with their clock receiver circuits. Now, those devices can read commands and data from the master device, but their own transmitter circuits have not yet been properly calibrated for internal and external delays.

[0047] The commands and procedures shown in algorithm 700 illustrate an example of the overall steps involved. First, the master device issues a command to select which device to time correct in step 702. The master device sets an initial delay for this slave device in step 704 (this step may be skipped in some embodiments). Then, in step 706, the master device initializes the bus to a known value and leaves it undriven. Note that this event may be combined with a naturally occurring synchronization pulse being sent on every row (time slots 15 and 0 in FIGS. 4 and 5). In step 708, the selected device responds by changing the current bus value based on the slave device's internal timing. In step 710, the master device then reads back the current value from the bus based on its own timing. In step 712, the master device may optionally write back the value it read from the bus if the purpose is to have the slave device adjust its internal timing itself. Note that the slave device can reliably read data from the master device because the synchronization pulse and command from the master device are equally delayed. Optional In step 714, the data is averaged before any correction is made. In step 716, it is considered whether the value is reliable at this delay position, if not it returns to step 706. In step 718, it is considered whether the delay estimation is complete, if so it changes the delay setting and continues with the new delay value (720), if not it informs the slave device that more reads are needed in step 719. If the delay value is the optimal value, it should be used for the slave device (722), and once all devices attached to the bus have been calibrated in step 724 the algorithm is complete.

[0048] FIG. 8 shows an exemplary embodiment of a circuit 800 for performing internal delay compensation within a slave device based on a DLL topology. In this example, delay cells are used to obtain locking with the master device and control the release of data from the slave device. If the clock recovery circuit is based on a DLL topology, using this circuit for delay compensation may be advantageous because two circuits (clock recovery and delay compensation) may be combined into one circuit. As shown, the circuit 800 includes an input receive buffer 802 for receiving bus data, a time gate 804 used to filter bus traffic from synchronization pulses once the slave device is locked to the master device, a bus synchronization circuit 806 that ensures safe synchronization to the master device and controls the time gate, delay cells 808 (eight are shown, but the number may vary depending on the application) controlled by the bus synchronization circuit and used to divide a single row of data into individual time slots, a multiplexer 810 that selects, delays, and controls output timing, a transmit register 812 that contains the next data to be transmitted by the slave device, and a transmit output buffer 814 connected to the bus. Based on the measured delay values, either the master or slave device will control the multiplexer settings, thereby adjusting the timing to an optimal value. This control may be performed once the system starts up, or may be performed continuously to compensate for environmental changes (e.g., temperature changes, which may affect internal and external delays in the bus system). Thus, by continuously monitoring and correcting these delays, these device variations can be compensated for, and the system can continue to operate in an optimal manner. If the required time adjustments exceed those supported by a single time slot, the slave devices may be configured to transmit pulses in different time slots to accommodate these larger delay adjustments (the delay adjustments shown support delay adjustments within a single time slot).

[0049] FIG. 9 illustrates an exemplary system 900 for performing internal delay correction within a slave device based on a digital correction unit, according to one or more embodiments. System 900 may include a clock recovery circuit 902, which includes a PLL locked to a synchronization pattern provided by the master device, a synchronization circuit, and a time gate (not shown) provided to remove data from affecting the clock recovery. This time gate may be activated only after the device acquires lock to the original synchronization pattern to ensure lock. System 900 may also include a timing counter 903, an adder 904 (time correction unit) that changes the time of a transmit event, a comparator 906 that detects the start of data transmission, a register 908 for slave device output data, and an actual transmit output buffer 910. In some cases, the actual timing event may be programmed instead of adding a delay to the start of data. In this way, adder 904 is not required; instead, the correct start of data is provided to comparator 906.

[0050] By using both edges of the clock for timing adjustment, timing accuracy can be improved by almost double. For example, by having a 250MHz internal high-speed clock, , both edges are used, allowing a timing correction of 2ns. Therefore, at the optimum delay setting, the error is at most 1ns (i.e., + / - 1.0ns). The reason the timing is limited to less than 2x in this case is due to the clock duty cycle being less than a perfect 50% in practical systems.

[0051] 10 shows an example system 1000 for performing internal delay correction within a slave device based on an integrator 1002, a delay cell 1004 controlled by the output from the integrator, and a transmitter output buffer 1006. Here, delay correction is performed continuously by summing the returned values ​​and using these integrated values ​​to control the delay cell. Note that due to internal leakage and other factors, this circuit may require delay measurements to be made periodically or it may drift from its optimum position.

[0052] FIG. 11 shows an example circuit 1100 for performing internal delay correction within a slave device based on a DAC (digital-to-analog converter) 1102, a delay cell 1104, and an output transmit buffer 1106. This circuit uses a digitally calculated optimal delay value to control the DAC, and the analog output from the DAC controls the delay of the delay cell, which in turn controls the output transmit buffer. The advantage of this circuit over system 1000 is that it drifts relatively little, and internal leakage currents do not move it significantly away from the optimal delay position. The disadvantage is the need for a DAC, which does not need to be highly accurate as long as it is monotonic and has a sufficient number of steps to control the delay cell. Thus, in some applications, a resolution as little as 6 bits may be sufficient to control the delay. For systems that experience significant drift with temperature, the calibration algorithm may need to be run continuously.

[0053] Four methods for obtaining controlled delay between a master device and a slave device are shown in Figures 12-15, respectively. There are other methods that can be used to control these devices, such as a dichotomous search or a binary search. However, the method described here has the advantage that it is simple and can ensure that the steps taken are small enough so that there is no risk of the slave device starting to overwrite any information provided by the master device or other devices attached to the bus. Furthermore, the algorithm described herein is very noise-robust to noise that affects delay with appropriate parameter selection.

[0054] FIG. 12 shows an example embodiment of a flowchart of the first algorithm. This method 1200 involves a linear search algorithm. For each cycle, the master device sets the bus, and the slave device responds by changing the bus value. Based on the value read by the master device, the delay within the slave device will be increased or decreased by a small amount of time. In other words, if the slave device writes to the bus too slowly, the delay within the slave device will be decreased by a small amount after executing the write to the master device; similarly, if the slave device writes too quickly (e.g., if more than half of all reads by the master device are seen to have changed), the delay value will be increased. This method ensures that delay jitter is well controlled by changing the delay in small steps (e.g., 0.05 ns), but this also means that for large delay changes (e.g., 20 ns), the algorithm may go through hundreds of steps (iterations) before reaching the ideal delay. Thus, this method is a compromise between fast settling time and good convergence, and requires a certain amount of time to achieve a desired result. For a given low jitter requirement, this will result in a long settling time. The method works as described in detail below.

[0055] The algorithm begins at step 1202, which is the entry point to the calibration procedure. Then, in step 1204, the master device sets the bus to a known value, and in step 1206, the slave device changes the value on the bus. After reading the current value from the bus, the master device can optionally write back the value it read from the bus in step 1209, and the slave device may use this value for self-calibration. This step may not be necessary if the master device controls the slave device delay. Note that the master device operates in steps 1204 and 1208 based on its own timing, and similarly, the slave device will perform step 1206 based on the slave device's internal timing. Typically, these timing references will be different, and therefore timing correction may be required. In step 1210, a decision is made based on the returned value from the bus (read in step 1208). If the value has changed, we know that the delay is too large—statistically speaking, the returned value is heavily affected by jitter and noise. Thus, if this is the case, the current delay will be adjusted slightly upward, say +0.05 ns. If not, i.e., if no change in the bus value was detected, then the delay is too large (again in a statistical sense) and we will make a small correction in the opposite direction, say -0.05 ns. These values ​​are just examples; many other values ​​could be used. It is a compromise, as choosing a larger value will result in a faster search time to find the optimal delay, but the final output jitter due to random fluctuations will be larger. In step 1216, we ensure that the output delay is within system limits; i.e., we do not increase its value beyond what is known as the maximum we can correct for, nor decrease it beyond the minimum the circuit can handle.Next, in step 1218, the integrated delay value is mapped from the internal register to an actual delay setting (e.g., the number of actual delay settings may be less than the precision used to calculate the value), and in step 1220, the actual slave device timing is corrected. Finally, in step 1220, it is determined whether the algorithm is complete. If the algorithm is not complete, it will continue from step 1204. The determination of whether the algorithm is complete can be made either by using the maximum known number of iterations the algorithm can take, or by using an average value of the number of returned 0s and 1s. When this average over many iterations (e.g., 100) reaches 0.50, the optimal delay timing correction is reached. To allow for some tolerance, the algorithm may terminate when the average reaches a value, for example, in the range of 0.47 to 0.53. In another embodiment, the master device may adjust the slave device delay in step 1209 (e.g., no delay change, increase the delay, or decrease the delay).

[0056] FIG. 13 shows a flowchart 1300 of the second algorithm. This method is an improved linear search algorithm by including two adaptation speeds. First, the method performs a larger delay adjustment (e.g., 1-2 ns). After the first transition is found (the master device samples from the slave device by measuring a value different from the previous value from the slave device), it changes to a slower tracking mode with a time step of around 0.05 ns to ensure jitter is controlled. This significantly improves the settling time of the simple method, but with just one noisy measurement, the method changes to the slow mode and then adapts more slowly. Jitter is slightly higher with this method compared to Method 1. This method functions as described in detail below.

[0057] The algorithm begins at step 1302 and sets a flag (first transition) equal to zero at step 1304. This flag is used to find the point at which the returned read value differs from the previous read bus value after a slave device response. In this example, the master device sets the bus to a known value and then releases the bus while the value may be maintained by the bus holder. In step 1308, the slave device modifies the bus based on its internal timing, and in step 1310, the master device reads the bus based on the master device internal timing. In step 1312, the master device may optionally write back the value it read from the bus so that the slave device can self-calibrate its own timing. This optional step is not required if the master device is directly setting the slave device's timing values, but may be included if the slave device is to control the timing itself. In another embodiment, the master device may also control slave device timing by issuing a change to the current delay value (e.g., no change, increase delay, decrease delay) in step 1312.

[0058] In step 1314, it is determined whether the bus value read back by the master device is the same as the previous value read back by the master device. (Note that in the first sequence of executing this algorithm, it shall be assumed that the two values ​​are the same because there is no information available and the flag "first transition" shall remain zero.) If the two values ​​are the same, the flag "first transition" shall remain zero, but if the two values ​​are different, it shall be set to 1 or true in step 1316. This flag is used to perform a fast search first and, if a transition is found, perform a slower, more accurate search. In step 1318, a decision is made based on the value of the "first transition" flag. If there is no change in value, continue with the fast search 1322, but if a single transition is found, continue with a slower, more accurate delay correction as specified in step 1320. The value of the delay value in fast forward mode may be, for example, 0.75 ns, but it will depend on the application, and the value for slower, more accurate stepping may be, for example, 0.125 ns, depending on the application. These values ​​can be easily expressed using binary arithmetic. The process performed in steps 1324-1336 may be the same as steps 1210-1222 described in Method 1 and is not repeated. This algorithm has the advantage of faster search time while maintaining the same jitter performance as Algorithm 1.

[0059] The third algorithm, shown in Figure 14, is an evolution of the second algorithm; this algorithm can constantly change between slow and fast modes based on the previous N values. If the N previous readings are all the same (i.e., trending in the same direction), the larger of the two steps will be taken (ΔT LARGE ). If there is any difference between the N most recent values ​​read, a smaller time step will be taken (ΔT SMALLThis method is much less sensitive to noise and jitter than Method 2 and achieves faster settling times with slightly more jitter than Method 2. This method works as described in detail below.

[0060] Algorithm 1400 begins at step 1402, and then the master device sets the bus to a known value and releases it at step 1404. A bus holder may be present and may maintain the bus state if no devices are driving the bus with a medium output impedance (e.g., in the range of 1-2 kΩ). The slave device changes the bus value at step 1406, and the master device reads back the bus value based on its own timing at step 1408. The master device may optionally write the read value back to the bus at step 1410 for the slave device to use for self-adjustment. If the master device is controlling the delay of the slave device, this step is not necessary, and the master device may control the delay of the slave device either by issuing an exact delay value or by controlling the current value (e.g., no change, increase delay, decrease delay). Step 1 At 412, a decision is made based on the past N samples read by the master device. If there is no change in the last N samples, then process 1414 is performed in which a large adaptation value is used. The value of the fast adaptation value (process 1414) may be 0.75 ns, and the value of the slow adaptation value (process 1416) may be 0.125 ns. The value of N may be 8 in various embodiments to ensure that there is no oscillation between the high and low adaptation values, even in the presence of large noise. Steps 1418-1432 are the same as steps 1210-1224, and therefore will not be repeated. This algorithm works well in the presence of large noise and will generally adapt as fast as possible using only two step values, although there may be some steps taken too slowly.

[0061] The fourth algorithm, shown in Figure 15, is a further evolution compared to the third algorithm shown in Figure 14. Here, the master device increases the time delay change whenever it samples the same value on the bus twice, and decreases the delay otherwise. At some point, an equilibrium is reached, giving an average read value close to 50% of the two possible return values ​​(L or H, 0 and 1) depending on the update coefficient. In other words, the length of the next delay adjustment is as follows for a value change: ΔT = α1 × ΔT, where α1 will typically be in the range of 1.05 to 1.2. It may be advantageous to choose a number that is easily represented without rounding errors in binary arithmetic, for example, 1 + 1 / 8 = 1.125, which can be realized as a coefficient using addition instead of multiplication.

[0062] If there are no changes in value, the length of the next delay adjustment is: ΔT = α2 × ΔT, where α2 will typically be in the range of 0.8 to 0.95. It may be advantageous to choose a number that is easily represented in binary arithmetic without rounding errors, for example, 1-1 / 8 = 0.875, which can be implemented as a coefficient using addition instead of multiplication. Due to the adaptive step size, this method works the fastest and has roughly the same jitter performance as Method 1 (jitter can be further reduced by slightly increasing the settling time). To ensure the stability of the algorithm, there are bounds on the minimum and maximum delay change, and therefore minimum and maximum step sizes in the delay are implemented. This method works as described in detail below.

[0063] In step 1502, algorithm 1500 begins. In step 1504, the master device sets the bus to a known value, and in step 1506, the slave device changes the bus value based on its own timing. In step 1508, the master device reads a value on the bus based on the master device's timing. In optional step 1510, the master device writes back the value it read. This step is only required if the slave device is attempting to self-adjust its internal timing. This step is not necessary if the master device is controlling the slave device's delay. In this case, the master device will control the slave device's timing by writing an absolute delay value or by issuing a change to the current delay value (e.g., no change, increase delay, decrease delay). In step 1512, a determination is made whether the two previous values ​​read from the bus by the master device are the same. In the first iteration of this algorithm, a default initial delay value, e.g., 0.75 ns, is used in step 1514. If the two returned values ​​are the same, this indicates that the delay adjustment is within the range of a noise-free delay adjustment. This means we should try to move faster. This is accomplished by multiplying the delay adjust value by a factor greater than 1, for example 1.125. However, if the two values ​​are different, this indicates that we are in a noisy region in the middle of the transition, often fluctuating between 0 and 1, so a smaller step is used (step 1516). Here, the delay adjust correction factor is less than 1 (for example, 0.87 5). From this point of view, we now limit the time adjustment in step 1518 to a certain range, for example, 1 / 128 to 1.0 ns, due to the limited precision of the calculation, to avoid overwriting data from other devices. Steps 1520 to 1534 may be the same as steps 1210 to 1224, and therefore, the description will not be repeated.

[0064] Finally, the average of the returned values ​​may be used as an indicator of when the algorithm has finished, for example, by forming a weighted average, e.g., average = 0.99 * average + 0.01 x (most recent reading). In some applications, a fixed, finite number of iterations may instead be used based on known information about noise and jitter levels and known settling characteristics; for example, the algorithm may be considered complete after 40 iterations.

[0065] Each of these methods can be complemented by forming an average of two or more values ​​sampled on the bus, which may be particularly effective when a master device is controlling slave devices, since in this case write operations take longer than reading a single bit, so it may be beneficial to perform multiple read operations before each write operation.

[0066] In some practical implementations, an initial guess for the delay is used. Since there is a known range within which the entire system must converge, say within -10 to +30 ns delay, it may be reasonable to choose an initial value equal to the midpoint of this range. However, to avoid issues with overwriting other device outputs, including overwriting the master device output, it may be advantageous to increase the starting point slightly, e.g., use an initial delay value of 15 ns in the example above. This means that it will take slightly longer to converge to the most negative delay setting compared to the most positive delay setting (i.e., converging to -10 ns will take longer than +30 ns). The most conservative design approach would choose the maximum delay as the initial value for maximum protection against premature overwrites from other devices.

[0067] FIG. 16 illustrates an example of extending Algorithm 1 to the use of multiple read samples before performing a delay adjustment. Apart from averaging multiple samples before performing an adjustment, algorithm 1600 may be similar to the first algorithm of FIG. 12. For example, steps 1606, 1608, 1610, 1612, and 1614 correspond to steps 1204, 1206, 1208, 1209, and 1210, respectively. Some modifications include initializing a value to zero (step 1604), forming a sum in steps 1616 and 1618 based on previous reads from the bus, repeating the read from the bus K times based on a decision made in step 1622, and forming a final delay correction in step 1624. Steps 1620, 1626, 1628, and 1630 may correspond to steps 1216, 1218, 1220, and 1222, respectively, of FIG. 12.

[0068] The second, third, and fourth algorithms can similarly be extended to use multiple samples before performing a delay adjustment. However, when the control algorithm is located in the slave device, it may be better to dynamically change the delay value between each read and write operation because the slave device itself can change multiple bits within the device based on reading a single bit from the bus. Thus, the update operation requires less bandwidth and is therefore potentially more efficient. In another embodiment, instead of updating the absolute delay value within the slave device, the master device would issue a change to the current value to reduce the bandwidth required for the adjustment.

[0069] In addition to these methods, methods using, for example, dichotomous and binary searches may also be used, however, due to problems with adjusting the delay so negatively that the slave device output data begins to collide with the master device value and associated unknown value, it is suggested that these methods should be used with some limit on the maximum step size included to avoid this situation.

[0070] A more accurate comparison of the four algorithms can be achieved using computer simulations. The simulations were based on the following specific settings for the algorithms: a typical jitter level of 1.2 ns (rms), Gaussian noise. In practical circuits, this would typically be in the range of 0.3 to 1.5 ns after receiving and controlling within the slave device.

[0071] First algorithm (Fig. 12): The step size was set to 0.05 ns and the delay adjustment precision was set to 0.1 ns.

[0072] Second algorithm (Figure 13): The step sizes were set to 0.125 ns and 0.75 ns. The delay adjustment precision was set to 0.1 ns. The initial step value was the larger step size (0.75 ns).

[0073] Third algorithm (Figure 14): The step sizes were set to 0.125 ns and 0.75 ns. The delay adjustment precision was set to 0.1 ns. If the level read back from the master device did not change for N=8 consecutive measurements, the step size was set to 0.75 ns. If there was any change before 8 measurements of the same value were achieved, the value was set back to the lower value (0.05 ns). The initial step value was the larger step size.

[0074] Fourth Algorithm (Figure 15): The delay size was set between 1 / 128 ns and 1 ns. The delay adjustment accuracy was set to 0.1 ns or 2.0 ns (see Table 1). The initial delay step was 0.75 ns. The delay step change was modified by a factor of 1.125 if the previous delay value was the same as the current read value by the master device. If there was a difference between the current value read by the master device and the previous value, the delay step size was multiplied by 0.875. Note that this multiplication of 1.125 and 0.875 can be implemented as either a simple addition (1 + 1 / 8) or (1 - 1 / 8) using binary arithmetic. The actual delay was updated based on the current read value; if the value was low, the last delay value was incremented by the delay step value. If the current read value was high, the actual delay was decremented by the current delay step value.

[0075] [Table 1]

[0076] In this embodiment, the error probability is 10 -12 and the in-lock search time and The variations in the delay and in-lock time base are based on 12 simulations. A delay jitter of 0.1 dt means an output resolution of 100 ps in the delay adjustment, and 2.0 dt means an output resolution of 2.0 ns in the delay adjustment.

[0077] FIG. 17 shows an example algorithm or bus command used to adjust the delay of a slave device, according to one or more embodiments. The algorithm 1700 begins at step 1702, where the master device selects a device to respond to. In step 1704, the master device may set an initial delay value for the slave device. Note that this step is optional. The slave device may already be adapted to a good delay value, and the algorithm may run simply for minor adjustments. The slave device may also have an initial internal value that will not require any adjustment. Again, in this case, the master device would not need to set the initial value internally in the slave device.

[0078] In step 1706, the master device sets the bus to a known value based on the master device's internal timing. By changing the known value that the master device sends out to the bus in step 1706 (e.g., alternating between L and H) before the slave device changes the value on the bus, the adjusted delay may be based on both falling and rising data edges from both the master and slave devices, thereby forming a more accurate average.

[0079] In step 1708, the slave device responds by writing a different value back onto the bus based on its own internal timing. In step 1710, the master device reads back the value on the bus based on its own timing. Typically, this read event occurs when the data from the slave device is deemed sufficiently settled. 1 / 2 time In step 1712, the master device writes the read value back to the bus. This can occur on the same row as the read event (e.g., in time slots 3-14, with the timing shown in Figures 4-5) or on a subsequent row. Alternatively, the master device may control the absolute delay or issue a change to the current delay in the slave device.

[0080] In step 1714, the slave device adjusts its own internal delay based on the value written back by the master device. The delay adaptation and adjustment may be performed as shown in four algorithms (shown in Figures 12-15, respectively).

[0081] In step 1716, a determination is made whether the adjustment procedure is complete. This may be based on a finite, known number of iterations (e.g., each delay adjustment command may use 32 delay adjustments), or it may be based on delay convergence (based on a roughly equal number of received logic 0s and 1s, the readback value reaching an average near 0.50, or the position remaining unchanged for some time). If the number of steps is not finite, either the master or slave device must provide feedback to communicate when the algorithm is complete; if not, continue adjustment from step 1706. Finally, in step 1718, a determination is made whether all devices are properly adjusted. If this is not the case, proceed to step 1702. The determination of when the algorithm is complete can be based on the current step size, the number of iterations used, or when the average readback value is within a given interval, e.g., 0.4-0.6, and a certain number of iterations is reached, or whether the adjusted delay value remains unchanged over a given number of iterations.

[0082] In other embodiments, the master device adjusts the internal timing of the slave device by issuing a change (e.g., no change, an increase, or a decrease) to the current delay value in step 1712.

[0083] In some embodiments, two slave devices may adjust the delay between them, as well as between a master and a slave device, where the receiving slave device reads the current bus value change and adjusts the timing of the sending slave device by reflecting the read value or by adjusting the actual delay at the other slave device.

[0084] In some embodiments, a slave device may adjust its own timing without any interaction from any other device, in which case the timing may be closely aligned with the received synchronization pattern but would not include adjustments for bus diameter and other delays in the system.

[0085] FIG. 18 shows an example of a master device reading two slave device values, according to one or more embodiments. Here, the slave device will respond with both falling and rising transitions. If the delay measurement is based on unknown or uncalibrated time steps internal to the slave device, this may be used to find the number of time steps required for a given time unit by finding the number or delay between the two settings. By dividing this value by two, one can find the number of delay units equal to half the clock period. Furthermore, this final method may allow the master device to obtain measurements of both rising and falling edge delays.

[0086] As described herein, when a slave device changes a bus value and the master device reads and then reflects that value so that the slave device can adjust its bus write timing for optimal reception reliability, the system timing topology is essentially Case 1 of Table 2, as identified by timing line 1902 in Figure 19. Figure 19 shows a master device and two slave devices connected to a common bus, according to one or more embodiments of the present disclosure and similar to system 100 of Figure 1, along with delays within the devices and on the bus itself. This is the case for standard slave-to-master calibration.

[0087] If another slave device, slave 2, reflects the value it reads from the bus state change by slave 1, this slave reflected value is adjusted according to the timing adjustments described herein. A variety of processes for can be used to optimize the timing of writes from slave 1 to slave 2. Such a system timing topology is essentially Case 2 of Table 2, as identified by timing line 2002 in Figure 20.

[0088] When a slave device adapts its write time to its own output, it compensates for the inherent delay from its internal timing to the externally observed output, and therefore its write is aligned with the corresponding master device synchronization edge. This is so because its internal read logic allows the same delay for both the master device synchronization signal and the self-generated write value or signal. Thus, in this case, the slave device timing will be very precisely aligned with the received master device timing without requiring expensive tuning / programming. Such a system timing topology is essentially Case 3 of Table 2, as identified by timing line 2102 in Figure 21.

[0089] In Case 3, the Slave 1 device writes to the bus and simultaneously reads back from the bus. This process is used to adjust Slave 1's write timing so that its output data is aligned with the synchronization pattern provided by the master device. This process may be used to correct for any internal timing differences between bus devices and ensure that outputs are perfectly aligned to the timing edges (real or virtual, provided by internal timing division) provided by the master device. If multiple devices are located near Slave 1, it is possible to write to all such devices simultaneously without any device modification because the edges will be aligned with the master device timing and other devices will receive data with the same time reference. Case 4 in Table 2 is similar to Case 3 but focuses on the master device. If the master's internal receive timing is fixed, a procedure similar to Case 2 can be used to correct for transmit and receive timing differences to obtain perfect timing, for example, for self-tests or collision tests. In various embodiments, Case 4 may be performed at bus startup, even before slave devices are attached to the bus, to save / reduce the time required to complete a full system timing calibration. The master device may use the initial 0-1 sync pulse to adjust its internal sampling point for reading from the bus. By adjusting the write timing and keeping the read point fixed, the external 0-1 event can be aligned with the master device's read point. In this way, small timing differences may be eliminated, resulting in faster bus operating speeds. For example, both the sync and data from the master device may be time-shifted.

[0090] FIG. 24A is a block diagram illustrating a bus device (e.g., master device 102) connected to bus 120 and including write timing adjustment module or logic 2406A, in accordance with one or more embodiments of the present disclosure, where an inherent write delay ΔT1 is associated with a transmitter / output port 108 within the bus device and an inherent read delay ΔT2 is associated with a receiver / input port 110 within the bus device. In FIG. 24A, master device 102 may be configured to adjust the write delay of master device 102 using write timing adjustment module 2406A to compensate for the inherent read delay ΔT2 and to properly align master write event 2406B and master read event 2406C with respect to bus communication timing, as described with respect to Case 4. In various embodiments, one or more of write timing adjustment module 2406A, master write event 2406B, and / or master read event 2406C may be implemented by and / or within bus control unit 106, as shown in FIG. 1. A similar timing adjustment module is It may be implemented within any of the slave devices described herein.

[0091] Various write timing adjustment examples are summarized in Table 1 below.

[0092] [Table 2]

[0093] Alternatively, or in addition to write timing adjustments, read timing adjustments may be made. In the case of read timing, the exact time at which a receive event occurs in a slave or master device is corrected by correcting the corresponding receive timing. In these cases, processes similar to those described herein are employed, but it is important to ensure that the timing changes occur in the correct manner.

[0094] For example, the write timing adjustment algorithm may be modified so that if the last value indicated a change (i.e., a proper read), it would decrease the read time (e.g., reach a point where the probability of 0 and 1 is about 50%), and increase the read time if there was no change in bus value. In other words, if a change was always read, the write position would normally be increased, in which case, if the read position were adjusted instead, the read delay would be decreased (i.e., the opposite adjustment).

[0095] In Case 5 of Table 3, the read time of the master device is adjusted based on the value provided by Slave 1. Since the internal delay of the exact read event is adjusted internally in the master device, there is no need to reflect the read value back onto the bus, because the master device already has the information it needs for read delay adjustment. In this respect, this read timing adjustment requires only half the bandwidth compared to the write timing adjustment. Therefore, in the previous description, we used two rows per adjustment step (slot It is possible to perform this read coordination on a single line (the slave device writes to the bus and the next line, the master device, writes back the written value).

[0096] In some embodiments, Cases 5 and 6 in Table 3 may be combined into a single read adjustment in which all devices simultaneously adjust their read delay timing. This is possible because attached devices reading from Slave 1 can adjust their read timing based on their own previous read values. Thus, multiple devices can simultaneously adjust their timing without increasing the time to complete the procedure. The only practical limitation is that the slowest device on the bus will determine the total adjustment time. In Case 6, the read timing of slave device Slave 2 is adjusted while the bus is being modified by Slave 1. Slave 2 reads a value from the bus and uses this value to adjust its read timing (i.e., trying to achieve 0s and 1s near 50%), so there is no need for Slave 2 to write back the value read from the bus. Figure 22 illustrates the difference between read timing calibration and write timing calibration. In the top row, each device can write and read within the same data row to calibrate its read timing, while in the bottom row, each device requires reflection to calibrate its write timing.

[0097] In Case 7, the master device adjusts its receive timing to perfectly align with its transmit timing. This may be used to compensate for delays internal to the master device and when the master device is used as part of a group write, with all members of the group aligning their internal timing to the output from the master device. In this way, the master device does not require a clock recovery circuit to obtain perfect receive timing. In various embodiments, Case 7 may be performed at bus startup, even before slave devices are attached to the bus, to save / reduce the time required to complete a full system timing calibration. The master device may use the initial 0-1 sync pulse to adjust its internal sampling point for reading from the bus. By adjusting the read timing and keeping the write time constant, it is possible to align the external 0-1 event with the master's read point. This may eliminate small timing differences, resulting in faster bus operating speeds.

[0098] 24B is a block diagram illustrating a bus device (e.g., master device 102) connected to bus 120 and including read timing adjustment module or logic 2406D, where an intrinsic write delay ΔT1 is associated with a transmitter / output port 108 within the bus device and an intrinsic read delay ΔT2 is associated with a receiver / input port 110 within the bus device, similar to the intrinsic delays described for Case 4 in FIG. 24A. In FIG. 24B, master device 102 may be configured to adjust the read delay of master device 102 using read timing adjustment module 2406A to compensate for the intrinsic write delay ΔT2 and properly align master write event 2406B and master read event 2406C with respect to bus communication timing, as described for Case 7. In various embodiments, one or more of the read timing adjustment module 2406D, master write event 2406B, and / or master read event 2406C may be implemented by and / or within the bus control unit 106, as shown in Figure 1. Similar timing adjustment modules may be implemented within any of the slave devices described herein.

[0099] In Case 8, the slave device adjusts its own receive timing to be aligned with the master device sync pulse. This is typically not necessary or related to system timing because sync and data are already aligned in this direction. This is because they are aligned (sync and data are delayed equally).

[0100] [Table 3]

[0101] A typical system timing adjustment may proceed as follows: For the general case of a single slave 1 writing to multiple devices (2-N), first, the write timing of slave 1 is optimized to align with the master device timing to conserve bandwidth (Case 3), and second, the read timing of devices 2-N (Cases 5-6) is optimized. For simple configurations, Cases 1-2 will cover all scenarios and give perfect alignment. With long cable delays, it may be necessary to write in a later time slot to avoid collisions between output and return signals. Alternatively, when communicating with multiple devices simultaneously, longer time slots may be used. If the reflected value is internal, there is no need to insert an extra line in the command sequence. This will make the adaptation process faster.

[0102] In additional embodiments, general system timing adjustment may include executing Cases 1, 6, and 7 according to various different orders of operation. For example, in one embodiment, system 100 may execute Case 7, in which the master device will adjust its receive or read timing to perfectly align with its transmit timing. In some embodiments, this may be performed substantially simultaneously with or before system 100 executes Case 1, in which a slave device changes a bus value, the master device reads that value, and then reflects that value so that the slave device can adjust its bus write or transmit timing as described herein. In various embodiments, system 100 then executes Case 6 and / or Case 8 to adjust all other slave device read timing. In some further embodiments, system 100 may implement the Case 2 and / or Case 3 embodiments to adjust all slave device write and read timing (e.g., transmit and receive timing) without requiring any master device read / write timing adjustments, or to minimize master device read / write timing adjustments (e.g., to minimize the time required for dynamic recalibration of system 100 when a new slave device attempts to join bus communications after the master device and multiple slave devices have already settled to their respective read / write timings).

[0103] More generally, any one or more of cases 1-8 may be performed in any order or combination by an embodiment of system 100 to provide dynamic write and read calibration for bus communications between bus-connected devices supported by and / or via bus 120 of system 100, as described herein. In various embodiments, such timing adjustments may include identifying and selecting appropriate time slots (e.g., as shown in FIG. 4 ) to facilitate timing calibration within the achievable range of each device (e.g., master or slave) communicatively coupled via bus 120. Furthermore, such timing adjustments may be performed using any of the processes and / or algorithms identified herein, which may be modified to adjust read timing and / or write timing, as described herein.

[0104] In some embodiments, it may be desirable for the bus clock rate to be adjustable. As long as the bandwidth of the circuits used for transmission and reception, and therefore the internal delay, remains the same, no new timing calibration is required. The general principle is to adjust on one clock edge during calibration to ensure a perfect receive eye pattern, and read on the next clock edge for normal operation. If the internal delay changes slightly during a change in synchronization / clock rate, calibration accuracy will be reduced; in some cases, recalibration may be necessary if the change in internal delay is too large. Otherwise, the same calibration value may be used. For example, FIG. 23 shows exemplary calibration timing for a bus system including a master device and two slave devices connected to a common bus implementing two different clock or synchronization rates, along with delays within the devices and on the bus itself, in accordance with one or more embodiments of the present disclosure.

[0105] The bus can be started in native pulse density modulation (PDM) mode, ensuring backward compatibility with PDM. Some embodiments can include a differential voltage detection algorithm configured to detect differential data and change from single-ended standard PDM mode (with no direct programming allowed except for changing the clock frequency) to differential mode. Similarly, the interface can start in differential mode, and when a single-ended standard PDM signal is detected, the interface changes to single-ended mode. Such a change can also occur with the use of specific time constants to change between these two operating modes when the signal is held at a specific level for a specific amount of time, or by duty cycle modulation of the clock or data lines.

[0106] In certain embodiments, a system may include a third single-ended mode with programming, such as that available in a controlled PDM (PDM+) system. Changing between the three modes (backward compatible PDM, programmable PDM, and differential) may occur through programming of the clock and data lines. In various embodiments, the differential mode of operation may be used for low EMI, and the backward compatible PDM mode may be used as a backup mode for general-purpose systems and / or bus-connected devices. may be used to ensure that

[0107] In some embodiments, system 100 may be configured to use a special synchronization word to perform timing calibration. When such a special synchronization word is used, special care must be taken to ensure that the transmitted command does not interfere with the selected synchronization word. Thus, during execution of a calibration command, the following responses are available: (1) a test value—an unknown value that is not controllable; (2) a reflected value—an unknown value that is controllable (reflecting what was read); and (3) a controllable, optional known value—this value may be inserted into the sequence of reads to avoid generating the special synchronization value.

[0108] In general, care should be taken to ensure that a sync word is not generated when known value (2) and controllable value (3) are used together. Because value (3) is controlled, it can always be guaranteed that a sync word will not be generated as long as the sync word length is at least two bits longer. In the case of a special read by the device from itself, or in the case of read delay adjustment, value (2) is not normally sent, and this should be taken into account when controlling value (3).

[0109] Where applicable, the various embodiments provided by the present disclosure may be implemented using hardware, software, or a combination of hardware and software. Also, where applicable, various hardware and / or logical components described herein may be combined into composite components comprising software, hardware, and / or both without departing from the scope of the present disclosure. Where applicable, various hardware and / or logical components described herein may be separated into subcomponents comprising software, hardware, or both without departing from the scope of the present disclosure. Additionally, where applicable, it is contemplated that software components may be implemented as hardware components, and vice versa.

[0110] The foregoing disclosure is not intended to limit the disclosure to the precise form or particular field of use disclosed. Accordingly, various alternative embodiments and / or modifications to the disclosure, whether expressly described or implied herein, are contemplated as possible in light of the present disclosure. While embodiments of the present disclosure have been described in this manner, those skilled in the art will recognize that changes can be made in form and detail without departing from the scope of the present disclosure. Accordingly, the present disclosure is limited only by the scope of the claims.

Claims

1. controlling a bus to facilitate communication between a plurality of devices, said communication being synchronized based at least in part on a time-multiplexed clock and data protocol; and a first device writing a first read timing value to the bus; the first device reading a second read timing value associated with the first read timing value written to the bus, wherein the writing and the reading occur within the same data row of the bus; and determining a read timing associated with the first device based at least in part on the first read timing value and the second read timing value, the read timing associated with the first device configured to control a read delay of the first device to calibrate communication on the bus from the first device to the first device.

2. The method further comprises: a second device writing a first write timing value to the bus; the first device reading a second write timing value associated with the first write timing value written to the bus, wherein the writing of the first write timing value and the reading of the second write timing value occur within the same data row of the bus, the method further comprising:

2. The method of claim 1, further comprising: the first device writing a response to the second device based at least in part on the second write timing value, the response configured to control a write delay of the second device to calibrate communications on the bus from the second device to the first device.

3. The method further comprises: the second device writing a third read timing value to the bus; and a third device reading a fourth read timing value associated with the third read timing value written to the bus, wherein the writing of the third read timing value and the reading of the fourth read timing value occur within the same data row of the bus, the method further comprising:

3. The method of claim 2, further comprising determining a read timing associated with the third device based at least in part on the third read timing value and the fourth read timing value, the read timing associated with the third device configured to control a read delay of the third device to calibrate communications on the bus from the second device to the third device.

4. The method further comprises: the second device writing a third read timing value to the bus; the first device reading a fourth read timing value associated with the third read timing value written to the bus, wherein the writing of the third read timing value and the reading of the fourth read timing value occur within the same data row of the bus, the method further comprising:

3. The method of claim 2, further comprising determining a read timing associated with the first device based at least in part on the third read timing value and the fourth read timing value, the read timing associated with the first device configured to control a read delay of the first device to calibrate communications on the bus from the second device to the first device.

5. The method further comprises: the first device or the second device writing a third write timing value to the bus; and the second device reading a fourth write timing value associated with the third write timing value written to the bus, wherein the writing and the reading occur within the same data row of the bus, the method further comprising:

3. The method of claim 2, further comprising determining a write timing associated with the second device based at least in part on the third write timing value and the fourth write timing value, the write timing associated with the second device configured to control a write delay of the second device to calibrate communications on the bus from the first device to other devices coupled to the bus.

6. The method further comprises: providing a first settling mode using a first delay step during initial correction to obtain a correct write delay position estimate; providing a second settling mode to obtain a more accurate write delay position for final adjustment of the write delay, the second settling mode using a second delay step smaller than the first delay step and settling slower than the first settling mode, the method further comprising: switching between the first settling mode and the second settling mode based at least in part on a plurality of read and write timing values; switching to the first settling mode if there is no change in the second write timing value over a preselected number of reads; and switching to the second settling mode if there are one or more changes in second write timing values ​​over the preselected number of reads.

7. The method further comprises: providing multiple adaptation speeds in the adaptation mode; determining whether the read second write timing value is equal to a previous second write timing value, and selectively increasing the adaptation speed up to a specified upper limit; 3. The method of claim 2, further comprising: determining whether the read second write timing value differs from the previous second write timing value; and selectively reducing the adaptation rate to a specified lower limit.

8. The method further comprises: the first device writing a first write timing value to the bus; and the first device reading a second write timing value associated with the first write timing value written to the bus, wherein the writing and the reading occur within the same data row of the bus, the method further comprising:

2. The method of claim 1, further comprising determining a write timing associated with the first device based at least in part on the first write timing value and the second write timing value, the write timing associated with the first device being configured to control a write delay of the first device to calibrate communications on the bus from the first device to the first device.

9. The method further comprises: adjusting the average of the second read timing values ​​read from the bus to have a probability between 0 and 1; and adjusting the read delay of the first device to avoid reading back the same value.

10. 1. A system comprising: a first device communicatively coupled to a bus configured to support synchronized communication among a plurality of devices based at least in part on a time-multiplexed clock and data protocol, the first device comprising: configured to write a first read timing value to the bus; and configured to read a second read timing value associated with the first read timing value, wherein the writing and the reading occur within the same data row of the bus, the first device further comprising: a system configured to determine a read timing associated with the first device based at least in part on the first read timing value and the second read timing value, the read timing associated with the first device configured to control a read delay of the first device to calibrate communications on the bus from the first device to the first device.

11. The system further comprises: a second device communicatively coupled to the bus, the second device comprising: configured to write a first write timing value to the bus; configured to read a response generated by the first device based at least in part on a second write timing value associated with the first write timing value written to the bus; 11. The system of claim 10, further configured to control a write delay of the second device based at least in part on the response generated by the first device to calibrate communications on the bus from the second device to the first device.

12. further comprising a third device communicatively coupled to the bus; The second device is configured to write a third read timing value to the bus, and the third device is configured to: and configured to read a fourth read timing value associated with the third read timing value written to the bus, wherein the writing of the third read timing value and the reading of the fourth read timing value occur within the same data row of the bus, the third device further comprising:

12. The system of claim 11, configured to determine a read timing associated with the third device based at least in part on the third read timing value and the fourth read timing value, the read timing associated with the third device configured to control a read delay of the third device to calibrate communications on the bus from the second device to the third device.

13. The second device is configured to write a third read timing value to the bus, and the first device is configured to: and configured to read a fourth read timing value associated with the third read timing value written to the bus, wherein the writing of the third read timing value and the reading of the fourth read timing value occur within the same data row of the bus, and the first device further comprising:

12. The system of claim 11, configured to determine a read timing associated with the first device based at least in part on the third read timing value and the fourth read timing value, the read timing associated with the first device configured to control a read delay of the first device to calibrate communications on the bus from the second device to the first device.

14. The second device configured to write a third write timing value to the bus; and reading a fourth write timing value associated with the third write timing value written to the bus, the writing and the reading occurring within the same data row of the bus, the second device further comprising:

12. The system of claim 11, configured to determine a write timing associated with the second device based at least in part on the third write timing value and the fourth write timing value, the write timing associated with the second device configured to control a write delay of the second device to calibrate communications on the bus from the first device to other devices coupled to the bus.

15. The first device configured to estimate the read delay of the first device; The system of claim 10 , configured to adjust the read delay of the first device to cause a variation in the second read timing value read by the first device.

16. 1. A system comprising: a first device communicatively coupled to a bus configured to support synchronized communication among a plurality of devices based at least in part on a time-multiplexed clock and data protocol; a second device communicatively coupled to the bus, the second device comprising: configured to write a first write timing value to the bus; configured to read a response generated by the first device based at least in part on a second write timing value associated with the first write timing value written to the bus; 11. A system configured to control a write delay of the second device based at least in part on the response generated by the first device to calibrate communications on the bus from the second device to the first device.

17. The first device configured to write a first read timing value to the bus; and configured to read a second read timing value associated with the first read timing value, wherein the writing and the reading occur within the same data row of the bus, the first device further comprising: configured to determine a read timing associated with the first device based at least in part on the first read timing value and the second read timing value; configured to write a third write timing value to the bus; and configured to read a fourth write timing value associated with the third read timing value, wherein writing the third write value and reading the fourth write value occur within the same data row of the bus, and the first device further:

17. The system of claim 16, further comprising: determining a write timing associated with the first device based at least in part on the first read timing value and the second read timing value; and configuring the read timing and write timing associated with the first device to control a read delay and a write delay of the first device to calibrate communications on the bus from the first device to the first device.

18. further comprising a third device communicatively coupled to the bus; The second device is configured to write a first read timing value to the bus, and the third device is configured to: and configured to read a second read timing value associated with the first read timing value written to the bus, wherein the writing of the first read timing value and the reading of the second read timing value occur within the same data row of the bus, the third device further comprising:

17. The system of claim 16, configured to determine a read timing associated with the third device based at least in part on the first read timing value and the second read timing value, the read timing associated with the third device configured to control a read delay of the third device to calibrate communications on the bus from the second device to the third device.

19. The second device is configured to write a first read timing value to the bus, and the first device is configured to: and configured to read a third read timing value associated with the first read timing value written to the bus, wherein the writing of the first read timing value and the reading of the second read timing value occur within the same data row of the bus, and the first device further comprises:

17. The system of claim 16, configured to determine a read timing associated with the first device based at least in part on the first read timing value and the second read timing value, the read timing associated with the first device configured to control a read delay of the first device to calibrate communications on the bus from the second device to the first device.

20. The second device configured to write a third write timing value to the bus; and reading a fourth write timing value associated with the third write timing value written to the bus, the writing and the reading occurring within the same data row of the bus, the second device further comprising:

17. The system of claim 16, further configured to determine a write timing associated with the second device based at least in part on the third write timing value and the fourth write timing value, the write timing associated with the second device configured to control a write delay of the second device to calibrate communications on the bus from the first device to other devices coupled to the bus.

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