Digital transceiver for data transmission driven by a synchronous spread spectrum clock signal - Patents.com

Abstract

A digital transceiver is provided. The digital transceiver includes a clock generator configured to generate a first clock signal having a fixed first frequency, and a transmitter driven by the first clock signal at the first frequency to transmit data. The digital transceiver further includes an inverter coupled to the clock generator to generate an inverted first clock signal at the first frequency. The digital transceiver further includes a frequency detector configured to compare the first frequency with a second frequency of a feedback signal in a feedback loop to determine a frequency control word F. The digital transceiver further includes a digitally controlled oscillator driven by the frequency control word F in the feedback loop to output a second clock signal having a time-averaged frequency substantially synchronous with the first frequency having a boundary spread, and a receiver driven by the second clock signal to receive data.

Description

[Technical Field]

[0001] The present invention provides Data transmission The present invention relates to a technology, and more particularly to a system driven by a synchronous spread spectrum clock signal. Data transmission This relates to a digital transceiver for use. [Background technology]

[0002] The problem of electromagnetic interference (EMI) has become increasingly serious with the development of many kinds of high-frequency electronic products and digital devices. One of the important anti-EMI techniques in use is based on spread-spectrum clock signal generators. However, high-speed Data transmission For applications, conventional spread spectrum implementation requires rigorous circuit design that faces many issues such as clock domain signal crossing, data alignment, and setup / hold check issues. Data transmission When applied to drive a Data transmission This leads to a significant increase in the number of devices that can be used. Therefore, on the one hand, typical high-data-rate transceivers based on RAM and FIFO transmission methods cannot be driven by spread-spectrum clock signals. On the other hand, these transceivers are designed to operate at extremely high frequencies (>100 MHz), which generates strong EMI. Using external shielding is one way to reduce EMI in these electronic products, but it increases the product's weight and cost, making it undesirable. Therefore, an improved digital transceiver is needed. Summary of the Invention [Means for solving the problem]

[0003] In one aspect, the present disclosure provides a digital transceiver. The digital transceiver includes a clock generator configured to generate a first clock signal having a fixed value of a first frequency. The digital transceiver further includes a transmitter driven by the first clock signal of the first frequency to transmit data. Further, the digital transceiver includes an inverter coupled to the clock generator to generate an inverted first clock signal of the first frequency. The digital transceiver also includes a frequency detector configured to compare the inverted first clock signal of the first frequency with a feedback signal of a second frequency that varies within a feedback loop to determine a frequency control word F including an integer part I + a fractional part r (0 < r < 1). Further, the digital transceiver includes a digital control oscillator driven by the frequency control word F in the feedback loop to output a second clock signal having a time-averaged frequency substantially synchronized with the first frequency having boundary diffusion. Further, the digital transceiver includes a receiver driven by the second clock signal to receive data.

[0004] Optionally, the frequency detector includes a fractional controller configured to generate a first control signal within a first time frame to decrease the integer part I of the frequency control word F and generate a second control signal within a second time frame to increase the integer part I of the frequency control word F. The first time frame and the second time frame are successively and temporally alternated in the feedback loop.

[0005] Optionally, the fractional controller includes a first input port receiving an inverted first clock signal, a second input port receiving a feedback signal, a trigger subcircuit, and a combinational logic subcircuit. The trigger subcircuit includes four D-type flip-flops coupled to the first input port via a 1 / 2 frequency divider and coupled to the second input port partially via an inverter, and configured to determine whether the first frequency is greater than or less than the second frequency. The combinational logic subcircuit includes two XOR gates, two inverters, and two AND gates coupled to the trigger subcircuit, and outputs a first control signal to the first control port in a first time frame if the first frequency is determined to be greater than the second frequency, and outputs a second control signal to the second control port in a second time frame if the first frequency is determined to be less than the second frequency.

[0006] Optionally, the first control signal is to control the integer portion I to decrease by 1 in each loop of the feedback within a first time frame, and the second control signal is to control the integer portion I to increase by 1 in each loop of the feedback within a second time frame.

[0007] Optionally, the digitally controlled oscillator includes a fundamental time unit Δ based on which the digitally controlled oscillator generates a first period T within the first time frame. A = I ΔN A pulses and a second period T in the second time frame B N with =(I+1) Δ B A combination with the pulse is generated.

[0008] Optionally, the digitally controlled oscillator has a time-averaged period T TAF =(1-r) T A +r·T B =(I+r) Δ=F Δ, where the fractional portion r is (N A +N B ) for N B is determined by the ratio of

[0009] Optionally, the direct periodic synthesizer includes a signal generator that generates K pulses having the same input frequency equal to the first frequency and an equally spaced phase shift Δ. The direct periodic synthesizer also includes a first K-1 multiplexer that is coupled via an accumulator to an accumulation register controlled by a frequency control word F, and that inputs the K pulses via a lower path to generate a low-level synthesized signal. The direct periodic synthesizer further includes a second K-1 multiplexer that is coupled via an adder to an adder register controlled by a half control word F / 2, and that inputs the K pulses via an upper path to generate a high-level synthesized signal.

[0010] Optionally, the direct period synthesizer further includes a 2-to-1 multiplexer that controls the transition between the upper and lower paths to generate a synthesized signal having an output frequency f2 that tracks the input frequency f1 of the K pulses, f2=1 / T TAF = K f1 / F and the time-averaged period T through the boundary diffusion determined by the frequency control word F TAF The output is the time-averaged frequency associated with

[0011] Optionally, the boundary diffusion is N A (T TAF -T A ) and the maximum phase shift of the output frequency f2 ahead of the input frequency f1 given by N B (T B -T TAF ) and the maximum phase shift of the output frequency f2 behind the input frequency f1.

[0012] Optionally, the signal generator is a clock generator based on a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), a voltage controlled temperature compensated crystal oscillator (VCTCXO) and an oven controlled crystal oscillator (OCXO).

[0013] Optionally, the direct period synthesizer further includes a toggle flip-flop coupled to the 2-1 multiplexer, which switches the transitions of the upper path and the lower path to selectively output the synthesized signal after the frequency control word F is switched between I and I+1 to reach dynamic equilibrium of the feedback loop.

[0014] Optionally, the composite signal is output as a second clock signal substantially synchronized with the first frequency of the first clock signal inverted within a boundary spread of the time-average frequency to drive a receiver.

[0015] Optionally, the receiver is configured to determine whether the data reception establishment time at the receiver is greater than a time average period T TAF minus the maximum phase shift of the second clock signal preceding the inverted first clock signal, and the time to maintain data reception at the receiver is less than half of the time-averaged period T TAF and configured to receive data transmitted from the transmitter with data integrity guaranteed by the condition that the inverted first clock signal is less than half of the inverted first clock signal minus the maximum phase shift of the second clock signal lagging the inverted first clock signal.

[0016] In one aspect, the present disclosure provides a digital transceiver, including the digital transceiver described herein, driven by a synchronous spread spectrum clock signal. Data transmission The transceiver chip is implemented in a digital integrated circuit as a system-on-chip (SOC).

[0017] In yet another aspect, the present disclosure provides a digital transceiver as described herein. TryA test system for testing a digital transceiver is provided. The test system includes a pseudorandom binary sequence (PRBS) generator driven by a first clock signal to generate random data stored in the digital transceiver. A transmitter of the digital transceiver is driven by the first clock signal to generate transmission data based on the random data stored in a first memory of the transmitter, and a receiver of the digital transceiver is driven by a second clock signal synchronized with the first clock signal having a frequency boundary spread to store received data and store the received data in a second memory of the receiver. A comparator is driven by the first clock signal to compare the received data with the transmitted data and generate error data. The error data is either 0, corresponding to a match between the received data and the random data originally generated by the PRBS, or 1, corresponding to a mismatch between the received data and the random data.

[0018] In yet another aspect, the present disclosure provides a data clock system driven by a synchronous spread spectrum clock signal. transmission A method is provided, the method including generating a first clock signal at a fixed first frequency. The method further includes driving a transmitter with the first clock signal to transmit data. The method further includes inverting the first clock signal to obtain an inverted first clock signal at the first frequency. The method further includes generating a plurality of pulses at the first frequency with equally spaced phase delays Δ. The method further includes obtaining a time-averaged period T from one of the plurality of pulses controlled by a frequency control word F. TAF and obtaining a synthesized signal having a time-average frequency based on (f), wherein the synthesized signal is used as a feedback signal in a feedback loop. The method further includes outputting a second clock signal based on the synthesized signal having the time-average frequency being locked to the first frequency and having a boundary spread determined by the fraction r when the frequency control word F is switched between integer I and integer I+1 in dynamic equilibrium within the feedback loop. The method further includes receiving data by driving a receiver with the second clock signal.

[0019] Optionally, inverting the first clock signal comprises providing an additional phase shift benefit for data reception.

[0020] Optionally, generating a plurality of pulses at a first frequency with equally spaced phase delays Δ includes using a clock generator based on a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), a voltage controlled temperature compensated crystal oscillator (VCTCXO) and an oven controlled crystal oscillator (OCXO).

[0021] Optionally, obtaining a composite signal having a time-average frequency includes inputting K pulses of a first frequency with equally spaced phase delays Δ using a first K-1 multiplexer coupled to an accumulation register controlled by a frequency control word F via an accumulator in the lower path, and generating a low-level composite signal; inputting K pulses of a first frequency with equally spaced phase delays Δ using a second K-1 multiplexer coupled to an adder register controlled by a half-frequency control word F / 2 via an adder in the upper path, and generating a high-level composite signal; and interlocking the lower path and the upper path using a 2-1 multiplexer to output either a low-level or a high-level composite signal.

[0022] Optionally, the step of driving the receiver with a second clock signal comprises: TAF minus the maximum phase shift of the second clock signal preceding the inverted first clock signal, and the time to maintain data reception at the receiver is less than half of the time-averaged period T TAF using a synthesized signal of a time-averaged frequency with a boundary spread under the condition that the time-averaged frequency is less than half of the maximum phase shift of the second clock signal lagging the inverted first clock signal minus the maximum phase shift of the second clock signal lagging the inverted first clock signal. [Brief explanation of the drawings]

[0023] The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] [Figure 1] 1 is a block diagram of a digital transceiver for data transmission with synchronous spread spectrum according to one embodiment of the present disclosure. [Figure 2] FIG. 1 is a schematic diagram illustrating generation of a synthesized clock signal based on a fundamental time unit and a frequency control word under time-averaged direct period synthesis, according to some embodiments of the present disclosure. [Figure 3] FIG. 1 is a functional diagram of a logic circuit for time-average frequency direct period synthesis, according to one embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic diagram illustrating K input pulses being loaded into the logic circuit of FIG. 3 at equally spaced phases of a basic time unit D, according to one embodiment of the present disclosure. [Figure 5] FIG. 1 is a functional diagram of a feedback loop based on time-average frequency locking, according to one embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic diagram of the logic circuitry of the frequency detector in the feedback loop of FIG. 5 according to one embodiment of the present disclosure. [Figure 7] FIG. 2 is a waveform diagram illustrating the phase relationships of multiple signals included in a digital transceiver according to one embodiment of the present disclosure. [Figure 8] FIG. 2 is a block diagram of a simplified test system for testing the digital transceiver of FIG. 1 in accordance with one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025] The present disclosure will now be more particularly described with reference to the following embodiments. It should be noted that the following description of some embodiments is presented herein for purposes of illustration and description only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0026] Data transmission Conventional spread spectrum clock signals applied to drive the data signal result in the phase relationship of the data signal becoming uncontrollable in the time domain, making it unsafe. Data transmission On the one hand, typical high-data-rate transceivers based on RAM and FIFO transmission schemes cannot be driven by spread-spectrum clock signals, and on the other hand, these transceivers are designed to operate at very high (>100 MHz) data signal frequencies, which generates strong electromagnetic interference (EMI).

[0027] Accordingly, the present disclosure provides, among other things, a novel digital transceiver and method for high data rate transmission driven by a synchronous clock signal with boundary spreading that substantially eliminates one or more problems due to limitations and drawbacks of the prior art. In one aspect, the present disclosure provides a digital transceiver according to some embodiments as set forth below.

[0028] Figure 1 shows a synchronous spread spectrum Data transmission1 is a block diagram of a digital transceiver for a mobile communication system. Referring to FIG. 1, the digital transceiver 1000 includes a transmitter 10 driven by a first clock signal having a first frequency f1 to transmit data, and a receiver 20 driven by a second clock signal having a second frequency f2 to receive data transmitted from the transmitter 10. In one embodiment, the first clock signal is generated by a clock generator 30. Optionally, the clock generator 30 may comprise a crystal oscillator (XO), a voltage-controlled crystal oscillator (VCXO), a temperature-compensated crystal oscillator (TCXO), a voltage-controlled temperature-compensated crystal oscillator (VCTCXO), and an oven-controlled crystal oscillator (OCXO). Optionally, the first frequency f1 of the first clock signal has a fixed value. Optionally, the first frequency f1 of the first clock signal is not a signal having spectrum spreading. In one embodiment, the second clock signal for driving the receiver 20 is configured to be a spread spectrum clock signal having a second frequency f2 substantially synchronized with the first frequency f1, and the falling / rising edges of the signal pulses are spread within a boundary range. As long as the boundary range of the second clock signal is appropriately set to meet the data establishment and maintenance times in the receiver 20, the receiver 20 driven by the second clock signal can correctly receive the transmitted data without losing data alignment.

[0029] Referring to FIG. 1, digital transceiver 1000 includes a time-average frequency locking loop for generating a synchronized clock signal with boundary spread. In one embodiment, inverter 40 is coupled to clock generator 30 to generate an inverted first clock signal, which is then fed to digitally controlled oscillator 50 in a feedback loop. Digitally controlled oscillator 50 is configured to generate a synthesized signal based on the principle of time-average frequency direct period synthesis. The synthesized signal is used as a feedback signal in the feedback loop and is eventually output as a second clock signal when the feedback loop reaches an equilibrium state.

[0030] 2 is a schematic diagram illustrating the generation of a synthesized clock signal based on a fundamental time unit and a frequency control word under time-averaged direct period synthesis according to some embodiments of the present disclosure. Referring to FIG. 2, a feedback frequency locking loop first uses a digital oscillator to generate a fundamental time unit Δ. Based on the fundamental time unit, different pulse periods T A and T B The digital control frequency control word F is represented by at least its integer part I, and the two pulse periods are divided by T. A = I Δ and T B = (I+1) Δ. The frequency control word F controls the digitally controlled oscillator 50 to set the two pulse periods T A and T B is used to synthesize an output signal having pulses with a time-averaged combination of . The synthesized signal has a time-averaged period T TAF =(1-r) T A +r·T B = (I + r) Δ. The time-averaged frequency is f TAF =1 / T TAF where r is a fraction between 0 and 1 that represents the probability of two different pulse periods occurring. The frequency control word F = I + r.

[0031] The digitally controlled oscillator 50 shown in Figure 1 above includes a frequency detector 100 that compares the first frequency of the input signal with the feedback frequency of the feedback signal in a feedback loop, and a time-average frequency direct period synthesizer 200 that generates a synthesized signal that is again used as the feedback signal, as shown in Figure 5. The feedback loop ultimately enables the feedback frequency of the feedback signal to track the first frequency of the input signal.

[0032] In a particular embodiment, frequency detector 100 is configured to compare an input signal at a first frequency f1 with a feedback signal at a second frequency f2 and alternately generate a first control signal fast and a second control signal slow to determine a frequency control word F in a feedback loop to enable second frequency f2 to track first frequency f1. FIG. 6 shows a schematic diagram of a logic circuit of a frequency detector in the feedback loop of FIG. 5 in accordance with one embodiment of the present disclosure. Referring to FIG. 6, frequency detector 100 includes a first input port that receives the input signal and a second input port that receives the feedback signal. Furthermore, frequency detector 100 includes a trigger subcircuit 1001 coupled to the first input port and the second input port and configured to detect a relationship between first frequency f1 and second frequency f2. Frequency detector 100 further includes a combining logic subcircuit 1002 coupled to trigger subcircuit 1001 and configured to generate a first control signal fast to the first control port within a first time frame and a second control signal slow to the second control port within a second time frame. The first time frame and the second time frame alternate one after the other.

[0033] In one embodiment, the trigger subcircuit 1001 includes four D-type flip-flops coupled to a first input port via a frequency divider and partially coupled to a second input port via an inverter. The trigger subcircuit 1001 is configured to determine whether a first frequency f1 is greater than or less than a second frequency f2. The combinational logic subcircuit 1002 includes two XOR gates, two inverters, and two AND gates and is configured to output a first control signal "fast" to a first control port within a first time frame based on a determination that the first frequency f1 is greater than the second frequency f2, or to output a second control signal "slow" to a second control port within a second time frame based on a determination that the first frequency f1 is less than the second frequency f2. In one embodiment, in a feedback loop, the first control signal "fast" drives the frequency control word F to decrease, and the second control signal "slow" drives the frequency control word F to increase. Finally, the first control signal "fast" and the second control signal "slow" are alternately generated, and the entire feedback loop reaches dynamic equilibrium when the frequency control word "F" is switched between two integers "I" and "I+1." In other words, the second frequency is substantially locked to the first frequency within the feedback loop. When the input frequency changes, i.e., when the locking target is changed, the frequency detector 100 operates to determine the frequency control word to achieve frequency locking in the feedback loop.

[0034] Returning to Figure 5, the frequency detector 100 operates in conjunction with the time-average frequency direct period synthesizer 200 to achieve frequency locking in a feedback loop. In one embodiment, Figure 3 shows a functional diagram of the logic circuitry of the time-average frequency direct period synthesizer 200, in accordance with one embodiment of the present disclosure. In one embodiment, in each loop, the frequency detector 100 detects the input frequency f in= f1 and provides a frequency control word F to the time-average frequency direct period synthesizer 200. Referring to Figure 3, K input pulses are generated by a simple voltage-controlled oscillator (VCO) based on a fundamental time unit Δ generated by a crystal oscillator (XO). Optionally, the K input pulses have the same frequency f in 4 shows a schematic diagram of K input pulses of the digitally controlled oscillator of FIG. 3 according to one embodiment of the present disclosure.

[0035] The K input pulses are input to two K-1 multiplexers, respectively. The first K-1 multiplexer (MUX_A) in the bottom half of the diagram is coupled via an accumulator to two pipeline registers controlled by control word F, allowing the K input pulses to pass down the path as the first output MUXOUT_A.

[0036] At transition time t6, the accumulator performs an accumulation calculation at each rising edge of the clock signal to process that the frequency control word F is a real number with a fractional part r and an integer part I. The K-1 multiplexers in the lower path control the length of the logic "0" of the output CLK1 at a low voltage level. At the first transition time t1, SEL_LOW is supplied to the first (or lower) K-1 multiplexer at the rising edge of CLK2, thus selecting one pulse out of the K pulses as the first output.

[0037] A second K-1 multiplexer (MUX_B) is coupled to a two-pipeline register controlled by half control word F / 2 via an adder, and receives K pulses via the upper path to generate a second high-level output MUXOUT_B. The adder has only the integer part I of the frequency control word F. The K-1 multiplexer in the upper path controls the length of the logic "1" on output CLK1 with a high voltage level.

[0038] 3, the 2-to-1 multiplexer MUX-C is controlled by CLK1 to control the transition of the upper path and the lower path, so that only one signal from either the upper path or the lower path reaches the toggle flip-flop circuit, which includes a D-type flip-flop and two inverters, to switch the output MUXOUT from "1" to "0" or from "0" to "1" on every rising edge of the clock.

[0039] At a second transition time t2, the selected signal passes through the first K-1 multiplexer MUX_A and is provided to the 2-1 multiplexer MUX-C.

[0040] At a third transition time t3, which occurs simultaneously with t2, when CLK2 is in a logic "1" state after the rising edge, CLK1 is in a logic "0" state, so the 2-to-1 multiplexer MUX-C selects the second output MUXOUT_B from the upper path as the MUXOUT sent to the toggle flip-flop.

[0041] At the fourth transition time t4, the rising edge of the second output MUXOUT_B reaches the toggle flip-flop, completing the 0 to 1 transition.

[0042] At the fifth transition time t5, CLK1 transitions to 1. Therefore, the 2-to-1 multiplexer MUX-C selects the first output of the sub-path, MUXOUT_A, to send to the toggle flip-flop. The whole process repeats in a feedback loop.

[0043] In this embodiment, the time-averaged frequency f TAF = K f inA synthesized signal having a frequency f / F is output from the digitally controlled oscillator 50 in each loop of feedback as the frequency control word F is varied. Eventually, the feedback loop reaches dynamic equilibrium when the frequency control word F determined by the frequency detector 100 is switched between integers I and I+1. This is because the second frequency f2 (see FIG. 5) in the feedback loop is synthesized by the time-averaged frequency direct periodic synthesizer 200 and output therefrom at a time-averaged frequency f TAF which represents substantially tracking the first or input frequency f1 over the extended phase range.

[0044]

number

[0045] N in the first time frame + N in the second time frame, A Cycle T A = I Δ and N B Cycle T B = (I+1) Δ can be expressed as the boundary spread in frequency of the composite signal from

[0046]

number

[0047] is N A (T TAF -T A ) represents the maximum phase shift of the second frequency f2 ahead of the input frequency f1, given by

[0048]

number

[0049] is N B (T B -T TAF ) represents the maximum phase shift of a second frequency f2 behind the input frequency f1.

[0050] FIG. 7 is a waveform diagram illustrating the phase relationships of multiple signals included in the digital transceiver 1000 according to one embodiment of the present disclosure. Referring to FIG. 7, in one example, the input signal is a square wave having a fixed first frequency f1, i.e., the first clock signal used to drive the transmitter 10 to transmit data. As can be seen in FIG. 7, the first clock signal has no boundary spread. In each cycle provided by the first clock signal, the transmission data is written to the memory of the transmitter 10 and transmitted. As shown in FIG. 1, the inverter 40 generates an inverted first clock signal having the same first frequency but an inverted phase. The inverted first clock signal is the input signal having the first frequency that is loaded into the digitally controlled oscillator 50. Optionally, the phase inversion performed by the inverter 40 on the first clock signal before loading the inverted first clock signal as an input signal into the digitally controlled oscillator 50 allows an additional cycle delay for operating the feedback time-average frequency locking loop. As shown in Figure 7, the input signal, denoted as TAF-FLL input f1, is inverted from the original transmitter clock f1, but has the same frequency f1, although they have opposite phases. The output signal (after the feedback loop reaches dynamic equilibrium) has a second frequency, denoted as receiver clock f2. f2 substantially tracks or is locked to f1, but has a spreading boundary L1 + L2. In other words, the output signal is provided as a second clock signal having a second frequency that is substantially synchronized with the first clock frequency with a spreading boundary.

[0051] In one embodiment, referring to FIG. 7, the period between the falling edge of the input signal in one cycle and the earliest rising edge of the output signal in the same cycle is equal to the minimum phase shift value

[0052]

number

[0053] In the same embodiment, the period between the falling edge of the input signal in one cycle and the latest rising edge of the output signal in the same cycle is given by the maximum phase shift value

[0054]

number

[0055] In order for the receiver 20 to correctly receive the data transmitted from the transmitter 10 without losing data alignment and security, the following conditions must be met: T SU <L3 min T H <T-L3 max where T SU represents the data establishment time required for the receiver, and T H represents the data maintenance time required for the receiver.

[0056] In another aspect, the present disclosure provides a data clock system driven by a synchronous spread spectrum clock signal. transmission The present invention provides a transceiver chip for a digital transceiver system, the digital transceiver chip including the digital transceiver 1000 described herein implemented in a digital integrated circuit as a system on a chip (SOC). Optionally, the digital transceiver 1000 is implemented in a field programmable gate array (FPGA) chip device. Optionally, the digital transceiver 1000 is implemented in an application specific integrated circuit (ASIC) chip device.

[0057] In yet another aspect, the present disclosure provides a test system for testing the digital transceiver described herein. FIG. 8 shows a block diagram of a simplified test system 2000 for testing the digital transceiver 1000 of FIG. 1 according to one embodiment of the present disclosure. Referring to FIG. 8, the test system 2000 includes a pseudo-random binary sequence (PRBS) generator 5 driven by a first clock signal to generate random data stored in a memory (RAM 11) of a transmitter 10 of the digital transceiver 1000. The transmitter 10, driven by the first clock signal having a first frequency f1, generates transmission data based on the random data generated by the PRBS 5. The receiver 20 of the digital transceiver 1000, driven by a second clock signal synchronized to the first clock signal and having a second frequency f2 with a frequency boundary spread, collects received data, and stores the collected data in a memory (RAM 21) of the receiver 20. The test system 2000 further includes a comparator 6, also driven by the first clock signal f1, that compares the received data with the transmitted data to generate error data. Optionally, the error data is 0, corresponding to a match between the received data and the random data initially generated by the PRBS 5. Optionally, the error data is 1, corresponding to a mismatch between the received data and the random data. Generally, since the digital transceiver 1000 includes a feedback time-average frequency locking loop that tracks the first or input frequency of the first clock signal with the second or output frequency of the second clock signal, during previous periods when the feedback loop is operating in frequency tracking without reaching dynamic equilibrium, error data 1 is output as part of the received data during those previous periods. Once dynamic equilibrium is reached and the digital transceiver 1000 is stabilized, a match between the input frequency of the first clock signal and the output frequency of the second clock signal can be established, resulting in error data of substantially 0, corresponding to perfect data alignment.

[0058] A synchronous spread spectrum clock signal drives the receiver of a digital transceiver system and (high speed) Data transmissionThe transmitter and receiver in the digital transceiver system are driven by different clock signals, and each module in the system has the capability to enable spread spectrum clock signal control, so that the transceiver system can flexibly use clock signals to drive data transmission and reception. The entire system circuit is simple, efficient, anti-EMI, and high-speed. Data transmission This application can be conveniently implemented in system-on-chip form.

[0059] In yet another aspect, the present disclosure provides a data clock system driven by a synchronous spread spectrum clock signal. transmission A method for a digital signal processing system is provided. The method includes generating a first clock signal at a fixed first frequency. The method also includes driving a transmitter with the first clock signal to transmit data. The method further includes inverting the first clock signal to obtain an inverted first clock signal at the first frequency. The method further includes generating a plurality of pulses at the first frequency with equally spaced phase delays Δ.

[0060] The method further comprises: obtaining a time-averaged period T from one of the plurality of pulses controlled by the frequency control word F; TAF The method includes obtaining a synthesized signal having a time-average frequency based on the fraction r. The synthesized signal is also used as a feedback signal in a feedback time-average frequency locking loop. The method further includes outputting a second clock signal based on the synthesized signal having the time-average frequency being locked to the first frequency and having a boundary spread determined by the fraction r when the frequency control word F is switched between integer I and integer I+1 in dynamic equilibrium within the feedback loop. The method further includes driving a receiver with the second clock signal to receive data.

[0061] In particular, generating a plurality of pulses at a first frequency with equally spaced phase delays Δ includes using a clock generator based on a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), a voltage controlled temperature compensated crystal oscillator (VCTCXO), and an oven controlled crystal oscillator (OCXO) based on an input signal, i.e., a first clock signal at a first frequency.

[0062] In one embodiment, inverting the first clock signal includes providing an additional phase shift benefit for data reception.

[0063] In one embodiment, obtaining a composite signal having a time-average frequency includes inputting K pulses of a first frequency with equal phase delays Δ using a first K-1 multiplexer coupled to an accumulation register controlled by a frequency control word F via an accumulator in a first path, and generating a low-level composite signal; inputting K pulses of a first frequency with equal phase delays Δ using a second K-1 multiplexer coupled to an adder register controlled by a half-frequency control word F / 2 via an adder in a second path, and generating a high-level composite signal; and interlocking the first and second paths using a 2-1 multiplexer to output either a low-level or a high-level composite signal.

[0064] Finally, the step of driving the receiver with the second clock signal causes the data reception establishment time at the receiver to be equal to the time-averaged period T TAF minus the maximum phase shift of the second clock signal preceding the inverted first clock signal, and the time to maintain data reception at the receiver is less than half of the time-averaged period T TAF using a synthesized signal of a time-averaged frequency with a boundary spread under the condition that the time-averaged frequency is less than half of the maximum phase shift of the second clock signal lagging the inverted first clock signal minus the maximum phase shift of the second clock signal lagging the inverted first clock signal.

[0065] The foregoing description of embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative and not restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described to explain the principles of the invention and practical application of its best mode, thereby enabling those skilled in the art to understand the invention in various embodiments with various modifications suited to the particular use or implementation contemplated. The scope of the present invention is intended to be defined by the claims appended hereto and their equivalents, and all terms are to be given their broadest reasonable meaning unless expressly stated otherwise. Thus, terms such as "invention," "the present invention," and the like do not necessarily limit the scope of the claims to any particular embodiment, and reference to exemplary embodiments of the present invention does not imply a limitation on the invention, and no such limitation should be inferred. The present invention is limited only by the spirit and scope of the appended claims. Furthermore, these claims may be referred to using "first," "second," etc. following a noun or element. Such terms should be understood as nomenclature and should not be construed as imposing a limit on the number of elements modified by such nomenclature, unless a specific number is given. Any benefits and advantages described may not apply to all embodiments of the present invention. It is understood that modifications can be made to the described embodiments by those skilled in the art without departing from the scope of the present invention, as defined by the following claims. Furthermore, elements and components of the present disclosure are not intended to be made available to the public, regardless of whether the element or component is explicitly recited in the following claims.

Claims

1. a clock generator configured to generate a first clock signal having a fixed first frequency; a transmitter clocked by the first clock signal at the first frequency to transmit data; an inverter coupled to the clock generator to generate an inverted first clock signal at the first frequency; a frequency detector configured to compare the inverted first clock signal of the first frequency with a feedback signal of a second frequency that varies in a feedback loop to determine a frequency control word F comprising an integer portion I plus a fractional portion r, where 0<r<1; a digitally controlled oscillator driven by said frequency control word F in said feedback loop to output a second clock signal having a time-average frequency synchronous to said first frequency having a boundary spread that is a frequency boundary spread; a receiver driven by the second clock signal to receive the data; the frequency detector includes a fractional controller configured to generate a first control signal in a first time frame to decrease the integer portion I of the frequency control word F and to generate a second control signal in a second time frame to increase the integer portion I of the frequency control word F, the first time frame and the second time frame being alternated in time one after the other in the feedback loop; a trigger subcircuit including four D-type flip-flops coupled to the first input port through a 1 / 2 frequency divider and coupled partially to the second input port through an inverter and configured to determine whether the first frequency is greater than or less than the second frequency; and a combinational logic subcircuit including two XOR gates, two inverters, and two AND gates coupled to the trigger subcircuit and configured to output the first control signal to a first control port in the first time frame if the first frequency is determined to be greater than the second frequency and to output the second control signal to a second control port in the second time frame if the first frequency is determined to be less than the second frequency.

2. 2. The digital transceiver of claim 1, wherein the first control signal is to control the integer portion I to decrease by 1 in each loop of feedback within the first time frame, and the second control signal is to control the integer portion I to increase by 1 in each loop of feedback within the second time frame.

3. The digitally controlled oscillator includes a fundamental time unit Δ based on which a first period T Ａ = I·ΔN Ａ pulses and a second period T Ｂ = (I + 1) · Δ Ｂ 3. The digital transceiver of claim 2, wherein a combination of pulses is generated.

4. The digitally controlled oscillator has a time-averaged period T ＴＡＦ = (1 - r) T Ａ +r T Ｂ = (I + r) · Δ = F · Δ, said fractional portion r being (N Ａ +N Ｂ ) for N Ｂ 4. The digital transceiver of claim 3, wherein the ratio of

5. 5. The digital transceiver of claim 4, wherein the direct periodic synthesizer includes: a signal generator for generating K pulses having the same input frequency equal to the first frequency and an equally spaced phase shift Δ; a first K-1 multiplexer coupled to an accumulation register controlled by the frequency control word F via an accumulator for inputting the K pulses via a lower path to generate the composite signal at a low level; and a second K-1 multiplexer coupled to an adder register controlled by a half control word F / 2 via an adder for inputting the K pulses via an upper path to generate the composite signal at a high level.

6. The direct period synthesizer further includes a 2-1 multiplexer that controls the transition between the upper path and the lower path to select the input frequency f １ Output frequency f ２ The composite signal having f ２ = 1 / T ＴＡＦ = K f １ / F and the boundary diffusion determined by the frequency control word F, the time-averaged period T ＴＡＦ 6. The digital transceiver of claim 5, wherein the digital transceiver outputs a time-averaged frequency related to

7. The boundary diffusion is N Ａ (T ＴＡＦ -T Ａ ) the input frequency f １ The output frequency f ２ and the maximum phase shift of N Ｂ (T Ｂ -T ＴＡＦ ) the input frequency f １ The output frequency f ２ 7. The digital transceiver of claim 6, further comprising a maximum phase shift of

8. 6. The digital transceiver of claim 5, wherein the signal generator is a clock generator based on a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), a voltage controlled temperature compensated crystal oscillator (VCTCXO), or an oven controlled crystal oscillator (OCXO).

9. 8. The digital transceiver of claim 7, wherein the direct period synthesizer further comprises a toggle flip-flop coupled to the 2-1 multiplexer that toggles the transitions of the upper path and the lower path to selectively output the synthesized signal after the frequency control word F is toggled between I and I+1 to reach dynamic equilibrium of the feedback loop.

10. 10. The digital transceiver of claim 9, wherein the composite signal is output as the second clock signal synchronized with the first frequency of the inverted first clock signal within the boundary spread of the time-average frequency to drive the receiver.

11. The receiver is configured to set a data reception establishment time for the receiver that is equal to or shorter than the time average period T ＴＡＦ minus the maximum phase shift of the second clock signal preceding the inverted first clock signal, and the time that data reception is maintained at the receiver is less than the time-averaged period T ＴＡＦ 11. The digital transceiver of claim 10, configured to receive the data transmitted from the transmitter with data integrity guaranteed by the condition that the phase shift of the second clock signal lags the inverted first clock signal by less than one-half of the phase shift of the second clock signal minus a maximum phase shift of the second clock signal lagging the inverted first clock signal.

12. A transceiver chip for data transmission driven by a synchronous spread spectrum clock signal, comprising a digital transceiver according to any one of claims 1 to 11 implemented in a digital integrated circuit as a system on chip (SOC).

13. A test system for testing a digital transceiver according to any one of claims 1 to 11, comprising: a pseudo-random binary sequence (PRBS) generator driven by a first clock signal to generate random data stored in the digital transceiver, a transmitter of the digital transceiver driven by the first clock signal to generate transmission data based on the random data stored in a first memory of the transmitter, a receiver of the digital transceiver driven by a second clock signal synchronized to the first clock signal having a frequency boundary spread to store received data and to store the received data in a second memory of the receiver; a comparator driven by the first clock signal to compare the received data with the transmitted data to generate error data, the error data being either 0 corresponding to a match between the received data and the random data originally generated by the PRBS, or 1 corresponding to a mismatch between the received data and the random data.

14. 1. A method of data transmission driven by a synchronous spread spectrum clock signal, comprising: generating a first clock signal at a fixed first frequency; driving a transmitter with the first clock signal to transmit data; inverting the first clock signal to obtain an inverted first clock signal at the first frequency; generating a plurality of pulses at said first frequency having equally spaced phase delays Δ; A time-averaged period T from one of the plurality of pulses controlled by a frequency control word F. ＴＡＦ obtaining a synthetic signal having a time-averaged frequency based on outputting a second clock signal based on the synthesized signal having the time-average frequency being locked to the first frequency and the frequency control word F having a boundary spread determined by a fraction r when the frequency control word F is switched between an integer I and an integer I+1 in dynamic equilibrium within the feedback loop; and driving a receiver with the second clock signal to receive the data; The boundary spreading is a frequency boundary spreading, The frequency control word F decreases the integer part I in a first control signal generated by the fractional controller and increases the integer part I in a second control signal generated by the fractional controller; the fractional controller includes a first input port receiving the inverted first clock signal, a second input port receiving the feedback signal, a trigger subcircuit including four D-type flip-flops coupled to the first input port through a 1 / 2 frequency divider and coupled partially to the second input port through an inverter and configured to determine whether the first frequency is greater than or less than the second frequency, and a combinational logic subcircuit including two XOR gates, two inverters, and two AND gates coupled to the trigger subcircuit and configured to output the first control signal to a first control port in a first time frame if the first frequency is determined to be greater than the second frequency and to output the second control signal to a second control port in a second time frame if the first frequency is determined to be less than the second frequency.

15. 15. The method of claim 14, wherein inverting the first clock signal comprises providing an additional phase shift benefit for data reception.

16. 15. The method of claim 14, wherein generating the plurality of pulses at the first frequency with equally spaced phase delay Δ comprises using a clock generator based on a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), a voltage controlled temperature compensated crystal oscillator (VCTCXO), or an oven controlled crystal oscillator (OCXO).

17. 17. The method of claim 16, wherein obtaining a composite signal having a time-average frequency comprises: inputting K pulses of the first frequency with equal phase delays Δ using a first K-1 multiplexer coupled in a first path via an accumulator to an accumulation register controlled by the frequency control word F; generating the composite signal at a low level; inputting the K pulses of the first frequency with equal phase delays Δ using a second K-1 multiplexer coupled in a second path via an adder to an adder register controlled by a half frequency control word F / 2; generating the composite signal at a high level; and interlocking the first path and the second path using a 2-1 multiplexer to output either the low level or the high level of the composite signal.

18. The step of driving the receiver with the second clock signal is performed such that the data reception establishment time at the receiver is equal to or shorter than the time average period T ＴＡＦ minus the maximum phase shift of the second clock signal preceding the inverted first clock signal, and the time that data reception is maintained at the receiver is less than the time-averaged period T ＴＡＦ 15. The method of claim 14, further comprising using the synthesized signal of the time-averaged frequency with the boundary spread under the condition that the time-averaged frequency is less than half of the maximum phase shift of the second clock signal lagging the inverted first clock signal minus a maximum phase shift of the second clock signal lagging the inverted first clock signal.

Images