Three-dimensional memory device and method of forming three-dimensional memory device

Abstract

Embodiments of a three-dimensional (3D) memory device and a method for forming the 3D memory device are disclosed. In the example, the 3D memory device includes a film stack having a plurality of pairs of conductive and dielectric layers stacked vertically on a substrate. Each pair of conductive and dielectric layers includes a dielectric layer and a conductive layer. The 3D memory device also includes a stepped region having a first stepped structure and a second stepped structure formed in the film stack, wherein both the first and second stepped structures extend laterally in a first direction and include a plurality of pairs of conductive and dielectric layers. The stepped region also includes stepped bridges connecting the first and second stepped structures.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to methods for forming three-dimensional (3D) memory devices. Prior Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0003] In 3D NAND memory, memory cells can be stacked vertically to increase storage capacity per unit area, where cells can be addressed from a common word line. To access the word lines of the vertically stacked cells, a stepped structure can be formed at one or both edges of the memory array. However, to further increase the storage capacity of 3D NAND memory, the number of cells and the size of the memory array have been significantly increased. This results in increased distance between the cells in the middle of the array and the electrical connections at the ends of the word lines, leading to greater parasitic resistance and slower read / write speeds. Therefore, there is a need to improve the stepped structure in 3D NAND memory to achieve higher storage density without sacrificing performance. Summary of the Invention

[0004] This disclosure describes embodiments of a three-dimensional (3D) memory device and a method for forming the same.

[0005] One aspect of this disclosure provides a three-dimensional (3D) memory device. In an example, the 3D memory device includes a film stack having pairs of conductive and dielectric layers vertically stacked on a substrate. Each pair of conductive and dielectric layers includes a dielectric layer and a conductive layer. The 3D memory device also includes a stepped region having a first stepped structure and a second stepped structure formed in the film stack, wherein both the first and second stepped structures extend laterally in a first direction and include pairs of conductive and dielectric layers. The stepped region also includes stepped bridges connecting the first and second stepped structures.

[0006] In some embodiments, the stepped bridge includes a plurality of pairs of conductive and dielectric layers. In some embodiments, the stepped bridge is configured to electrically connect the conductive layer in each pair of conductive and dielectric layers of the first stepped structure to the conductive layer in the corresponding pair of conductive and dielectric layers of the second stepped structure.

[0007] In some embodiments, the stepped bridge extends laterally in a first direction and has a width smaller than that of the first stepped structure and the second stepped structure.

[0008] In some embodiments, the stepped bridge extends laterally in a second direction perpendicular to the first direction, and has a first surface that is longer than a second surface opposite to the first surface.

[0009] In some embodiments, the 3D memory device further includes a plurality of storage strings that penetrate vertically through the film stack, each of the plurality of storage strings having a core filling film, a channel layer surrounding the core filling film, and a storage film surrounding the channel layer.

[0010] In some embodiments, a plurality of storage strings are distributed on opposite sides of the first step region.

[0011] In some embodiments, the first stepped structure and the second stepped structure are symmetrical to each other along a first direction.

[0012] In some embodiments, the 3D memory device further includes a plurality of contact structures electrically connected to the conductive layers of the first and second step structures. In some embodiments, a first subgroup of the plurality of contact structures is formed on the conductive layer of the first step structure, and a second subgroup of the plurality of contact structures is formed on the conductive layer of the second step structure, wherein the second subgroup of the plurality of contact structures is different from the first subgroup of the plurality of contact structures.

[0013] In some embodiments, the first stepped region is located at the center of the storage array of the 3D memory device. In some embodiments, the 3D memory device further includes one or more bottom select gate (BSG) cutouts that divide the storage array into two or more sub-blocks, each sub-block including a sub-BSG. In some embodiments, one or more BSG cutouts vertically penetrate one or more pairs of conductive and dielectric layers at the bottom portion of the film stack.

[0014] In some embodiments, the 3D memory device further includes a second stepped region having a third stepped structure and a fourth stepped structure formed in a film stack. The third stepped structure and the fourth stepped structure extend laterally in a first direction. The 3D memory device also includes a second stepped bridge connecting the third stepped structure and the fourth stepped structure. The stepped bridge and the second stepped bridge are located on opposite sides of the first stepped region and the second stepped region, respectively.

[0015] Another aspect of this disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing alternating stacked layers of dielectric material on a substrate, wherein the alternating stacked layers of dielectric material comprise a plurality of dielectric layer pairs. Each dielectric layer pair includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. The method further includes forming a first dielectric stair, a second dielectric stair, and a dielectric bridge in the alternating stacked layers of dielectric material, wherein the first dielectric stair and the second dielectric stair are connected by a dielectric bridge.

[0016] In some embodiments, the method further includes replacing the second dielectric layer in the alternating dielectric material stack with a conductive layer to form a film stack of alternating conductive and dielectric layers.

[0017] In some embodiments, the method further includes forming a plurality of contact structures on the conductive layer of the film stack.

[0018] In some embodiments, the method further includes: forming a first dielectric layer and a second dielectric layer on a substrate before forming alternating dielectric material stacks; and forming one or more bottom select gate (BSG) cutouts that extend vertically through the first dielectric layer and the second dielectric layer into the substrate.

[0019] In some embodiments, the method further includes forming a plurality of storage strings that vertically penetrate alternating layers of dielectric material, wherein each of the plurality of storage strings includes a core filling film, a channel layer surrounding the core filling film, and a storage film surrounding the channel layer.

[0020] In some embodiments, forming a plurality of storage strings includes forming a plurality of storage strings on opposite sides of a first dielectric step and a second dielectric step.

[0021] Other aspects of this disclosure can be understood by those skilled in the art based on the specification, the scope of the invention claims, and the drawings. Simple Explanation of the Diagram

[0022] The drawings incorporated herein and forming part of the specification illustrate embodiments of the present disclosure, and together with the specification, serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure. Figure 1 shows a schematic top view of an exemplary three-dimensional (3D) memory die according to some embodiments of the present disclosure. Figure 2 shows a schematic top view of a region of a 3D memory die according to some embodiments of the present disclosure. Figure 3 shows a perspective view of a portion of an exemplary 3D storage array structure according to some embodiments of the present disclosure. Figure 4 shows a perspective view of an exemplary 3D memory structure according to some embodiments of the present disclosure. Figures 5 and 6 show top views of 3D memory structures according to some embodiments of the present disclosure. Figures 7A, 7B, 8A, and 8B show perspective views of 3D memory structures according to some embodiments of the present disclosure. Figure 9 illustrates a flowchart of an exemplary method for forming a 3D memory structure according to some embodiments of the present disclosure. Figures 10A and 10B show cross-sectional views of a 3D memory structure at a certain process step according to some embodiments of the present disclosure. Figure 10C shows a top view of the 3D memory structure in Figures 10A and 10B according to some embodiments of the present disclosure. Figures 11A and 11B show cross-sectional views of a 3D memory structure at a certain process step according to some embodiments of the present disclosure. Figure 12A shows a cross-sectional view of a 3D memory structure at a certain process step according to some embodiments of the present disclosure. Figure 12B shows a top view of the 3D memory structure in Figure 12A according to some embodiments of the present disclosure. Figure 13A shows a cross-sectional view of a 3D memory structure at a certain process step according to some embodiments of the present disclosure. Figure 13B shows a top view of the 3D memory structure in Figure 13A according to some embodiments of the present disclosure. Figures 14A and 14B show cross-sectional views of a 3D memory structure at a certain process step according to some embodiments of the present disclosure. Figure 14C shows a top view of the 3D memory structure in Figures 14A and 14B according to some embodiments of the present disclosure. Figure 15A shows a cross-sectional view of a 3D memory structure at a certain process step according to some embodiments of the present disclosure. Figure 15B shows a top view of the 3D memory structure in Figure 15A according to some embodiments of the present disclosure. Figure 16 shows a cross-sectional view of a 3D memory structure at a certain process step according to some embodiments of the present disclosure. Figure 17A shows a cross-sectional view of a 3D memory structure at a certain process step according to some embodiments of the present disclosure. Figure 17B shows a top view of the 3D memory structure in Figure 17A according to some embodiments of the present disclosure. The features and advantages of the invention will become more apparent from the specific embodiments described below in conjunction with the accompanying drawings, in which similar reference numerals always identify corresponding elements. In the drawings, similar reference numerals generally indicate equivalent, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost (one or more) numerals of the corresponding reference numeral. Embodiments of this disclosure will be described with reference to the accompanying drawings. Implementation

[0023] While specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0024] Note that references to "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0025] Generally, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or plural" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one" or "described" can also be understood to convey either a singular or a plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily clearly described.

[0026] It should be readily understood that the meanings of “above,” “on top,” and “above” in this disclosure should be interpreted in the broadest sense, such that “above” not only means “directly on something,” but also includes “on something” with an intermediate feature or layer in between. Moreover, “on top” or “above” not only means “above” or “above” something, but also includes “above” or “above” something without an intermediate feature or layer in between (i.e., directly on something).

[0027] Furthermore, for ease of description, spatial relative terms such as "below," "below," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or feature and another (one or more) elements or features as shown in the figures. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or process steps. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein can be interpreted accordingly in a similar manner.

[0028] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. Unless otherwise noted, the top surface of the substrate is typically where semiconductor devices are formed, and thus the semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0029] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper structure, or may have a smaller extent than the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, or / and along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or have one or more layers on, above, or / and below it. Layers may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (in which contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0030] In this disclosure, for ease of description, the term "step" is used to refer to components that are substantially the same height in the vertical direction. For example, a word line and the underlying gate dielectric layer can be referred to as a "step", a word line and the underlying insulating layer can be referred to together as a "step", word lines of substantially the same height can be referred to as a "step of word lines" or similar.

[0031] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, and the range of values ​​higher than and / or lower than the expected value. The range of values ​​may be attributable to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a given quantity value that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a given quantity value that varies, for example, within 10%–30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0032] In this disclosure, the terms "horizontal / horizontally / transverse / laterally" mean nominally parallel to the transverse surface of the substrate, and the terms "vertical" or "perpendicularly" mean nominally perpendicular to the transverse surface of the substrate.

[0033] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of storage cell transistors (referred to herein as "storage strings," such as NAND strings) on a laterally oriented substrate, such that the storage strings extend in a vertical direction relative to the substrate.

[0034] Figure 1 illustrates a top view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100 may be any part of a memory chip (package), a memory die, or a memory die, and may include one or more storage planes 101, each of which may include a plurality of storage blocks 103. Equivalent and parallel operations may be performed at each storage plane 101. A storage block 103 of a size of megabytes (MB) is the minimum size for performing an erase operation. As shown in Figure 1, the exemplary 3D memory device 100 includes four storage planes 101, and each storage plane 101 includes six storage blocks 103. Each storage block 103 may include a plurality of storage cells, wherein each storage cell may be addressed by interconnections such as bit lines and word lines. Bit lines and word lines may be arranged vertically (e.g., in columns and rows, respectively), thereby forming an array of metal lines. In Figure 1, the orientations of the bit lines and word lines are labeled "BL" and "WL". In this disclosure, storage block 103 is also referred to as a "storage array" or "array". A storage array is the core area in a memory device that performs storage functions.

[0035] The 3D memory device 100 also includes a peripheral region 105, which is the area surrounding the storage plane 101. The peripheral region 105 contains numerous digital, analog, and / or mixed-signal circuits for supporting the functions of the storage array, such as page buffers, row and column decoders, and sense amplifiers. As will be apparent to those skilled in the art, the peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc.

[0036] It should be noted that the arrangement of the storage planes 101 in the 3D memory device 100 shown in Figure 1 and the arrangement of the storage blocks 103 in each storage plane 101 are for illustrative purposes only and do not limit the scope of this disclosure.

[0037] Referring to Figure 2, an enlarged top view of region 108 in Figure 1 according to some embodiments of the present disclosure is shown. Region 108 of the 3D memory device 100 may include a stepped region 210 and a channel structure region 211. The channel structure region 211 may include an array of storage strings 212, each comprising a plurality of stacked storage cells. The stepped region 210 may include a stepped structure (see Figure 3) and an array of contact structures 214 formed on the stepped structure. In some embodiments, a plurality of slot structures 216 extending in the WL direction across the channel structure region 211 and the stepped region 210 may divide the storage block into a plurality of storage fingers 218. At least some of the slot structures 216 may serve as common source contacts for the array of storage strings 212 in the channel structure region 211. Top Select Gate (TSG) cutouts 220 may be positioned, for example, in the middle of each storage finger 218, to divide the TSG of the storage finger 218 into two parts, thereby dividing the storage finger into two storage slabs 224, wherein storage cells sharing the same word line in the storage slabs 224 form programmable (read / write) storage pages. Although erase operations on 3D NAND memory can be performed at the block level, read and write operations can be performed at the page level. The size of a storage page can be kilobits (KB). In some embodiments, region 108 also includes dummy storage strings 222 for controlling process variations during manufacturing and / or for additional mechanical support.

[0038] Figure 3 shows a perspective view of a portion of an exemplary three-dimensional (3D) storage array structure 300 according to some embodiments of the present disclosure. The storage array structure 300 includes a substrate 330, an insulating film 331 over the substrate 330, steps of a lower select gate (LSG) 332 over the insulating film 331, and steps of a plurality of control gates (also referred to as "word lines (WLs)," such as word lines 333), the steps of which are stacked on top of the LSG 332 to form a film stack layer 335 of alternating conductive and dielectric layers. For clarity, the dielectric layer adjacent to the steps of the control gates is not shown in Figure 3.

[0039] Each step's control gate is separated by slot structures 216-1 and 216-2 passing through the film stack 335. The storage array structure 300 also includes a step of top select gate (TSG) 334 above the stack of control gates (e.g., word lines 333). The stack of TSG 334, control gates (e.g., word lines 333), and LSG 332 is also referred to as a "gate electrode". The storage array structure 300 also includes storage strings 212 and doped source line regions 344 in portions of the substrate 330 between adjacent LSGs 332. Each storage string 212 includes a channel hole 336 extending through the film stack 335 of insulating film 331 and alternating conductive and dielectric layers. The storage string 212 also includes a storage film 337 on the sidewall of the channel hole 336, a channel layer 338 above the storage film 337, and a core fill film 339 surrounded by the channel layer 338. Storage cells 340 may be formed at the intersection of a control gate (e.g., word line 333) and a storage string 212. The portion of the channel layer 338 below the control gate (e.g., word line 333) is also referred to as a channel for the storage cells 340. The storage array structure 300 also includes a plurality of bit lines (BLs) 341 connected to the storage string 212 above the TSG 334. The storage array structure 300 also includes a plurality of metal interconnects 343 connected to gate electrodes via a plurality of contact structures 214. The edges of the film stack layer 335 are configured in a stepped shape to allow electrical connections to each step of the gate electrode.

[0040] In Figure 3, for illustrative purposes, steps of three control gates (e.g., word lines 333-1, 333-2, and 333-3) are shown alongside a step of a TSG 334 and a step of an LSG 332. In this example, each storage string 212 may include three storage cells 340-1, 340-2, and 340-3, respectively, corresponding to the control gates (e.g., word lines 333-1, 333-2, and 333-3). In some embodiments, the number of control gates and storage cells may be more than three to increase storage capacity. The storage array structure 300 may also include other structures, such as TSG cutouts, common source contacts, and dummy storage strings. These structures are not shown in Figure 3 for clarity.

[0041] To achieve higher storage capacity in 3D memory, the number of storage cells 340 and the size of the storage block 103 (in Figure 1) or channel structure region 211 (in Figure 3) have been significantly increased. As a result, the distance from the storage cell 340 in the middle of the storage block 103 or channel structure region 211 to the contact structure 214 at the end of the word line 333 has also increased, leading to greater parasitic resistance and slower read / write speeds. To address this issue, a stepped structure can be formed in the middle of the storage block 103 (or channel structure region 211), where a set of contact structures 214 and metal interconnects 343 can be formed for each set of stepped structures. However, to form an electrical connection between the word line 333 located in the middle of the storage block 103 and the word line driver circuitry located in the peripheral region 105, the layout of the metal interconnects 343 is complex and can cause wiring congestion and increase manufacturing costs.

[0042] This disclosure provides a stepped structure for 3D NAND memory, which can be placed at the center of a storage array with reduced wiring congestion and better area efficiency. Therefore, the number of metal interconnects and manufacturing costs can be reduced.

[0043] Figure 4 shows a perspective view of a 3D memory structure 400 according to some embodiments of the present disclosure. The 3D memory structure 400 includes a stepped region similar to the stepped region 210 discussed above with reference to Figures 2 and 3. Figure 5 shows a top view of a 3D storage array 500 according to some embodiments of the present disclosure. The stepped region 210 of the 3D memory structure 400 may be arranged in the middle of the 3D storage array 500. The 3D storage array 500 may be any part of the storage block 103 in Figure 1.

[0044] Referring to Figure 4, the 3D memory structure 400 includes a substrate (e.g., substrate 330 in Figure 3) and a stack of alternating conductive and dielectric layers (e.g., film stack 335 in Figure 3) disposed on the front surface 330f of the substrate 330. In some embodiments, the substrate 330 may provide a platform for forming subsequent structures. In some embodiments, the subsequent structures are formed in a vertical direction (e.g., the z-direction orthogonal to the front surface of the substrate 330). In Figure 4, the x and y directions are along a plane parallel to the front surface 330f of the substrate and parallel to the corresponding word line (WL) and bit line (BL) directions shown in Figures 1 through 3.

[0045] In some embodiments, substrate 330 may be any suitable semiconductor substrate having any suitable semiconductor material (e.g., single-crystal, polycrystalline, or monocrystalline semiconductor). For example, substrate 330 may include silicon, silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, substrate 330 may include a layer of semiconductor material formed on a processed wafer, such as glass, plastic, or another semiconductor substrate.

[0046] The front surface 330f of the substrate 330 is also referred to herein as the "main surface" or "top surface" of the substrate. Material layers may be disposed on the front surface 330f of the substrate 330. The "top layer" or "upper layer" is the layer furthest from or further from the front surface 330f of the substrate. The "bottom layer" or "lower layer" is the layer closest to or further from the front surface 330f of the substrate.

[0047] In some embodiments, the film stack 335 includes a plurality of conductive layers 454 and dielectric layers 456 alternately stacked on top of each other. The film stack 335 may extend in a lateral direction parallel to the front surface 330f of the substrate 330, while the conductive layers 454 and dielectric layers 456 may alternate in a vertical direction. In other words, except for the layer at the bottom of the film stack 335, each conductive layer 454 may be sandwiched between two dielectric layers 456, and each dielectric layer 456 may be sandwiched between two conductive layers 454. The conductive layers 454 may all have the same thickness or different thicknesses. Similarly, the dielectric layers 456 may all have the same thickness or different thicknesses. In some embodiments, the conductive layer 454 may include a conductive material, such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicides (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof. The dielectric layer 456 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the dielectric layer 456 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or / and any combination thereof.

[0048] The formation of the film stack 335 may include configuring the dielectric layers 456 to all have the same thickness or to have different thicknesses. An exemplary thickness of the dielectric layers 456 may range from 10 nm to 500 nm, preferably about 25 nm. Similarly, the conductive layers 454 may all have the same thickness or to have different thicknesses. An exemplary thickness of the conductive layers 454 may range from 10 nm to 500 nm, preferably about 35 nm. It should be understood that the number of conductive layers 454 and dielectric layers 456 in Figure 4 is for illustrative purposes only, and the film stack 335 may include any suitable number of layers. In some embodiments, the film stack 335 may include layers other than the conductive layers 454 and dielectric layers 456, and may be made of different materials and / or have different thicknesses.

[0049] In some embodiments, similar to storage cell 340 and storage string 212 in Figure 3, 3D memory structure 400 may also include a plurality of storage cells vertically stacked as storage strings. As shown in Figure 4, storage string 212 extends through film stack layer 335, wherein each storage string 212 may include a core filling film 339, a channel layer 338, and a storage film 337 (similar to those in Figure 3). The center of storage string 212 may be the core filling film 339. The channel layer 338 surrounds the core filling film 339, and the storage film 337 surrounds the channel layer 338. In some embodiments, the channel layer 338 includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the storage film 337 is a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. Each storage string 212 may have a cylindrical shape (e.g., columnar). In some embodiments, the channel layer 338, tunneling layer, storage layer, and barrier layer may be arranged in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon nitride, or any combination thereof. The barrier layer may include silicon oxide, silicon nitride, a high dielectric constant (high k) dielectric material, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the storage film 337 includes an ONO dielectric material (e.g., a tunneling layer including silicon oxide, a storage layer including silicon nitride, and a barrier layer including silicon oxide).

[0050] In some embodiments, the conductive layer 454 may function as a control gate or word line 333 for the storage cell 340. As shown in Figure 4, the storage string 212 may also include one or more lower select gates 332 (e.g., source select gates or bottom select gates) at its lower end (i.e., source terminal). The storage string 212 may also include one or more top select gates 334 (e.g., drain select gates) at its upper end (i.e., drain terminal). As used herein, the “upper end” of a component (e.g., storage string 212) is the end that is further away from the substrate 330 in the vertical direction, and the “lower end” of a component (e.g., storage string 212) is the end that is closer to the substrate 330 in the vertical direction. As shown in Figure 4, for each storage string 212, the top select gate 334 may be above the lower select gate 332. Figure 4 illustrates one lower select gate 332 and one top select gate 334 in the film stack layer 335. It should be understood that any suitable number of conductive layers 454 in the film stack 335 can be used as a lower selector 332 and a top selector 334.

[0051] In some embodiments, the 3D memory structure 400 may include one or more stepped structures in the stepped region 210, wherein each of the conductive layers 454 terminates at a different length in the horizontal x-direction. In some embodiments, the top selector 334 is the shortest, and the bottom selector 332 is the longest.

[0052] In some embodiments, the 3D memory structure 400 further includes a plurality of contact structures similar to the contact structures 214 in Figures 2 and 3. The top select gate 334, word line 333, and bottom select gate 332 can be electrically connected to one or more of the contact structures 214. Metal interconnects formed in the back-end process can be electrically connected to each conductive layer 454 via the contact structures 214. Therefore, by using a stepped structure, each storage cell 340 in the 3D memory structure 400 can be controlled to perform read, write, or erase operations via the corresponding word line 333. In some embodiments, the contact structure 214 can include any suitable conductive material, such as W, Ti, TiN, Cu, TaN, Al, Co, Ni, or any combination thereof.

[0053] In some embodiments, the stepped region 210 may include two stepped structures 210-L and 210-R that are symmetrical to each other along the y-direction. In some embodiments, a first subgroup of contact structures is formed on the conductive layer of the first stepped structure, and a second subgroup of contact structures is formed on the conductive layer of the second stepped structure. The second subgroup of contact structures is different from the first subgroup of contact structures. In some embodiments, a contact structure 214 may be formed for each other conductive layer 454 in each stepped structure. For example, for stepped structure 210-R, contact structure 214 may be formed to make electrical contact with odd-numbered character lines 333-1, 333-3, 333-5, 333-7, 333-9… and for stepped structure 210-L, contact structure 214 may be formed to make electrical contact with even-numbered character lines 333-2, 333-4, 333-6, 333-8… As a result, the minimum spacing s between contact structures 214 on different character lines 333 can be increased (e.g., doubled). Therefore, process tolerance can be increased for contact structure 214, and manufacturing yield can be improved. It should be noted that each step structure can include any suitable number of contact structures 214 on conductive layer 454, and is not limited to a single contact structure as shown in Figure 4.

[0054] In some embodiments, the stepped region 210 can be located anywhere within the storage array. In some embodiments, the stepped region 210 can be located at the center of the storage array. For example, the stepped region 210 can be placed in a 3D storage array 500, which can be any part of the storage block 103 in Figure 1. Referring to Figures 4 and 5, the storage strings 212 in the channel structure region 211 can be distributed along the x-direction on opposite sides of the stepped region 210.

[0055] In some embodiments, the 3D memory structure 400 further includes a stepped bridge 450 extending along an x-direction parallel to the character line 333. In the x-direction, the stepped bridge 450 is longer at the top and shorter at the bottom, with the top and bottom relative to their distances from the substrate. The stepped bridge 450 has a width w in the y-direction that is smaller than the total width of the stepped structures 210-L and 210-R. The stepped bridge 450 can connect corresponding character lines 333 between the stepped structures 210-L and 210-R. For example, the stepped bridge 450 can electrically connect character lines 333 in stepped structure 210-L and corresponding character lines 333 in stepped structure 210-R, the character lines 333 being formed of the same conductive layer 454. Therefore, for each step region 210, only one set of word line drivers with a set of interconnecting metal lines is needed to address each word line 333, wherein each word line 333 can be electrically connected from either step structure 210-L or step structure 210-R to at least one contact structure 214.

[0056] In some embodiments, the stepped bridge 450 may also be formed in the film stack layer 335, and may further include a plurality of conductive layers 454 and a plurality of dielectric layers 456. In this example, the stepped bridge 450 may be vertically disposed on the stepped structures 210-L and 210-R, wherein the bottom of the stepped bridge 450 may contact the bottom selector 332. In some embodiments, the stepped bridge 450 connects only the character line 333 between the stepped structures 210-L and 210-R. In some embodiments, the stepped bridge 450 may also connect the top selector 334 between the stepped structures 210-L and 210-R.

[0057] In some embodiments, the stepped bridge 450 may include a conductive material different from that of the conductive layer 454. In some embodiments, the stepped bridge 450 may include a thickness different from that of the conductive layer 454.

[0058] In some embodiments, the 3D memory structure 400 further includes one or more back select gate (BSG) cutouts 446, which can divide the lower select gate 332 (also referred to as the back select gate) into two or more sub-BSGs 332-1, 332-2, 332-3…, wherein the sub-BSGs 332-1, 332-2, 332-3… are electrically isolated from each other. Referring to Figures 4 and 5, in some embodiments, the BSG cutouts 446 and the sub-BSGs 332-1, 332-2, 332-3… extend along the x-direction and can divide the storage array 500 into multiple sub-blocks 448. By introducing BSG notches 446, the storage blocks of the 3D memory device (e.g., storage block 103 in Figure 1 and storage array 500 in Figure 5) can have improved bottom-select transistors (BSTs) due to reduced parasitic capacitance and coupling effects between the BSG 332 and adjacent dielectric layers. Furthermore, the partitioned BSG structure allows for erasing specific sub-blocks instead of the entire storage block 103. Therefore, erase time and data transfer time can be significantly reduced, and data storage efficiency can also be improved. For illustrative purposes only, Figures 4 and 5 show two BSG notches 446 and three sub-blocks 448. Note that the number of BSG notches 446 and sub-blocks 448 can be any suitable number and is not limited thereto.

[0059] As illustrated in the example in Figure 5, in some embodiments, the step bridge 450 has a width w smaller than the width d of the sub-block 448, such that at least one contact structure 214 (e.g., contact structure 214-L) can be formed on each of the sub-BSGs 332-1, 332-2, 332-3... in the step region 210.

[0060] In some embodiments, the 3D memory structure 400 may further include one or more Top Select Gate (TSG) cutouts 220. The TSG cutouts 220 may divide the TSG 334 into two or more sub-TSGs 334-1, 334-2, 334-3, ... and may divide each storage block 103 into storage slabs 224. As shown in the example of Figure 4, in some embodiments, the 3D memory structure 400 may have the same number of TSG cutouts 220 and BSG cutouts 446, and the TSG cutouts 220 and BSG cutouts 446 may be aligned with each other. In some embodiments, such as the 3D storage array 500 in Figure 5, the 3D memory structure 400 may have more TSG cutouts 220 than BSG cutouts 446. In this example, the TSG cutouts 220 may further divide the sub-block 448 into two or more storage slabs 224. In some embodiments, for each step structure 210-L / 210-R, a contact structure 214-T may be formed on each sub-TSG 334-1, 334-2, 334-3, ... . In some embodiments, the step bridge 450 may also be formed as electrically connecting one or more sub-TSGs 334 of the two step structures 210-L and 210-R. In some embodiments, each memory chip 224 can be read or programmed independently by controlling the corresponding sub-TSG. This reduces read / programming time and improves data transfer and storage efficiency. For illustrative purposes, three TSG cutouts 220 in each step structure are shown in Figure 4. It should be noted that the number of TSG cutouts 220 may be any suitable number and is not limited thereto.

[0061] In some embodiments, the 3D memory structure 400 may be filled with any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, SiOCN, or any combination thereof. For example, the insulating material may be filled between the contact structures 214 and inside the BSG cutouts 446 and TSG cutouts 220 in the stepped region 210. For simplicity, all of the insulating material is omitted in Figure 4.

[0062] The step bridge 450 can be located anywhere within the step region 210. Figures 4 and 5 illustrate a configuration where the step bridge 450 is located on a sub-block 448-1 near the slot structure 216 or near the edge of the storage array 500. In some embodiments, the step bridge 450 can be located at the center of the step region 210, for example, in sub-block 448-2.

[0063] To reduce resistance, in some embodiments, the width w of the stepped bridge 450 can be designed to be wider than the width shown in Figures 4 and 5. In this example, when the width w of the stepped bridge 450 is close to the width d of the sub-block 448, the process tolerance for forming the contact structure 214-L on one or more sub-BSGs 332 may be too small.

[0064] Figure 6 shows a top view of a 3D storage array 600 according to some embodiments of the present disclosure. The 3D storage array 600 may include two or more stepped regions 210-1, 210-2, ..., wherein the stepped regions 210-1, 210-2, ... may be located at the center of the 3D storage array 600. The 3D storage array 600 may be any part of the storage block 103 in Figure 1. Storage strings 212 and channel structure regions 211 may be arranged along the x-direction on opposite sides of the stepped regions 210-1, 210-2, ... In this example, the width w of the stepped bridge 450 is close to or greater than the width d of the sub-block 448. The stepped bridge 450 may be arranged on different sub-blocks 448 in two or more stepped regions, such that at least one contact structure 214 can be formed for each sub-BSG. For example, as shown in Figure 6, the step bridge 450-1 in step region 210-1 can be disposed in sub-block 448-1, and the step bridge 450-2 in step region 210-2 can be disposed in sub-block 448-3. Therefore, at least one contact structure 214-L can be formed on each sub-BSG of each sub-block 448. It should be noted that the construction of the 3D storage array 600 in Figure 6 is exemplary. Other arrangements of the step regions 210 can also be formed in the 3D storage array 600.

[0065] In some embodiments, the step bridge 450 may be implemented in various step structures to form a step region at the center of the storage array.

[0066] Figures 7A and 7B illustrate step structures 700A and 700B according to some embodiments of the present disclosure, wherein for the 3D storage array 600 shown in Figure 6, step structure 700A can be used for step region 210-1 and step structure 700B can be used for step region 210-2, or vice versa.

[0067] In this example, step structure 700A can provide electrical connections to word lines 333 in the upper portion of the membrane stack 335, and step structure 700B can provide electrical connections to word lines 333 in the lower portion of the membrane stack 335. Step structure 700A includes a first set of step steps 760, and step structure 700B includes a second set of step steps 762, the second set of step steps 762 having a vertical offset V relative to the first set of step steps. For example, when there are a total of n word lines, the first set of step steps 760 can be formed for n / 2 word lines 333 in the upper portion of the membrane stack 335, and the second set of step steps 762 can be formed for n / 2 word lines 333 in the lower portion of the membrane stack 335. Therefore, contact structures (omitted from Figures 7A and 7B for clarity) can be formed on the stepped structures 700A and 700B to provide electrical connections to the respective n / 2 word lines. Similar to the 3D memory structure 400, 3D storage array 500, and 3D storage array 600, stepped bridges 450 can also be formed for the stepped structures 700A and 700B to connect word lines 333 of the same step (i.e., formed by the same conductive layer in the film stack 335). In some embodiments, similar to the stepped structure in Figure 4, the stepped bridge 450 further includes a conductive layer and a dielectric layer of the film stack 335. In some embodiments, the stepped structures 700A and 700B may also include TSG cutouts and BSG cutouts similar to the previously discussed TSG cutout 220 and BSG cutout 446.

[0068] Figures 8A and 8B illustrate step structures 800A and 800B according to some embodiments of the present disclosure, wherein for the 3D storage array 600 shown in Figure 6, step structure 800A can be used for step region 210-1 and step structure 800B can be used for step region 210-2, or vice versa.

[0069] Similar to the staircase structures 700A and 700B in Figures 7A and 7B, staircase structures 800A and 800B may also have a vertical offset V. In addition to the staircase steps in the x-direction, staircase structures 800A and 800B also include staircase steps in the y-direction. Details of staircase structures having staircase steps in both the x and y directions can be found in co-pending U.S. Patent Application 16 / 458,401, filed July 1, 2019, entitled "Three-Dimensional Memory Device and Fabrication Methods Thereof," and U.S. Patent Application 16 / 422,434, filed May 24, 2019, entitled "Staircase Structure with Multiple Divisions for Three-Dimensional Memory," the entire contents of which are incorporated herein by reference.

[0070] In some embodiments, the stepped structures 800A and 800B may have ny steps in the y direction, wherein each step in the y direction exposes one conductive layer in the film stack 335. In some embodiments, the stepped structures 800A and 800B may have nx steps in the x direction, wherein each step in the x direction has a step height that is the same as the thickness of (ny+1) conductive and dielectric layers in the film stack 335.

[0071] In some embodiments, the step structure 800A and step structure 800B may further include a step bridge 450. Similarly, the step bridge 450 extends in the x-direction and connects the conductive layer (or character line) on the same step (at the same level of the step). In this example, contact structures for the character line can be formed on the step in both the x and y directions.

[0072] Figure 9 illustrates an exemplary fabrication process 900 for forming a 3D memory structure similar to the 3D memory structure 400 shown in Figure 4, according to some embodiments of the present disclosure. It should be understood that the process steps shown in fabrication process 900 are not exhaustive, and other process steps may be performed before, after, or between any shown process steps. In some embodiments, some process steps of the exemplary fabrication process 900 may be omitted, or other process steps not described herein may be included for simplicity. In some embodiments, the process steps of fabrication process 900 may be performed in different sequences and / or varied.

[0073] Figures 10A to 10C, 11A to 11B, 12A to 12B, 13A to 13B, 14A to 14C, 15A to 15B, 16, and 17A to 17B are cross-sectional or top views of a 3D memory device at various process steps according to some embodiments of the present disclosure.

[0074] As shown in Figure 9, fabrication process 900 begins at process step S910, where a bottom select gate (BSG) cutout 446 may be formed in the dielectric layer pair 1066. Figures 10A and 10B show cross-sectional views of an exemplary structure 1000 according to some embodiments of the present disclosure along the x and y directions, respectively. Figure 10C shows a top view of the structure 1000. The cross-sections in Figures 10A and 10B are along lines BB' and AA'. As shown in Figures 1, 2, 5, and 6, the x and y directions are along the word line direction and bit line direction, respectively. The structure 1000 includes a dielectric layer pair 1066 disposed on a substrate 330. In some embodiments, the structure 1000 may include a plurality of dielectric layer pairs 1066, wherein each dielectric layer pair 1066 includes a dielectric layer 456 (also referred to as a first dielectric layer) and a sacrificial layer 1068 (also referred to as a second dielectric layer) different from the dielectric layer 456.

[0075] Dielectric layer 456 may be similar to the dielectric layer discussed above with reference to Figure 4. In some embodiments, dielectric layer 456 comprises any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide with F doping, C doping, N doping, and / or H doping. Dielectric layer 456 may also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide. In some embodiments, dielectric layer 456 may be any combination of the above materials.

[0076] Forming a dielectric layer 456 on substrate 330 may include any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density plasma CVD (HDP-CVD), thermal oxidation, nitriding, any other suitable deposition method, or / and combinations thereof.

[0077] In some embodiments, the sacrificial layer 1068 comprises any suitable material different from the dielectric layer 456 and which can be selectively removed relative to the dielectric layer 456. For example, the sacrificial layer 1068 may comprise silicon oxide, silicon oxynitride, silicon nitride, TEOS, polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, and any combination thereof. In some embodiments, the sacrificial layer 1068 also comprises an amorphous semiconductor material, such as amorphous silicon or amorphous germanium. The sacrificial layer 1068 can be formed using techniques similar to those used for the dielectric layer 456, such as CVD, PVD, ALD, thermal oxidation, or nitriding, or any combination thereof.

[0078] In some embodiments, dielectric layer 456 may be silicon oxide, and sacrificial layer 1068 may be silicon nitride. The thicknesses of dielectric layer 456 and sacrificial layer 1068 may be in the range of 10 nm to 500 nm.

[0079] In some embodiments, one or more BSG notches 446 extending vertically into the substrate 330 may be formed in the dielectric layer pair 1066. The BSG notches 446 extend laterally in the x-direction, with a width t1 ranging from 50 nm to 500 mm. Forming the BSG notches 446 includes, but is not limited to: forming one or more trenches extending into the substrate 330 in the dielectric layer pair 1066; and filling one or more trenches with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, SiOCN, or any combination thereof. In some embodiments, forming the BSG notches 446 further includes forming coplanar surfaces using chemical mechanical polishing (CMP).

[0080] In some embodiments, peripheral devices (not shown) may be formed in a peripheral region 105 (see Figure 1) on the front surface 330f of the substrate 330. In some embodiments, an active device region (not shown) may also be formed in a storage block 103 (see Figure 1) on the front surface 330f of the substrate 330. In some embodiments, the substrate 330 may also include an insulating film 331 (not shown in Figure 4) on the front surface 330f. The insulating film 331 may be made of the same or different material as the alternating dielectric material stack layers 1164.

[0081] Peripheral devices can include any suitable semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), diodes, resistors, capacitors, etc. Peripheral devices can be used in the design of digital, analog, and / or mixed-signal circuits that support the storage functions of the memory core, such as row and column decoders, drivers, page buffers, sense amplifiers, timing and control units.

[0082] The active device region within the storage block is surrounded by an isolation structure, such as shallow trench isolation. Doped regions, such as p-type doped wells and / or n-type doped wells, can be formed in the active device region depending on the function of the array devices within the storage block.

[0083] In some embodiments, the structure 1000 of the 3D memory device may include a stepped region 210 and a channel structure region 211. In some embodiments, the channel structure region 211 may be arranged along the x-direction on opposite sides of the stepped region 210. The channel structure region 211 may be used to form a storage string 212 in subsequent processes, in which the stepped region 210 may be used to form a stepped structure.

[0084] At process step S920, a plurality of dielectric layer pairs 1066 may be disposed on substrate 330 to form alternating dielectric material stacks 1164. Figures 11A and 11B show cross-sectional views of an exemplary structure 1100 according to some embodiments of the present disclosure along the x and y directions, respectively. The alternating dielectric material stacks 1164 extend in a lateral direction parallel to the front surface 330f of substrate 330. In the alternating dielectric material stacks 1164, dielectric layers 456 and sacrificial layers 1068 may be alternately stacked on top of each other. In other words, each sacrificial layer 1068 may be sandwiched between two dielectric layers 456, and each dielectric layer 456 may be sandwiched between two sacrificial layers 1068 (except for the bottom and top layers).

[0085] The formation of alternating dielectric material stacks 1164 may include configuring dielectric layers 456 to have the same thickness or different thicknesses. An exemplary thickness of dielectric layer 456 may range from 10 nm to 500 nm, preferably about 25 nm. Similarly, sacrificial layers 1068 may have the same thickness or different thicknesses. An exemplary thickness of sacrificial layer 1068 may range from 10 nm to 500 nm, preferably about 35 nm. It should be understood that the number of dielectric layer pairs 1066 in Figures 11A and 11B is for illustrative purposes only, and any suitable number of layers may be included in the alternating dielectric material stacks 1164.

[0086] In some embodiments, the alternating dielectric material stack 1164 may include layers other than dielectric layer 456 and sacrificial layer 1068, and may be made of different materials and / or have different thicknesses.

[0087] At process step S930, a top selective gate (TSG) cutout 220 may be formed in the upper portion of the alternating dielectric material stack 1164. Figure 12A shows a cross-sectional view of an exemplary structure 1200 along the y-direction according to some embodiments of the present disclosure. Figure 12B shows a top view of structure 1200, wherein the cross-section in Figure 12A is along line AA' in Figure 12B. In some embodiments, one or more TSG cutouts 220 may extend vertically through one or more dielectric layer pairs 1066. The TSG cutouts 220 may extend laterally in the x-direction, wherein the width t2 is in the range of 50 nm to 500 nm. Forming the TSG notch 220 includes, but is not limited to: forming one or more trenches in one or more dielectric layer pairs 1066 in the upper portion of the alternating dielectric material stack 1164; and filling one or more trenches with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, SiOCN, or any combination thereof. In some embodiments, forming the TSG notch 220 also includes forming coplanar surfaces using chemical mechanical polishing (CMP).

[0088] At process step S940, a hard mask 1378 may be formed on the alternating dielectric material stack layers 1164. Figure 13A shows a cross-sectional view of an exemplary structure 1300 at process step S940, while Figure 13B shows a top view of structure 1300. The cross-sectional view in Figure 13A is along line CC' in the y-direction.

[0089] In some embodiments, the hard mask 1378 may include a dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, silicon-containing antireflective coating (SiARC), amorphous silicon, polycrystalline silicon, high-k dielectric material, or any combination thereof. In subsequent steps, the hard mask 1378 may be used to form a stepped bridge. The hard mask 1378 may define the width and length of the stepped bridge. The hard mask 1378 may include a sufficiently large thickness to protect the underlying alternating dielectric material stack 1164 during subsequent etching processes. The hard mask 1378 can be disposed on the alternating dielectric material stack 1164 using CVD, ALD, PVD, thermal oxidation or nitriding, evaporation, sputtering, spin coating, or any suitable thin film deposition process. The hard mask can then be patterned using lithography processes and etching processes such as reactive ion etching (RIE).

[0090] At process step S950, a first dielectric step 1470 and a second dielectric step 1472 may be formed in the stepped region 210, wherein the first and second dielectric steps may be connected by a dielectric bridge 1474. Figures 14A and 14B show cross-sectional views of an exemplary structure 1400 according to some embodiments of the present disclosure along the x and y directions, respectively. Figure 14C shows a top view of the structure 1400, wherein the cross-sections in Figures 14A and 14B are along lines BB' and CC'. In some embodiments, the stepped region 210 may be disposed in the middle of alternating dielectric material stacks 1164.

[0091] In the first dielectric step 1470 and the second dielectric step 1472, a step 1476 or "step layer" refers to a stack of layers having the same lateral dimension in a surface parallel to the substrate surface 330f. Each step 1476 terminates with a length shorter than the step below it by the lateral dimension "a" shown in Figure 14A. In some embodiments, each step 1476 includes a dielectric layer pair 1066. In some embodiments, each step 1476 may include two or more dielectric layer pairs 1066.

[0092] The first dielectric step 1470 and the second dielectric step 1472 (see Figure 14C) can be formed by applying repeated etch trimming processes on alternating dielectric material stacks 1164 using a patterned mask 1480. In some embodiments, the patterned mask 1480 may comprise a photoresist or a carbon-based polymer material. In some embodiments, the patterned mask 1480 may also comprise a hard mask, such as silicon oxide, silicon nitride, TEOS, silicon-containing antireflective coating (SiARC), amorphous silicon, polycrystalline silicon, or any combination thereof.

[0093] The etching trimming process includes an etching process and a trimming process. During the etching process, portions of each step 1476 with exposed surfaces can be removed. Remaining portions of each step 1476 that are covered by the upper step or by a patterned mask are not etched. The etching depth is the thickness of the step 1476. In some embodiments, the thickness of the step 1476 is the thickness of a dielectric layer pair 1066. The etching process for dielectric layer 456 can be highly selective for the sacrificial layer 1068, and / or vice versa. Therefore, the underlying dielectric layer pair 1066 can act as an etch stop layer. By switching the etching process for each layer, the step 1476 can be etched during one etch cycle. As a result, one step 1476 is formed during each etch trimming cycle.

[0094] In some embodiments, the stepped steps 1476 may be etched using anisotropic etching, such as reactive ion etching (RIE) or other dry etching processes. In some embodiments, the dielectric layer 456 is silicon oxide. In this example, etching of the silicon oxide may include RIE using a fluorine-based gas (e.g., fluorocarbon (CF4), hexafluoroethane (C2F6), CHF3, or C3F6, and / or any other suitable gas). In some embodiments, the silicon oxide layer may be removed using a wet chemical agent, such as hydrofluoric acid, or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etching method may be used. In some embodiments, the sacrificial layer 1068 is silicon nitride. In this example, etching of the silicon nitride may include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, or / and combinations thereof. The methods and etchants used to remove individual layer stacks should not be limited to the embodiments of this disclosure.

[0095] The trimming process involves applying a suitable etching process (e.g., isotropic dry etching or wet etching) to the patterned mask such that the patterned mask can be laterally pulled back. The lateral pull-back dimension determines the lateral dimension "a" of each step of the first dielectric step 1470 and the second dielectric step 1472. After the patterned mask trimming, a portion of the topmost step 1476 is exposed, while another portion of the topmost step 1476 remains covered by the patterned mask. The next cycle of the etching trimming process restarts with the etching process.

[0096] In some embodiments, the patterned mask finishing process may include dry etching, such as RIE using O2, Ar, N2, etc.

[0097] In some embodiments, the topmost step 1476 may be covered by a dielectric layer 456. In some embodiments, the topmost step 1476 may also be covered by other dielectric materials. A process step to remove the dielectric layer 456 and / or other dielectric materials may be added to the etching process of each etch trimming cycle to form the first dielectric step 1470 and the second dielectric step 1472.

[0098] In some embodiments, the dielectric bridge 1474 may be formed simultaneously with the first dielectric step 1470 and the second dielectric step 1472, wherein the dielectric bridge 1474 may be defined by a hard mask 1378. During the etching trimming process, portions of the alternating dielectric material stacks 1164 beneath the hard mask 1378 can be protected from etching. As a result, for each step 1476, the dielectric layer 456 and the sacrificial layer 1068 in the first dielectric step 1470 and the second dielectric step 1472 can be connected via the dielectric bridge 1474.

[0099] In some embodiments, the hard mask 1378 and the patterned mask used for the etching trimming process can be removed after process step S950.

[0100] At process step S960, according to some embodiments of this disclosure, a plurality of storage strings 212 may be formed in alternating dielectric material stacks 1164 in channel structure region 211. Figure 15A shows a cross-sectional view of an exemplary structure 1500 at process step S960. Figure 15B shows a top view of structure 1500. The cross-sectional view in Figure 15A is along line BB' in the x-direction. The storage strings 212 are similar to the storage strings previously discussed with reference to Figures 3 and 4.

[0101] In some embodiments, rather than forming a plurality of storage strings 212, an insulating layer 1582 may be disposed over the first dielectric step 1470 and the second dielectric step 1472. The insulating layer 1582 may comprise any suitable insulator, such as spin-coated glass, silicon oxide, low-k dielectric materials (e.g., carbon-doped oxides (CDO, SiOC, or SiOC:H), or fluorine-doped oxides (SiOF)), etc. The insulating layer 1582 may be disposed by CVD, PVD, sputtering, spin coating, etc. In some embodiments, a planarization process, such as RIE etch-back or chemical mechanical polishing (CMP), may be performed to form a coplanar surface parallel to the surface 330f of the substrate 330.

[0102] In order to form a plurality of storage strings 212, a plurality of channel holes (e.g., channel holes 336) may first be formed in alternating dielectric material stacks 1164, the plurality of channel holes penetrating the entire alternating dielectric material stacks 1164 and extending into the substrate 330.

[0103] After forming the channel holes 336, a storage film 337 can be disposed on the sidewall of each channel hole 336. In some embodiments, the storage film 337 may be a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. Next, a channel layer 338 and a core-filling film 339 can be disposed inside the channel holes 336. The channel layer 338 covers the sidewall of the storage film 337 inside the channel holes 336. The channel layer 338 may be any suitable semiconductor material, such as silicon. The core-filling film 339 may be any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, spin-coated glass, boron- or phosphorus-doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof.

[0104] In some embodiments, dummy memory strings (e.g., dummy memory strings 222 in the second figure) may also be formed adjacent to memory strings 212 and / or in the stepped regions of alternating dielectric material stacks 1164. While memory strings 212 can be used for memory storage, dummy memory strings 222 can be used to provide structural support and improve process uniformity during manufacturing. In some embodiments, dummy memory strings 222 may also include a core filler film 339 and may be formed using a technique similar to that used for memory strings 212.

[0105] At process step S970, an alternating conductive and dielectric film stack 335 can be formed by replacing the sacrificial layer 1068 in the alternating dielectric material stack 1164 in Figure 15A with a conductive layer 454. Figure 16 shows a cross-sectional view of an exemplary structure 1600 according to some embodiments of the present disclosure. The film stack 335 is similar to the film stack discussed previously with reference to Figures 3 and 4. After replacing the sacrificial layer with a conductive layer, stepped structures 210-L and stepped structures 210-R can be formed in the stepped region 210.

[0106] The alternating conductive and dielectric film stack 335 includes a conductive layer 454 sandwiched between dielectric layers 456. In structure 1600, each step 1686 includes a pair of conductive and dielectric layers 1684. In some embodiments, each step 1686 may include two or more pairs of conductive and dielectric layers, each pair having a conductive layer 454 and a dielectric layer 456.

[0107] To form the stepped structures 210-L and 210-R, the sacrificial layer 1068 in the alternating dielectric material stacks 1164 in Figure 15A can be selectively removed over the dielectric layer 456 to form a plurality of horizontal tunnels. The selective etching of the sacrificial layer 1068 can include wet or dry chemical etching. A conductive layer 454 can then be formed in the horizontal tunnels.

[0108] The conductive layer 454 may comprise any suitable conductive material appropriate for the gate electrode, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or / and any combination thereof. The conductive material may be deposited by CVD, PVD, ALD, sputtering, evaporation, etc. In some embodiments, the conductive layer 454 may also be a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, or / and combinations thereof. In some embodiments, the polycrystalline material may be combined with any suitable type of dopant (e.g., boron, phosphorus, or arsenic). In some embodiments, the conductive layer 454 may also be an amorphous semiconductor.

[0109] In some embodiments, a gate dielectric layer may be formed in the horizontal tunnel prior to the conductive layer 454 to reduce leakage current between adjacent word lines (gate electrodes) and / or reduce leakage current between the gate and the channel. The gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, or / and any suitable combination thereof. The gate dielectric layer may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or / and any combination thereof. The gate dielectric layer may be formed by one or more suitable deposition processes such as CVD, PVD, or / and ALD.

[0110] The conductive layer 454 acts as a gate electrode at its intersection with the storage string 212. It should be noted that the number of storage strings and gate electrodes in Figure 16 is shown for illustrative purposes and can be any suitable number to increase storage capacity.

[0111] At process step S980, contact structure 214 is formed on stepped structures 210-L and 210-R. Figure 17A shows a cross-sectional view of an exemplary structure 1700 at process step S980. Figure 17B shows a top view of structure 1700. The cross-sectional view in Figure 17A is along line BB' in the x-direction. Contact structure 214 may be similar to the contact structures previously discussed with reference to Figures 2 through 4.

[0112] Forming the contact structure 214 includes forming a plurality of contact holes through the insulating layer 1582 and disposing of a conductive material in the plurality of contact holes.

[0113] In some embodiments, photoresist or polymeric material may be used as a masking layer to etch contact holes 1788. One or more masking and patterning processes may be used to form contact holes 1788. In some embodiments, insulating layer 1582 may include an etch stop layer (not shown) that protects the underlying structure until all contact holes 1788 are formed on each step 1686. Contact holes 1788 extend through insulating layer 1582, thereby exposing conductive layer 454.

[0114] The contact structure 214 can be formed by providing a conductive material in the contact hole 1788. In some embodiments, the contact structure 214 may include a metal or metal compound, such as tungsten, cobalt, nickel, copper, aluminum, titanium, tantalum, tantalum nitride (TaN), or / and any combination thereof. The metal or metal compound may be formed by any suitable deposition method, such as sputtering, thermal evaporation, electron beam evaporation, ALD, PVD, or / and any combination thereof. In some embodiments, the contact structure 214 may also include a metal silicate, including WSix, CoSix, NiSix, or AlSix, etc.

[0115] In some embodiments, the contact structure 214 may be coplanar with the insulating layer 1582 using a planarization process (e.g., CMP process).

[0116] The contact structure 214 allows the conductive paths for the vertically stacked conductive layers 454 to be routed upwards to the surface, enabling various interconnections for 3D memory devices to be implemented in the back-end process.

[0117] In some embodiments, contact structures 214-T and 214-L may be formed on gate electrodes for the top selector gate (TSG) 334 and the bottom selector gate (LSG) or bottom selector gate (BSG) 332, respectively. In some embodiments, one or more contact structures 214 may be formed on the same TSG 334, word line 333, and BSG 332.

[0118] After replacing the sacrificial layer 1068 with the conductive layer 454, the dielectric bridge 1474 in Figure 15B is transformed into the stepped bridge 450 in Figure 17B. As a result, the conductive layers 454 of the stepped structures 210-L and 210-R can be connected via the stepped bridge 450. Therefore, each character line 333 can be electrically connected to either the stepped structure 210-L or the stepped structure 210-R. In some embodiments, contact structures 214 can be formed on the odd-numbered character lines 333 in the stepped structure 210-L and the even-numbered character lines 333 in the stepped structure 210-R. In this configuration, the spacing of the contact structures can be increased at adjacent stepped steps 1686.

[0119] In summary, this disclosure describes various embodiments of 3D memory devices and methods of manufacturing thereof.

[0120] One aspect of this disclosure provides a three-dimensional (3D) memory device. In an example, the 3D memory device includes a film stack having a plurality of pairs of conductive and dielectric layers stacked vertically on a substrate. Each pair of conductive and dielectric layers includes a dielectric layer and a conductive layer. The 3D memory device also includes a stepped region having first and second stepped structures formed in the film stack, wherein both the first and second stepped structures extend laterally in a first direction and include a plurality of pairs of conductive and dielectric layers. The stepped region also includes stepped bridges connecting the first and second stepped structures.

[0121] Another aspect of this disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing alternating stacked layers of dielectric material on a substrate, wherein the alternating stacked layers of dielectric material comprise a plurality of dielectric layer pairs. Each dielectric layer pair includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. The method further includes forming a first dielectric stair, a second dielectric stair, and a dielectric bridge in the alternating stacked layers of dielectric material, wherein the first and second dielectric staircases are connected by dielectric bridges.

[0122] The foregoing description of specific embodiments will thus fully reveal the general nature of this disclosure, enabling others to readily modify and / or adapt it to various applications (e.g., specific embodiments) by applying knowledge of the art without engaging in excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the disclosure and guidance presented herein, such adaptations and modifications are intended to be within the meaning and scope of equivalent forms of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive and not limiting purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on this disclosure and guidance.

[0123] Embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may be defined as long as the specific functions and their relationships are properly performed.

[0124] The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of this disclosure conceived by one or more inventors, and therefore are not intended to limit the scope of this disclosure and the appended patent applications in any way.

[0125] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be limited only by the scope of the appended patent applications and their equivalents.

[0126] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0127] 100: Three-dimensional memory device 101: Storage plane 103: Storage Block 105: Surrounding Area 108: Area 210: Stepped area 210-1: Stepped Area 210-2: Stepped Area 210-L: Stepped structure 210-R: Stepped structure 211: Channel structure area 212: Storage string 214: Contact Structure 214-L: Contact Structure 214-T: Contact Structure 216: Gap Structure 216-1: Gap Structure 216-2: Gap Structure 218: Storage finger section 220: Top selection gate cut 222: Dummy storage string 224: Storage chip 300: Storage Array Structure 330: Base 330f: Front surface 331: Insulating film 332: Lower Selector Gate 332-1: Sub-BSG 332-2: Sub-BSG 332-3: Sub-BSG 333: Character Line 333-1: Character Line 333-2: Character Line 333-3: Character Line 333-4: Character Line 333-5: Character Line 333-6: Character Line 333-7: Character Line 333-8: Character Line 333-9: Character Line 334: Top Selection Gate 334-1: Sub-TSG 334-2: Sub-TSG 334-3: Sub-TSG 335: Film stacking layer 336: Channel Hole 337: Storage membrane 338: Channel Layer 339: Core Filler Membrane 340: Storage Unit 340-1: Storage Unit 340-2: Storage Unit 340-3: Storage Unit 341: Bitline 343: Metal interconnect 344: Source Line Region 400:3D memory structure 446: Back selection gate cut 448-1: Sub-block 448-2: Sub-block 448-3: Sub-block 450: Stepped Bridge 450-1: Stepped Bridge 450-2: Stepped Bridge 454: Conductive layer 456: Dielectric layer 500:3D Storage Array 600:3D Storage Array 700A: Stepped structure 700B: Stepped structure 760: First set of steps 762: Second set of steps 800A: Stepped structure 800B: Stepped structure 900: Manufacturing Process 1000: Structure 1066: Dielectric layer pair 1068: Sacrifice Layer 1100: Structure 1164: Alternating stacked dielectric material layers 1200: Structure 1300: Structure 1378: Hard Mask 1400: Structure 1470: First Dielectric Step 1472: Second Dielectric Step 1474: Dielectric Bridge 1476: Staircase Steps 1480: Patterned Mask 1500: Structure 1582: Insulation layer 1600: Structure 1684: Pair of conductive and dielectric layers 1686: Stairs and steps 1700: Structure 1788: Contact Hole a: Horizontal dimension d: width s: minimum interval S910: Manufacturing Steps S920: Manufacturing Steps S930: Manufacturing Steps S940: Manufacturing Steps S950: Manufacturing Steps S960: Manufacturing Steps S970: Manufacturing Steps S980: Manufacturing Steps t1: Width t2: width V offset: Vertical offset w: width

Claims

1. A three-dimensional (3D) memory device, comprising: A film stack layer comprising a plurality of vertically stacked pairs of conductive and dielectric layers, wherein each pair of conductive and dielectric layers comprises a dielectric layer and a conductive layer; A first stepped region, comprising: a first stepped structure; a second stepped structure, wherein both the first and second stepped structures extend laterally in a first direction and include the conductive and dielectric layer pairs; and a first stepped bridge connecting the first and second stepped structures; and a second stepped region located on one side of the first stepped region along the first direction, the second stepped region comprising: a third stepped structure; a fourth stepped structure, wherein both the third and fourth stepped structures extend laterally in the first direction; a second stepped bridge connecting the third and fourth stepped structures; and a top selective gate (TSG) cutout extending along the first direction and perpendicularly passing through the upper portion of the film stack; wherein the first stepped bridge and the second stepped bridge are located on opposite sides of the first and second stepped regions, respectively, the width of the first stepped bridge along a second direction being less than twice the distance between adjacent TSG cutouts, the second direction being perpendicular to the first direction.

2. The three-dimensional memory device according to claim 1, wherein the first stepped region is in the middle of the storage array of the three-dimensional memory device.

3. The three-dimensional memory device according to claim 1, wherein the width of the TSG cut along a second direction is between 50 nm and 500 nm.

4. The 3D memory device as claimed in claim 1, wherein the first step bridge includes the conductive layer and dielectric layer pairs.

5. The 3D memory device as claimed in claim 4, wherein the first step bridge is configured to connect the conductive layer in each conductive layer and dielectric layer pair of the first step structure to the conductive layer in the corresponding conductive layer and dielectric layer pair of the second step structure.

6. The 3D memory device as claimed in claim 1, wherein the first step bridge extends laterally in the first direction, and the width of the first step bridge in a second direction is less than the total width of the first step structure and the second step structure.

7. The 3D memory device as claimed in claim 1, further comprising: A plurality of storage strings vertically penetrate the membrane stack, each storage string comprising: a core filling membrane; a channel layer surrounding the core filling membrane; and a storage membrane surrounding the channel layer.

8. The 3D memory device as claimed in claim 7, wherein the storage strings are distributed on opposite sides of the first step region.

9. The 3D memory device as claimed in claim 1, further comprising: A plurality of contact structures are electrically connected to the conductive layers of the first step structure and the second step structure.

10. The 3D memory device of claim 9, wherein a first subgroup of the contact structures is formed on the conductive layer of the first stepped structure; and a second subgroup of the contact structures is formed on the conductive layer of the second stepped structure, wherein the second subgroup of the contact structures is different from the first subgroup of the contact structures.

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