Package structure and chip packaging method

Abstract

Provided in the embodiments of the present disclosure are a package structure and a chip packaging method. The structure comprises: a first plastic packaging body, in which a first chip and a silicon wafer are packaged, wherein the silicon wafer is provided with a silicon through hole, and a bonding pad is connected to at least one end of the silicon through hole; a second plastic packaging body, which is stacked with the first plastic packaging body, wherein a second chip is packaged in the second plastic packaging body, at least one bonding pad of the second chip is connected to the first chip or the bonding pad of the silicon wafer on a first side of the first plastic packaging body by means of a first welding member, and the first side of the first plastic packaging body refers to the side adjacent to the second plastic packaging body; and a first redistribution layer, which is stacked on a second side of the first plastic packaging body, wherein the second side of the first plastic packaging body refers to the side opposite the first side, and the first chip and a bonding pad of the silicon wafer on the second side are connected to the first redistribution layer by means of a second welding member.

Description

Packaging structure and chip packaging method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure is based on and claims the priority of Chinese patent application No. 202310635391.3 filed on May 31, 2023, and all the disclosed contents thereof are incorporated into the present disclosure by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of chip packaging, and more particularly, to a packaging structure and a chip packaging method. Background Art

[0004] The Ball Grid Array (BGA) package is a key form of chip packaging. It typically uses flip-chip technology, connecting the chip's active surface to the substrate via an array of solder balls, while a heatsink is attached to the back of the chip.

[0005] However, the aforementioned chip packaging method requires a substrate, which results in a complex packaging process and high raw material supply costs. Therefore, it can be seen that the chip packaging method in the related art has the problem of complex packaging process and high raw material supply costs due to the need for a substrate.

[0006] Summary of the Invention

[0007] The embodiments of the present disclosure provide a packaging structure and a chip packaging method to at least solve the problems of the chip packaging method in the related art, such as the need to use a substrate, which leads to complex packaging process and high raw material supply cost.

[0008] According to one embodiment of the present disclosure, a packaging structure is provided, comprising: a first plastic package, wherein the first plastic package encapsulates: a first chip; a silicon wafer; wherein the silicon wafer has a through-silicon via, and at least one end of the through-silicon via is connected to a solder pad; a second plastic package stacked with the first plastic package, wherein the second plastic package encapsulates: a second chip; wherein at least one solder pad of the second chip is connected to a solder pad of the first chip or silicon wafer on a first side of the first plastic package through a first soldering member, and the first side of the first plastic package is a side adjacent to the second plastic package; and a first redistribution layer stacked on the second side of the first plastic package, wherein the second side of the first plastic package is a side opposite to the first side, and the solder pads of the first chip and silicon wafer on the second side are connected to the first redistribution layer through a second soldering member.

[0009] According to another embodiment of the present disclosure, a packaging method is provided, comprising: performing a plastic encapsulation process on a first chip and a silicon wafer to obtain a first plastic encapsulation body, wherein the silicon wafer has a through-silicon via, and at least one end of the through-silicon via is connected to a solder pad, and the solder pads of the first chip and the silicon wafer located on a first side of the first plastic encapsulation body are exposed to the first plastic encapsulation body; welding at least one solder pad of a second chip to a solder pad of the first chip or silicon wafer on the first side of the first plastic encapsulation body through a first soldering member, and performing a plastic encapsulation process on the second chip and the first plastic encapsulation body to obtain a second plastic encapsulation body, wherein the first plastic encapsulation body and the second plastic encapsulation body are stacked, and the first side of the first plastic encapsulation body is a side adjacent to the second plastic encapsulation body; performing a rewiring process on the second soldering member planted on the solder pads of the first chip and the silicon wafer located on the second side of the first plastic encapsulation body to obtain a first rewiring layer, wherein the first rewiring layer is stacked on the second side of the first plastic encapsulation body, and the second side of the first plastic encapsulation body is a side opposite to the first side.

[0010] According to another embodiment of the present disclosure, a packaging device is provided, comprising: a first processing unit, configured to perform a plastic encapsulation process on a first chip and a silicon wafer to obtain a first plastic encapsulation body, wherein the silicon wafer has a through-silicon via (TSV), at least one end of the TSV is connected to a solder pad, and the solder pads of the first chip and the silicon wafer located on a first side of the first plastic encapsulation body are exposed to the first plastic encapsulation body; a second processing unit, configured to perform a soldering process on at least one soldering pad of a second chip to a solder pad of the first chip or the silicon wafer on the first side of the first plastic encapsulation body via a first soldering member, and to perform a plastic encapsulation process on the second chip and the first plastic encapsulation body to obtain a second plastic encapsulation body, wherein the first plastic encapsulation body and the second plastic encapsulation body are stacked, and the first side of the first plastic encapsulation body is a side adjacent to the second plastic encapsulation body; and a third processing unit, configured to perform a rewiring process on the second soldering member implanted on the solder pads of the first chip and the silicon wafer located on the second side of the first plastic encapsulation body to obtain a first rewiring layer, wherein the first rewiring layer is stacked on the second side of the first plastic encapsulation body, and the second side of the first plastic encapsulation body is a side opposite to the first side.

[0011] According to another embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when running.

[0012] According to another embodiment of the present disclosure, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a cross-sectional schematic diagram of an exemplary packaging structure according to an embodiment of the present disclosure;

[0014] FIG2 is a cross-sectional schematic diagram of another exemplary packaging structure according to an embodiment of the present disclosure;

[0015] FIG3 is a cross-sectional schematic diagram of another exemplary packaging structure according to an embodiment of the present disclosure;

[0016] FIG4 is a schematic flow chart of an exemplary chip packaging method according to an embodiment of the present disclosure;

[0017] FIG5 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0018] FIG6 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0019] FIG7 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0020] FIG8 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0021] FIG9 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0022] FIG10 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0023] FIG11 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0024] FIG12 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0025] FIG13 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0026] FIG14 is a schematic diagram of another exemplary packaging method according to an embodiment of the present disclosure;

[0027] FIG15 is a cross-sectional schematic diagram of another exemplary package structure according to an embodiment of the present disclosure;

[0028] FIG16 is a structural block diagram of a chip packaging device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] According to one aspect of an embodiment of the present disclosure, a packaging structure is provided. Exemplarily, the packaging structure may be a packaging structure obtained by integrating heterogeneous chips in the same package body, and the heterogeneous chip may be a heterogeneous functional chip, which may be a functional chip with I / O (Input / Output) pins of different sizes and numbers. For chip packaging, BGA packaging is an important packaging form of current chip packaging products. BGA packaging generally adopts flip-chip technology, connecting the active surface of the chip to the substrate through an array of solder balls, and at the same time attaching a heat dissipation cover to the back of the chip. However, BGA packaging requires the use of a substrate, the packaging process is complicated, and the cost of raw material supply is high.

[0032] In order to at least partially solve the above problems, an embodiment provides a packaging structure that can realize chip packaging without a substrate. The packaging structure can be a fan-out high-integration chip packaging structure obtained by using a fan-out packaging method for chip packaging. Here, the fan-out packaging method is obtained by connecting multiple pins (usually 4 or more) to a flat surface, and these pins are scattered over the entire surface, and the shape is similar to a fan, hence the name "Fan-out". Unlike the traditional QFP (Quad Flat Package) that arranges each row of pins at an equal angle, the fan-out package can provide higher density, smaller model and more flexible wiring capabilities, and is particularly suitable for occasions that require compact space design, such as mobile devices, wireless communication equipment and consumer electronics.

[0033] As an exemplary embodiment, FIG1 is a cross-sectional schematic diagram of an exemplary package structure according to an embodiment of the present disclosure. As shown in FIG1 , the package structure includes: a first plastic package body 101, a second plastic package body 102 stacked with the first plastic package body 101, and a first redistribution layer 110 stacked on the second side of the first plastic package body 101, wherein:

[0034] The first plastic package 101 contains:

[0035] A first chip 103; a silicon wafer 104; wherein the silicon wafer 104 has a through silicon via 105, and at least one end of the through silicon via 105 is connected to a pad;

[0036] The second plastic package 102 contains:

[0037] The second chip 107; wherein at least one pad of the second chip 107 is connected to the pad of the first chip 103 or the silicon wafer 104 on the first side of the first plastic package 101 through the first soldering member 108, and the first side of the first plastic package 101 is the side adjacent to the second plastic package 102;

[0038] The second side of the first plastic package 101 is opposite to the first side, and the pads of the first chip 103 and the silicon die 104 on the second side are connected to the first redistribution layer 110 through the second soldering member 109 .

[0039] Compared to traditional BGA packaging, the packaging structure provided in this embodiment does not require a substrate, reducing the packaging process and raw material supply costs. Utilizing wafer-level packaging technology, multiple different chip packaging processes can be performed simultaneously on the same machine, reducing chip packaging time, increasing chip output, and improving chip yield. The absence of redundant circuit design reduces power consumption. The lack of a substrate reduces packaging costs. The ability to directly integrate different functional chips into a system-on-chip on the wafer improves chip performance and integration, and also provides a technical path for extending Moore's Law. For example, the packaging structure in this embodiment can be packaged using a fan-out packaging method.

[0040] Regarding the first plastic package 101, the first plastic package 101 encapsulates a first chip 103 and a silicon wafer 104. Here, the number of silicon wafers 104 can be one or more, at least one silicon wafer 104 serves as a silicon (Si) dielectric layer, and each silicon wafer 104 can have a circuit laid out using at least one TSV (Through-silicon via) 105 and at least one corresponding pad, and a pad is connected to at least one end of the TSV. The size and number of TSVs on different silicon wafers can be different. Here, the TSV structure refers to a small hole or deep groove made on a single crystal silicon wafer for circuit connection or gas transmission, etc.

[0041] For the second plastic package 102, a group of second chips 107 are encapsulated in the second plastic package 102. The first chip 103 and the second chip 107 can be heterogeneous chips. The first chip 103 and each second chip 107 can be functional chips with I / O pins of different sizes and numbers. Moreover, different second chips 107 can also be functional chips with I / O pins of different sizes and numbers, or functional chips with I / O pins of the same size and number. The number of second chips 107 can be one or two or more. In this embodiment, there is no limitation on the chip type and quantity of the first chip 103 and the second chip 107.

[0042] Illustratively, the first chip and the second chip may both be integrated chips. The types of integrated chips are not limited and they can be freely matched according to integration needs.

[0043] The first redistribution layer 110 is used to realize the redistribution of the first chip and the second chip. The first redistribution layer 110 is stacked on the second side of the first plastic package 101 and connected to the first chip 103 and the silicon wafer 104 through the second welding member.

[0044] As an exemplary solution, depending on the different functional integration requirements, the first chip can freely select the chip type, which can be but is not limited to one of the following: ASIC (Application Specific Integrated Circuit) chip (i.e., dedicated integrated chip); Logic IC (logic integrated circuit) chip.

[0045] As an exemplary solution, depending on the functional integration requirements, the second chip can be freely selected from a variety of chip types, and different second chips can be freely combined. The number of second chips can be one or more, and can include, but is not limited to, at least one of the following: a memory chip, a NAND (NAND flash) chip, an integrated circuit (e.g., an analog) chip, an RF (Radio Frequency) chip, or a Wide I / O DRAM (Wide I / O Dynamic Random Access Memory) chip.

[0046] Exemplarily, the number of second chips can be two, both of which can be functional chips, one of the second chips is one of the following: Memory, NAND, Analog, RF chip, etc., which can be selected according to needs, and the other second chip is one of the following: Memory, Wide I / O DRAM chip, etc., which can be selected according to needs.

[0047] There are many ways to package a chip, such as 2D (Dimensions) packaging, 2.5D packaging, and 3D packaging.

[0048] 2D packaging refers to the packaging that integrates the die (bare crystal) into the chip in a flat manner on a two-dimensional plane. 2D packaging is limited by the physical limitations of the two-dimensional plane.

[0049] 2.5D packaging involves laying the die flat on an interposer in a two-dimensional plane, utilizing the interposer's wiring and TSVs to expand the I / O count and interconnect with the substrate. While 2.5D packaging does increase the I / O count to some extent, it still falls within the physical limitations of a two-dimensional plane.

[0050] 3D packaging involves creating TSVs and wiring directly on the die, achieving vertical electrical interconnection between dies. While 3D packaging transcends the physical limitations of two-dimensional surfaces, it imposes certain requirements on die type, quantity, I / O count and size, and TSV count and size. 3D packaging is primarily used for stacking chips of the same type and matching dimensions.

[0051] For example, in this embodiment, silicon wafer interconnection bridging technology can be used to break the physical limitations of the die on the two-dimensional plane. The first chip and the second chip are sealed in the vertical direction, that is, the chips with heterogeneous functions are sealed in the vertical direction in a 3D stacking manner. Compared with the aforementioned 2D, 2.5D and 3D packaging, it can improve the integration, reduce the packaging volume, improve the power density of the system, shorten the chip interconnection distance to improve the system performance such as signal integrity and power integrity. At the same time, the packaging structure in this embodiment uses a silicon wafer as the Si dielectric layer, instead of using a whole-chip interposer for line switching. In addition, dies of different types, different I / O numbers and sizes, and different TSV numbers and sizes can be sealed according to needs, which is flexible in design.

[0052] By leveraging existing silicon interconnect bridge technology, stacking chips in a quasi-3D fashion can shorten chip interconnect distances and improve system performance, such as signal integrity and power integrity. Furthermore, by utilizing silicon interconnect bridge designs with varying TSV sizes and numbers, functional chips of varying sizes can be integrated, providing greater flexibility in the design.

[0053] For example, in this embodiment, one or more silicon wafers are encapsulated within a first plastic package to facilitate the sealing of a first chip and at least one second chip in a quasi-3D manner. The size and number of through-silicon vias (TSVs) on each silicon wafer can match the size and number of pads on the second chip to which each silicon wafer is connected. This enhances chip packaging flexibility and accommodates different functional chips or combinations of functional chips.

[0054] For the second chip 107 , each pad of each second chip 107 is interconnected with the first chip 103 or a pad of one of the at least one silicon chip 104 on the first side of the first plastic package 101 through a first soldering member 108 .

[0055] Exemplarily, when the number of silicon wafers is two or more, at least one of the size and number of through silicon vias on at least two silicon wafers is different. For example, the sizes of the through silicon vias on at least two silicon wafers are different. For another example, the numbers of the through silicon vias on at least two silicon wafers are different.

[0056] Exemplarily, the first soldering members 108 may be located within the second plastic package 103. The number of the first soldering members 108 may be one or more, and may match the number of solder pads on the first side of the first plastic package 101 of the first chip 103 or the at least one silicon chip 104, and also match the number of solder pads on the first side of the first plastic package 101 that the second chip 107 needs to connect to. The first soldering members 108 may be of various types, including but not limited to at least one of the following: solder balls and solder pillars. The materials of the solder balls include, but are not limited to, one or a combination of two or more metals such as copper, nickel, tin, gold, silver, aluminum, and titanium. The materials of the solder pillars include, but are not limited to, one or a combination of two or more metals such as copper, nickel, tin, gold, silver, aluminum, and titanium.

[0057] Regarding the first plastic package 101 , the second side of the first plastic package 101 has a first redistribution layer 110 obtained by redistributing second soldering members 109 implanted on the pads of the first chip 103 and at least one silicon chip 104 on the second side.

[0058] Second soldering members 109 can be located within first plastic package 101. The number of second soldering members 109 can match the number of solder pads on the second side of first plastic package 101 for first chip 103 or at least one silicon wafer 104. Second soldering members 109 can be of various types, including but not limited to at least one of the following: solder balls and solder pillars. The materials of solder balls include, but are not limited to, one or a combination of two or more metals such as copper, nickel, tin, gold, silver, aluminum, and titanium. The materials of solder pillars include, but are not limited to, one or a combination of two or more metals such as copper, nickel, tin, gold, silver, aluminum, and titanium.

[0059] It should be noted that solder balls of different sizes and quantities can be planted on the pads on the surface of the first chip 103 and the Si dielectric layer by means of ball planting. The first chip 103 and the second chip 107 can freely select chip types and specifications according to different requirements of integrated functions, and the interconnection methods between chips and between chips and inner and outer layer circuits can also be freely selected, not limited to tin ball welding and copper column welding between copper and copper.

[0060] In this embodiment, the first redistribution layer 110 is obtained through RDL (Re-Distribution Layer) processing. The redistribution layer can be used to reroute wiring to the desired area and achieve a higher contact density. The redistribution process effectively adds one or more layers to the original wafer. First, a dielectric layer is deposited for isolation. Then, the original contacts are exposed, and a new metal layer is deposited to achieve the rerouting.

[0061] It should be noted that this embodiment provides a packaging structure (fan-out packaging structure) that utilizes silicon wafer interconnect bridges to integrate chips with different functions into a single integrated system-on-chip. Unlike previous silicon wafer bridges, this embodiment utilizes silicon wafers with TSV (Through Silicon Via) structures of varying sizes and quantities and bumping interconnect technology to integrate heterogeneous chips with varying sizes and numbers of I / O pins into the same package, offering a flexible design. Furthermore, the heterogeneous functional chips are packaged vertically alongside functional chips (e.g., ASIC chips) in a quasi-3D stacking manner, increasing integration, reducing package size, improving system power density, and shortening chip interconnect distances to enhance system performance, such as signal integrity and power integrity.

[0062] At the same time, the fan-out high-integration chip packaging structure provided in this embodiment rewires the circuits of heterogeneous chips through RDL technology, thereby realizing the integration of chips with different functions. Compared with traditional BGA packaging, it has the following characteristics and advantages: no substrate is required, which reduces the packaging process and raw material supply costs; wafer-level packaging technology is used to improve chip yield; different functional chips can be directly integrated into a system chip on the wafer, thereby improving chip performance and integration.

[0063] The packaging structure provided in this embodiment includes: a first plastic package, in which: a first chip; a silicon wafer; wherein the silicon wafer has a through-silicon via, and at least one end of the through-silicon via is connected to a pad; a second plastic package stacked with the first plastic package, in which: a second chip; wherein at least one pad of the second chip is connected to the pad of the first chip or silicon wafer on the first side of the first plastic package through a first welding piece, and the first side of the first plastic package is a side adjacent to the second plastic package; a first redistribution layer stacked on the second side of the first plastic package, wherein the second side of the first plastic package is a side opposite to the first side, and the pads of the first chip and silicon wafer on the second side are connected to the first redistribution layer through the second welding piece. This can solve the problems of complex packaging process and high raw material supply cost caused by the need to use a substrate in the chip packaging method in the related art, simplify the chip packaging process, and reduce the raw material supply cost.

[0064] As an exemplary solution, as shown in Figure 2, at least one side of the first chip 103 has a second redistribution layer 201 obtained by redistributing the solder bumps of the first chip 103, and at least one side of each second chip 107 has a third redistribution layer 202 obtained by redistributing the solder bumps of each second chip 107.

[0065] The formation of the second and third redistribution layers 201 and 202 is similar to the formation of the first redistribution layer 110 in the aforementioned embodiment and will not be further described here. The second redistribution layer 201 can be used to implement redistribution of the first chip, and the third redistribution layer 202 can be used to implement redistribution of the second chip.

[0066] Here, bumps and rewiring layers occupy the planar area where the chip is bonded to the substrate. TSVs can stack chips to utilize three-dimensional space. More importantly, stacking technology improves the electrical properties of multi-chip connections, and TSVs can achieve lower power consumption and greater bandwidth for transmission between chips.

[0067] According to this embodiment, by rewiring the solder bumps of the packaged chips, heterogeneous chips can be conveniently packaged, thereby improving the convenience of chip packaging.

[0068] As an exemplary solution, as shown in Figure 3, a third welding part 301 is welded on the first redistribution layer 110. The number of the third welding parts 301 can be the same as the number of pads on the second side of the first plastic package of the first chip and silicon wafer connected to the first redistribution layer 110, which can be at least one of the following: solder balls, solder columns, wherein the material of the solder balls and the material of the solder columns can be similar to those in the aforementioned embodiments and are not repeated here.

[0069] According to this embodiment, by welding the welding parts on the rewiring layer, an interface can be provided outward, thereby improving the convenience of function provision.

[0070] According to another aspect of the present disclosure, a chip packaging method is provided. The chip packaging method can be used to package heterogeneous chips to obtain the aforementioned packaging structure. For example, as shown in FIG4 , FIG4 is a flow chart of an exemplary chip packaging method according to an embodiment of the present disclosure. As shown in FIG4 , the flow of the method can include the following steps:

[0071] Step S402 , performing plastic packaging on the first chip and the silicon wafer to obtain a first plastic packaging body.

[0072] The packaging method of this embodiment can be applied to chip packaging scenarios, for example, scenarios where heterogeneous functional chips need to be integrated into a system-on-chip to improve chip processing capabilities. The number of packaged chips can be one or more, and the types of the packaged chips can be completely identical, partially identical, or completely different. The packaging method can adopt fan-out packaging, rerouting the circuits of the heterogeneous chips using RDL technology to achieve the integration of chips with different functions.

[0073] When performing chip packaging, the first chip and the silicon wafer can be plastic-sealed with a plastic packaging material to obtain a first plastic packaging body. The first chip, the silicon wafer and the first plastic packaging body are similar to those in the above embodiment and are not described in detail here.

[0074] For example, the functional chip a (Logic IC, corresponding to the first chip) and the Si dielectric layer can be encapsulated with the plastic encapsulation material once. At this time, the inner solder balls (corresponding to the second welding parts) are completely wrapped by the plastic encapsulation material, and the plastic encapsulation body 1 (corresponding to the first plastic encapsulation body) plays a good protective and supporting role.

[0075] Step S404: solder at least one pad of the second chip to the pad of the first chip or silicon wafer on the first side of the first plastic package body through a first soldering member, and then plastic-seal the second chip and the first plastic package body to obtain a second plastic package body.

[0076] To obtain the first plastic package, at least one pad of the second chip can be soldered to a pad of the first chip or silicon wafer on the first side of the first plastic package via a first soldering member. The pad to which each pad of each second chip is connected can be pre-set to achieve automatic soldering of the chips.

[0077] After the above-mentioned welding process is completed, the second chip and the first plastic package body can be plastic-encapsulated to obtain a second plastic package body. The first plastic package body and the second plastic package body are stacked, and the first side of the first plastic package body is the side adjacent to the second plastic package body. The second plastic package body can completely wrap the second chip and the first plastic package body, and a certain thickness needs to be maintained from its edge to ensure the reliability and high performance of the chip.

[0078] For example, after planting the required number of solder balls of different sizes on the pads of functional chip a and the Si dielectric layer, the pads of chip b and chip c (corresponding to a group of second chips) that have undergone rewiring processing are aligned with the solder balls and soldered, and then the plastic package body is plastic-sealed for the second time. At this time, plastic package body 2 needs to completely wrap chip b (Memory 1), chip c (Memory 2) and plastic package body 1, and a certain thickness needs to be maintained from its edge to ensure the reliability and high performance of the chip.

[0079] Step S406 , performing a rewiring process on the first chip and the second soldering member implanted on the soldering pads of the silicon wafer on the second side of the first plastic package to obtain a first rewiring layer.

[0080] After the second plastic encapsulation, a rewiring process can be performed on the second soldering member implanted on the soldering pads of the first chip and silicon wafer located on the second side of the first plastic encapsulation body to obtain a first rewiring layer. The soldering pads of the first chip and silicon wafer on the second side are connected to the first rewiring layer via the second soldering member. The first rewiring layer is stacked and arranged on the second side of the first plastic encapsulation body, where the second side of the first plastic encapsulation body is opposite to the first side. The manner of performing the rewiring process is similar to that in the aforementioned embodiment and will not be described in detail here.

[0081] For example, a fan-out packaging method can be used to rewire the functional chip a and the balls planted for the first time on the Si dielectric layer, and outer solder balls can be welded on the manufactured outer metal circuits to complete the packaging.

[0082] Through the above steps, the first chip and the silicon wafer are plastic-sealed to obtain a first plastic-sealed body, wherein the silicon wafer has a through-silicon via, and at least one end of the through-silicon via is connected to a pad, and the pads of the first chip and the silicon wafer located on the first side of the first plastic-sealed body are exposed to the first plastic-sealed body; at least one pad of the second chip is welded to the pad of the first chip or the silicon wafer on the first side of the first plastic-sealed body through a first welding member, and the second chip and the first plastic-sealed body are plastic-sealed to obtain a second plastic-sealed body, wherein the first plastic-sealed body and the second plastic-sealed body are stacked. The first side of the first plastic package is adjacent to the second plastic package; the second welding parts planted on the first chip and the silicon wafer on the welding pads on the second side of the first plastic package are re-wired to obtain a first re-wiring layer, wherein the first re-wiring layer is stacked and arranged on the second side of the first plastic package, and the second side of the first plastic package is the side opposite to the first side. This can solve the problems of complex packaging process and high raw material supply cost caused by the need to use a substrate in the chip packaging method in the related art, simplify the chip packaging process, and reduce material costs.

[0083] As an exemplary solution, before the first chip and the silicon wafer are plastic-encapsulated, the method further includes:

[0084] S11, mounting the first chip and the silicon wafer on the first adhesive film in sequence, wherein the first adhesive film is laid flat on the first supporting carrier.

[0085] To ensure the stability of the plastic encapsulation, a first adhesive film can be laid flat on a first support carrier before the first chip and silicon wafer are plastic encapsulated, and the first chip and silicon wafer are sequentially mounted on the first adhesive film to prevent the first chip and silicon wafer mounted thereon from shifting. Here, the first support carrier can be a carrier wafer, which can be made of silicon, has a flat surface, and can provide support. The first adhesive film can be adhesive, and the material of the adhesive film is not limited in this embodiment.

[0086] For example, as shown in FIG5 , a support carrier 1 501 with a flat surface and capable of supporting is selected, and a layer of adhesive film 1 (Adhesive film) 502 is laid on top of the support carrier 1 to prevent displacement, wherein the support carrier 1 is a carrier wafer; then, the functional chip a (Logic IC) and the Si dielectric layer are sequentially mounted on the supportive and adhesive film 1 502, as shown in FIG6 , wherein the two layers on the outside of the functional chip are RDLs, the outer rectangle is a copper pillar pad, and the shape is a TSV through-silicon via, which is located on the Si dielectric layer.

[0087] Then, solder balls of varying sizes and quantities can be planted on the pads on the surface of the functional chip a and the Si dielectric layer using a ball planting method, as shown in Figure 7. Next, the functional chip a and the Si dielectric layer are molded with a molding compound, completely encapsulating the inner solder balls, as shown in Figure 8.

[0088] According to this embodiment, the chip and the silicon wafer are sequentially mounted using the adhesive film laid flat on the support carrier, which can prevent the chip and / or the silicon wafer from shifting and improve the stability of the plastic package.

[0089] As an exemplary solution, after the first chip and the silicon wafer are plastic-sealed, the method further includes:

[0090] S21, sequentially covering a second adhesive film and a second supporting carrier on a second side of the first plastic packaging body, wherein the second adhesive film and the second supporting carrier are larger in size than the first plastic packaging body;

[0091] S22, performing a flipping operation on the first plastic package body, and removing the first supporting carrier and the first adhesive film in sequence.

[0092] After the first chip and silicon wafer are plastic-encapsulated, the pads of the first chip and silicon wafer that need to be soldered to the pads on the second chip are located on the side connected to the first adhesive film. To this end, the first plastic encapsulation body can be flipped over, and the first support carrier and the first adhesive film can be removed in sequence to expose the pads on the first chip and silicon wafer.

[0093] In order to ensure the stability of subsequent processing, before performing the flipping operation on the first plastic packaging body, the second side of the first plastic packaging body can be covered with a second adhesive film and a second supporting carrier in sequence. The size of the second adhesive film and the second supporting carrier is larger than that of the first plastic packaging body to facilitate subsequent processing (for example, secondary plastic packaging).

[0094] For example, a slightly larger and sticky film 2 902 and support carrier 2 901 can be added to the plastic package 1, as shown in FIG9 . The plastic package 1 is then flipped over to expose the support carrier 1 and film 1 at the bottom, as shown in FIG10 . Finally, the support carrier 1 and film 1 are removed, exposing the pads of the functional chip a and the Si dielectric layer, as shown in FIG11 .

[0095] After planting the required number of solder balls of different sizes on the pads of functional chip a and the Si dielectric layer, align the pads of chip b (Memory 1 chip) and chip c (Memory 2 chip) after rewiring with the solder balls and solder them. Then, the plastic package body is plastic-sealed for the second time. At this time, plastic package body 2 needs to completely wrap chip b, chip c and plastic package body 1, and a certain thickness needs to be maintained from its edge to ensure the reliability and high performance of the chip, as shown in Figure 12.

[0096] According to this embodiment, by adding a new support carrier and adhesive film, flipping the plastic package body, and removing the previous support carrier and adhesive film, the stability of subsequent processing can be ensured, and the convenience of plastic packaging processing can be improved.

[0097] As an exemplary solution, before rewiring the first chip and the second soldering member implanted on the solder pad on the second side of the first plastic package, the method further includes:

[0098] S31, sequentially covering a third adhesive film and a third supporting carrier on a side of the second plastic packaging body opposite to the first plastic packaging body;

[0099] S32, performing a flipping operation on the second plastic package body, and removing the second supporting carrier and the second adhesive film in sequence.

[0100] The second welding part is located in the first plastic package, on a side opposite to a group of second chips. In order to re-wire the second welding part, the second plastic package can be flipped over, and the second supporting carrier and the second adhesive film can be removed in sequence to expose the second welding part planted on the pads of the first chip and at least one silicon wafer located on the second side of the first plastic package.

[0101] To ensure stability during subsequent processing, a third film and a third support carrier may be sequentially applied to the side of the second plastic encapsulation body opposite the first plastic encapsulation body before the second plastic encapsulation body is flipped over. For example, the third film or other support component may be applied only to the side of the second plastic encapsulation body opposite the first plastic encapsulation body, which is not limited in this embodiment.

[0102] For example, after a layer of adhesive film 3 1301 is applied to the surface of the plastic package on one side of chip b and chip c, the plastic package is turned over to expose the support carrier 2 and the adhesive film 2, which are then removed, as shown in FIG13 .

[0103] According to this embodiment, a layer of adhesive film is applied to stabilize the plastic package body, thereby improving the stability of the plastic package body and facilitating subsequent processing procedures.

[0104] Exemplarily, before rewiring the first chip and the second soldering member implanted on the solder pads of the silicon wafer on the second side of the first plastic package, the method further includes:

[0105] S41, thinning the second side of the first plastic package to expose the first chip and the second soldering member implanted on the soldering pad of the silicon wafer located on the second side of the first plastic package.

[0106] During the plastic encapsulation process, if the plastic encapsulation position is precisely controlled, that is, the plastic encapsulation is performed to a position where the second soldering member is exposed, the plastic encapsulation accuracy requirement is high, which not only increases the cost but also easily leads to the problem of inaccurate plastic encapsulation. In this embodiment, the second side of the first plastic encapsulation body can be thinned to expose the second soldering member implanted by the pads of the first chip and the silicon wafer located on the second side of the first plastic encapsulation body. Here, the rewiring process can be implemented using a fan-out packaging method, and the thinning process can be implemented by cutting, grinding, etc., which is not limited in this embodiment.

[0107] For example, the upper layer of the plastic package 1 can be thinned (Mold Grinding) to expose the functional chip a and the first implanted balls on the Si dielectric layer. A fan-out fan-out packaging method is used to rewire them, and outer solder balls are welded on the manufactured outer metal circuits. Finally, the adhesive film 3 is removed and the packaging is completed, as shown in Figure 14.

[0108] According to this embodiment, by thinning the plastic package body to expose the required welding parts, the requirements for the plastic packaging process can be reduced, the convenience of chip plastic packaging can be improved, and the cost can be reduced.

[0109] As an exemplary solution, before the first chip and the silicon wafer are plastic-encapsulated, the method further includes:

[0110] S51 , performing TSV processing and pad processing on the silicon wafer to obtain a silicon wafer with TSVs, wherein the size and number of the TSVs on the silicon wafer match the size and number of pads of the second chip to which the silicon wafer is connected.

[0111] In this embodiment, in order to achieve sealing with chips of different specifications, each silicon wafer in at least one silicon wafer can be processed with silicon vias and pads, so that each silicon wafer has a circuit laid out by at least one silicon via and at least one pad.

[0112] Here, the pads on each silicon wafer may correspond one-to-one to the TSVs, and the TSV through-silicon via structures may be of different sizes, the size of which may match the size of the pads of the second chip to which each silicon wafer is connected, or the TSVs on each silicon wafer may be of the same size, while the sizes of the TSVs on different silicon wafers may be different. For example, the number of TSVs on each silicon wafer may match the number of pads of the second chip to which each silicon wafer is connected, or the number of TSVs on each silicon wafer may be fixed, and the number of silicon wafers may be adjusted to achieve matching of the number of TSVs on the silicon wafer with the number of pads of the second chip to which the silicon wafer is connected. This is not limited in this embodiment.

[0113] For example, the functional chip a is processed with the redistribution layer RDL and copper pillar pads in sequence, and the Si dielectric layer is processed with TSV silicon through-hole technology to make circuits and pads. The number and size of TSV silicon through-holes can be matched according to the different sizes and numbers of I / O pins of the chip to be sealed.

[0114] Through this embodiment, functional chips of different sizes are integrated by utilizing the design of silicon wafer interconnection bridges with different TSV sizes and numbers, thereby improving the flexibility of the integrated design.

[0115] The packaging structure in the embodiments of the present disclosure is explained below with reference to an exemplary embodiment. This exemplary embodiment provides a fan-out highly integrated packaging structure, which can be obtained using a fan-out highly integrated chip packaging method. The packaging structure includes: a first chip, function chip a (Logic IC), and a set of second chips, including function chip b (Memory 1 chip) and function chip c (Memory 2 chip).

[0116] As shown in Figure 15, the package structure includes:

[0117] 1501, support carrier 1 (removed after the process is completed);

[0118] 1502, film 1 (removed after the process is completed);

[0119] 1503, functional chip a;

[0120] 1504, redistribution layer RDL1;

[0121] 1505, copper pillar pad;

[0122] 1506, TSV;

[0123] 1507, Si dielectric layer;

[0124] 1508, inner solder balls;

[0125] 1509, plastic package 1;

[0126] 1510, support carrier 2 (removed after the process is completed);

[0127] 1511, film 2 (removed after the process is completed);

[0128] 1512, functional chip b;

[0129] 1513, functional chip c;

[0130] 1514, plastic package 2;

[0131] 1515, film 3 (removed after the process is completed);

[0132] 1516, redistribution layer RDL2;

[0133] 1517, outer solder balls.

[0134] The chip type, I / O size, and quantity in this structure can be integrated into the system-on-chip by replacing different chip specifications based on the actual application scenario. The interconnection methods between chips and between chips and internal and external circuits in this structure can also be freely selected, and are not limited to solder ball welding and copper pillar welding between copper.

[0135] This illustrative example utilizes wafer-level packaging technology to integrate heterogeneous functional chips into a single chip with multiple signal processing capabilities. This packaging technology differs from other advanced packaging technologies. For example, unlike conventional 2D fan-out packaging, it vertically integrates the chips into a single chip, increasing integration density and reducing package size under the same conditions. The resulting chip is an integrated system-on-chip (SoC), integrating more functional units per unit volume, thereby increasing system power density.

[0136] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0137] According to another aspect of the embodiments of the present disclosure, a chip packaging device is also provided, which is used to implement the above-mentioned embodiments and exemplary implementations, and the details that have been described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and conceivable.

[0138] FIG16 is a structural block diagram of a chip packaging device according to an embodiment of the present disclosure. As shown in FIG16 , the device includes:

[0139] A first processing unit 1602 is configured to perform a plastic encapsulation process on the first chip and the silicon wafer to obtain a first plastic encapsulation body, wherein the silicon wafer has a through silicon via (TSV), at least one end of the TSV is connected to a pad, and the pads of the first chip and the silicon wafer located on a first side of the first plastic encapsulation body are exposed to the first plastic encapsulation body;

[0140] A second processing unit 1604 is configured to solder at least one pad of the second chip to a pad on a first side of the first plastic package of the first chip or silicon wafer via a first soldering member, and to plastic-encapsulate the second chip and the first plastic package to obtain a second plastic package, wherein the first plastic package and the second plastic package are stacked, and the first side of the first plastic package is adjacent to the second plastic package.

[0141] The third processing unit 1606 is used to rewire the first chip and the second welding part implanted on the pad on the second side of the first plastic package to obtain a first rewiring layer, wherein the first rewiring layer is stacked on the second side of the first plastic package, and the second side of the first plastic package is the side opposite to the first side.

[0142] According to this embodiment, the first chip and the silicon wafer are plastic-sealed to obtain a first plastic-sealed body, wherein: The silicon wafer has a through-silicon via (TSV), and at least one end of the TSV is connected to a solder pad. The solder pads of the first chip and the silicon wafer located on the first side of the first plastic package are exposed to the first plastic package. At least one solder pad of the second chip is soldered to the solder pad of the first chip or the silicon wafer on the first side of the first plastic package through a first soldering piece, and the second chip and the first plastic package are plastic-sealed to obtain a second plastic package, wherein the first plastic package and the second plastic package are stacked and arranged, and the first side of the first plastic package is a side adjacent to the second plastic package. The second soldering piece planted on the solder pads of the first chip and the silicon wafer located on the second side of the first plastic package is re-wired to obtain a first re-wiring layer, wherein the first re-wiring layer is stacked and arranged on the second side of the first plastic package, and the second side of the first plastic package is a side opposite to the first side. This can solve the problems of the chip packaging method in the related art, such as the complex packaging process and high raw material supply cost caused by the need to use a substrate, simplify the chip packaging process, and reduce material costs.

[0143] Exemplarily, the above device further includes:

[0144] The mounting unit is used to mount the first chip and the silicon wafer in sequence on the first adhesive film before performing plastic packaging on the first chip and the silicon wafer, wherein the first adhesive film is laid flat on the first supporting carrier.

[0145] Exemplarily, the above device further includes:

[0146] A first covering unit is used to sequentially cover a second adhesive film and a second supporting carrier on a second side of the first plastic packaging body after the first chip and the silicon wafer are plastic-sealed, wherein the second adhesive film and the second supporting carrier are larger in size than the first plastic packaging body;

[0147] The first execution unit is used to perform a flipping operation on the first plastic package body and remove the first supporting carrier and the first adhesive film in sequence.

[0148] Exemplarily, the above device further includes:

[0149] a second covering unit, configured to sequentially cover a third adhesive film and a third supporting carrier on a side of the second plastic package body opposite to the first plastic package body before rewiring the first chip and the second soldering member planted on the solder pads of the silicon wafer on the second side of the first plastic package body;

[0150] The second execution unit is used to perform a flipping operation on the second plastic package body and remove the second supporting carrier and the second adhesive film in sequence.

[0151] Exemplarily, the above device further includes:

[0152] The fourth processing unit is used to thin the second side of the first plastic package body before rewiring the second welding parts planted on the welding pads of the first chip and the silicon wafer on the second side of the first plastic package body to expose the second welding parts planted on the welding pads of the first chip and the silicon wafer on the second side of the first plastic package body.

[0153] Exemplarily, the above device further includes:

[0154] The fifth processing unit is used to perform through-silicon via processing and pad processing on the silicon wafer before plastic-sealing the first chip and the silicon wafer to obtain a silicon wafer with through-silicon vias, wherein the size and number of the through-silicon vias on the silicon wafer match the size and number of pads of the second chip to which the silicon wafer is connected.

[0155] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0156] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0157] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0158] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0159] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0160] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0161] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0162] The foregoing is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that the present disclosure is susceptible to various modifications and variations. Any modifications, equivalent substitutions, improvements, and the like made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A packaging structure, comprising: A first plastic package body, wherein the first plastic package body encapsulates: a first chip; A silicon wafer; wherein the silicon wafer has a through silicon via, and at least one end of the through silicon via is connected to a pad; A second plastic package body stacked with the first plastic package body, wherein the second plastic package body encapsulates: a second chip; wherein at least one pad of the second chip is connected to the pad of the first chip or the silicon wafer on the first side of the first plastic package body through a first welding member, and the first side of the first plastic package body is a side adjacent to the second plastic package body; A first rewiring layer is stacked on the second side of the first plastic package, wherein the second side of the first plastic package is opposite to the first side, and the pads of the first chip and the silicon wafer on the second side are connected to the first rewiring layer through a second welding member.

2. The packaging structure according to claim 1, wherein: At least one side of the first chip has a second rewiring layer obtained by rewiring the solder bumps of the first chip, and at least one side of the second chip has a third rewiring layer obtained by rewiring the solder bumps of the second chip.

3. The packaging structure according to claim 1, wherein: The first chip and the second chip are sealed in a vertical direction.

4. The packaging structure according to claim 1, wherein: The first welding component is located in the second plastic package body, and the second welding component is located in the first plastic package body.

5. The packaging structure according to claim 1, wherein: The first welding member is at least one of the following: a solder ball, a solder column; the second welding member is at least one of the following: a solder ball, a solder column.

6. The packaging structure according to claim 1, wherein: The first chip is a dedicated integrated chip or a logic integrated circuit chip.

7. The packaging structure according to claim 1, wherein: The number of the second chips is two, one of the second chips is at least one of the following: a memory chip, a NAND flash memory chip, an integrated circuit chip, a radio frequency chip, and the other second chip is at least one of the following: a memory chip, a broadband input and output dynamic random access memory chip.

8. The packaging structure according to claim 1, wherein: The size and number of the through silicon vias on the silicon wafer match the size and number of the pads of the second chip connected to the silicon wafer.

9. The packaging structure according to claim 1, wherein: There are multiple silicon wafers, and at least two of the silicon wafers have different sizes and numbers of through silicon vias.

10. The packaging structure according to any one of claims 1 to 9, wherein: A third welding member is welded on the first redistribution layer, and the third welding member is at least one of the following: a solder ball, a solder column.

11. A chip packaging method, comprising: Performing plastic encapsulation on the first chip and the silicon wafer to obtain a first plastic encapsulation body, wherein the silicon wafer has a through silicon via, at least one end of the through silicon via is connected to a pad, and the pads of the first chip and the silicon wafer located on a first side of the first plastic encapsulation body are exposed to the first plastic encapsulation body; Welding at least one pad of the second chip to the pad of the first chip or the silicon wafer on the first side of the first plastic package body through a first welding member, and plastic-sealing the second chip and the first plastic package body to obtain a second plastic package body, wherein the first plastic package body and the second plastic package body are stacked, and the first side of the first plastic package body is a side adjacent to the second plastic package body; The first chip and the second welding part implanted on the pad of the silicon wafer on the second side of the first plastic package are re-wired to obtain a first re-wiring layer, wherein the first re-wiring layer is stacked on the second side of the first plastic package, and the second side of the first plastic package is the side opposite to the first side.

12. The method according to claim 11, wherein: Before the first chip and the silicon wafer are plastic-sealed, the method further includes: The first chip and the silicon wafer are sequentially mounted on a first adhesive film, wherein the first adhesive film is laid flat on a first supporting carrier.

13. The method according to claim 12, wherein: After the first chip and the silicon wafer are plastic-sealed, the method further includes: A second adhesive film and a second supporting carrier are sequentially covered on the second side of the first plastic packaging body, wherein the sizes of the second adhesive film and the second supporting carrier are larger than the size of the first plastic packaging body; The first plastic package body is turned over, and the first supporting carrier and the first adhesive film are removed in sequence.

14. The method according to claim 13, wherein: Before rewiring the first chip and the second soldering member planted on the pad of the silicon wafer on the second side of the first plastic package, the method further includes: Sequentially covering a third adhesive film and a third supporting carrier on a side of the second plastic packaging body opposite to the first plastic packaging body; The second plastic package body is turned over, and the second supporting carrier and the second adhesive film are removed in sequence.

15. The method according to claim 11, wherein: Before rewiring the first chip and the second soldering member planted on the pad of the silicon wafer on the second side of the first plastic package, the method further includes: The second side of the first plastic package is thinned to expose the first chip and the second welding member implanted on the pad of the silicon wafer located on the second side of the first plastic package.

16. The method according to any one of claims 11 to 15, wherein: Before the first chip and the silicon wafer are plastic-sealed, the method further includes: The silicon wafer is subjected to through silicon via processing and pad processing to obtain the silicon wafer having the through silicon via, wherein the size and number of the through silicon vias on the silicon wafer match the size and number of the pads of the second chip connected to the silicon wafer.

Images