Storage array

Abstract

The present disclosure provides a storage array, comprising storage units distributed in a matrix array, wherein each storage unit comprises two memories, and one P-channel field effect transistor and two N-channel field effect transistors which are alternately connected; the source electrode of the P-channel field effect transistor is connected to the drain electrode of each N-channel field effect transistor; the drain electrode of the P-channel field effect transistor is connected to the source electrode of the N-channel field effect transistor; the two memories are respectively connected to the source electrode of the P-channel field effect transistor and the source electrode of the N-channel field effect transistor. Use of the present invention can improve the density of the storage array and reduce the requirements for the driving capability of field effect transistors.

Description

A storage array

[0001] This application claims priority to a patent application filed on June 25, 2023, entitled “A Storage Array” and having application number 202310736845.6. Technical Field

[0002] The present disclosure relates to the technical field of semiconductors and CMOS hybrid integrated circuits, and in particular to a RRAM storage array circuit using CMOS. Background Art

[0003] With the continuous development of artificial intelligence and deep learning technologies, artificial neural networks have been widely used in fields such as natural language processing, image recognition, autonomous driving, and graph neural networks. However, the increasing size of networks has led to a significant consumption of energy in the transfer of data between memory and traditional computing devices such as CPUs and GPUs, which is known as the von Neumann bottleneck. The most important calculation in artificial neural network algorithms is vector-matrix multiplication. Compute-in-memory (Compute-In-Memory) based on non-volatile memory (NVM) stores weights in non-volatile memory cells and performs simulated vector-matrix multiplication calculations in the array, avoiding the frequent transfer of data between memory and computing units. This is considered a promising approach to resolving the von Neumann bottleneck.

[0004] Currently, non-volatile memory devices such as RRAM, PCRAM, MRAM, FeRAM, and FeFET store weights as their conductance values ​​after they are written. These devices are organized into arrays, with a voltage input at one end serving as the input for a vector-matrix multiplication. The array is then calculated using Ohm's law and Kirchhoff's laws. The resulting current at the other end is the sum of the vector-matrix multiplication, typically read out using an analog-to-digital converter (ADC).

[0005] Among the various new types of non-volatile memories mentioned above, two-terminal non-volatile memories have attracted widespread attention and research due to their higher theoretical density and reduced process costs brought about by their simple structure. In practical applications, two-terminal memories need to form a storage array to achieve high-density structure and high-speed reading and writing. The current existing methods mainly use a 1-transistor-1 memory (1T1R) array, and the transistors in the mainstream method are usually N-type. However, in actual use, on the one hand, due to the low power supply Vdd at advanced nodes, the maximum gate voltage that can be applied to the transistor is limited. On the other hand, when the N-type transistor has a source resistor, the non-zero source voltage will further reduce the gate-source voltage of the transistor. Therefore, there is a problem of insufficient drive current during the operation of two-terminal memories at advanced nodes, which limits the further reduction of device size and the improvement of storage array density.

[0006] Summary of the Invention

[0007] In view of the above problems, the purpose of the present disclosure is to provide a memory array to solve the problems existing in existing memory circuits, such as voltage limitation, resulting in insufficient driving current, and restricting the miniaturization of devices and the improvement of memory array density.

[0008] The memory array provided by the present disclosure includes memory cells distributed in a matrix array, and the memory cells include two memories and a P-channel field-effect transistor and two N-channel field-effect transistors that are alternately connected; wherein the source of the P-channel field-effect transistor is connected to the drain of the N-channel field-effect transistor; the drain of the P-channel field-effect transistor is connected to the source of the N-channel field-effect transistor; and the two memories are respectively connected to the source of the P-channel field-effect transistor and the source of the N-channel field-effect transistor.

[0009] In addition, an optional technical solution is that the storage unit includes a first N-channel field effect transistor, a first P-channel field effect transistor and a second N-channel field effect transistor connected in sequence; wherein the gates of the first N-channel field effect transistor, the second N-channel field effect transistor and the first P-channel field effect transistor are respectively connected to different word lines; and the source of the first N-channel field effect transistor and the source of the second N-channel field effect transistor are respectively connected to different source lines.

[0010] In addition, an optional technical solution is that the source line is connected to the positive voltage VDD, and the saturation current of the first P-channel field effect transistor is expressed as:

[0011] Among them, V sg =V s <VDD, and V tp represents the intrinsic parameter of the first P-channel field effect transistor, V sgrepresents the source-gate voltage of the first P-channel field effect transistor, V s represents the source voltage of the first P-channel field effect transistor.

[0012] In addition, an optional technical solution is that the memory includes a first memory and a second memory, wherein the first memory is connected to the source of the first P-channel field effect transistor, and the second memory is connected to the source of the second N-channel field effect transistor.

[0013] In addition, an optional technical solution is to include M×N memory cells, where M represents the number of rows, N represents the number of columns, and the word lines include a word line N connected to the gate of the N-channel field-effect transistor, and a word line P connected to the gate of the P-channel field-effect transistor; wherein the word line N and the bit line of the memory cells located in the same row are shared, and the word line P and the source line of the memory cells located in the same column are shared.

[0014] In addition, the optional technical solution includes a save mode, a write 1 mode, a write 0 mode and a read mode; wherein, in the save mode, each storage unit does not work and saves its own original data; in the write 1 mode and the write 0 mode, the designated storage unit is in a state representing 1 and 0 respectively, and the voltage of the designated storage unit is less than the preset voltage VDD; in the read mode, the source line of the storage unit is connected to the read voltage, so that the read current passes through the storage unit to the bit line, and the corresponding state of the storage unit is read from the bit line.

[0015] In addition, an optional technical solution is that in the storage mode, all word lines N, bit lines and source lines are connected to GND, and the word line P is connected to the preset voltage VDD; the P-channel field effect transistor and the N-channel field effect transistor are both in the off state.

[0016] In addition, an optional technical solution is that in write 1 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, the target bit line of the target memory cell is connected to GND, and the remaining bit lines are connected to the write 1 voltage, and the target memory cell is written to state 1.

[0017] In addition, an optional technical solution is that, in write 0 mode, word line N is connected to a preset voltage VDD, and word line P and source line are connected to GND; after the target memory cell is selected, the bit line of the target memory cell is connected to a preset write 0 voltage, and the source lines of the remaining memory cells are connected to a preset write 0 voltage, and the write current flows from the bit line through the target memory cell to the source line, and the target memory cell is written to state 0.

[0018] In addition, an optional technical solution is that in read mode, the word line N is connected to the preset voltage VDD and the source line is connected to the read voltage; after the target memory cell is selected, the read current flows through the target memory cell to the bit line via the source line, and the corresponding state of the memory cell is read from the bit line.

[0019] Utilizing the above-mentioned memory array, the memory cell includes two memories and one P-channel field-effect transistor and two N-channel field-effect transistors that are alternately connected; wherein the source of the P-channel field-effect transistor is connected to the drain of the N-channel field-effect transistor; and the drain of the P-channel field-effect transistor is connected to the source of the N-channel field-effect transistor. This can increase the driving capability of the circuit when the input is at a high level, thereby alleviating driving problems and facilitating further improvement of the density of the memory array.

[0020] To achieve the above and related purposes, one or more aspects of the present disclosure include features that will be described in detail later. The following description and the accompanying drawings describe certain exemplary aspects of the present disclosure in detail. However, these aspects indicate only some of the various ways in which the principles of the present disclosure can be used. In addition, the present disclosure is intended to include all of these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By referring to the following description in conjunction with the accompanying drawings, and with a more complete understanding of the present disclosure, other objects and results of the present disclosure will become more apparent and easier to understand. In the accompanying drawings:

[0022] FIG1 is a schematic structural diagram of a storage unit of a storage array according to an embodiment of the present disclosure;

[0023] FIG2 is a schematic structural diagram of a matrix array of a storage array according to an embodiment of the present disclosure;

[0024] FIG3 is a schematic diagram of operating voltages of a memory array according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In the following description, for illustrative purposes, numerous specific details are set forth to provide a comprehensive understanding of one or more embodiments. However, it will be apparent that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of one or more embodiments.

[0026] The maximum gate voltage that can be applied to transistors in current N-type transistor memory arrays is limited, and when N-type transistors have source resistance, a non-zero source voltage will further reduce the gate-source voltage of the transistor. Therefore, there is a problem of insufficient driving current during the operation of two-terminal memory at advanced nodes. To solve the above problem, the present disclosure provides a memory array, wherein the memory cell includes two memories and a P-channel field-effect transistor and two N-channel field-effect transistors that are alternately connected; wherein the source of the P-channel field-effect transistor is connected to the drain of the N-channel field-effect transistor; and the drain of the P-channel field-effect transistor is connected to the source of the N-channel field-effect transistor. The memory device can be driven in parallel by two NMOS devices, thereby increasing the driving capability when the circuit input is high, alleviating the driving problem, and facilitating further improvement of the density of the memory array.

[0027] In the description of this disclosure, the line connecting the gate of the transistor is called the word line (WL), the line connecting the source of the transistor is called the source line (SL), and the line connecting one end of the device is called the bit line (BL).

[0028] To describe the memory array of the present disclosure in detail, specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0029] 1 and 2 respectively illustrate a schematic structure of a memory cell and a matrix array structure of a memory array according to an embodiment of the present disclosure.

[0030] As shown in both Figures 1 and 2, the memory array of the embodiment of the present disclosure includes memory cells distributed in a matrix array, each memory cell further including two memories and a P-channel field effect transistor (PMOS) and two N-channel field effect transistors (NMOS) alternately connected; wherein, the P-channel field effect transistor is located between the two N-channel field effect transistors, the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor; the two memories are respectively connected to the source of the P-channel field effect transistor and the source of the N-channel field effect transistor.

[0031] Specifically, in the structure described in Figure 1, the memory cell includes a first N-channel field effect transistor, a first P-channel field effect transistor, and a second N-channel field effect transistor connected in sequence; wherein the gates of the first N-channel field effect transistor, the second N-channel field effect transistor, and the first P-channel field effect transistor are respectively connected to different word lines; and the source of the first N-channel field effect transistor and the source of the second N-channel field effect transistor are respectively connected to different source lines.

[0032] Among them, the gate of the first N-channel field effect transistor is connected to the word line WL0, the gate of the first P-channel field effect transistor is connected to the word line WL1, the gate of the second N-channel field effect transistor is connected to the word line WL2, the source line includes a source line SL0 connected to the source of the first N-channel field effect transistor and a source line AL1 connected to the drain of the second N-channel field effect transistor, and the memory includes a first memory connected to the source of the P-channel field effect transistor and a second memory connected to the source of the N-channel field effect transistor, wherein the first memory is connected to the bit line BL0, and the second memory is connected to the bit line BL1.

[0033] In addition, the present disclosure is equivalent to a central PMOS connecting two 1T1R units. The conduction of the field effect transistor can be controlled by the signals on WL0, WL1, and WL2, and the operating voltage applied on SL and BL can complete the reading and writing of the memory in the storage unit.

[0034] Among them, for the PMOS as a gating device, the source line is connected to the positive voltage VDD, so that the positive voltage can be effectively transmitted. At this time, the saturation current of the first P-channel field effect transistor is expressed as:

[0035] Among them, V sg =V s <VDD, and V tp represents the intrinsic parameter of the first P-channel field effect transistor, V sg represents the source-gate voltage of the first P-channel field effect transistor, V s Represents the source voltage of the first P-channel field effect transistor. It can be seen that when PMOS transmits positive voltage, due to its V sg Affected by the voltage at the other end, the gate-source voltage drop of a PMOS device can reach VDD, while for an NMOS device, the maximum is only VDD-I*R, where I*R is typically 0.7V. In this case, the saturation current of a PMOS device will be significantly higher than that of an NMOS device of the same size. In other words, when the same current flows, the voltage drop is much smaller than that of an NMOS device.

[0036] In the memory cell shown in FIG1 , when SL0 and SL1 are both connected to a positive voltage and all field-effect transistors are turned on, it can be considered that two NMOS devices are connected in parallel to drive the device together, thereby alleviating the problem of insufficient driving capability of the original transistors and facilitating further improvement of storage density.

[0037] Figure 2 shows a typical memory array structure formed by the memory cells of Figure 1 , where WLN0, WLN1, BL0, and BL1 are shared within the same row, and WLP, SL0, and SL1 are shared within the same column. The figure illustrates the specific connection relationship between two rows and two columns. The specific memory array structure may also include M×N memory cells, where M represents the number of rows and N represents the number of columns. The word lines include a word line N connected to the gate of an N-channel field-effect transistor and a word line P connected to the gate of a P-channel field-effect transistor. Memory cells in the same row share the word line N and bit line, while memory cells in the same column share the word line P and source line.

[0038] In a specific embodiment of the present disclosure, a memory array has four operating modes, namely, a save mode, a write 1 mode, a write 0 mode, and a read mode; wherein, in the save mode, each memory cell does not work and saves its own original data; in the write 1 mode and the write 0 mode, the specified memory cell is in a state representing 1 and 0, respectively, and the voltage of the specified memory cell is less than a preset voltage VDD; in the read mode, the source line of the memory cell is connected to a read voltage, so that a read current passes through the memory cell to the bit line, and the corresponding state of the memory cell is read from the bit line.

[0039] Specifically, in the save mode, all word lines N, bit lines and source lines are connected to GND, and word line P is connected to the preset voltage VDD; P-channel field effect transistors and N-channel field effect transistors are both in the off state; in the write 1 mode, word line N is connected to the preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to the preset write 1 voltage, the target bit line of the target memory cell is connected to GND, and the remaining bit lines are connected to the write 1 voltage, and the target memory cell is written to state 1; in the write 0 mode, word line N is connected to the preset voltage VDD, and word line P is connected to GND. The preset voltage VDD, word line P and source line are connected to GND; after the target memory cell is selected, the bit line of the target memory cell is connected to the preset write 0 voltage, and the source lines of the remaining memory cells are connected to the preset write 0 voltage. The write current flows from the bit line through the target memory cell to the source line, so that the target memory cell is written to state 0; in the read mode, the word line N is connected to the preset voltage VDD, and the source line is connected to the read voltage; after the target memory cell is selected, the read current flows through the target memory cell through the source line to the bit line, and the corresponding state of the memory cell is read from the bit line.

[0040] As a specific example, FIG3 shows a schematic structure of an operating voltage of a memory array according to an embodiment of the present disclosure.

[0041] As shown in Figures 1 through 3, the memory array has four operating modes: save mode, write-1 mode, write-0 mode, and read mode. Assuming a positive voltage applied to SL causes a write-1 to the memory, while a positive voltage applied to BL causes a write-0 to the memory, VDD and GND are used to represent the high level and ground, respectively, in the circuit. Specifically, assuming the target device of the current operation is the device on the left of the (0,0) memory cell in the upper left corner of Figure 2, the operation flow is shown in Figure 3. Initially, the memory array is in an inactive, data-saving state, and then the write-1, read, and write-0 operations are performed on the designated cells.

[0042] Specifically, in the non-working state, all WLN, BL, and SL are connected to GND, and all WLP are connected to VDD. At this time, all transistors are in the off state, and the array does not work.

[0043] Write 1 mode: For the (0, 0) memory cell, WLN0 and WLN1 are connected to VDD, WLP and BL0 are connected to GND, SL0, SL1, and BL1 are connected to the write 1 corresponding voltage, and SL1 of the remaining memory cells is connected to the write 1 voltage. The other line connections are the same as the non-working state. At this time, all MOS of the (0, 0) memory cell are turned on, and the write current flows from SL0 and SL1 through the target memory to BL0. No current flows through other memories, and the target device is written to 1.

[0044] Read mode: For the (0,0) memory cell, WLN0 is connected to VDD, SL0 is connected to the read voltage, and the connection method of the other lines is the same as the non-working state. At this time, the NMOS on the left side of the (0,0) memory cell is turned on, and the read current flows from SL0 through the target memory to BL0. The corresponding state of the target device can be read from BL0.

[0045] Write 0 mode: For the (0, 0) memory cell, WLN0 and WLN1 are connected to VDD, WLP is connected to GND, SL0, SL1, and BL1 are connected to GND, BL0 is connected to the write 0 corresponding voltage, and SL0 of the other memory cells is connected to the write 0 voltage. The other line connections are consistent with the non-working state. At this time, all MOS of the (0, 0) memory cell are turned on, and the write current flows from BL0 through the target memory to SL0 and SL1. No current flows through other memories, and the target device is written to 0.

[0046] It should be noted that the present disclosure above only explains the method of operating a single storage cell in an array at a time, and only one row and one column are selected at a time. However, those with ordinary knowledge in this technical field should understand that this operation method can be easily extended to the selection of multiple rows and columns, so that read and write operations can be performed on cells in multiple rows and columns in parallel, thereby increasing the data throughput of the array.

[0047] According to the memory array disclosed above, a single memory cell includes two memories and a P-channel field-effect transistor and two N-channel field-effect transistors that are alternately connected; wherein the source of the P-channel field-effect transistor is connected to the drain of the N-channel field-effect transistor; and the drain of the P-channel field-effect transistor is connected to the source of the N-channel field-effect transistor. The memory device can be driven in parallel by two NMOS devices, thereby increasing the driving capability when the circuit input is at a high level, alleviating driving problems, and facilitating further improvement in the density of the memory array.

[0048] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0049] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present disclosure. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments shown herein, but is intended to be embodied in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A storage array, characterized in that: The invention comprises storage units distributed in a matrix array, wherein the storage units include two memories and a P-channel field effect transistor and two N-channel field effect transistors connected alternately; wherein, The source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; The drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor; The two memories are respectively connected to the source of the P-channel field effect transistor and the source of the N-channel field effect transistor.

2. The storage array according to claim 1, wherein: The storage unit comprises a first N-channel field effect transistor, a first P-channel field effect transistor and a second N-channel field effect transistor connected in sequence; wherein, The gates of the first N-channel field effect transistor, the second N-channel field effect transistor and the first P-channel field effect transistor are respectively connected to different word lines; A source of the first N-channel field effect transistor and a source of the second N-channel field effect transistor are respectively connected to different source lines.

3. The storage array according to claim 2, wherein: The source line is connected to a positive voltage VDD, and the saturation current of the first P-channel field effect transistor is expressed as: Among them, V sg =V s <VDD, and V tp represents the intrinsic parameter of the first P-channel field effect transistor, V sg represents the source-gate voltage of the first P-channel field effect transistor, V s represents the source voltage of the first P-channel field effect transistor.

4. The storage array as claimed in claim 2, characterized in that: The memory includes a first memory and a second memory, wherein: The first memory is connected to the source of the first P-channel field effect transistor, and the second The memory is connected to the source of the second N-channel field effect transistor.

5. The storage array as claimed in claim 2, characterized in that: The storage unit comprises M×N storage units, wherein M represents the number of rows, N represents the number of columns, and the word lines comprise a word line N connected to the gate of the N-channel field effect transistor, and a word line P connected to the gate of the P-channel field effect transistor; wherein, The memory cells in the same row share a word line N and a bit line, and the memory cells in the same column share a word line P and a source line.

6. The storage array as claimed in claim 5, characterized in that: It includes save mode, write 1 mode, write 0 mode and read mode; among them, In the saving mode, each storage unit does not work and saves its own original data; In the write 1 mode and the write 0 mode, the designated storage cell is in a state representing 1 and 0, respectively, and the voltage of the designated storage cell is less than a preset voltage VDD; In the read mode, the source line of the memory cell is connected to a read voltage, so that a read current passes through the memory cell to reach the bit line, and the corresponding state of the memory cell is read from the bit line.

7. The storage array according to claim 6, wherein: In the storage mode, all word lines N, bit lines and source lines are connected to GND, and the word line P is connected to a preset voltage VDD; The P-channel field effect transistor and the N-channel field effect transistor are both in an off state.

8. The storage array according to claim 6, wherein: In the write 1 mode, the word line N is connected to a preset voltage VDD, and the word line P is connected to GND; After the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, the target bit line of the target memory cell is connected to GND, and the remaining bit lines are connected to the write 1 voltage, and the target memory cell is written to state 1.

9. The storage array according to claim 6, wherein: In the write 0 mode, the word line N is connected to a preset voltage VDD, the word line P and the source Wire and connect to GND; After the target memory cell is selected, the bit line of the target memory cell is connected to a preset write 0 voltage, the source lines of the remaining memory cells are connected to the preset write 0 voltage, the write current flows from the bit line through the target memory cell to the source line, and the target memory cell is written to state 0.

10. The storage array according to claim 6, wherein: In the read mode, the word line N is connected to a preset voltage VDD, and the source line is connected to a read voltage; After the target memory cell is selected, a read current flows through the target memory cell to a bit line via a source line, and a corresponding state of the memory cell is read from the bit line.

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