Calculation circuit, communication device, control circuit, storage medium and calculation method

Abstract

A calculation circuit (10) is characterized by including a conversion unit (100) that divides a quantized signal other than the most significant bit, which is a sign bit, into a plurality of bit strings, converts each of the plurality of divided bit strings into a sequence of stochastic representations representing a numerical value as the ratio of ones present, and outputs the sign bit and the plurality of sequences of stochastic representations.

Description

Arithmetic circuit, communication device, control circuit, storage medium, and arithmetic method

[0001] The present disclosure relates to an arithmetic circuit, a communication device, a control circuit, a storage medium, and an arithmetic method for stochastic signal processing.

[0002] With the increase in demand for communications, there is a demand for improved frequency utilization efficiency in communication devices used in cellular systems, satellite communications, etc. To improve frequency utilization efficiency, it is desirable to not only widen the bandwidth of signal processing but also to flexibly control radio resources such as frequency, time, and power in response to changes in propagation paths, communication demand, etc. Communication devices achieve advanced and high-speed signal processing using digital devices such as ASICs (Application Specific Integrated Circuits) and FPGAs (Field Programmable Gate Arrays).

[0003] Digital devices that perform digital signal processing are susceptible to soft errors, such as inversion of bit values ​​in internal circuits, due to radiation. Satellite-mounted equipment often uses devices designed specifically for space that have enhanced soft error resistance, but these devices are inferior in terms of cost and performance to consumer devices widely used on Earth. Therefore, if the soft error resistance of consumer devices can be improved and used for space applications, it is expected that satellites will have higher performance and lower costs. Furthermore, since soft errors caused by radiation are not only a concern for satellite-mounted equipment but also for terrestrial facilities, there is a need to improve soft error resistance for mission-critical equipment.

[0004] Stochastic signal processing is a technology that is expected to improve soft error resistance. In conventional binary operations, the closer to the MSB (Most Significant Bit), the greater the numerical error due to bit inversion. However, stochastic signal processing performs operations by expressing numerical values ​​using the ratio of "0" and "1" in random numbers of sequence length N, so there is no weighting between bits and soft error resistance can be expected to improve. In addition, stochastic signal processing has the advantage of simplifying the circuit configuration for addition, multiplication, etc., and digital filters using stochastic signal processing are being studied in Non-Patent Document 1.

[0005] H. Ichihara, T. Sugino, S. Ishii, T. Iwagaki and T. Inoue, “Compact and Accurate Digital Filters Based on Stochastic Computing,” in IEEE Transactions on Emerging Topics in Computing. DOI: 10.1109 / TETC. 2016.2608825

[0006] Digital payloads, including channelizers, process signals with a bandwidth wider than the bandwidth that can be processed at the device's operating speed, requiring parallel processing according to the sequence length. Conventional stochastic signal processing can reduce the circuit size by reducing the sequence length, but there is a trade-off in that the granularity of numerical conversion becomes coarser and calculation errors increase. Generally, communication devices are required to meet a specified allowable communication performance, so the shortest sequence length that satisfies the calculation errors required for that performance is uniquely determined, making it difficult to reduce the circuit size.

[0007] The present disclosure has been made in view of the above, and aims to provide an arithmetic circuit that can improve soft error resistance while suppressing an increase in circuit size.

[0008] In order to solve the above-mentioned problems and achieve the object, the arithmetic circuit according to the present disclosure is characterized by including a conversion unit that divides all bits of a quantized signal except for the most significant bit, which is a sign bit, into multiple bit strings, converts each of the divided multiple bit strings into a sequence of probability representations that express numerical values ​​with a proportion of 1s, and outputs the sign bit and multiple sequences of probability representations.

[0009] The arithmetic circuit according to the present disclosure has the effect of being able to improve soft error resistance while suppressing an increase in circuit size.

[0010] 6 is a diagram showing an example of the configuration of an arithmetic circuit according to the first embodiment; FIG. 6 shows an example of the configuration of a conversion unit according to the first embodiment; FIG. 6 shows an example of the configuration of a multiplication unit included in the arithmetic unit; FIG. 6 shows a specific example of input 1 and input 2; FIG. 6 shows an output when the two values ​​shown in FIG. 5 are input to the conversion unit; FIG. 6 is an explanatory diagram of the processing of the multiplication unit when the series shown in FIG. 6 is input;

[0011] Hereinafter, an arithmetic circuit, a communication device, a control circuit, a storage medium, and an arithmetic method according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0012] 1 is a diagram showing an example of the configuration of an arithmetic circuit 10 according to embodiment 1. The arithmetic circuit 10 has a conversion unit 100, an arithmetic unit 200, and a reconversion unit 300.

[0013] First, we will explain the configuration and operation of the conversion unit 100. The conversion unit 100 divides an input signal, which is a quantized signal, into a most significant bit, which is a code bit, and multiple bit strings, and converts each of the multiple bit strings into a sequence of probability expressions that express numerical values ​​with a proportion of 1s.

[0014] 2 is a diagram illustrating an example configuration of a converter 100 according to the first embodiment. Here, an example configuration of the converter 100 will be described in which the converter 100 divides an input signal into the most significant bit, which is a sign bit, and two bit strings, specifically, a first bit string and a second bit string. The converter 100 includes an absolute value converter 101 and the same number of stream converters 104 as the number of bit strings to be divided by the converter 100. In this example, the converter 100 divides the input signal into two bit strings, and therefore the converter 100 includes two stream converters 104-1 and 104-2.

[0015] The input signal is assumed to be an N-bit quantized binary value. In this case, the converter 100 extracts and outputs the most significant bit as a sign bit, and the N-1 bits excluding the most significant bit are input to the absolute value converter 101. The absolute value converter 101 includes a two's complement converter 102 and a selector 103. In the absolute value converter 101, the two's complement converter 102 converts the input bits into a two's complement number and outputs it. The selector 103 selects an output based on the value of the most significant bit. Specifically, if the most significant bit is 1, i.e., the input signal has a negative value, the selector 103 outputs the binary value converted by the two's complement converter 102. If the most significant bit is 0, i.e., the input signal has a positive value, the selector 103 outputs the binary value input to the absolute value converter 101 as is.

[0016] The conversion unit 100 divides the binary value output from the absolute value conversion unit 101 into two bit strings. These two bit strings are referred to as the first bit string and the second bit string. The first bit string is input to the stream conversion unit 104-1, and the second bit string is input to the stream conversion unit 104-2. Here, the first bit string is a bit string with higher order bits than the second bit string. If the number of bits in the first bit string is M, then the number of bits in the second bit string is expressed as N-1-M.

[0017] The sequence converters 104-1 and 104-2 convert the input bit strings into data sequences for calculation by stochastic signal processing and output the data sequences. The conversion in the sequence converters 104-1 and 104-2 means converting values ​​expressed in binary to stochastic numbers in stochastic signal processing. The sequence converters 104-1 and 104-2 convert the "values ​​obtained by normalizing the binary values ​​within a range from 0 to 1" so that they approximate the "probability of a 1 occurring in the sequence." The sequence converters 104-1 and 104-2 can use a hyperuniform distribution, pseudorandom numbers, or the like as a method for generating data sequences. The sequence converters 104-1 and 104-2 may generate data sequences each time using a generating polynomial, or may store a table in advance that indicates the correspondence between input binary values ​​and output data sequences and determine the output data sequence by referencing the table. Hereinafter, the converted data sequence may be referred to as a sequence of probability representation, or simply as a sequence. Furthermore, the sequence of probability representations obtained after the first bit sequence is converted by sequence conversion unit 104-1 is referred to as the first sequence, and the sequence of probability representations obtained after the second bit sequence is converted by sequence conversion unit 104-2 is referred to as the second sequence.

[0018] FIG. 3 is a diagram showing an example of conversion in the conversion unit 100 according to the first embodiment. The input signal is assumed to be a 6-bit signed binary. The comparative example is a case in which the input signal is converted into a sequence of probability representations without being divided, which is equivalent to the number of bits M of the first bit string in this embodiment being 0. In FIG. 3, the binary "n / a" in the comparative example indicates "no assignment." In this case, the number of bits of the sequence required for numerical representation with the same precision as 5 bits, excluding the most significant bit indicating the sign, is 2. 5 -1 = 31 bits or more, and is expressed as a sequence in which the same number of 1s as the input signal (dec) are generated. Here, the number of bits of the sequence of probability representation required for numerical representation with the same precision as the j-bit bit string of binary representation is "2 j −1" and can be called the minimum sequence length. Note that the sequence of 0s and 1s in the sequence is not limited to the example in FIG. 3, and can be a sequence obtained using a hyper-uniform distribution, pseudo-random numbers, or the like, as described above.

[0019] On the other hand, when the 5-bit binary value converted to an absolute value, excluding the most significant bit which is the sign bit of the 6 bits of the input signal, is divided by M=2 bits into a first bit string of the most significant 2 bits and a second bit string of the least significant 3 bits, the conversion unit 100 converts the first sequence and the second sequence into sequences of probability representation with the same number of bits. The conversion unit 100 outputs, as the first sequence, a sequence in which 1 occurs only at a rate close to the absolute value of the most significant 2 bits, and outputs, as the second sequence, a sequence in which 1 occurs only at a rate close to the absolute value of the least significant 3 bits. In this case, the minimum sequence length when converting the most significant 2 bits into a sequence of probability representation is "2 2 -1 = 3 bits, and the minimum sequence length when converting the lower 3 bits into a sequence of probability expression is "2 3 -1 = 7 bits." In this case, in the example of FIG. 3 , whereas conventionally 6-bit binary data, including the code, would be converted to 33 bits, this is converted to a total of 17 bits, consisting of a 1-bit code, an 8-bit first sequence, and an 8-bit second sequence. Note that, since the number of bits required to represent the most significant 2 bits is 3 bits, the first sequence may be 3 bits, for a total of 12 bits. However, the first bit sequence, which is the most significant 2 bits, has a greater weight with respect to the value of the input signal than the second bit sequence, which is the least significant 3 bits. Therefore, if an error such as an error in calculation or an error due to radiation occurs, the impact on the overall value will be greater. For this reason, by expressing the first sequence using the same 8 bits as the second sequence, the possibility of a large error occurring can be reduced. Note that, although the sequence length of the first sequence and the sequence length of the second sequence are set to be the same here, this is not a limitation. It is preferable that the conversion unit 100 makes the length of the most significant bit string among the divided multiple bit strings, in this case the first bit string, the shortest among the multiple bit strings, and makes the magnitude of the difference between the sequence length of the probability representation sequence after conversion by the conversion unit 100 and the shortest sequence length the largest in the most significant sequence.

[0020] Next, the configuration and operation of the calculation unit 200 will be described. The calculation unit 200 performs probabilistic signal processing using a combinational circuit on the sequence of probability representations converted by the conversion unit 100. Here, typical applications of digital signal processing include image processing and modulation / demodulation. Digital signal processing is implemented using combinational circuits, and often uses multiplication and addition. Depending on the application of the device in which the calculation circuit 10 is installed, the calculation unit 200 can be configured using a combinational circuit that combines functions such as multiplication and addition. Here, multiplication, which is a component, will be described. In the following description, for the code, first sequence, and second sequence output from the conversion unit 100, when two values ​​are multiplied, the code of the first value will be S1, the first sequence will be U1, and the second sequence will be L1, while the code of the second value will be S2, the first sequence will be U2, and the second sequence will be L2.

[0021] If the binary values ​​of each sequence before sequence conversion are u1, l1, u2, and l2, for example, when the number of bits in the second bit sequence is 3, the first value is (u1 x 8 + l1) and the second value is (u2 x 8 + l2). When multiplying two values, for example, multiplication of values ​​(A + B) and (C + D) is (A + B) x (C + D) = AC + AD + BC + BD, and therefore, excluding the signs, the multiplication result of the above two values ​​is (u1 x u2 x 64) + (u1 x l2 x 8) + (u2 x l1 x 8) + (l1 x l2).

[0022] 4 is a diagram showing an example configuration of the multiplication unit 210 included in the calculation unit 200. Here, the two values ​​to be multiplied are referred to as input 1 and input 2. Input 1 is an example of a first value, and input 2 is an example of a second value. The multiplication unit 210 receives as input a code S1, a first series U1, and a second series L1 that are output from the conversion unit 100 when input 1 is input to the conversion unit 100, and a code S2, a first series U2, and a second series L2 that are output from the conversion unit 100 when input 2 is input to the conversion unit 100.

[0023] The multiplication unit 210 includes AND units 211-1 to 211-4, each corresponding to a combination of the first series U1 and second series L1 of input 1 and the first series U2 and second series L2 of input 2, an XOR unit 212 that calculates the exclusive OR of the code S1 of input 1 and the code S2 of input 2, shift units 213-1 to 213-4, each corresponding to the AND units 211-1 to 211-4, and a parallel addition unit 214. The AND units 211-1 to 211-4 calculate the logical product of the corresponding combinations. For example, the AND unit 211-1 is provided corresponding to the combination of the first series U1 of input 1 and the first series U2 of input 2, and calculates the logical product of the first series U1 of input 1 and the first series U2 of input 2, and outputs the result to the shift unit 213-1. AND unit 211-2 is provided corresponding to the combination of the first series U1 of input 1 and the second series L2 of input 2, and calculates the logical product of the first series U1 of input 1 and the second series L2 of input 2, and outputs the result to shift unit 213-2. AND unit 211-3 is provided corresponding to the combination of the second series L1 of input 1 and the first series U2 of input 2, and calculates the logical product of the second series L1 of input 1 and the first series U2 of input 2, and outputs the result to shift unit 213-3. AND unit 211-4 is provided corresponding to the combination of the second series L1 of input 1 and the second series L2 of input 2, and calculates the logical product of the second series L1 of input 1 and the second series L2 of input 2, and outputs the result to shift unit 213-4.

[0024] The XOR unit 212 calculates the exclusive OR of the code S1 of input 1 and the code S2 of input 2, and outputs the calculation result as a sign bit to the parallel addition unit 214. The XOR unit 212 outputs "1" if the values ​​of the codes S1 and S2 are different, and outputs "0" if the values ​​of the codes S1 and S2 are the same.

[0025] Each of shift units 213-1 to 213-4 shifts the input sequence to the left and outputs the sequence after the shift processing to parallel addition unit 214. Specifically, shift unit 213-1 performs a left shift of 2×(N-M-1) bits and outputs the sequence after the shift processing to parallel addition unit 214. Each of shift units 213-2 and 213-3 performs a left shift of N-M-1 bits and outputs the sequence after the shift processing to parallel addition unit 214. Shift unit 213-4 outputs the input sequence as is to parallel addition unit 214 without performing shift processing.

[0026] The parallel addition unit 214 adds all the sequences in parallel, adds the sign bit output by the XOR unit 212 to the parallel addition result, and outputs the result.

[0027] Next, we will explain the configuration and operation of the reconversion unit 300. The reconversion unit 300 adds a sign to each value of the sequence, calculates the sum, and then divides by the maximum value that can be expressed by the sequence, thereby reconverting the sequence expressed as a probability into the original quantized signal expressed in binary.

[0028] Here, the processing of the arithmetic circuit 10 will be described using a specific example. FIG. 5 is a diagram showing a specific example of input 1 and input 2. Input 1 is "010100" in 6-bit binary representation, and is composed of a code "0" and an absolute value "10 100", with a true value of "20". Input 2 is "101101" in 6-bit binary representation, and is composed of a code "1" and an absolute value "01 101", with a true value of "-13". When each of the two values ​​shown in FIG. 5 is input to the conversion unit 100, the converted series is shown in FIG. 6.

[0029] FIG. 6 is a diagram illustrating the output when the two values ​​shown in FIG. 5 are input to the conversion unit 100. Here, the conversion unit 100 divides the bit string, excluding the most significant bit, into the most significant 2 bits and the least significant 3 bits. For the first series U1 of input 1, the 2-bit binary value before series conversion is "10" (=2 / 3), so the conversion unit 100 outputs, as the first series U1, a series "01100111" (=5 / 8), in which 1 occurs at a rate close to 2 / 3. For the second series L1 of input 1, the 3-bit binary value before series conversion is "100" (=4 / 7), so the conversion unit 100 outputs, as the second series L1, a series "01110110" (=5 / 8), in which 1 occurs at a rate close to 4 / 7. The same applies to input 2. Here, the reason why the series representing the same value, 5 / 8, are different is because, as mentioned above, the conversion unit 100 performs conversion using a pseudo-random number sequence.

[0030] Fig. 7 is an explanatory diagram of the processing of the multiplication unit 210 when the series shown in Fig. 6 is input. For "U1 × U2", the output of the AND unit 211-1 is "00100010", and the post-shift output after the shift unit 213-1 performs a shift process to shift the output of the AND unit 211-1 left by 2 × (N-M-1) bits, that is, 6 bits, is "0 0 64 0 0 0 64 0". The outputs of AND units 211-2 and 211-3 for "U1 x L2" and "L1 x U2" are "00100011" and "00100010", respectively, and the post-shift outputs after shift units 213-2 and 213-3 perform a shift process to shift the outputs of AND units 211-2 and 211-3 left by N-M-1 bits, i.e., 3 bits, are "0 0 8 0 0 0 8 8" and "0 0 8 0 0 0 8 0". For "L1 x L2", the output of AND unit 211-4 is "00110010", and the output of shift unit 213-4 is "0 1 1 0 0 0 1 0". In this case, parallel addition section 214 outputs, as the multiplication result, a code bit "1" and a sequence "0 1 81 0 0 0 81 8" obtained by adding multiple outputs from shift sections 213-1 to 213-4 in parallel.

[0031] Here, a specific example of the processing of the reconversion unit 300 will be described assuming that the calculation unit 200 outputs the output of the multiplication unit 210 shown in Figure 7 as the calculation result. Because the calculation result is the code "1" and the sequence "0 1 81 0 0 0 81 8," the reconversion unit 300 obtains the multiplication result value "-0.264" by dividing "-171," which is the sum of each value in the sequence with a sign added, by 64 x 8 + 8 x 8 + 8 x 8 + 1 x 8 = 648, the maximum value that the sequence can represent. When the true value of input 1, "20," and the true value of input 2, "-13," are normalized within the range of 0 to 1, the true value of the multiplication result is (20 / 32) x (-13 / 32) ≈ 0.253, which confirms that this is an approximate calculation.

[0032] Although the probability representation sequence is 8 bits in this example, using a larger value would improve soft error resistance and prevent errors even when bit inversion occurs due to radiation. Furthermore, if a table showing the correspondence between input binary values ​​and data sequences is prepared in advance and the sequence converter 104 uses this table to convert the input binary values ​​into a probability representation sequence, it is possible to grasp the range of calculation errors that may occur in all multiplications based on the combinations of binary values ​​and data sequences. For example, if the binary values ​​have 64 possible values, 64 data sequences are generated, and the number of combinations when sequences are multiplied together is 64 x 64 = 4096. Therefore, errors can be suppressed by generating a sequence with a number of bits that takes into account the maximum value of calculation errors that may occur in all combinations as well as redundancy for soft error resistance.

[0033] Furthermore, in the first embodiment, an example has been described in which an input binary value is divided into a sign bit, a first sequence, and a second sequence, but it is also possible to divide the input signal other than the most significant bit into three or more multiple sequences, such as a third sequence, a fourth sequence, etc. Even in this case, the configuration of multiplication unit 210 can be realized using the same concept as above.

[0034] 8 is a flowchart for explaining the operation of the arithmetic circuit 10 according to the first embodiment. The conversion unit 100 of the arithmetic circuit 10 divides the quantized signal into a code bit, a first bit string, and a second bit string, and converts each of the first bit string and the second bit string into a sequence of probability expressions that express numerical values ​​with a proportion of 1s (step S101).

[0035] The calculation unit 200 performs stochastic signal processing using a combinational circuit on the sequence converted by the conversion unit 100 (step S102). The reconversion unit 300 adds the proportion of 1s in the multiple sequences calculated by the calculation unit 200, and reconverts them into a quantized signal (step S103).

[0036] Note that step S101 in FIG. 8 is an example of the first step of the calculation method by the calculation circuit 10, step S102 is an example of the second step of the calculation method, and step S103 is an example of the third step of the calculation method.

[0037] Next, the hardware configuration of the arithmetic circuit 10 will be described. In the arithmetic circuit 10, the conversion unit 100, the arithmetic unit 200, and the reconversion unit 300 are realized by processing circuits. The processing circuit may be a processor and memory that executes a program stored in memory, or may be dedicated hardware. The processing circuit is also called a control circuit.

[0038] FIG. 9 is a diagram illustrating a configuration example of a processing circuit 90 in which the processing circuit included in the arithmetic circuit 10 according to the first embodiment is realized by a processor 91 and a memory 92. The processing circuit 90 illustrated in FIG. 9 is a control circuit and includes a processor 91 and a memory 92. When the processing circuit 90 is configured with the processor 91 and the memory 92, each function of the processing circuit 90 is realized by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 92. In the processing circuit 90, each function is realized by the processor 91 reading and executing the program stored in the memory 92. That is, the processing circuit 90 includes the memory 92 for storing a program that results in the processing of the arithmetic circuit 10 being executed. This program can also be said to be a program that causes the arithmetic circuit 10 to execute each function realized by the processing circuit 90. This program may be provided by a storage medium on which the program is stored, or by other means such as a communication medium.

[0039] The above program can also be said to be a program that causes the arithmetic circuit 10 to execute the following steps: a conversion unit 100 divides all but the most significant bit, which is the sign bit, of the quantized signal into a plurality of bit strings, converts each of the divided plurality of bit strings into a series of probability representations that express numerical values ​​with a proportion of 1s present, and outputs the sign bit and a plurality of series of probability representations. This program can also cause the arithmetic circuit 10 to execute the following steps: a second step in which the arithmetic unit 200 calculates the series of probability representations converted in the first step by stochastic signal processing using a combinational circuit, and a third step in which the reconversion unit 300 adds the proportions of 1s present among the plurality of series after calculation in the second step, and reconverts them into a quantized signal.

[0040] Here, the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic unit, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor), etc. The memory 92 is, for example, a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable ROM), or an EEPROM (Electrically EPROM), a magnetic disk, a flexible disk, an optical disk, a compact disk, a minidisk, or a DVD (Digital Versatile Disc).

[0041] 10 is a diagram illustrating an example of a processing circuit 93 in the arithmetic circuit 10 according to the first embodiment, configured with dedicated hardware. The processing circuit 93 illustrated in FIG. 10 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof. The processing circuit may be partially implemented with dedicated hardware and partially implemented with software or firmware. In this manner, the processing circuit can achieve the above-described functions with dedicated hardware, software, firmware, or a combination thereof.

[0042] As described above, the arithmetic circuit 10 according to the first embodiment includes a conversion unit 100 that divides all bits of a quantized signal except for the most significant bit, which is a sign bit, into a plurality of bit strings, converts each of the divided plurality of bit strings into a sequence of probability representations that express numerical values ​​with a proportion of 1s present, and outputs the sign bit and a plurality of sequences of probability representations. This makes it possible to suppress an increase in circuit size while suppressing errors even when bit inversion occurs due to, for example, radiation, and to obtain an arithmetic circuit 10 that can improve soft error resistance.

[0043] Here, in order to suppress approximation errors, it is preferable that the sequence length of the probability representation sequence be equal to or greater than the minimum sequence length obtained by subtracting 1 from the jth power of 2 where j is the length of the bit sequence. In this case, the conversion unit 100 sets the length of the most significant bit sequence among the divided multiple bit sequences to the shortest among the multiple bit sequences, and sets the magnitude of the difference between the sequence length of the probability representation sequence and the minimum sequence length to the largest for the most significant sequence, thereby further suppressing errors.

[0044] The arithmetic circuit 10 may further include an arithmetic unit 200 that performs stochastic signal processing using a combinational circuit on the multiple sequences of probability representations converted by the conversion unit 100, and a reconversion unit 300 that adds up the proportion of 1s in the multiple sequences after the calculation by the arithmetic unit 200, and reconverts them into a quantized signal. The arithmetic unit 200 may be configured according to the functions required of the arithmetic circuit 10. For example, the arithmetic unit 200 may include a multiplication unit 210 that multiplies a first value and a second value indicated by the code bits and the multiple sequences of probability representations output by the conversion unit 100. The multiplication unit 210 may have, for example, an XOR unit 212 which is an exclusive OR operation unit that operates the exclusive OR of the sign bit of the first value and the sign bit of the second value; AND units 211-1 to 211-4 which are a plurality of AND operation units that are provided for each combination of a plurality of series of first values ​​and a plurality of series of second values ​​and that operate to operate the logical product of the combinations; a plurality of shift units 213-1 to 213-4 which are provided corresponding to each of the plurality of AND operation units and shift the series output by the corresponding AND operation unit; and a parallel addition unit 214 which adds in parallel the shifted series output by the plurality of shift units 213-1 to 213-4 and adds the exclusive OR to the parallel addition result as a sign bit.

[0045] Moreover, according to the first embodiment, it is possible to provide a processing circuit 90 for controlling the arithmetic circuit 10. This processing circuit 90 can cause the arithmetic circuit 10 to execute the steps of dividing the bits of the quantized signal other than the most significant bit, which is the sign bit, into a plurality of bit strings, converting each of the divided plurality of bit strings into a sequence of probability representations that expresses a numerical value with a proportion of 1s present, and outputting the sign bit and the plurality of sequences of probability representations.

[0046] Furthermore, according to the first embodiment, it is possible to provide a storage medium storing a program for controlling the arithmetic circuit 10. In this case, the program can cause the arithmetic circuit 10 to execute the steps of dividing the bits of the quantized signal other than the most significant bit, which is the sign bit, into a plurality of bit strings, converting each of the divided plurality of bit strings into a sequence of probability representations that express numerical values ​​with a proportion of 1s present, and outputting the sign bit and the plurality of sequences of probability representations.

[0047] Furthermore, according to the first embodiment, it is also possible to provide a calculation method for the calculation circuit 10. This calculation method includes a first step in which the conversion unit 100 divides all but the most significant bit, which is the sign bit, of the quantized signal into a plurality of bit sequences, converts each of the divided plurality of bit sequences into a sequence of probability representations that expresses a numerical value with a proportion of 1s present, and outputs the sign bit and a plurality of sequences of probability representations. This calculation method can further include a second step in which the calculation unit 200 calculates the sequence of probability representations converted in the first step by using a combinational circuit through stochastic signal processing, and a third step in which the reconversion unit 300 adds the proportions of 1s present among the plurality of sequences calculated in the second step, and reconverts them into a quantized signal.

[0048] Another method for reducing the circuit scale is to convert only a portion of the bit string into a sequence of probability representations and leave the remainder as binary values. However, this method does not provide the same effect of improving soft error resistance as using a sequence of probability representations for the remaining bit string, which is the binary value. For this reason, it has been necessary to improve the soft error resistance of the remaining bit string by using another method, such as by adding redundancy. In contrast, the method described in the first embodiment has the advantage that it is not necessary to take measures such as adding redundancy.

[0049] Second Embodiment In the first embodiment, the basic configuration of the arithmetic circuit 10 and the specific configuration and operation when the arithmetic unit 200 performs multiplication are described. In the second embodiment, a case where an arithmetic circuit mounted on a communication device realizes an FIR (Finite Impulse Response) filter is described.

[0050] 11 is a diagram illustrating a configuration example of a communication device 20 having an arithmetic circuit 10a according to the second embodiment. The communication device 20 includes the arithmetic circuit 10a. As described above, the arithmetic circuit 10a realizes an FIR filter. The arithmetic circuit 10a is obtained by replacing the arithmetic unit 200 of the arithmetic circuit 10 according to the first embodiment shown in FIG. 1 with an arithmetic unit 200a. The specific configuration and operation of the arithmetic unit 200a included in the arithmetic circuit 10a that realizes the FIR filter will be described below.

[0051] FIG. 12 illustrates a configuration example of an arithmetic unit 200a included in an arithmetic circuit 10a that implements an FIR filter according to the second embodiment. The arithmetic unit 200a includes a delay register unit 270, a shift register unit 280, and a product-sum operation unit 290. A typical FIR filter performs a convolution operation on each of the I-channel and Q-channel baseband signals delayed by a shift register by performing a product-sum operation using tap coefficients. FIG. 12 illustrates a configuration example of an arithmetic unit 200a that implements a half-band filter, which is a type of FIR filter. In a half-band filter, every other tap coefficient becomes 0 from the center tap, so no operation is required at the tap coefficients that become 0. Therefore, the arithmetic unit 200a only needs to delay the I-channel baseband signal by the center tap using the delay register unit 270. The arithmetic unit 200a performs convolution on the Q-channel baseband signal using the shift register unit 280 and the product-sum operation unit 290. The Ich signal and Qch signal of the baseband signal are expressed in three types: code, first series, and second series, so that the input signal passes through the conversion unit 100 of the arithmetic circuit 10a and the output signal passes through the reconversion unit 300 of the arithmetic circuit 10a. In the following description, Ich may be referred to as the I channel, and Qch may be referred to as the Q channel.

[0052] 13 is a diagram illustrating a configuration example of a delay register unit 270 included in the arithmetic unit 200a of the arithmetic circuit 10a according to the second embodiment. The delay register unit 270 delays the code, first sequence, and second sequence of the I-channel baseband signal by a plurality of delay elements 271 until the timing of the center tap is reached. The delay elements 271 are, for example, flip-flops. In this way, the delay register unit 270 delays the code, first sequence, and second sequence output by the conversion unit 100 for the I-channel signal of the baseband signal.

[0053] 14 is a diagram illustrating an example of the configuration of a shift register unit 280 included in the arithmetic unit 200a of the arithmetic circuit 10a according to the second embodiment. The shift register unit 280 is based on the same basic concept as a general shift register, with multiple delay elements 281 connected in cascade and sequentially shifting the code, first sequence, and second sequence of the Q channel of the baseband signal to simultaneously output n pieces of time-shifted data. Here, n corresponds to the number of taps of the FIR filter. In this way, the shift register unit 280 outputs the code, first sequence, and second sequence of the Q channel signal of the baseband signal, as well as the code, first sequence, and second sequence with different delay amounts for the Q channel signal of the baseband signal.

[0054] 15 is a diagram showing an example of the configuration of a product-sum calculation unit 290 included in the calculation unit 200a of the arithmetic circuit 10a according to the second embodiment. The product-sum calculation unit 290 includes a plurality of multiplication units 291-1 to 291-n, a parallel addition unit 292, a serial addition unit 293, and a conversion unit 294. Hereinafter, when there is no need to distinguish between the multiplication units 291-1 to 291-n, they may be simply referred to as multiplication units 291.

[0055] The product-sum operation unit 290 receives n inputs R(1) to R(n) output from the shift register unit 280. Each of the inputs R(1) to R(n) includes a Qch code, a first sequence, and a second sequence. The product-sum operation unit 290 performs a product-sum operation on the n Qch codes, the first sequence, and the second sequence output from the shift register unit 280, and the tap coefficients. Here, since the half-band filter has symmetrical tap coefficients, the first input R(1) and the nth input R(n) can be multiplied by the same tap coefficient. Therefore, the input R(1) sequence is multiplied by the tap coefficient TAP(1) sequence, and the input R(n) sequence is multiplied by the tap coefficient TAP(1) sequence. Similarly, the product-sum operation unit 290 performs an operation on a pair of two shift register outputs that are symmetrically positioned around the center tap. Each of the tap coefficients TAP(1) to TAP(k) includes a code, a first sequence, and a second sequence, similar to the inputs R(1) to R(n).

[0056] Each of the multiple multipliers 291 is provided corresponding to one of the inputs R(1) to R(n). Each of the sequences of TAP(1) to TAP(k) is input to a set of multipliers 291. For example, the sequence of TAP(1) is input to a set of multipliers 291-1 and 291-n corresponding to the inputs R(1) and R(n). The sequence of TAP(2) is input to a set of multipliers 291-2 and 291-(n-1) corresponding to the inputs R(2) and R(n-1). This allows the product-sum calculation unit 290 to perform calculations on a set of two shift register outputs that are symmetrically positioned with respect to the center tap using a common tap coefficient.

[0057] The parallel addition unit 292 adds the multiplication results output by each of the multiplication units 291-1 to 291-n for each sequence element, and outputs the parallel addition result to the serial addition unit 293. The serial addition unit 293 adds each element in the sequence of the parallel addition result. Note that if other signal processing is performed downstream of the FIR filter, the product-sum operation unit 290 converts the binary output from the serial addition unit 293 again into a code, a first sequence, and a second sequence in the conversion unit 294.

[0058] The detailed configuration of multiplication units 291-1 to 291-n can be the same as the configuration of multiplication unit 210 shown in Fig. 4. Here, when the tap coefficients are fixed values, some tap coefficients may have small values ​​and the first sequence of the Qch signal may be 0. In this case, the configuration of multiplication unit 291 can be reduced compared to that shown in Fig. 4.

[0059] FIG. 16 is a diagram illustrating an example of the configuration of the multiplication unit 291 shown in FIG. 15. FIG. 16 illustrates the configuration of the multiplication unit 291 when the first series of tap coefficients is 0 and the code is a fixed, positive value. In this case, the multiplication unit 291 includes AND units 211-2 and 211-4, shift units 213-2 and 213-4, and a parallel addition unit 214. Because the code is a fixed, positive value, the multiplication unit 291 omits the XOR unit 212. When the code is a fixed, negative value, this can be achieved by inverting the Qch code S1 using a NOT circuit. Furthermore, when the tap coefficients are powers of 2 or ±1, the multiplication unit 291 can be realized using a bit shift or a NOT circuit.

[0060] Here, the method for dividing bits other than the most significant bit into the first bit sequence and the second bit sequence in the conversion unit 100 of the arithmetic circuit 10a can be determined based on a trade-off between the circuit size of the arithmetic circuit 10a or the communication device 20 in which the arithmetic circuit 10a is installed, the allowable calculation error, and error tolerance. For example, the designer of the arithmetic circuit 10a can evaluate, by simulation or the like, the number of bits M of the first bit sequence required to keep the calculation error within the allowable value, and adopt the case that results in the smallest circuit size. Furthermore, if the shift register output is input 1 and the tap coefficients are input 2, the designer of the arithmetic circuit 10a can evaluate, by simulation or the like, the allocation of the most significant bits of the shift register output (input 1) and the tap coefficients (input 2), since there is a similar trade-off relationship, and adopt the case that results in the smallest circuit size. In this way, when the conversion unit 100 divides all but the most significant bit of the quantized signal into the first bit sequence and the second bit sequence, the number of bits of the first bit sequence and the second bit sequence is determined based on the circuit size of the arithmetic circuits 10, 10a, the arithmetic error allowable in the arithmetic circuits 10, 10a, and the error tolerance of the arithmetic circuits 10, 10a.

[0061] In addition, in the second embodiment, a half-band filter has been described as a specific example of the FIR filter realized by the arithmetic circuit 10a, but the filter configuration is not limited to this. The arithmetic circuit 10a can achieve the same effects as in this embodiment even if its configuration is changed to various filters that can be realized by digital signal processing.

[0062] As described above, according to the second embodiment, it is possible to provide an arithmetic circuit 10a that realizes a filter included in the communication device 20. Like the arithmetic circuit 10, the arithmetic circuit 10a includes a conversion unit 100, an arithmetic unit 200a, and a reconversion unit 300. The arithmetic unit 200a can include a delay register unit 270 that delays the code bits and each of the multiple series output by the conversion unit 100 for the I-channel signal of the baseband signal, a shift register unit 280 that delays the code bits and each of the multiple series output by the conversion unit 100 for the Q-channel signal of the baseband signal and outputs the multiple code bits and series with different delay amounts for the Q-channel signal of the baseband signal, and a product-sum operation unit 290 that performs a product-sum operation on the multiple code bits and series with different delay amounts output from the shift register unit 280. As a result, in the calculation circuit 10a that realizes the filter of the communication device 20, all but the most significant bit of the quantized signal is divided into multiple bit strings, and each of the multiple bit strings is converted into a series of probability representations, and then calculations are performed in the calculation unit 200a.As a result, similar to the calculation circuit 10, it is possible to achieve the effect of improving soft error resistance while suppressing an increase in circuit size.

[0063] The shift register unit 280 has a plurality of delay elements 281, the same number as the number of taps of the cascaded filter, and by sequentially shifting each of the code bits and multiple sequences output by the conversion unit 100 for the Q-channel signal between the delay elements 281, it is possible to simultaneously output a plurality of code bits and sequences with different delay amounts, the same number as the number n of taps of the filter.

[0064] The filter realized by the arithmetic circuit 10 a can be a half-band filter. In this case, the product-sum operation unit 290 performs an operation on a set of code bits and sequences output from the shift register unit 280 that have the same corresponding tap coefficients of the half-band filter.

[0065] Furthermore, according to the second embodiment, it is also possible to provide a communication device 20 having a filter realized by the arithmetic circuit 10a.

[0066] Furthermore, according to the second embodiment, it is possible to provide a calculation method in the calculation circuit 10a that realizes a filter included in the communication device 20. This calculation method includes the first step, second step, and third step described in the first embodiment, in which in the second step, the calculation unit 200a delays each of the code bits and multiple sequences output by the conversion unit 100 for the I-channel signal of the baseband signal, delays each of the code bits and multiple sequences output by the conversion unit 100 for the Q-channel signal of the baseband signal, outputs multiple code bits and sequences with different delay amounts for the Q-channel signal of the baseband signal, and performs a product-sum operation on the multiple code bits and sequences with different delay amounts. In this calculation method, the filter is a half-band filter, and in the second step, the calculation unit 200a performs a calculation on a set of multiple code bits and sequences with different delay amounts that have the same corresponding tap coefficients of the half-band filter.

[0067] The configurations shown in the above embodiments are merely examples, and may be combined with other known technologies, or different embodiments may be combined with each other. It is also possible to omit or modify parts of the configurations as long as they do not deviate from the gist of the invention.

[0068] 10, 10a Arithmetic circuit, 20 Communication device, 90, 93 Processing circuit, 91 Processor, 92 Memory, 100, 294 Conversion unit, 101 Absolute value conversion unit, 102 2's complement conversion unit, 103 Selector, 104-1, 104-2 Series conversion unit, 200, 200a Arithmetic unit, 210, 291, 291-1 to 291-n Multiplication unit, 211-1 to 211-4 AND unit, 212 XOR unit, 213-1 to 213-4 Shift unit, 214, 292 Parallel addition unit, 270 Delay register unit, 271, 281 Delay element, 280 Shift register unit, 290 Product-sum calculation unit, 293 Serial addition unit, 300 Reconversion unit.

Claims

1. An arithmetic circuit comprising: a conversion unit that divides all bits of a quantized signal except for the most significant bit, which is the code bit, into multiple bit strings, converts each of the divided multiple bit strings into a sequence of probability representations that express numerical values ​​with a proportion of 1s, and outputs the code bit and the multiple sequences of probability representations.

2. The arithmetic circuit according to claim 1, characterized in that the sequence length of the probability expression is equal to or greater than the minimum sequence length of the value obtained by subtracting 1 from the jth power of 2 where j is the length of the bit string.

3. The arithmetic circuit described in claim 2, characterized in that the conversion unit makes the length of the most significant bit string among the multiple divided bit strings the shortest among the multiple bit strings, and makes the magnitude of the difference between the sequence length of the sequence of the probability representation and the shortest sequence length the largest in the most significant sequence.

4. The arithmetic circuit according to any one of claims 1 to 3, further comprising: a calculation unit that uses a combinational circuit to perform probabilistic signal processing on the multiple sequences of probability representation converted by the conversion unit; and a reconversion unit that adds up the proportion of sequences containing 1 among the multiple sequences after the calculation by the calculation unit, and reconverts them into a quantized signal.

5. The arithmetic circuit according to claim 4, characterized in that the arithmetic unit has a multiplication unit that multiplies a first value and a second value indicated by the code bit output by the conversion unit and the multiple sequences of probability representation.

6. The arithmetic circuit according to claim 5, characterized in that the multiplication unit comprises: an exclusive OR operation unit which operates an exclusive OR between the sign bit of the first value and the sign bit of the second value; a plurality of AND operation units which are provided for each combination of each of the plurality of sequences of the first value and each of the plurality of sequences of the second value and which operate a logical AND of the combinations; a plurality of shift units which are provided corresponding to each of the plurality of AND operation units and which shift the sequence output by the corresponding AND operation unit; and a parallel addition unit which adds in parallel the shifted sequences output by the plurality of shift units and adds the exclusive OR to a result of the parallel addition as a sign bit.

7. The arithmetic circuit according to claim 4, wherein the arithmetic unit in an arithmetic circuit realizing a filter equipped in a communications device comprises: a delay register unit which delays the code bit and each of the multiple series output by the conversion unit for an I channel signal of a baseband signal; a shift register unit which delays the code bit and each of the multiple series output by the conversion unit for a Q channel signal of the baseband signal, and outputs the multiple code bits and the series with different delay amounts for the Q channel signal of the baseband signal; and a product-sum operation unit which performs a product-sum operation on the multiple code bits and the series with different delay amounts output from the shift register unit.

8. The arithmetic circuit according to claim 7, characterized in that the shift register unit has a plurality of delay elements, the number of which is equal to the number of taps of the filter connected in cascade, and by sequentially shifting the code bit and each of the plurality of sequences output by the conversion unit for the Q channel signal between the delay elements, a plurality of the code bits and the sequences with different delay amounts, the same number as the number of taps, are simultaneously output.

9. The arithmetic circuit according to claim 7, wherein the filter is a half-band filter, and the product-sum calculation unit performs a calculation on the code bits and the series output from the shift register unit that have the same corresponding tap coefficients of the half-band filter as a set.

10. A communication device comprising a filter realized by an arithmetic circuit according to any one of claims 7 to 9.

11. A control circuit for controlling an arithmetic circuit, comprising the steps of: dividing all bits of a quantized signal except for the most significant bit, which is the code bit, into a plurality of bit strings; converting each of the divided plurality of bit strings into a sequence of probability expressions expressing numerical values ​​with a proportion of 1s; and outputting the code bit and the plurality of sequences of probability expressions.

12. A storage medium storing a program for controlling an arithmetic circuit, the program causing the arithmetic circuit to execute the steps of: dividing all bits of a quantized signal except for the most significant bit, which is the code bit, into multiple bit strings; converting each of the multiple bit strings into a sequence of probability expressions expressing numerical values ​​with a proportion of 1s; and outputting the code bit and the multiple sequences of probability expressions.

13. A calculation method in a calculation circuit, comprising: a first step in which a conversion unit divides all bits of a quantized signal except for the most significant bit, which is a sign bit, into a plurality of bit strings, converts each of the divided plurality of bit strings into a sequence of probability representations expressing numerical values ​​with a proportion of 1s, and outputs the sign bit and the plurality of sequences of probability representations.

14. The method of claim 13, further comprising: a second step in which a calculation unit calculates the sequence of probability representations converted in the first step by probabilistic signal processing using a combinational circuit; and a third step in which a reconversion unit adds up the proportion of 1s present in the multiple sequences calculated in the second step, and reconverts the sequence into a quantized signal.

15. A calculation method according to claim 14, in which in the second step, in an arithmetic circuit realizing a filter provided in a communication device, the code bit and each of the multiple series output by the conversion unit for an I channel signal of a baseband signal are delayed, the code bit and each of the multiple series output by the conversion unit for a Q channel signal of the baseband signal are delayed, the multiple code bits and the series with different delay amounts are output for the Q channel signal of the baseband signal, and a product-sum operation is performed on the multiple code bits and the series with different delay amounts.

16. The method according to claim 15, wherein the filter is a half-band filter, and in the second step, the calculation unit performs calculations on a set of the code bits and the sequences having different delay amounts and the same corresponding tap coefficients of the half-band filter.

Images