Port bandwidth guaranteed packet switching chip and implementation method thereof

Abstract

The invention discloses a port bandwidth guaranteed packet switching chip and a method for implementing port bandwidth guarantee in the packet switching chip. A mechanism similar to a time division multiplexing in a circuit switching system is used for assigning a corresponding number of time division slices according to sizes of different port bandwidths, which causes that the bandwidth can be strictly guaranteed once a plurality of ports at different rates start data burst transmission, thereby preventing complicated dispatching mechanism and greatly reducing design difficulty. Meanwhile, configuration of the time division slices can be changed accordingly by software configuration according to combined change of port rate and port number, which greatly improves flexibility. In addition,the design method can lower requirement for sending cached data to a port, further saving space of the chip.

Description

Technical field

[0001] The present invention relates to the field of data communication, in particular to a technology for realizing port bandwidth guarantee in a packet switching chip. Background technique

[0002] The ports in the packet switching chip, such as the Ethernet port, have such characteristics. Once the message header starts to be sent, the internal scheduling unit needs to continuously schedule the remaining part of the message at the same rate as the port and transmit it to this port. Once the internal scheduling rate cannot keep up, an underflow error occurs on the port, causing a complete message to be divided into two or more messages, which are discarded when the peer device receives it.

[0003] Furthermore, when there are multiple ports with different rates, and there are multiple combinations of these ports with different rates, for example, for a packet switching chip with a switching capacity of 88Gbps, any combination of ports that can accommodate the swit...

Examples

Embodiment 1

[0037] When the port combination of the packet switching chip is configured as 48 Gigabit ports (numbered {G1, G2, G3,..., G48}) plus 4 10 Gigabit ports (numbered {X1, X2, X3, X4}), its configuration in Calendar can be as figure 2 (a) The way shown. From figure 2 As you can see in (a), there are a total of 88 entries in Calendar. Each entry is equivalent to the bandwidth of a gigabit port. Each gigabit port occupies an entry in Calendar, and a 10-Gigabit port occupies 10 in Calendar. Items. The entries occupied by the four 10 Gigabit ports {X1, X2, X3, X4} are interspersed between the entries of the gigabit ports starting from the entry G1 of the first gigabit port until the entry G40 of the 40th gigabit port. ; And from the entry G41 of the 41st Gigabit port, it is arranged continuously to the entry G48 of the 48th Gigabit port, which makes the distribution spacing of the 10 Gigabit ports in the Calendar quite different, and increases the transmission of the 10 Gigabit port...

Embodiment 2

[0040] When the chip’s port combination is configured as 8 10 Gigabit ports (numbered {X1, X2, X3, X4, X5, X6, X7, X8}), its configuration in Calendar is as follows image 3 Shown. From image 3 It can be seen that each entry in the Calendar is equivalent to the bandwidth of a 10 Gigabit port, and each 10 Gigabit port occupies an entry in the Calendar, and such a configuration makes the distribution of the 10 Gigabit ports even.

Technical field

[0001] The present invention relates to the field of data communication, in particular to a technology for realizing port bandwidth guarantee in a packet switching chip. Background technique

[0002] The ports in the packet switching chip, such as the Ethernet port, have such characteristics. Once the message header starts to be sent, the internal scheduling unit needs to continuously schedule the remaining part of the message at the same rate as the port and transmit it to this port. Once the internal scheduling rate cannot keep up, an underflow error occurs on the port, causing a complete message to be divided into two or more messages, which are discarded when the peer device receives it.

[0003] Furthermore, when there are multiple ports with different rates, and there are multiple combinations of these ports with different rates, for example, for a packet switching chip with a switching capacity of 88Gbps, any combination of ports that can accommodate the swit...

Examples

Embodiment 1

[0037] When the port combination of the packet switching chip is configured as 48 Gigabit ports (numbered {G1, G2, G3,..., G48}) plus 4 10 Gigabit ports (numbered {X1, X2, X3, X4}), its configuration in Calendar can be as figure 2 (a) The way shown. From figure 2 As you can see in (a), there are a total of 88 entries in Calendar. Each entry is equivalent to the bandwidth of a gigabit port. Each gigabit port occupies an entry in Calendar, and a 10-Gigabit port occupies 10 in Calendar. Items. The entries occupied by the four 10 Gigabit ports {X1, X2, X3, X4} are interspersed between the entries of the gigabit ports starting from the entry G1 of the first gigabit port until the entry G40 of the 40th gigabit port. ; And from the entry G41 of the 41st Gigabit port, it is arranged continuously to the entry G48 of the 48th Gigabit port, which makes the distribution spacing of the 10 Gigabit ports in the Calendar quite different, and increases the transmission of the 10 Gigabit port...

Embodiment 2

[0040] When the chip’s port combination is configured as 8 10 Gigabit ports (numbered {X1, X2, X3, X4, X5, X6, X7, X8}), its configuration in Calendar is as follows image 3 Shown. From image 3 It can be seen that each entry in the Calendar is equivalent to the bandwidth of a 10 Gigabit port, and each 10 Gigabit port occupies an entry in the Calendar, and such a configuration makes the distribution of the 10 Gigabit ports even.

Images