A display panel, a display method and a display device

Abstract

The embodiment of the present invention provides a display panel and a display method and a display device thereof, which relate to the field of display technology and solve the problem of increased cost of display devices caused by using a double-layer COF when the amount of data is large. The display panel includes: a plurality of mutually intersecting and insulated first gate lines and data lines; and a plurality of sub-pixels; a plurality of sub-pixels located in the same row are divided into m pixel groups, each of the pixel groups includes n sub-pixels, and the n sub-pixels located in the same pixel group are respectively connected to the n first gate lines one by one, and the n sub-pixels are connected to the same data line; wherein m>1, n≥2, and m and n are positive integers. It is used to reduce the number of data lines in the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display method and a display device. Background Art

[0002] At present, with the rapid development of science and technology, various display devices have gradually developed, for example, liquid crystal display devices (Liquid Crystal Display, LCD for short) and organic light-emitting diode display devices (Organic Light-Emitting Diode Display, OLED for short).

[0003] Taking OLED display devices as an example, the IC (Integrated Circuit) of OLED display devices is often bound to the OLED display panel using COF (Chip On Film). However, when the resolution of the OLED display panel reaches FHD level or above, since each sub-pixel in the same row is connected to a data line, the number of data lines is large, and a single-layer COF cannot output data above the FHD level, so a double-layer COF must be used. However, the price of a double-layer COF is three times or even higher than that of a single-layer COF, which leads to an increase in the cost of OLED display devices. Summary of the invention

[0004] The embodiments of the present invention provide a display panel and a display method thereof, and a display device, which solve the problem of increased cost of the display device caused by using a double-layer COF when the amount of data is large.

[0005] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0006] In a first aspect, a display panel is provided, comprising: a plurality of mutually intersecting and insulated first gate lines and data lines; and a plurality of sub-pixels; the plurality of sub-pixels in the same row are divided into m pixel groups, each of the pixel groups comprises n sub-pixels, the n sub-pixels in the same pixel group are respectively connected to the n first gate lines one by one, and the n sub-pixels are connected to the same data line; wherein m>1, n≥2, and m and n are positive integers.

[0007] Preferably, the pixel circuit of each sub-pixel includes a writing module, a driving module, and a light-emitting device; the writing module is respectively connected to the driving module, the first scanning signal terminal and the data voltage terminal, and is used to write the signal of the data voltage terminal into the driving module under the control of the first scanning signal terminal; the driving module is also connected to the anode and the first voltage terminal of the light-emitting device, and is used to drive the light-emitting device to emit light under the control of the first voltage terminal after the signal of the data voltage terminal is written into the driving module; the cathode of the light-emitting device is connected to the second voltage terminal; wherein the first scanning signal terminal of the pixel circuit in each sub-pixel in the same pixel group is respectively connected to n first gate lines one by one, and the data voltage terminal of the pixel circuit in each sub-pixel is connected to the same data line.

[0008] Preferably, the display panel also includes a second gate line parallel to the first gate line, and the pixel circuit of each sub-pixel also includes a compensation module; the compensation module is respectively connected to the driving module and the second scanning signal terminal, and is used to compensate for the threshold voltage of the driving transistor in the driving module under the control of the second scanning signal terminal; wherein the second scanning signal terminal of the pixel circuit in each sub-pixel in the same pixel group is connected to the same second gate line.

[0009] Preferably, the pixel circuit of each sub-pixel also includes an initialization module and a light-emitting control module; the initialization module is respectively connected to the driving module, the first signal terminal and the initial voltage terminal, and is used to initialize the driving module under the control of the first signal terminal and the initial voltage terminal; the light-emitting control module is respectively connected to the driving module, the enable signal terminal and the first voltage terminal, and the anode of the light-emitting device, and is used to control the light-emitting device to emit light under the control of the enable signal terminal and the first voltage terminal.

[0010] Preferably, the initialization module is also connected to the anode of the light-emitting device, and the initialization module is also connected to the second scanning voltage terminal or the first signal terminal, and is used to initialize the anode of the light-emitting device under the control of the second scanning signal terminal or the first signal line.

[0011] Preferably, the n sub-pixels in the same pixel group emit light of different colors.

[0012] Preferably, n sub-pixels emitting light of different colors in the same pixel group constitute a pixel unit for emitting white light.

[0013] Preferably, the n sub-pixels in the same pixel group emit light of the same color.

[0014] Preferably, when the sub-pixels located in the same row of the display panel are arranged in sequence of red sub-pixels, green sub-pixels, blue sub-pixels and green sub-pixels; one pixel group includes the red sub-pixels, the green sub-pixels, the blue sub-pixels and the green sub-pixels arranged in sequence; or, the pixel group includes a first pixel group and a second pixel group, the first pixel group includes adjacent red sub-pixels and green sub-pixels; the second pixel group includes adjacent blue sub-pixels and green sub-pixels.

[0015] In a second aspect, a display device is provided, comprising the above-mentioned display panel.

[0016] In a third aspect, a display method of the above-mentioned display panel is provided, comprising: inputting scanning signals to n first gate lines respectively connected to n sub-pixels in the same pixel group in sequence in n time periods, and the n sub-pixels are sequentially enabled; wherein, a scanning signal is input to one of the first gate lines in each time period; when one of the first gate lines receives the scanning signal, the sub-pixels connected to the first gate line are enabled, and the data line inputs data signals to the enabled sub-pixels.

[0017] Preferably, in the case where the pixel circuit of each sub-pixel includes a writing module, the sequential inputting of scanning signals to the n first gate lines respectively connected to the n sub-pixels in the same pixel group includes: in the writing stage of one frame, sequentially inputting scanning signals to the first scanning signal terminals of the pixel circuits in each sub-pixel in the same pixel group in n time periods; wherein a signal is input to one of the first scanning signal terminals in each time period; when one of the first gate lines receives a scanning signal, the sub-pixel connected to the first gate line is enabled, and the data line inputs a data signal to the enabled sub-pixel, including: when one of the first scanning signal terminals receives a scanning signal, the writing module connected to the first scanning signal terminal is enabled, and the data voltage terminal inputs a data signal to the enabled writing module.

[0018] Further preferably, in the case where the pixel circuit of each sub-pixel also includes a compensation module, the method includes: in the writing stage of one frame, inputting a scanning signal to the second scanning signal terminal of the pixel circuit in each sub-pixel in the same pixel group; when the second scanning signal terminal of the pixel circuit in each sub-pixel in the same pixel group receives the scanning signal, compensating for the threshold voltage of the driving transistor in the driving module of the pixel circuit in each sub-pixel; wherein the duration of the scanning signal input to the second scanning signal terminal is the same as the duration of the scanning signal input to n first scanning signal terminals.

[0019] The embodiments of the present invention provide a display panel and a display method thereof, and a display device, wherein n sub-pixels in each pixel group are connected one by one to n first gate lines respectively, and the n sub-pixels in each pixel group are connected to the same data line, so when the n first gate lines sequentially input scanning signals, one data line can sequentially input data signals to the n sub-pixels, and since the n sub-pixels in the same row are connected to one data line, compared with the prior art in which each sub-pixel in the same row is connected to one data line, the number of data lines is reduced, and after the number of data lines is reduced, a single-layer COF can be used, thereby reducing the cost of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of a pixel circuit provided by an embodiment of the present invention Figure 1 ;

[0023] Figure 3(a) shows Figure 2 A specific structural diagram of each module of the pixel circuit shown in FIG. Figure 1 ;

[0024] Figure 3(b) shows Figure 2 A specific structural diagram of each module of the pixel circuit shown in FIG. Figure 2 ;

[0025] Figure 4 A schematic diagram of a pixel circuit provided by an embodiment of the present invention Figure 2 ;

[0026] Figure 5 for Figure 4 A specific structural schematic diagram of each module of the pixel circuit shown;

[0027] Figure 6 A third structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0028] Figure 7(a) shows Figure 6 A specific structural diagram of each module of the pixel circuit shown in FIG. Figure 1 ;

[0029] Figure 7(b) shows Figure 6 A specific structural diagram of each module of the pixel circuit shown in FIG. Figure 2 ;

[0030] Figure 8(a) shows Figure 6 A specific structural schematic diagram of each module of the pixel circuit shown in FIG. 3;

[0031] Figure 8(b) shows Figure 6 A specific structural diagram of each module of the pixel circuit shown in FIG. Figure 4 ;

[0032] Fig. 9 For driving Figure 7(a)-Figure 8(b) The timing diagram of each signal used in the pixel circuit shown;

[0033] Fig.10 A schematic flow chart of a display method of a display panel provided by an embodiment of the present invention.

[0034] Reference numerals:

[0035] 01-pixel group; 10-sub-pixel; 20-writing module; 30-driving module; 40-light-emitting device; 50-compensation module; 60-initialization module; 70-light-emitting control module. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] An embodiment of the present invention provides a display panel, such as Figure 1 As shown, it includes: a plurality of mutually intersecting and insulated first gate lines (G1, G2, G3...G t-1 , G t ) and data lines (D1, D2, D3...D n-1 , D n ); and also includes multiple sub-pixels 10.

[0038] Multiple sub-pixels 10 located in the same row are divided into m pixel groups 01, each pixel group 01 includes n sub-pixels 10, the n sub-pixels 10 located in the same pixel group 01 are respectively connected to n first gate lines, and the n sub-pixels located in the same pixel group 01 are connected to the same data line; wherein, m>1, n≥2, m and n are positive integers.

[0039] It should be noted that, first, a plurality of sub-pixels 10 located in the same row are divided into m pixel groups 01 , and the number of the pixel groups 01 is not limited and can be any number greater than 1.

[0040] The number of pixel groups 01 divided by the multiple sub-pixels 10 in different rows may be the same or different. Since the n sub-pixels 10 in the same pixel group 01 are connected to the same data line, in order to minimize the number of data lines, it is preferred in the embodiment of the present invention that the number of pixel groups 01 divided by the multiple sub-pixels 10 in each row is the same, for example, the multiple sub-pixels 10 in each row are divided into 100 pixel groups.

[0041] Second, there is no limitation on the number of sub-pixels 10 included in each pixel group 01, and it can be 2, 3, or more than 3. Since each pixel group 01 is connected to a data line, signals are input to the n sub-pixels 10 in the pixel group 01 through the data line. If the number of sub-pixels 10 in the pixel group 01 is too large, it may affect the display. Therefore, the number of sub-pixels 10 included in each pixel group 01 should be based on not affecting the normal display of the display panel. On this basis, the number of sub-pixels 10 included in each pixel group 01 may be the same or different. In an embodiment of the present invention, preferably, the number of sub-pixels 10 included in each pixel group 01 is the same. In addition, in an embodiment of the present invention, preferably, each pixel group 01 includes n adjacent sub-pixels 10.

[0042] Third, there is no limitation on the n sub-pixels 10 in the same pixel group 01. The colors of the light emitted by the n sub-pixels 10 in the same pixel group 01 may be different; or the colors of the light emitted by the n sub-pixels 10 in the same pixel group 01 may be the same. For example, if the sub-pixels 10 in the same row are arranged in sequence of red sub-pixels (R), green sub-pixels (G), and blue sub-pixels (B), a pixel group 01 may be composed of red sub-pixels, green sub-pixels, and blue sub-pixels, or a pixel group 01 may be composed of n red sub-pixels, or a pixel group 01 may be composed of n green sub-pixels, or a pixel group 01 may be composed of n blue sub-pixels. When the colors of the light emitted by the n sub-pixels 10 in the same pixel group 01 are different, it is further preferred in the embodiment of the present invention that the n sub-pixels 10 in the same pixel group 01 that emit light of different colors constitute a pixel unit for emitting white light. For example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel constitute a pixel group 01; or, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel constitute a pixel group 01.

[0043] For a display panel whose resolution adopts a display rendering algorithm, when the sub-pixels 10 located in the same row of the display panel are arranged in sequence as red sub-pixels (R), green sub-pixels (G), blue sub-pixels (B), and green sub-pixels (G), the red sub-pixels, green sub-pixels, blue sub-pixels, and green sub-pixels arranged in sequence may constitute a pixel group 01; or the pixel group 01 may include a first pixel group and a second pixel group, the first pixel group includes adjacent red sub-pixels and green sub-pixels; the second pixel group includes adjacent blue sub-pixels and green sub-pixels.

[0044] Fourthly, the display panel provided in the embodiment of the present invention may be a liquid crystal display panel or an organic electroluminescent display panel, which is not limited thereto.

[0045] Fifth, since the n sub-pixels 10 in each pixel group 01 are connected to one data line, signals are sequentially input to the n sub-pixels 10 through one data line, thereby reducing the number of data lines. Here, when n is 2, the number of data lines is reduced by 1 / 2 compared with the prior art that each sub-pixel 10 in the same row is connected to one data line; when n is 3, the number of data lines is reduced by 2 / 3 compared with the prior art that each sub-pixel 10 in the same row is connected to one data line; when n is 4, the number of data lines is reduced by 3 / 4 compared with the prior art that each sub-pixel 10 in the same row is connected to one data line, and so on, which will not be repeated here.

[0046] Here, although each sub-pixel 10 in the pixel group 01 is connected to a first gate line, which increases the number of first gate lines, the first gate lines are connected to the gate driving circuit, not to the COF, and thus will not lead to an increase in COF cost.

[0047] An embodiment of the present invention provides a display panel, wherein n sub-pixels 10 in each pixel group 01 are respectively connected to n first gate lines, and the n sub-pixels 10 in each pixel group 01 are connected to the same data line, so when the n first gate lines sequentially input scanning signals, one data line can sequentially input data signals to the n sub-pixels 10, and since the n sub-pixels 10 in the same row are connected to one data line, compared with the prior art in which each sub-pixel 10 in the same row is connected to one data line, the number of data lines is reduced, and after the number of data lines is reduced, a single-layer COF can be used, thereby reducing the cost of the display device.

[0048] It should be noted that the embodiment of the present invention does not limit the pixel circuit of the sub-pixel 10, and it can be any pixel circuit.

[0049] Preferably, the pixel circuit of the sub-pixel 10 is as follows Figure 2As shown, it includes a writing module 20 , a driving module 30 , and a light emitting device 40 .

[0050] The writing module 20 is respectively connected to the driving module 30, the first scanning signal terminal G (i.e., the gate signal terminal for reading the data signal) and the data voltage terminal Vdata, and is used to write the signal of the data voltage terminal Vdata to the driving module 30 under the control of the first scanning signal terminal G.

[0051] The driving module 30 is also connected to the anode of the light emitting device 40 and the first voltage terminal V1, and is used to drive the light emitting device 40 to emit light under the control of the first voltage terminal V1 after the signal of the data voltage terminal Vdata is written into the driving module 30.

[0052] The cathode of the light emitting device 40 is connected to the second voltage terminal V2.

[0053] Among them, the first scanning signal terminals G of the pixel circuits in each sub-pixel 10 in the same pixel group 01 are connected to n first gate lines one by one respectively, and the data voltage terminals Vdata of the pixel circuits in each sub-pixel 10 in the same pixel group 01 are connected to the same data line.

[0054] Here, the second voltage terminal V2 may be a ground terminal.

[0055] In addition, in the same pixel group 01, since the contribution of each sub-pixel 10 to white balance and the working range are different, the time for each sub-pixel in a pixel group 01 to receive the scanning signal may also be different. For example, the time for inputting the scanning signal to the first sub-pixel is 0.2 seconds, and the time for inputting the scanning signal to the second sub-pixel is 0.5 seconds, which can be adjusted accordingly according to the display screen and display effect. The size of the data signal input from the same data line to the data voltage terminal Vdata of the pixel circuit in each sub-pixel 10 in the same pixel group 01 may be the same or different, which is related to the display screen and display effect.

[0056] Specifically, as shown in FIG. 3( a ) and FIG. 3( b ), the writing module 20 includes a first transistor T1 , a gate of the first transistor T1 is connected to the first scanning signal terminal G, a first electrode is connected to the data voltage terminal Vdata, and a second electrode is connected to the driving module 30 .

[0057] The driving module 30 is shown in Figure 3(a), and includes a driving transistor Td and a storage capacitor Cst. The gate of the driving transistor Td is connected to the first end of the storage capacitor Cst, the first electrode is connected to the first voltage terminal V1, the second electrode is connected to the anode of the light-emitting device L40, and the second end of the storage capacitor Cst is connected to the second electrode of the first transistor T1.

[0058] Alternatively, the driving module 30 is shown in Figure 3(b), including a driving transistor Td and a storage capacitor Cst, the gate of the driving transistor Td is connected to the first end of the storage capacitor Cst, the first electrode is connected to the first voltage terminal V1, the second electrode is connected to the anode of the light-emitting device L40, and the second end of the storage capacitor Cst is connected to the first voltage terminal V1.

[0059] It should be noted that the writing module 20 may also include a plurality of switch transistors connected in parallel with the first transistor T1. The above is merely an example of the writing module 20. Other structures having the same functions as the writing module 20 are not described one by one here, but they should all belong to the protection scope of the present invention. The driving module 30 may also include a plurality of driving transistors Td connected in parallel. The above is merely an example of the driving module 30. Other structures having the same functions as the driving module 30 are not described one by one here, but they should all belong to the protection scope of the present invention.

[0060] Preferably, Figure 4 As shown, the display panel also includes a second gate line parallel to the first gate line, and the pixel circuit of each sub-pixel 10 also includes a compensation module 50; the compensation module 50 is respectively connected to the driving module 30 and the second scanning signal terminal S (that is, the gate signal terminal for compensating the threshold voltage), and is used to compensate the threshold voltage of the driving transistor Td in the driving module 30 under the control of the second scanning signal terminal S; wherein the second scanning signal terminal S of the pixel circuit in each sub-pixel 10 in the same pixel group 01 is connected to the same second gate line.

[0061] Specifically, Figure 5 As shown, the compensation module 50 includes a second transistor T2, a gate of the second transistor T2 is connected to the second scanning signal terminal S, a first electrode is connected to the gate of the driving transistor Td, and a second electrode is connected to the second electrode of the driving transistor Td.

[0062] It should be noted that the compensation module 50 may also include a plurality of switch transistors connected in parallel with the second transistor T2. The above is merely an example of the compensation module 50, and other structures having the same functions as the compensation module 50 will not be described in detail here.

[0063] Preferably, Figure 6 As shown, the pixel circuit of each sub-pixel 10 further includes an initialization module 60 and a light emitting control module 70 .

[0064] The initialization module 60 is connected to the driving module 30 , the first signal terminal Reset and the initial voltage terminal Vinit respectively, and is used to initialize the driving module 30 under the control of the first signal terminal Reset and the initial voltage terminal Vinit.

[0065] The light control module 70 is respectively connected to the driving module 30, the enable signal terminal EM, the first voltage terminal V1, and the anode of the light emitting device 40, and is used to control the light emitting device 40 to emit light under the control of the enable signal terminal EM and the first voltage terminal V1.

[0066] Specifically, as shown in FIG. 7( a) and FIG. 7( b), the initialization module 60 includes a third transistor T3, a gate of the third transistor T3 is connected to the first signal terminal Reset, a first electrode is connected to the initial voltage terminal Vinit, and a second electrode is connected to the gate of the driving transistor Td.

[0067] The light-emitting control module 70 is shown in Figure 7(a), and includes a fourth transistor T4 and a fifth transistor T5. The gate of the fourth transistor T4 is connected to the enable signal terminal EM, the first electrode is connected to the first voltage terminal V1, and the second electrode is connected to the first electrode of the driving transistor Td; the gate of the fifth transistor T5 is connected to the enable signal terminal EM, the first electrode is connected to the second electrode of the driving transistor Td, and the second electrode is connected to the anode of the light-emitting device 40.

[0068] Alternatively, the light-emitting control module 70 is shown in Figure 7(b), including a fourth transistor T4 and a fifth transistor T5, the gate of the fourth transistor T4 is connected to the enable signal terminal EM, the first electrode is connected to the third voltage terminal V3, and the second electrode is connected to the second end of the storage capacitor Cst; the gate of the fifth transistor T5 is connected to the enable signal terminal EM, the first electrode is connected to the second electrode of the driving transistor Td, and the second electrode is connected to the anode of the light-emitting device 40.

[0069] Here, when the fourth transistor T4 is connected in the manner shown in FIG. 7( b), the first electrode of the fourth transistor T4 is connected to the third voltage terminal V3. The third voltage terminal V3 may be the same as or different from the first voltage terminal V1. When the third voltage terminal V3 may be different from the first voltage terminal V1, the light-emitting control module 70 is also connected to the third voltage terminal V3.

[0070] It should be noted that the initialization module 60 may also include a plurality of switch transistors connected in parallel with the third transistor T3. The above is only an example of the initialization module 60. Other structures with the same function as the initialization module 60 are not described in detail here. The light control module 70 may also include a plurality of switch transistors connected in parallel with the fourth transistor T4 and / or the fifth transistor T5. The above is only an example of the light control module 70. Other structures with the same function as the light control module 70 are not described in detail here.

[0071] Further preferably, as shown in Figure 8(a) and Figure 8(b), the initialization module 60 is also connected to the anode of the light-emitting device 40, and the initialization module 60 is also connected to the second scanning voltage terminal S or the first signal terminal Reset, and is used to initialize the anode of the light-emitting device 40 under the control of the second scanning signal terminal S or the first signal line Reset.

[0072] Specifically, the initialization module 60 further includes a sixth transistor T6, a gate of the sixth transistor T6 is connected to the second scan voltage terminal S or the first signal terminal Reset, a first electrode is connected to the initial voltage terminal Vinit, and a second electrode is connected to the anode of the light emitting device L40.

[0073] It should be noted that the initialization module 60 may also include a plurality of switch transistors connected in parallel with the sixth transistor T6. The above is merely an example of the initialization module 60, and other structures having the same functions as the initialization module 60 will not be described in detail here.

[0074] In addition, as shown in FIG. 8( b ), the initialization module 60 may further include a seventh transistor T7 , the gate of the seventh transistor T7 being connected to the first signal terminal Reset, the first electrode being connected to the third voltage terminal V3 , and the second electrode being connected to the second terminal of the storage capacitor Cst.

[0075] Based on the above, the embodiment of the present invention does not limit the type of transistors in each module, and the driving transistor Td, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be N-type transistors or P-type transistors. The following embodiments of the present invention are all described by taking the above transistors as P-type transistors as an example.

[0076] The first electrode of the transistor may be a drain electrode, and the second electrode may be a source electrode; or the first electrode may be a source electrode, and the second electrode may be a drain electrode. This is not limited in the embodiment of the present invention.

[0077] In addition, according to different conduction modes of transistors, the transistors in the above pixel circuit can be divided into enhancement-type transistors and depletion-type transistors, which are not limited in the embodiments of the present invention.

[0078] Embodiment 1

[0079] The following combination Fig. 9 The timing diagrams of the various signal terminals shown in FIG. 8( a ) provide a detailed description of the working process of the pixel circuit shown in FIG. 8( a ) within an image frame.

[0080] The above image frame includes an initialization phase t1, a data writing and compensation phase t2, and a light emitting phase t3. In addition, the embodiments of the present invention are described by taking the transistor as a p-type transistor as an example.

[0081] Specifically, in the initialization phase t1 of an image frame, the first signal terminal Reset inputs a low-level start signal, and the first scanning signal terminal G, the second scanning signal terminal S, and the enable signal terminal EM input a high-level cutoff signal. Based on this, the third transistor T3 and the sixth transistor T6 (taking the gate of the sixth transistor as an example of being connected to the first signal terminal Reset) are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the driving transistor Td are all turned off.

[0082] Among them, the third transistor T3 is turned on, the voltage of the initial voltage terminal Vinit is written to the first end of the storage capacitor Cst, and the voltage of the first voltage terminal V1 is written to the second end of the storage capacitor Cst, and the voltage across the storage capacitor Cst is initialized. Here, the voltage of the initial voltage terminal Vinit should be higher than the turn-on voltage of the driving transistor Td. After the voltage of the initial voltage terminal Vinit is written to the first end of the storage capacitor Cst, the driving transistor Td should remain in the off state. The sixth transistor T6 is turned on, and the voltage of the initial voltage terminal Vinit is written to the anode of the light-emitting device L40, and the anode of the light-emitting device L40 is initialized to improve the contrast of the display screen.

[0083] In the data writing and compensation stage t2 of an image frame, the first scanning signal terminal G in the pixel circuit of each sub-pixel 10 in the same pixel group 01 is sequentially input with a low-level start signal. Taking the same pixel group 01 including the first sub-pixel, the second sub-pixel, and the third sub-pixel as an example, the first scanning signal terminal G(n-1) in the pixel circuit of the first sub-pixel, the first scanning signal terminal G(n-2) in the pixel circuit of the second sub-pixel, and the first scanning signal terminal G(n-3) in the pixel circuit of the third sub-pixel are sequentially input with a low-level start signal. The second scanning signal terminal S is always input with a low-level start signal in the data writing and compensation stage t2, and the first signal terminal Reset and the enable signal terminal EM are input with a high-level cut-off signal. Based on this, the second transistors T2 in the pixel circuits of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all turned on, the first transistor T1 in the pixel circuit of the first sub-pixel is turned on when a low-level turn-on signal is input to the first scanning signal terminal G(n-1), and the first transistor T1 in the pixel circuit of the second sub-pixel is turned on when a low-level turn-on signal is input to the first scanning signal terminal G(n-2). At this time, the first transistor T1 in the pixel circuit of the first sub-pixel is in a cut-off state, and the first transistor T1 in the pixel circuit of the third sub-pixel is turned on when a low-level turn-on signal is input to the first scanning signal terminal G(n-3). At this time, the first transistor T1 in the pixel circuit of the second sub-pixel is in a cut-off state, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all cut off.

[0084] Among them, the first transistor T1 in the pixel circuit of the first sub-pixel is turned on, and the voltage of the data voltage terminal Vdate is written to the source of the driving transistor Td. At this time, the source voltage Vs of the driving transistor Td is equal to Vdate, and the writing of the data voltage is realized. The pixel circuit of the second sub-pixel and the pixel circuit of the third sub-pixel are similar to the pixel circuit of the first sub-pixel, and will not be repeated here.

[0085] Based on this, the storage capacitor Cst can maintain the node B at a low level, and the driving transistor Td is turned on. On this basis, under the control of the second scanning signal terminal S, the second transistor T2 is turned on. At this time, the gate voltage Vg and the drain voltage Vd of the driving transistor Td are the same, that is, Vg=Vd. At this time, Vgd=Vg-Vd=0>Vth, and Vth is negative. Therefore, the driving transistor Td is in a saturated state.

[0086] In this case, the data voltage at the data voltage terminal Vdate charges the storage capacitor Cst through the first transistor T1 and the driving transistor Td, and the storage capacitor Cst charges the gate of the driving transistor Td (i.e., point B) until the gate voltage of the driving transistor Td is Vdate+Vth. Because when the gate voltage of the driving transistor Td is Vdata+Vth, the gate-source voltage Vgs of the driving transistor Td is Vg-Vs=Vdata+Vth-Vdata=Vth, and the driving transistor Td is in the cut-off state at this time. Among them, for P-type transistors, the cut-off condition is Vgs≥Vth, and Vth is a negative value. In this way, the threshold voltage Vth of the driving transistor Td is locked to the gate of the driving transistor Td, thereby realizing compensation for the threshold voltage Vth of the driving transistor Td.

[0087] In the light-emitting stage t3 of an image frame, the enable signal terminal EM inputs a low-level start signal, the first scanning signal terminal G, the second scanning signal terminal S and the first signal terminal Reset input a high-level cut-off signal. The fourth transistor T4, the driving transistor Td and the fifth transistor T5 are turned on, and the remaining transistors are turned off.

[0088] In this case, the fourth transistor T4 is turned on, and the voltage V A =V1. Under the action of the storage capacitor Cst, the voltage at point B is maintained at V B =Vdata+Vth. At this time, the gate-source voltage of the driving transistor Vgs=Vg-Vs=V B -V A =(Vdata+Vth)-V1=Vdata+Vth-V1<Vth, Vth is a negative value, so the driving transistor Td is turned on.

[0089] Based on this, the driving current I flowing through the light emitting device L40 is:

[0090] I=K / 2×(Vgs-Vth) 2

[0091] =K / 2×(Vdata+Vth–V1-Vth) 2

[0092] =K / 2×(Vdata-V1) 2 .

[0093] Wherein, K is the current constant associated with the driving transistor Td, and is related to the process parameters and geometric dimensions of the driving transistor Td, such as the electron mobility μ, the capacitance per unit area C ox , width-to-length ratio W / L, etc.

[0094] In the prior art, the threshold voltage Vth of the driving transistor Td between different pixel units drifts, resulting in different threshold voltages Vth of each driving transistor Td. It can be seen from the above formula that the driving current I used to drive the light-emitting device L40 to emit light has nothing to do with the threshold voltage Vth of the driving transistor Td, thereby eliminating the influence of the threshold voltage Vth of the driving transistor Td on the light-emitting brightness of the light-emitting device L, and improving the uniformity of the brightness of the light-emitting device L40.

[0095] It should be noted that, in the data writing and compensation stage t2, when the pixel circuits of each sub-pixel 10 in the same pixel group 01 write the data voltage in sequence, since the second scanning signal terminal S always inputs a low-level signal, each driving transistor Td always compensates for the threshold voltage Vth in the data writing and compensation stage t2, thereby ensuring sufficient threshold voltage compensation time.

[0096] An embodiment of the present invention provides a display device, including the above-mentioned display panel.

[0097] Among them, the display device provided by the embodiments of the present invention can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images) and whether text or pictures. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0098] The embodiment of the present invention provides a display device, including the display panel as described above. The display device provided by the embodiment of the present invention has the same advantageous effects as the display panel provided by the foregoing embodiment of the present invention. Since the display panel has been described in detail in the foregoing embodiment, it will not be described again here.

[0099] An embodiment of the present invention provides a display method of the above display panel, such as Fig.10 As shown, including:

[0100] S100, input scanning signals to n first gate lines respectively connected to n sub-pixels 10 in the same pixel group 01 in sequence in n time periods, and the n sub-pixels 10 are sequentially turned on; wherein a scanning signal is input to one first gate line in each time period.

[0101] Among them, whether the data signal of the data line is input to the sub-pixel 10 is determined by the first gate line connected to each sub-pixel 10. When the first gate line connected to the sub-pixel 10 inputs the scanning signal, the sub-pixel 10 is selected and the signal on the data line can be input to the sub-pixel.

[0102] Here, the n first gate lines are sequentially input with scanning signals in n time periods, and only one first gate line is input with scanning signals in each time period. Thus, only one sub-pixel 10 is turned on in each time period.

[0103] It should be noted that in the same pixel group 01, since each sub-pixel 10 has different contributions to white balance and different working ranges, the time for each sub-pixel in a pixel group 01 to receive the scanning signal may also be different. For example, the time for inputting the scanning signal to the first sub-pixel is 0.2 seconds, and the time for inputting the scanning signal to the second sub-pixel is 0.5 seconds. This can be adjusted accordingly according to the display picture and display effect.

[0104] S101 . When a first gate line receives a scan signal, the sub-pixel 10 connected to the first gate line is turned on, and the data line inputs a data signal to the turned-on sub-pixel 10 .

[0105] Here, the data line inputs a data signal to the enabled sub-pixel 10, and the size of the input data signal is related to the display image and the display effect. The size of the data signal input to each sub-pixel 10 in the same pixel group 01 may be the same or different.

[0106] An embodiment of the present invention provides a display method for a display panel, wherein n sub-pixels 10 in each pixel group 01 are connected one by one to n first gate lines respectively, and the n sub-pixels 10 in each pixel group 01 are connected to the same data line, so when the n first gate lines sequentially input scanning signals, one data line can sequentially input data signals to the n sub-pixels 10, and since the n sub-pixels 10 in the same row are connected to one data line, compared with the prior art in which each sub-pixel 10 in the same row is connected to one data line, the number of data lines is reduced, and after the number of data lines is reduced, a single-layer COF can be used, thereby reducing the cost of the display device.

[0107] Preferably, when the pixel circuit of each sub-pixel 10 includes a writing module 20, step S100 includes: Fig. 9As shown, in the writing stage of a frame, the scanning signal is sequentially input to the first scanning signal terminal G of the pixel circuit in each sub-pixel 10 in the same pixel group in n time periods; wherein a signal is input to a first scanning signal terminal G in each time period.

[0108] Step S101 includes: when a first scanning signal terminal G receives a scanning signal, the writing module 20 connected to the first scanning signal terminal G is enabled, and the data voltage terminal Vdata inputs a data signal to the enabled writing module 20 .

[0109] It should be noted that Fig. 9 Taking a pixel group 01 including three sub-pixels 10 as an example, G(n-1), G(n-2), and G(n-3) input signals to the first scanning signal terminal G of the pixel circuit in the three sub-pixels 10 in three time periods in turn. Specifically, a signal is input to G(n-1) in the first time period, a signal is input to G(n-2) in the second time period, at which time G(n-1) is turned off and no signal is input, and a signal is input to G(n-3) in the third time period, at which time G(n-2) is turned off and no signal is input.

[0110] Here, the size of the data signal input to the data line voltage terminal Vdata of the pixel circuit in each sub-pixel 10 in the same pixel group is related to the display screen, and the size of the data signal input to each data voltage terminal Vdata is determined according to the display screen.

[0111] Further preferably, in the case where the pixel circuit of each sub-pixel 10 further includes a compensation module 50, as shown in FIG. Fig. 9 As shown, in the writing stage of a frame, a scanning signal is input to the second scanning signal terminal S of the pixel circuit in each sub-pixel 10 in the same pixel group 01; when the n second scanning signal terminals S receive the scanning signal, the threshold voltage of the driving transistor Td in the driving module 30 of the pixel circuit in each sub-pixel 10 is compensated; wherein, the duration of the scanning signal input to the second scanning signal terminal S is the same as the duration of the scanning signal input to the n first scanning signal terminals G.

[0112] Among them, since the second scanning signal terminal S of the pixel circuit in each sub-pixel 10 in the same pixel group 01 is connected to the same second gate line, the same second gate line simultaneously inputs a scanning signal to the second scanning signal terminal S of the pixel circuit in each sub-pixel 10 in the same pixel group 01 to compensate for the threshold voltage of the driving transistor Td in the driving module 30 of the pixel circuit in each sub-pixel 10.

[0113] In the embodiment of the present invention, since the duration of the second scanning signal terminal S inputting the scanning signal is the same as the duration of the n first scanning signal terminals G inputting the scanning signal, for the same pixel group 01, when the n first scanning signal terminals G receive the scanning signals in sequence, the second scanning signal terminal S is always in a state of receiving the signal, thereby ensuring that the threshold voltage compensation time is sufficient.

[0114] It should be noted that when the structures of the modules in the above pixel circuit are different, the specific driving method is as described in the above embodiment 1, which will not be described again here.

[0115] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: A plurality of first gate lines and data lines that cross each other and are insulated; and a plurality of sub-pixels; The multiple sub-pixels in the same row are divided into m pixel groups, each of the pixel groups includes n sub-pixels, the n sub-pixels in the same pixel group are connected to the n first gate lines one by one, and the n sub-pixels are connected to the same data line; Wherein, m>1, n≥2, m and n are positive integers; The display panel further includes a second gate line parallel to the first gate line, and n sub-pixels in the same pixel group are connected to the same second gate line.

2. The display panel according to claim 1, characterized in that: The pixel circuit of each sub-pixel includes a writing module, a driving module, and a light-emitting device; The writing module is connected to the driving module, the first scanning signal terminal and the data voltage terminal respectively, and is used to write the signal of the data voltage terminal into the driving module under the control of the first scanning signal terminal; The driving module is also connected to the anode of the light emitting device and the first voltage terminal, and is used to drive the light emitting device to emit light under the control of the first voltage terminal after the signal of the data voltage terminal is written into the driving module; The cathode of the light emitting device is connected to the second voltage terminal; Among them, the first scanning signal terminals of the pixel circuits in each sub-pixel in the same pixel group are respectively connected to n first gate lines one by one, and the data voltage terminals of the pixel circuits in each sub-pixel are connected to the same data line.

3. The display panel according to claim 2, characterized in that: The pixel circuit of each sub-pixel further includes a compensation module; The compensation module is connected to the driving module and the second scanning signal terminal respectively, and is used to compensate the threshold voltage of the driving transistor in the driving module under the control of the second scanning signal terminal; Wherein, the second scanning signal end of the pixel circuit in each sub-pixel in the same pixel group is connected to the same second gate line.

4. The display panel according to claim 3, characterized in that: The pixel circuit of each sub-pixel further includes an initialization module and a light emitting control module; The initialization module is connected to the driving module, the first signal terminal and the initial voltage terminal respectively, and is used to initialize the driving module under the control of the first signal terminal and the initial voltage terminal; The light-emitting control module is respectively connected to the driving module, the enable signal terminal, the first voltage terminal, and the anode of the light-emitting device, and is used to control the light-emitting device to emit light under the control of the enable signal terminal and the first voltage terminal.

5. The display panel according to claim 4, characterized in that: The initialization module is also connected to the anode of the light emitting device, and is also connected to the second scanning voltage terminal or the first signal terminal, and is used to initialize the anode of the light emitting device under the control of the second scanning signal terminal or the first signal line.

6. The display panel according to any one of claims 1 to 5, characterized in that: The n sub-pixels in the same pixel group emit light of different colors.

7. The display panel according to claim 6, characterized in that: The n sub-pixels emitting light of different colors in the same pixel group constitute a pixel unit for emitting white light.

8. The display panel according to any one of claims 1 to 5, characterized in that: The n sub-pixels in the same pixel group emit light of the same color.

9. The display panel according to any one of claims 1 to 5, characterized in that: In the case where the sub-pixels located in the same row of the display panel are arranged in the order of red sub-pixel, green sub-pixel, blue sub-pixel and green sub-pixel; One of the pixel groups includes the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the green sub-pixel arranged in sequence; Alternatively, the pixel group includes a first pixel group and a second pixel group, the first pixel group includes adjacent red sub-pixels and green sub-pixels; the second pixel group includes adjacent blue sub-pixels and green sub-pixels.

10. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-9.

11. A display method of a display panel according to any one of claims 1 to 9, characterized in that: include: Inputting scanning signals to n first gate lines respectively connected to n sub-pixels in the same pixel group in sequence in n time periods, and the n sub-pixels are sequentially switched on; wherein a scanning signal is input to one of the first gate lines in each time period; When one of the first gate lines receives a scanning signal, the sub-pixels connected to the first gate line are turned on, and the data line inputs a data signal to the turned-on sub-pixels.

12. The display method according to claim 11, characterized in that: In the case where the pixel circuit of each sub-pixel includes a writing module, sequentially inputting scanning signals to n first gate lines respectively connected to n sub-pixels in the same pixel group includes: In a writing phase of a frame, scanning signals are sequentially input to the first scanning signal terminals of the pixel circuits in each sub-pixel in the same pixel group in n time periods; wherein a signal is input to one of the first scanning signal terminals in each time period; When one of the first gate lines receives a scan signal, the sub-pixel connected to the first gate line is enabled, and the data line inputs a data signal to the enabled sub-pixel, including: when one of the first scan signal terminals receives a scan signal, the write module connected to the first scan signal terminal is enabled, and the data voltage terminal inputs a data signal to the enabled write module.

13. The display method according to claim 12, characterized in that: In the case where the pixel circuit of each sub-pixel further includes a compensation module, the method includes: In a writing phase of a frame, a scanning signal is input to a second scanning signal terminal of a pixel circuit in each sub-pixel in the same pixel group; When the second scanning signal terminal of the pixel circuit in each sub-pixel in the same pixel group receives the scanning signal, the threshold voltage of the driving transistor in the driving module of the pixel circuit in each sub-pixel is compensated; The duration of the scanning signal input to the second scanning signal terminal is the same as the duration of the scanning signals input to the n first scanning signal terminals.

Images