Electronic Devices

Abstract

The present invention provides an electronic device, the subject of which is to improve its performance. The electronic device (EA1) comprises: a substrate (CS1) having an upper surface (surface) (CSt) on which a semiconductor chip is mounted and a lower surface (back surface) (CSb) on the opposite side of the upper surface; and a frame (housing) (HS) fixed to the substrate via an adhesive material (BD1). The frame has through holes formed on one short side and the other short side in the X direction, respectively. The substrate is arranged between the through holes. A portion of the upper surface of the substrate is fixed in a manner opposite to a portion of a step surface, and the step surface is formed at a height different from that of the lower surface (HSb) of the frame. In addition, the interval (distance D1) between the portion of the step surface extending along the short side of the frame, i.e., the step surface (Hf6), and the upper surface of the substrate is larger than the interval (distance D3) between the portion of the step surface extending along the long side of the frame, i.e., the step surface (Hf5), and the upper surface of the substrate.

Description

Technical Field

[0001] The present invention relates to an electronic device (semiconductor module), and for example, to an effective technique applied to an electronic device equipped with a case covering a semiconductor component mounted on a substrate. Background Art

[0002] Japanese Patent Application Laid-Open No. 08-236667 (Patent Document 1) describes an electronic device having a plurality of semiconductor devices mounted on a wiring substrate, wherein the plurality of semiconductor devices include semiconductor chips having insulated gate bipolar transistors (IGBTs) and semiconductor chips having diodes.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 08-236667 Summary of the invention

[0006] Power conversion circuits such as inverter circuits are incorporated into power supply systems that drive air conditioners, automobiles, or various industrial equipment. As an example of the configuration of the power conversion circuit, there is an electronic device (power conversion device, semiconductor module) that has a plurality of semiconductor chips having transistors (power transistors) that function as switching elements mounted on a substrate, and these semiconductor chips are electrically connected to each other.

[0007] As a form of electronic device, there is a structure in which a plurality of semiconductor components such as semiconductor chips mounted on a substrate are connected to each other via conductive components such as wiring or wires on the substrate. In addition, there is also a structure in which a housing having a through hole for inserting screws is installed on the substrate, and the housing is screwed and fixed on the mounting substrate, etc., so that the electronic device can be fixed on the mounting substrate (hereinafter, the module having the above structure is referred to as a housing module).

[0008] As a measure to improve the performance of the housing module, i.e., the electronic device, the inventors of the present application conducted research on reducing the installation area of ​​the housing module. As a result, it was found that in the housing module, depending on the position of the hole for inserting the screw, the force of screwing is transmitted to the substrate and damages the substrate.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] An electronic device according to one embodiment includes: a substrate having a surface for mounting a semiconductor chip and a back surface opposite to the surface; and a housing fixed to the substrate via an adhesive material. The housing has a first hole formed on one short side and a second hole formed on the other short side in a first direction as a long side direction. In a top view from the back side of the substrate, the substrate is arranged between the first hole and the second hole. A portion of the surface of the substrate is fixed in a manner opposite to a portion of a step surface (which is formed at a different height from the lower surface of the housing) via the adhesive material. In addition, the interval between a portion of the step surface extending along the short side of the housing and the surface of the substrate is greater than the interval between a portion of the step surface extending along the long side of the housing and the surface of the substrate.

[0011] Effects of the Invention

[0012] According to the above-mentioned embodiment, the performance of the electronic device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a circuit diagram of a three-phase inverter circuit arranged between a DC power supply and a three-phase induction motor.

[0014] Figure 2 It is a timing chart for explaining the operation of the three-phase inverter circuit.

[0015] Figure 3 This is a circuit diagram showing the configuration of a motor circuit including an inverter circuit and a three-phase induction motor according to one embodiment.

[0016] Figure 4 It means that there is Figure 3 A top view showing the shape of the transistor on the surface side of a semiconductor chip.

[0017] Figure 5 Yes means Figure 4 A bottom view of the back side of a semiconductor chip is shown.

[0018] Figure 6 Yes means Figure 4 and Figure 5 A cross-sectional view showing an example of the structure of a transistor included in the semiconductor chip shown.

[0019] Figure 7 It means that there is Figure 3 FIG. 1 is a top view of the shape of the surface side of the semiconductor chip of the diode shown.

[0020] Figure 8 Yes means Figure 7 A bottom view of the back side of a semiconductor chip is shown.

[0021] Fig. 9 Yes means Figure 7 and Figure 8 2 is a cross-sectional view of a structural example of a diode included in the semiconductor chip shown.

[0022] Fig.10 Yes means Figure 3 A perspective view of the appearance of the electronic device shown.

[0023] Fig.11 Yes means Fig.10 A bottom view of the back side of the electronic device is shown.

[0024] Fig.12 It is along Fig.11 Cross-sectional view of line A-A.

[0025] Fig.13 Yes means Fig.11 A top view of the layout of the upper surface side of the substrate is shown.

[0026] Fig.14 It means that Fig.10 The electronic device shown is a cross-sectional view of a state in which the electronic device is bonded to a mounting substrate and then screwed and fixed.

[0027] Fig.15 is to be used as Fig.14 A cross-sectional view of the electronic device of the research example after being bonded to a mounting substrate and then screwed and fixed.

[0028] Fig.16 Yes means Fig.14 2 is an enlarged cross-sectional view of the adhesive material before deformation.

[0029] Fig.17 It means Fig.16 An enlarged cross-sectional view of the periphery of the adhesive material on the flange portion opposite to the flange portion shown.

[0030] Fig.18 Yes means Fig.11 A bottom view of the lower surface side of the frame shown.

[0031] Fig.19 It is along Fig.18 An enlarged cross-sectional view showing the periphery of the step difference surface in an enlarged manner in the cross-section taken along line AA of FIG.

[0032] Fig. 20 It is along Fig.18 The A-A line section will be Fig.19 The step surface shown is an enlarged cross-sectional view showing an enlarged view of the periphery of the step surface on the opposite side.

[0033] Fig.21 It means along the Fig.18 An enlarged cross-sectional view of the relationship between the layer difference surface and the substrate in the cross-section along the BB line.

[0034] Fig. 22 Yes means Fig.10 An explanatory diagram of the assembly process of the electronic device shown.

[0035] Fig.23 is Fig. 22 A cross-sectional view of a substrate prepared in the substrate preparation step shown.

[0036] Fig.24 It means in Fig.23 The cross-sectional view shows a state where a plurality of semiconductor chips are mounted on a substrate.

[0037] Fig.25 It means in Fig.24 A cross-sectional view of a semiconductor chip connected to a wire is shown.

[0038] Fig.26 It means in Fig.25 A cross-sectional view showing a state where a plurality of terminals are mounted on a substrate is shown.

[0039] Fig. 27 It is indicated schematically in Fig.26 A cross-sectional view showing a step of mounting a substrate on a frame.

[0040] Fig.28 It means for Fig.21 An enlarged cross-sectional view of a modified example.

[0041] Fig.29 It means for Fig.21 An enlarged cross-sectional view of another modified example.

[0042] Description of Reference Numerals

[0043] ADP Anode (Anode pad, surface electrode)

[0044] BD1 Adhesive material (glue)

[0045] BD2 Thermally Conductive Material (Thermal Grease)

[0046] BOL Screws

[0047] BP1 Base plate (mounting base plate, bottom plate)

[0048] BPt top surface (face, main surface, mounting surface)

[0049] BW wire (conductive part)

[0050] CAP Capacitor Element

[0051] CDP cathode (cathode pad, back electrode)

[0052] CP Collector (Collector pad, back electrode)

[0053] CS1 base plate

[0054] CSb lower surface (back surface, main surface, front surface)

[0055] CSe1, CSe2 edge (long edge, substrate edge)

[0056] CSe3, CSe4 edge (short edge, substrate edge)

[0057] CSt top surface (face, surface, main surface)

[0058] Css1, Css2 side (long side)

[0059] Css3, Css4 side (short side)

[0060] D1, D2, D3, D4, D5, D6, D7, P1, P2, P3, P4 Distance (interval, separation distance)

[0061] E DC Power Supply

[0062] E1, E2 potential

[0063] EA1, EA2, EA3, EAH Electronics

[0064] EF1 External force

[0065] EP emitter (emitter pad, surface electrode)

[0066] ER, NR1, NR2, NR3, NR4, PR1, PR2, PR3, PR4 semiconductor region

[0067] FLG Flange (part)

[0068] FWD diode (freewheeling diode)

[0069] GC Gate Control Circuit

[0070] GE Gate

[0071] GOX gate insulation film

[0072] GP Gate (gate pad, surface electrode)

[0073] Hf1, Hf3, Hf9, Hf10, HSb Lower surface (surface, mounting surface)

[0074] Hf2, Hf4 upper surface (surface, screw insertion surface, flange upper surface)

[0075] Hf5, Hf6, Hf7, Hf8, Hf11, Hf12, Hf13, Hf14, Hf15, Hf16 layer difference surface (surface, substrate holding surface)

[0076] HS frame (shell, housing)

[0077] HSe1, HSe2, HSe5, HSe6 Edges (long edges, frame edges)

[0078] HSe3, HSe4, HSe7, HSe8 Edges (short edges, frame edges)

[0079] HSF support part (frame)

[0080] Hsi1, Hsi2, Hsi3, Hsi4 inner side

[0081] HST cover (cover material, cover parts, cover)

[0082] HT High-side terminal (positive potential terminal)

[0083] INV inverter circuit

[0084] LD terminal

[0085] LG1, LG2, LG3 bridge arm

[0086] LT Low-side terminal (negative potential terminal)

[0087] MG Sealing material (gel-like insulating material)

[0088] MP, MPB, MPH, MPL, MPT, MPU, MPV, MPW Metal patterns (patterns formed by metal, metal films, patterns)

[0089] MPb bottom surface (back side)

[0090] MPt Upper surface (surface)

[0091] MT three-phase induction motor

[0092] PKT Containment Department (Part)

[0093] Q1 Transistor

[0094] RT rotors

[0095] SC1, SC2, SCH, SCL semiconductor chips

[0096] SCb back side (front side, lower side, main side)

[0097] SCt surface (face, top surface, main surface)

[0098] SD Conductive adhesive materials (chip bonding materials, conductive components, connecting components, bonding materials)

[0099] STG Support Table

[0100] SW1, SW2, SW3, SW4, SW5, SW6 switches

[0101] THH Through hole (hole, threaded hole, screw insertion hole)

[0102] TR Groove

[0103] TU output terminal

[0104] TV output terminal

[0105] TW Output Terminal

[0106] VL1 imaginary line (center line) DETAILED DESCRIPTION

[0107] (Description format, basic terms, and usage of this application)

[0108] In this application, the description of the implementation mode is divided into multiple parts for convenience as needed, but they are not independent of each other, regardless of the order of the description, and the parts of a single example, one part of the other part, or a part or all of the modification, etc., are not independent of each other, regardless of the order of the description. In addition, in principle, repeated descriptions of the same parts are omitted. In addition, except for the case where it is specifically stated that it is not the case, the case where it is theoretically limited to the number, and the case where it is obviously not the case from the context, the constituent elements of the implementation mode are not essential.

[0109] Similarly, in the description of the implementation methods, etc., for materials, components, etc., the phrase "X formed by A" does not exclude the inclusion of elements other than A, unless it is specifically stated otherwise or it is obvious from the context that it is not the case. For example, when talking about components, it means "X containing A as a main component". For example, the phrase "silicon component" is not limited to pure silicon, and of course includes multi-component alloys with silicon as the main component, such as SiGe (silicon germanium) alloy, and components containing other additives. In addition, the phrases such as gold plating, Cu layer, and nickel plating include not only pure metal components, but also components with gold, Cu, nickel, etc. as the main components, unless it is specifically stated otherwise.

[0110] Moreover, when referring to a specific numerical value or quantity, it may be a value exceeding or less than the specific numerical value, unless it is specifically stated otherwise, is theoretically limited to that number, or is obviously not the case from the context.

[0111] In addition, in each figure of the embodiment, the same or similar parts are denoted by the same or similar symbols or reference numerals, and the description is not repeated in principle.

[0112] In addition, in the drawings, in contrast, when the situation becomes complicated or the distinction from the void is clear, the hatching line may be omitted even for a cross section. In connection with this, when the situation can be clearly understood from the description, the outline of the background may be omitted even for a hole closed on a plane. Furthermore, even if it is not a cross section, hatching lines or dot patterns may be added to make it clear that it is not a void or to make it clear that the boundary of the area is clear.

[0113] In the present embodiment, a power conversion device which is a semiconductor module including an inverter circuit (power conversion circuit) is described as an example of an electronic device in which a plurality of semiconductor devices are mounted on a substrate.

[0114] An inverter circuit is a circuit that converts direct current into alternating current. For example, if the positive and negative of a direct current power supply are output alternately, the direction of the current is reversed accordingly. In this case, because the direction of the current is reversed alternately, it can be considered that the output is alternating current. This is the principle of an inverter circuit. Here, even if it is alternating current, there are various forms represented by single-phase alternating current and three-phase alternating current. In this embodiment, a three-phase inverter circuit that converts direct current into three-phase alternating current is illustrated. However, the technical idea of ​​this embodiment is not limited to the case where it is applicable to a three-phase inverter circuit, for example, it can also be widely applied to a single-phase inverter circuit, etc.

[0115] <Structure of three-phase inverter circuit>

[0116] Figure 1 This is a circuit diagram of a three-phase inverter circuit arranged between a DC power supply and a three-phase induction motor. Figure 1 As shown in FIG. 1 , in order to convert the DC power source E into a three-phase AC power, a three-phase inverter circuit INV composed of six switches SW1 to SW6 is used. Specifically, Figure 1As shown, the three-phase inverter circuit INV has a bridge arm LG1 in which switches SW1 and SW2 are connected in series, a bridge arm LG2 in which switches SW3 and SW4 are connected in series, and a bridge arm LG3 in which switches SW5 and SW6 are connected in series, and the bridge arms LG1 to LG3 are connected in parallel. At this time, switches SW1, SW3, and SW5 constitute an upper arm, and switches SW2, SW4, and SW6 constitute a lower arm.

[0117] In addition, a point U between the switch SW1 and the switch SW2 is connected to the U phase of the three-phase induction motor MT. Similarly, a point V between the switch SW3 and the switch SW4 is connected to the V phase of the three-phase induction motor MT, and a point W between the switch SW5 and the switch SW6 is connected to the W phase of the three-phase induction motor MT. In this way, a three-phase inverter circuit INV is constructed.

[0118] <Circuit Operation>

[0119] Next, the operation of the three-phase inverter circuit INV having the above-described configuration will be described. Figure 2 2 is a timing diagram for explaining the operation of a three-phase inverter circuit. Figure 2 As shown, in the three-phase inverter circuit INV, the bridge arm LG1 (refer to Figure 1 ) operates as follows. For example, when switch SW1 is turned on, switch SW2 is turned off. On the other hand, when switch SW1 is turned off, switch SW2 is turned on. In addition, the bridge arm LG2 (refer to Figure 1 ) and the bridge arm LG3 formed by the switch SW5 and the switch SW6 (refer to Figure 1 ) respectively operate in the same manner as the bridge arm LG1. That is, when the switch SW3 is turned on, the switch SW4 is turned off. On the other hand, when the switch SW3 is turned off, the switch SW4 is turned on. In addition, when the switch SW5 is turned on, the switch SW6 is turned off. On the other hand, when the switch SW5 is turned off, the switch SW6 is turned on.

[0120] Moreover, if Figure 2 As shown, three switch pairs (i.e., Figure 1The switching actions of the bridge arms LG1, LG2, and LG3 shown in the figure are performed in a manner that has a phase difference of 120 degrees. At this time, the potentials of each point U, point V, and point W change to E2 (for example, a ground potential of 0 (V)) and E1 according to the switching actions of the three switch pairs. In addition, for example, the line voltage between the U phase and the V phase is a voltage obtained by subtracting the potential of the V phase from the potential of the U phase, so a voltage waveform that changes to +E1, E2 (0), and -E1 is drawn. The line voltage between the V phase and the W phase is a voltage waveform that is 120 degrees out of phase with the line voltage between the U phase and the V phase, and the line voltage between the W phase and the U phase is a voltage waveform that is 120 degrees out of phase with the line voltage between the V phase and the W phase. In this way, by switching the switches SW1 to SW6, each line voltage becomes a step-shaped AC voltage waveform, and the AC voltage waveforms of the mutual line voltages have a phase difference of 120 degrees. Therefore, the three-phase inverter circuit INV can convert the DC power supplied from the DC power source E into a three-phase AC power.

[0121] <Circuit Configuration Example>

[0122] The electronic device EA1 of this embodiment (see Figure 3 ) is used for a driving circuit of a three-phase induction motor used in, for example, an automobile, an air conditioning device, or industrial equipment. The driving circuit includes an inverter circuit, which is a circuit having a function of converting direct current into alternating current. Figure 3 This is a circuit diagram showing the configuration of a motor circuit including an inverter circuit and a three-phase induction motor according to the present embodiment.

[0123] Figure 3 In the embodiment, the motor circuit has a three-phase induction motor MT and an inverter circuit INV. The three-phase induction motor MT is configured to be driven by voltages of three phases with different phases. In the three-phase induction motor MT, a rotating magnetic field is generated around the rotor RT as a conductor by using three-phase alternating currents called U phase, V phase, and W phase, which have phases offset by 120 degrees from each other. In this case, the magnetic field rotates around the rotor RT. This means that a magnetic flux that crosses the rotor RT as a conductor is generated. As a result, electromagnetic induction is generated in the rotor RT as a conductor, so that an induced current flows in the rotor RT. The flow of induced current in the rotating magnetic field means that a force is applied to the rotor RT by Fleming's left-hand rule, and the rotor RT is rotated by this force. In this way, in the three-phase induction motor MT, the rotor RT can be rotated by using three-phase alternating current. Therefore, in the three-phase induction motor MT, three-phase alternating current is required. Therefore, in the motor circuit, three-phase alternating current is supplied to the three-phase induction motor by using the inverter circuit INV that generates alternating current from direct current.

[0124] The following describes an actual configuration example of the inverter circuit INV. Figure 3 As shown, for example, in the inverter circuit INV of this embodiment, a transistor Q1 and a diode FWD are provided corresponding to the three phases. That is, in the actual inverter circuit INV, for example Figure 1 The switches SW1 to SW6 shown are respectively Figure 3 The transistor Q1 and the diode FWD are connected in reverse parallel as shown. Figure 3 In the embodiment, the upper arm and the lower arm of the bridge arm LG1, the upper arm and the lower arm of the bridge arm LG2, and the upper arm and the lower arm of the bridge arm LG3 are respectively constituted by components in which the transistor Q1 and the diode FWD are connected in anti-parallel.

[0125] Figure 3 The transistor Q1 shown is a power transistor (transistor for power circuit) assembled in a circuit such as a power conversion circuit where a large current flows, and in the example of this embodiment, it is, for example, an IGBT. As a modified example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can be used as a switching element of the inverter circuit INV. According to this power MOSFET, since it is a voltage-driven type in which the on / off action is controlled by the voltage applied to the gate, it has the advantage of being able to switch quickly. On the other hand, in the power MOSFET, there is a property that the on-resistance becomes higher and the heat generation becomes larger as the high withstand voltage is achieved. This is because, in the power MOSFET, the withstand voltage is ensured by thickening the thickness of the low-concentration epitaxial layer (drift layer), but if the thickness of the low-concentration epitaxial layer becomes thicker, the resistance will increase as a side effect.

[0126] In addition, as a switching element, there are also bipolar transistors that can handle large power, but bipolar transistors are current-driven transistors that use base current to control on / off operations, so they have a switching speed that is generally slower than the aforementioned power MOSFET.

[0127] Therefore, in applications where high power is required and fast switching is required, it is preferred to use an IGBT as a switching element. The IGBT is formed by combining a power MOSFET and a bipolar transistor, and is a semiconductor element that has both the fast switching characteristics of a power MOSFET and the high voltage resistance of a bipolar transistor. That is, according to the IGBT, high power and fast switching can be achieved, so it is called a semiconductor element suitable for applications that require high current and fast switching. As described above, in the inverter circuit INV of this embodiment, an IGBT is used as the transistor Q1 constituting the switching element.

[0128] In addition, in the inverter circuit INV of the present embodiment, a transistor Q1 and a diode FWD are connected in reverse parallel between a high-side terminal (positive potential terminal) HT supplied with a relatively high potential and each phase (U phase, V phase, W phase) of the three-phase induction motor MT. In addition, a transistor Q1 and a diode FWD are also connected in reverse parallel between each phase of the three-phase induction motor MT and a low-side terminal (negative potential terminal) LT supplied with a relatively low potential. That is, two transistors Q1 and two diodes FWD are provided for each single phase, and six transistors Q1 and six diodes FWD are provided in three phases. Moreover, a gate control circuit GC is connected to the gate of each transistor Q1, and the switching action of the transistor Q1 is controlled by the gate control circuit GC. In the inverter circuit INV thus constructed, by controlling the switching action of the transistor Q1 with the gate control circuit GC, direct current is converted into three-phase alternating current, and the three-phase alternating current is supplied to the three-phase induction motor MT.

[0129] In the inverter circuit INV of this embodiment, a transistor Q1 is used as a switching element, and a diode FWD is provided in a manner connected in reverse parallel to the transistor Q1. From the perspective of simply realizing the switching function by using the switching element, it can be considered that the transistor Q1 as a switching element is required and the diode FWD is not required. In this regard, when the load connected to the inverter circuit INV contains an inductor, the diode FWD needs to be provided.

[0130] When the load is a pure resistor without inductance, there is no energy to flow back, so the diode FWD is not required. However, when a circuit containing inductance such as a motor is connected to the load, there is a mode in which the load current flows in the opposite direction to the turned-on switch. That is, when the load contains inductance, energy may return from the inductance of the load to the inverter circuit INV (current may flow in reverse).

[0131] At this time, in the transistor Q1 monomer as an IGBT, there is no function that can make the return current flow, so it is necessary to connect the diode FWD in reverse parallel with the transistor Q1. That is, in the inverter circuit INV, when the load contains inductance such as motor control, when the transistor Q1 is turned off, the energy (1 / 2LI2) accumulated in the inductance must be released. However, in the transistor Q1 monomer, the return current for releasing the energy accumulated in the inductance cannot flow. Therefore, in order to reflux the electric energy accumulated in the inductance, the diode FWD is connected in reverse parallel with the transistor Q1. In other words, the diode FWD has the function of making the return current flow in order to release the electric energy accumulated in the inductance. According to the above content, in the inverter circuit connected to the load containing inductance, it is necessary to set the diode FWD in reverse parallel with the transistor Q1 as a switching element. This diode FWD is called a freewheeling diode.

[0132] In addition, in the case of the inverter circuit INV of this embodiment, for example, Figure 3 As shown in FIG. 1 , a capacitive element CAP is connected between the high-side terminal HT and the low-side terminal LT. The capacitive element CAP has a function of, for example, smoothing switching noise in the inverter circuit INV and stabilizing the system voltage. Figure 3 In the example shown, the capacitance element CAP is provided outside the inverter circuit INV, but the capacitance element CAP may be provided inside the inverter circuit INV.

[0133] <Structure of semiconductor chips>

[0134] Next, the invention will be described with reference to the accompanying drawings. Figure 3 The structure of the semiconductor chip of the transistor Q1 and the diode FWD constituting the inverter circuit INV is shown. Figure 4 It means that there is Figure 3 A top view showing the shape of the transistor on the surface side of a semiconductor chip. Figure 5 Yes means Figure 4 A bottom view of the back side of a semiconductor chip is shown. Figure 6 It means having Figure 4 and Figure 5 A cross-sectional view of a structural example of a transistor in a semiconductor chip shown.

[0135] exist Figure 3 In the case of the electronic device EA1 shown, the transistor Q1 and the diode FWD constituting the inverter circuit INV are formed on mutually independent semiconductor chips. Hereinafter, the semiconductor chip on which the transistor Q1 is formed will be described, and then the semiconductor chip on which the diode FWD is formed will be described.

[0136] like Figure 4 and Figure 5As shown, the semiconductor chip SC1 of this embodiment has a surface (surface, upper surface, main surface) SCt (see Figure 4 ) and the back surface (surface, lower surface, main surface) SCb on the opposite side of the surface SCt (refer to Figure 5 ). The front surface SCt and the back surface SCb of the semiconductor chip SC1 are respectively quadrilateral. The area of ​​the front surface SCt and the area of ​​the back surface SCb are equal, for example.

[0137] In addition, if Figure 4 As shown, the semiconductor chip SC1 has a gate (gate pad, surface electrode) GP and an emitter (emitter pad, surface electrode) EP formed on the surface SCt. Figure 4 In the example shown, a gate electrode GP and a plurality of ( Figure 4 The exposed area of ​​each of the plurality of emitters EP is larger than the exposed area of ​​the gate GP. The emitter EP and the inverter circuit INV (see Figure 3 ) output terminal or low-side terminal LT (refer to Figure 3 ) connection. Therefore, by making the exposed area of ​​the emitter EP large, the impedance of the transmission path where a large current flows can be reduced. In addition, a plurality of emitters EP are electrically connected to each other. In addition, as for Figure 4 In a modification example, a single emitter EP with a large area may be provided instead of multiple emitters EP. In addition, when a single emitter EP with a large area is provided, openings may be provided at multiple locations of the insulating film covering the emitter EP, and multiple portions of the emitter EP may be exposed in the multiple openings.

[0138] In addition, if Figure 5 As shown, the semiconductor chip SC1 has a collector electrode (collector pad, back electrode) CP formed on the back surface SCb. The collector electrode CP is formed on the entire back surface SCb of the semiconductor chip SC1. Figure 4 and Figure 5 It can be seen that the exposed area of ​​the collector electrode CP is larger than the exposed area of ​​the emitter electrode EP. Figure 3 ) output terminal or high-side terminal HT (refer to Figure 3 Therefore, by increasing the exposed area of ​​the collector electrode CP, the impedance of the transmission path through which a large current flows can be reduced.

[0139] Furthermore, Figure 4 and Figure 5 Although the basic structure of the semiconductor chip SC1 is described in the above, various modifications can be applied. Figure 4In addition to the electrodes shown, electrodes for temperature detection, electrodes for voltage detection, electrodes for current detection, etc., electrodes for monitoring the operating state of the semiconductor chip SC1, or electrodes for inspecting the semiconductor chip SC1, etc. may be provided. When these electrodes are provided, they are exposed on the surface SCt of the semiconductor chip SC1 in the same manner as the gate GP. In addition, these electrodes are equivalent to electrodes for signal transmission, and the exposed area of ​​each electrode is smaller than the exposed area of ​​the emitter EP.

[0140] Furthermore, the transistor Q1 included in the semiconductor chip SC1 has, for example, Figure 6 The structure is as shown. A p+ type semiconductor region PR1 is formed on the collector electrode CP formed on the back side SCb of the semiconductor chip SC1. An n+ type semiconductor region NR1 is formed on the p+ type semiconductor region PR1, and an n- type semiconductor region NR2 is formed on the n+ type semiconductor region NR1. Moreover, a p-type semiconductor region PR2 is formed on the n- type semiconductor region NR2, and a trench TR is formed that penetrates the p-type semiconductor region PR2 and reaches the n- type semiconductor region NR2. Moreover, an n+ type semiconductor region ER that becomes an emitter region is formed to match the trench TR. A gate insulating film GOX, for example, formed of a silicon oxide film, is formed inside the trench TR, and a gate GE is formed across the gate insulating film GOX. The gate GE is formed of, for example, a polysilicon film and is formed in a manner that buries the trench TR.

[0141] In the transistor Q1 thus constructed, the gate GE is connected to Figure 4 Similarly, the n+ type semiconductor region ER serving as the emitter region is electrically connected to the emitter EP. The p+ type semiconductor region PR1 serving as the collector region is electrically connected to the collector electrode CP formed on the back surface SCb of the semiconductor chip SC1.

[0142] The transistor Q1 configured in this way has both the fast switching characteristics and voltage drive characteristics of a power MOSFET and the low on-voltage characteristics of a bipolar transistor.

[0143] Furthermore, the n+ type semiconductor region NR1 is called a buffer layer. The n+ type semiconductor region NR1 is provided to prevent the breakdown phenomenon caused by the depletion layer growing from the p-type semiconductor region PR2 into the n-type semiconductor region NR2 and contacting the p+ type semiconductor region PR1 formed in the lower layer of the n-type semiconductor region NR2 when the transistor Q1 is turned off. In addition, the n+ type semiconductor region NR1 is provided for the purpose of limiting the amount of holes injected from the p+ type semiconductor region PR1 to the n-type semiconductor region NR2.

[0144] In addition, the gate of transistor Q1 is connected to Figure 3At this time, the signal from the gate control circuit GC is connected via the gate GP (refer to Figure 6 ) is applied to the gate GE of transistor Q1 (refer to Figure 6 ), thereby enabling the switching action of the transistor Q1 to be controlled from the gate control circuit GC.

[0145] Next, the formation of Figure 3 The diode FWD is shown as a semiconductor chip. Figure 7 It means that there is Figure 3 FIG. 1 is a top view of the shape of the surface side of the semiconductor chip of the diode shown. Figure 8 Yes means Figure 7 A bottom view of the back side of the semiconductor chip is shown. Fig. 9 Yes means Figure 7 and Figure 8 2 is a cross-sectional view of a structural example of a diode included in the semiconductor chip shown.

[0146] like Figure 7 and Figure 8 As shown, the semiconductor chip SC2 of this embodiment has a surface (surface, upper surface, main surface) SCt (see Figure 7 ) and the back surface (surface, lower surface, main surface) SCb on the opposite side of the surface SCt (refer to Figure 8 ). The surface SCt and the back surface SCb of the semiconductor chip SC2 are respectively quadrilateral. The area of ​​the surface SCt and the area of ​​the back surface SCb are equal, for example. Figure 4 and Figure 7 It can be seen that the semiconductor chip SC1 (refer to Figure 4 ) has a surface area of ​​SCt larger than that of the semiconductor chip SC2 (refer to Figure 7 ) has a large surface area of ​​SCt.

[0147] In addition, if Figure 7 As shown in FIG. 1 , the semiconductor chip SC2 has an anode (anode pad, surface electrode) ADP formed on the surface SCt. Figure 8 As shown, the semiconductor chip SC2 has a cathode (cathode pad, back electrode) CDP formed on the back surface SCb. The cathode CDP is formed on the entire back surface SCb of the semiconductor chip SC2.

[0148] In addition, the diode FWD included in the semiconductor chip SC2 has, for example, Fig. 9 As shown in the structure. Fig. 9As shown, an n+ type semiconductor region NR3 is formed on the cathode CDP formed on the back side SCb of the semiconductor chip SC2. Furthermore, an n- type semiconductor region NR4 is formed on the n+ type semiconductor region NR3, and p- type semiconductor regions PR3 separated from each other are formed on the n- type semiconductor region NR4. A p- type semiconductor region PR4 is formed between the p-type semiconductor regions PR3. An anode ADP is formed on the p-type semiconductor region PR3 and the p- type semiconductor region PR4. The anode ADP is composed of, for example, aluminum-silicon.

[0149] According to the diode FWD configured in this way, when a positive voltage is applied to the anode ADP and a negative voltage is applied to the cathode CDP, the pn junction between the n-type semiconductor region NR4 and the p-type semiconductor region PR3 is forward biased and current flows. On the other hand, when a negative voltage is applied to the anode ADP and a positive voltage is applied to the cathode CDP, the pn junction between the n-type semiconductor region NR4 and the p-type semiconductor region PR3 is reverse biased and current does not flow. In this way, the diode FWD having a rectifying function can be operated.

[0150] <Structure of electronic devices>

[0151] Next, the composition is described. Figure 3 An example of the configuration of the electronic device EA1 of the inverter circuit INV is shown. Fig.10 Yes means Figure 3 The perspective view of the appearance of the electronic device shown. In addition, Fig.11 Yes means Fig.10 The bottom view of the back side of the electronic device is shown. Fig.11 Although it is a top view, the adhesive material BD1 exposed around the lower surface CSb of the substrate CS1 is shown by adding hatching. Fig.12 It is along Fig.11 A-A line cross-sectional view. In addition, Fig.13 Yes means Fig.11 A top view of the layout of the upper surface side of the substrate is shown.

[0152] constitute Figure 3 The electronic device EA1 of the present embodiment of the inverter circuit INV shown in FIG. Fig.10 As shown, the upper surface side is covered by a frame (housing, housing) HS. The electronic device EA1 is a housing module, and a plurality of semiconductor chips SC1 and SC2 (see Fig.13 ) is housed in a frame body HS, and a plurality of terminals LD serving as external terminals are exposed from the frame body HS.

[0153] The frame HS has a plurality of semiconductor chips SC1 and SC2 (see Fig.13) and a supporting part (frame) HSF supporting the cover part HST. The supporting part HSF and the cover part HST constituting the frame body HS are respectively parts made of resin, for example, polyethylene terephthalate (hereinafter referred to as PET) as a main raw material. Furthermore, in the case of the present embodiment, the cover part HST and the supporting part HSF are independent of each other and are separable parts. However, the cover part HST and the supporting part HSF may be inseparable from each other. For example, the cover part HST and the supporting part HSF may be bonded and fixed via an adhesive material. Alternatively, the cover part HST and the supporting part HSF may be formed as a whole.

[0154] In addition, if Fig.11 As shown, the support portion HSF continuously surrounds the periphery of the substrate CS1. Fig.12 As shown, the cover HST covers the entire upper surface (surface, surface, main surface) CSt of the substrate CS1. A space is provided inside the support portion HSF, and a plurality of semiconductor chips SC1 and SC2 mounted on the substrate CS1 are accommodated in the space (accommodation portion PKT) surrounded by the support portion HSF, the cover HST and the substrate CS1. The details will be described later, and the peripheral portion of the upper surface CSt of the substrate CS1 is bonded and fixed to the frame HS via the adhesive material (glue) BD1.

[0155] In addition, a plurality of terminals LD protrude from the cover HST of the frame HS. A plurality of through holes (not shown) are formed in the cover HST of the frame HS, and the plurality of terminals LD are respectively inserted into the plurality of through holes. The plurality of terminals LD are respectively external terminals of the electronic device EA1 and are connected to the Fig.13 The plurality of semiconductor chips SC1 on the substrate CS1 shown are electrically connected.

[0156] In addition, if Fig.11 As shown, the housing HS of the electronic device EA1 has a side (long side) HSe1 extending along the X direction, a side (long side) HSe2 located on the opposite side of the side HSe1, and a side (long side) HSe2 extending along the X direction ( Fig.11 The side (short side) HSe3 extending in the Y direction (orthogonal to the center) and the side (short side) HSe4 located on the opposite side of the side HSe3. In addition, the side HSe1 and the side HSe2 are relatively longer than the side HSe3 and the side HSe4. Furthermore, Fig.11 In the example shown, the housing HS of the electronic device EA1 forms a quadrilateral ( Fig.11 The top view shape of the electronic device EA1 is a rectangle. However, there are various variations other than a quadrilateral. For example, the intersection of the side HSe3 and the side HSe1 in the four corners of the quadrilateral can be cut off obliquely relative to the X direction and the Y direction to form a pentagon. In this case, the obliquely cut corners can be used as alignment marks for identifying the direction of the electronic device EA1.

[0157] In addition, if Fig.10 and Fig.11 As shown in FIG. 1 , the frame HS has a flange portion (part) FLG, which is a mounting portion for fixing the electronic device EA1 to, for example, a heat sink or a supporting member. Fig.11 As shown, the flange portions FLG are arranged at both ends of the support portion HSF in the long side direction of the frame HS, that is, in the X direction, when viewed from above. In other words, in the X direction, the two flange portions FLG are arranged on opposite sides of each other across the receiving portion PKT for receiving the substrate CS1. In addition, through holes (holes, threaded holes, screw insertion holes) THH are respectively formed in the center of the plurality of flange portions FLG. The through hole THH is an opening portion of the flange portion FLG that penetrates the frame HS in the thickness direction. When the electronic device EA1 is fixed to, for example, a radiator or a supporting component, a screw BOL (refer to the later-described through hole THH) can be inserted into the through hole THH. Fig.15 ), screw the electronic device EA1 into place.

[0158] Fig.11 In the illustrated example, two through holes THH are formed along a virtual line (center line) VL1 extending in the X direction, which is the longitudinal direction, so as to connect the center of the side HSe3 and the center of the side HSe4 . Fig.11 In the example shown, the imaginary line VL1 is a straight line connecting the center point of the through hole THH arranged on one side and the center point of the through hole THH arranged on the other side in the X direction (passing through these two center points). Fig.11 In the example shown, when viewed from the bottom surface (front, back, main surface) CSb of the substrate CS1, the imaginary line VL1 passes through (through) the bottom surface CSb of the substrate CS1. Here, the center point of the bottom surface CSb of the substrate CS1 can be defined as Fig.13 The center point of the upper surface (surface, surface, main surface) CSt of the substrate CS1 shown is the same. That is, Fig.13 The lower surface CSb of the substrate CS1 shown in FIG. Fig.11 ) and the center point of the upper surface CSt is the intersection of a line (not shown) connecting the midpoint of the side (long side, substrate side) CSe1 of the substrate CS1 and the midpoint of the side (long side, substrate side) CSe2, and a line (not shown) connecting the midpoint of the side (short side, substrate side) CSe3 and the midpoint of the side (short side, substrate side) CSe4. The detailed structure of the frame HS other than the above will be described later.

[0159] Next, the substrate CS1 accommodated in the accommodation portion PKT of the housing HS of the electronic device EA1 and the components fixed to the substrate CS1 will be described.

[0160] like Fig.12 and Fig.13 As shown, the electronic device EA1 includes a substrate CS1, a plurality of metal patterns (patterns formed of metal, metal films, patterns) MP formed on an upper surface CSt of the substrate CS1, and a plurality of semiconductor chips SC1 mounted on a portion of the plurality of metal patterns MP.

[0161] like Fig.12 As shown, the substrate CS1 has a chip mounting surface for mounting a plurality of semiconductor chips SC1, namely an upper surface (surface, main surface, face) CSt and a lower surface (back surface, main surface, face) CSb located on the opposite side of the upper surface CSt. The substrate CS1 is a ceramic substrate formed of a ceramic material. As a material constituting the substrate CS1, in addition to oxide materials such as alumina (aluminum oxide: Al2O3), nitride materials such as aluminum nitride (AlN) can also be used. In addition, as a material constituting the main component of the substrate, in addition to the above-mentioned aluminum, a material with silicon (silicon element: Si) as the main component can also be used. As a material used with silicon as the main component, nitride materials such as silicon nitride (Si3N4) can be exemplified.

[0162] like Fig.13 As shown, the substrate CS1 has a side (long side, substrate side) CSe1 extending (extending) along the X direction, a side (long side, substrate side) CSe2 located on the opposite side of the side CSe1, and a side (long side, substrate side) CSe2 intersecting the X direction ( Fig.13 The side (short side, substrate side) CSe3 extending (extending) in the Y direction (orthogonal to the center), and the side (short side, substrate side) CSe4 located on the opposite side of the side CSe3. In addition, the side CSe1 and the side CSe2 are relatively longer than the side CSe3 and the side CSe4. Fig.13 In the example shown, the substrate CS1 is formed into a quadrilateral (to be specific, a rectangle) in a plan view.

[0163] In addition, if Fig.12 As shown, a plurality of metal patterns M are bonded to the upper surface CSt and the lower surface CSb of the substrate CS1. These plurality of metal patterns MP are, for example, a laminated film formed by laminating a nickel (Ni) film on the surface of a copper (Cu) film, and a copper film is directly bonded to the upper surface CSt or the lower surface CSb of the substrate CS1. As in the present embodiment, the substrate CS1 on which the semiconductor chip SC1 is directly mounted on the metal pattern MP formed of copper is sometimes also referred to as a DBC (Direct Bonding Copper) substrate.

[0164] The metal pattern MPB formed on the lower surface CSb side of the substrate CS1 is a metal film constituting a heat dissipation path of the electronic device EA1, and is uniformly formed in a manner covering most of the lower surface CSb of the substrate CS1. By forming a metal film on the lower surface CSb of the substrate CS1 as a ceramic substrate, the heat dissipation of the electronic device EA1 can be improved. In addition, the plurality of metal patterns MP formed on the upper surface CSt of the substrate CS1 respectively constitute the inverter circuit INV (refer to Figure 3 ) are separated from each other (separated by a gap).

[0165] The plurality of metal patterns MP include a potential E1 supplied to a high side (see Figure 3 ) of the metal pattern MPH. In addition, the plurality of metal patterns MP include a potential E2 (see Figure 3 ) metal pattern MPL. In addition, the plurality of metal patterns MP include metal patterns MPU, MPV, MPW to which a potential that changes according to the switching action of the transistor Q1 is supplied. In addition, the plurality of metal patterns MP include a plurality of metal patterns MPT for connecting the external terminal LD ​​of the electronic device EA1.

[0166] The metal pattern MPU, the metal pattern MPV, and the metal pattern MPW are supplied with different potentials in a manner having a phase difference of 120 degrees. Therefore, the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW are separated from each other (spaced apart). In addition, the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW are respectively connected to the metal pattern MPT connected to the output terminal LD ​​(output terminals TU, TV, and TW) via a plurality of wires BW. Therefore, Figure 3 The transmission paths for outputting the U-phase, V-phase, and W-phase shown include Fig.13 Wire BW shown.

[0167] In the metal pattern MPH, the U phase, V phase, and W phase (refer to Figure 3 ) are supplied with the same potential (high side potential E1 (refer to Figure 3 )). Therefore, the metal pattern MPH is not divided corresponding to the distinction between the U phase, the V phase, and the W phase, but is formed as one. In other words, the high-side potential E1 is not supplied to each of the plurality of semiconductor chips SCH via the wire BW. Fig.13 As a modified example, the metal pattern MPH may be divided corresponding to the distinction among the U phase, V phase, and W phase, and the divided metal patterns MPH may be electrically connected via conductor patterns such as wires (not shown).

[0168] In addition, in the metal pattern MPL, the U phase, the V phase, and the W phase (see Figure 3) are supplied with the same potential (low-side potential E2 (refer to Figure 3 )). Therefore, the metal pattern MPL is not divided corresponding to the difference between the U phase, the V phase, and the W phase, but is formed as a whole. Fig.13 The modified example can also be divided corresponding to the difference between the U phase, the V phase and the W phase. Fig.13 In the metal pattern MPL shown, the divided metal patterns MPL are electrically connected to each other via conductive members such as wires (not shown).

[0169] In addition, a terminal LD ​​is connected to each of the multiple metal patterns MPT among the multiple metal patterns MP. In addition, a plurality of terminals LD are formed on each of the metal patterns MPH and the metal pattern MPL among the multiple metal patterns MP. In addition, a terminal LD ​​is respectively mounted on each of the short sides CSe3 and CSe4 among the four sides along the upper surface CSt of the substrate CS1 on the metal pattern MPH and the metal pattern MPL.

[0170] In addition, each of the metal patterns MPU, MPV, and MPW among the above-mentioned multiple metal patterns MP is not equipped with a terminal LD. In other words, each of the metal patterns MPU, MPV, and MPW among the multiple metal patterns MP is not directly connected to the terminal LD. The metal pattern MPU, MPV, and MPW are electrically connected to the metal pattern MPT via multiple wires BW, respectively. In other words, the metal pattern MPU, MPV, and MPW are electrically connected to the terminal LD ​​via multiple wires BW and the metal pattern MPT, respectively.

[0171] In addition, a plurality of semiconductor chips SC1 and semiconductor chips SC2 are mounted on a portion of the plurality of metal patterns MP (metal pattern MPH, metal pattern MPU, metal pattern MPV, and metal pattern MPW). Figure 6 As described above, the switching element is formed with an IGBT, that is, a transistor Q1, which is mounted on each of the metal pattern MPH, the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW. The chip mounted on the metal pattern MPH in the semiconductor chip SC1 is equivalent to the high-side switches SW1, SW3, and SW5 (see Figure 1 ) semiconductor chip SCH. In addition, the chips mounted on the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW in the semiconductor chip SC1 are equivalent to the switches SW2, SW4, and SW6 on the low side (see Figure 1 ) of the semiconductor chip SCL. In addition, a plurality of semiconductor chips SC2 are used as Fig. 9As described above, the diode FWD is included. Each of the plurality of semiconductor chips SC2 is mounted on the metal pattern MPH, the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW so as to be grouped with each of the plurality of semiconductor chips SCL.

[0172] like Fig.12 As shown, in this embodiment, the semiconductor chip SC1 is bonded and fixed to the metal pattern MP via a conductive adhesive material (chip soldering material, conductive component, connecting component, bonding material) SD in a manner that the back surface SCb of the semiconductor chip SC1 faces the upper surface (surface) MPt of the metal pattern MP. The conductive adhesive material SD is a conductive resin containing, for example, solder or a plurality (a large number) of conductive particles (for example, silver particles) in the resin. Figure 5 As shown in FIG. 1 , a collector electrode CP is formed on the back surface SCb of the semiconductor chip SC1. Fig.12 The conductive adhesive material SD shown is electrically connected to the metal pattern MP.

[0173] In addition, although Fig.13 The illustration is omitted, but the semiconductor chip SC2 is respectively provided with the back surface SCb of the semiconductor chip SC2 (refer to Figure 8 ) and the upper surface (surface) MPt of the metal pattern MP (refer to Fig.12 ) relative to each other through the conductive adhesive material SD (refer to Fig.12 ) is bonded and fixed on the metal pattern MP. Figure 8 As shown, a cathode CDP is formed on the back side SCb of the semiconductor chip SC2. Fig.12 The conductive adhesive material SD shown is electrically connected to the metal pattern MP.

[0174] In addition, if Fig.13 As shown, at the emitter EP of the semiconductor chip SC1 (refer to Figure 4 ) is connected to a plurality of wires BW. Specifically, the emitter EP of the semiconductor chip SCH for the high side is connected to one of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW via a plurality of wires BW. In other words, the emitter EP of the semiconductor chip SCH for the high side is connected to one of the output terminal TU of the U phase, the output terminal TV of the V phase, and the output terminal TW of the W phase. In addition, the emitter EP of the semiconductor chip SCL for the low side is connected to the metal pattern MPL via a plurality of wires BW. In other words, the emitter EP of the semiconductor chip SCL for the low side is connected to the metal pattern MPL supplied with Figure 3 The low-side potential E2 shown is electrically connected to a low-side terminal LT.

[0175] In addition, if Fig.13 As shown, in the gate GP of the semiconductor chip SC1 (refer to Figure 4 ) is connected to a wire BW. In detail, Fig.13 As shown, the semiconductor chip SCH for the high side and the semiconductor chip SCL for the low side each have a gate GP (see Figure 4 ) are electrically connected to the metal pattern MPT via the wire BW. The metal pattern MPT supplies power to the transistor Q1 (see Figure 3 ) is a driving signal (gate signal) that drives the switching action.

[0176] In addition, at the anode ADP (refer to Figure 7 ) is connected with a plurality of wires BW. In detail, the anode ADP of the semiconductor chip SC2 for high side is connected to one of the metal pattern MPU, the metal pattern MPV and the metal pattern MPW via a plurality of wires BW. In addition, the anode ADP of the semiconductor chip SC2 for high side is also connected to the metal pattern MPT for output via a plurality of wires BW. In other words, the anode ADP of the semiconductor chip SC2 for high side is connected to one of the output terminal TU of the U phase, the output terminal TV of the V phase and the output terminal TW of the W phase. In addition, the anode ADP of the semiconductor chip SC2 for low side is connected to the metal pattern MPL via a plurality of wires BW. In other words, the anode ADP of the semiconductor chip SC2 for low side is connected to the metal pattern MPL supplied with Figure 3 The low-side potential E2 shown is electrically connected to a low-side terminal LT.

[0177] Fig.13 The plurality of wires BW shown are metal wires, and in this embodiment, are formed of, for example, aluminum. However, there are various modifications in the material of the wires BW, and gold or copper may be used in addition to aluminum.

[0178] In addition, if Fig.12As shown, the space between the frame HS and the substrate CS1 is filled with a sealing material (gel-like insulating material) MG. A plurality of semiconductor chips SC1 and a plurality of wires BW are sealed by the sealing material MG, respectively. The sealing material MG is a component that protects a plurality of semiconductor chips SC1, SC2, a plurality of wires BW and a portion of the terminal LD. As a component for sealing, there is a method of using a resin material such as epoxy resin that cures by heating and can ensure a certain degree of strength. However, after the sealing material MG is cured, when the temperature of the electronic device EA1 changes, stress is generated inside the electronic device EA1 due to the difference in linear expansion coefficient between the substrate CS1 and the sealing material MG. Therefore, in this embodiment, a gel-like material (polymer compound) that is softer than epoxy resin is used to form the sealing material MG. In detail, in this embodiment, the sealing material MG is silicone gel. Silicone gel is a polymer compound having a main skeleton composed of siloxane bonds, and is a type of silicone resin. Silicone resin is classified as a thermosetting resin that cures by applying thermal energy, and has the characteristic that the elasticity after curing is low elasticity, such as natural rubber. In addition, among silicone resins, silicone gel is a resin that becomes a gel state after curing, and the density of the cross-linked structure of the chain polymer is lower than that of the elastomer called silicone rubber. Therefore, the elasticity of silicone gel after curing is lower than the physical properties of silicone rubber after curing. Fig.12 The adhesive material BD1 shown uses silicone rubber, but the sealing material MG has lower elasticity than the adhesive material BD1. In other words, the sealing material MG is softer than the adhesive material BD1 and is easily deformed. The sealing material MG, which is a silicone gel, is deformed to reduce the stress generated when the temperature of the electronic device EA1 changes.

[0179] <Installation of electronic devices>

[0180] Next, as a mounting method of the electronic device EA1 as a housing module, a method of mounting the electronic device EA1 on the mounting substrate will be described. Fig.14 It means that Fig.10 The electronic device shown is a cross-sectional view of a state where it is bonded to a mounting substrate and then screwed and fixed. Fig.15 It means that in the Fig.14 A cross-sectional view of an electronic device of a research example is shown in a state where the electronic device is bonded to a mounting substrate and then screwed and fixed. Fig.14 and Fig.15 In FIG. 1 , a blank arrow is used to schematically represent the external force EF1 applied to the electronic device EAH by screwing in the screw BOL. In addition, Fig.14 and Fig.15 In FIG. 1 , the thickness of the arrow schematically indicates the magnitude of the external force EF1. In addition, Fig.14 and Fig.15 Corresponding to along Fig.13The cross section along line A-A is shown.

[0181] Fig.14 The electronic device EA1 and Fig.15 In the electronic device EAH shown in FIG. 1 , in the through hole THH (refer to Fig.11 ), the amount of adhesive material BD1 sandwiched between the substrate CS1 and the frame HS is different. Specifically, in the electronic device EA1 and the electronic device EAH, the height of the step surface relative to the substrate CS1 near the through hole THH in the frame HS is different. Fig.15 In the case of the electronic device EAH described above, it is equivalent to the following Fig.16 The distance D1 and Fig.17 The distance D2 between Fig.19 The distance D3 and Fig. 20 The distance D4 shown is the same as Fig.14 The electronic device EA1 shown is different. Moreover, because the height of the step difference surface is different, Fig.15 The amount of adhesive material BD1 sandwiched between the substrate CS1 and the frame HS in the electronic device EAH shown is less than that in Fig.14 The amount of adhesive material BD1 interposed between the substrate CS1 and the frame body HS in the electronic device EA1 is shown. The electronic device EA1 and the electronic device EAH are the same except for the above-mentioned differences, so repeated description is omitted. Fig.14 The detailed structure of the step surface of the electronic device EA1 will be described later.

[0182] like Fig.14 As shown, as a method of fixing the housing module, i.e., the electronic device EA1, to the substrate (mounting substrate, bottom plate) BP1, there is known a method of configuring the electronic device EA1 on the substrate BP1 via a heat-conductive material (heat-dissipating paste) BD2 and then screwing in the screws BOL. The heat-conductive material BD2 is a material in which, for example, metal particles or metal oxide particles with high thermal conductivity are mixed in a high-viscosity liquid (semi-solid) such as a grease. Grease is a grease in which a material (thickener) for adjusting the viscosity and the like is added to a lubricating oil (base oil), and the viscosity is higher than that of oil. In the present embodiment, a heat-dissipating paste with excellent heat resistance and cold resistance and using silicone grease as a base oil is used as the heat-conductive material BD2. By forming on the lower surface CSb (refer to Fig.11) and the substrate BP1, so that the cross-sectional area of ​​the heat dissipation path from the metal pattern MPB to the substrate BP1 is widened, thereby improving the heat dissipation characteristics. In addition, the grease used as the heat conductive material BD2 is a material that is softer and easier to deform than the substrate CS1 or the adhesive material BD1. Therefore, when the electronic device EA1 is fixed to the substrate BP1 by screwing in the screws BOL, the heat conductive material BD2 functions as a stress relief layer that disperses the stress of the substrate CS1 transmitted from the substrate BP1 to the electronic device EA1.

[0183] When screwing in the BOL screw, Fig.14 As shown, the lower surface Hf1 and the lower surface Hf3 of the flange portion FLG are pressed so as to approach the upper surface (surface, main surface, mounting surface) BPt of the substrate BP1. As a result, an external force EF1 is applied to the frame body HS in a direction approaching the substrate BP1. Fig.14 As schematically shown, the magnitude of the external force EF1 is not constant, but in the electronic device EA1, the external force EF1 is relatively large at a position close to the screw BOL. In addition, the external force EF1 is relatively small at a position far from the screw BOL. Fig.15 The electronic device EAH of the research example shown in the figure has a through hole THH formed in the center of the flange portion FLG (see Fig.11 ), a screw BOL is inserted into the through hole THH. Therefore, in the Y direction, the external force EF1 applied to the flanges FLG at both ends of the support part HSF is greater than the external force EF1 applied to the area between the flanges FLG. As a result, the portion around the flange FLG of the frame HS is deformed, and the flange FLG is pressed to a position closer to the upper surface BPt of the substrate BP1 than other portions.

[0184] At this time, if Fig.14 and Fig.15 As shown in the enlarged view, an external force EF1 is applied from the frame HS to the side (short side) CSe3 (and side (short side) CSe4) of the substrate CS1 which is short from the screw BOL. It is known that there is a case where the substrate CS1 is damaged depending on the degree of the external force EF1 applied to the substrate CS1.

[0185] In particular, from the perspective of miniaturizing the plane area (installation area) of the electronic device EA1, it is preferable to reduce the distance from the screw BOL to the substrate CS1, but the smaller the distance from the screw BOL to the substrate CS1, the stronger the force applied to the substrate CS1.

[0186] The numerical values ​​shown below are just an example, and various modifications are of course applicable. Fig.11In the case of the electronic device EA1 of the present embodiment shown in FIG. Fig.15 The same is true for the electronic device EAH shown in the figure), when viewed from above, the distance between the centers of the two through holes THH is 55 mm. In addition, the opening diameter of the through hole THH (the diameter of the circular opening) is about 4 mm, which is larger than the distance between the side HSe1 of the frame HS and the side CSe1 of the substrate CS1 (about 3 mm). In addition, the length of the long side direction of the substrate CS1, that is, the length in the X direction (that is, the length of the side CSe1 and the side CSe2) is 42 mm, and the length in the Y direction (the length of the side CSe3 and the side CSe4) is 36 mm. Therefore, the length from the center of a through hole THH to the sides CSe3 and CSe4 of the substrate CS1 is about 5 to 6 mm. In addition, the shortest distance from the edge of a through hole THH to the sides CSe3 and CSe4 of the substrate CS1 is smaller than the opening diameter of the through hole THH.

[0187] When applying the above numerical example to Fig.15 In the case of the electronic device EAH shown, it can be seen that the damage of the substrate CS1 becomes conspicuous.

[0188] In addition, according to the research of the inventor of the present application, it is found that as long as the distance from the screw BOL to the substrate CS1 is sufficiently long, the damage to the substrate CS1 can be reduced. This is considered to be because the external force EF1 applied to the substrate CS1 can be reduced by positioning the screw BOL away from the substrate CS1. However, in this case, there is a problem that the installation area of ​​the electronic device is large due to the long distance between the screw BOL and the substrate CS1.

[0189] <Detailed structure of the housing>

[0190] Therefore, the inventors of the present application have studied the technology of reducing the mounting area while suppressing the damage of the substrate CS1 and found the following method. Fig.14 As shown, the following method is used: the external force EF1 applied to the substrate CS1 is mitigated by thickening the thickness of the adhesive material BD1 sandwiched between the substrate CS1 and the support portion HSF of the frame HS. As mentioned above, the adhesive material BD1 is formed of a low-elastic material such as silicone rubber. Therefore, when the external force EF1 is applied to the adhesive material BD1, the adhesive material BD1 formed of a low-elastic material is deformed compared to the substrate CS1, so that the direction of the external force EF1 is dispersed. In other words, the component of the external force EF1 that acts in a direction that may cause damage to the substrate CS1 is mitigated by the deformation of the adhesive material BD1. The above-mentioned component that acts in a direction that may cause damage to the substrate CS1 is, for example, a component in the thickness direction (Z direction) of the substrate CS1. The thickness direction of the substrate CS1 refers to Fig.12The direction from one side to the other side among the upper surface CSt and the lower surface CSb of the substrate CS1 shown. In other words, the thickness direction of the substrate CS1 refers to the direction intersecting the two directions of the X direction and the Y direction. The degree of mitigation of the external force EF1 by the adhesive material BD1 increases in direct proportion to the amount of the adhesive material BD1. Therefore, in the side CSe3 and the side CSe4 of the substrate CS1, by increasing the amount of the adhesive material BD1 sandwiched between the substrate CS1 and the frame HS, the damage of the substrate CS1 can be suppressed.

[0191] Increasing the amount of adhesive material BD1 interposed between the substrate CS1 and the frame body HS at the side CSe3 and the side CSe4 of the substrate CS1 can be achieved by the following method. Fig.16 Yes means Fig.14 The enlarged cross-sectional view of the adhesive material before deformation is shown in FIG. Fig.17 It means Fig.16 The flange portion shown is an enlarged cross-sectional view of the periphery of the adhesive material of the flange portion on the opposite side.

[0192] Fig.16 The lower surface Hf1 and the upper surface Hf2 shown constitute Fig.11 The upper surface and the lower surface of the flange portion FLG on the side HSe3 of the two flange portions FLG shown. Fig.11 Among the through holes THH shown, the through hole (first hole) THH formed on the side HSe3 is an opening extending from one of the lower surface Hf1 and the upper surface Hf2 to the other. Fig.17 The lower surface Hf3 and the upper surface Hf4 shown constitute Fig.11 The upper surface and the lower surface of the flange portion FLG on the side HSe4 of the two flange portions FLG shown. Fig.11 Among the through holes THH shown, the through hole (second hole) THH formed on the side HSe4 is an opening extending from one of the lower surface Hf3 and the upper surface Hf4 to the other.

[0193] like Fig.16As shown, the support portion HSF of the frame HS has a lower surface (surface, mounted surface, flange lower surface) Hf1 constituting the lower surface HSb of the frame HS (lower surface of the flange FLG), and an upper surface (surface, screw insertion surface, flange upper surface) Hf2 located on the opposite side of the lower surface Hf1. In addition, the support portion HSF of the frame HS is located at a height between the lower surface Hf1 and the upper surface Hf2 with the lower surface Hf1 as a reference plane, and a portion thereof has a step surface (surface, substrate holding surface) Hf6 opposite to the upper surface CSt of the substrate CS1. At this time, by increasing the interval between the step surface Hf6 and the upper surface CSt of the substrate CS1, that is, the distance D1, the amount (thickness) of the adhesive material BD1 sandwiched between the substrate CS1 and the frame HS in the side CSe3 of the substrate CS1 is increased.

[0194] In addition, as indicated Fig.16 The periphery of the flange portion FLG on the opposite side of the flange portion FLG shown in FIG. Fig.17 As shown, the support portion HSF of the frame HS has a lower surface (surface, mounted surface, flange lower surface) Hf3 constituting the lower surface HSb of the frame HS (lower surface of the flange FLG), and an upper surface (surface, screw insertion surface, flange upper surface) Hf4 located on the opposite side of the lower surface Hf3. In addition, the support portion HSF of the frame HS is located at a height between the lower surface Hf3 and the upper surface Hf4 with the lower surface Hf3 as a reference plane, and a portion thereof has a step surface (surface, substrate holding surface) Hf8 opposite to the upper surface CSt of the substrate CS1. At this time, by increasing the interval between the step surface Hf8 and the upper surface CSt of the substrate CS1, that is, the distance D2, the amount (thickness) of the adhesive material BD1 sandwiched between the substrate CS1 and the frame HS in the side CSe4 of the substrate CS1 is increased. Fig.16 and Fig.17 In the example shown, the distance D1 and the distance D2 are equal to each other, for example, the same as the thickness of the substrate CS1, which is about 0.5 mm. Fig.13 Among the plurality of metal patterns MP shown, the thickness of the metal pattern MP for the semiconductor chip SC1 is greater. Furthermore, in the example of this embodiment, the thicknesses (length in the Z direction, film thickness) of the plurality of metal patterns MP are equal, for example, about 0.3 mm. Moreover, the thickness of the metal pattern MP can be applied to various variations. Therefore, for example, in the case where the thickness of the metal pattern is thick, there is also a possibility that Fig.16 The distance D1 shown and / or Fig.17 The distance D2 shown is smaller than the thickness of the metal pattern MP.

[0195] also, Fig.16 The distance D1 and Fig.17 The magnitude of each distance D2 shown can be expressed as follows. That is, Fig.12 The plurality of semiconductor chips SC1 shown have a front surface SCt and a back surface SCb. In the thickness direction of the substrate CS1, that is, in the Z direction, Fig.16 The step surface Hf6 of the frame HS shown is located at Fig.12 The height between the surface SCt and the back surface SCb of the semiconductor chip SC1 shown in FIG. Fig.17 The step surface Hf8 of the frame HS shown is located at Fig.12 The height between the front surface SCt and the back surface SCb of the semiconductor chip SC1 is shown.

[0196] In addition, if Fig.16 and Fig.17 As shown, in this embodiment, in the thickness direction of the substrate CS1, that is, in the Z direction, the lower surface Hf1 (and Fig.17 The lower surface Hf3 shown in the figure is located at a height between the upper surface CSt of the substrate CS1 and the lower surface MPb of the metal pattern MPB. In other words, at least a portion of the metal pattern MPB formed on the lower surface CSb of the substrate CS1 is located at a height between the upper surface CSt of the substrate CS1 and the lower surface MPb of the metal pattern MPB. Fig.17 The lower surface Hf3) shown in FIG. 1 is an extended surface that protrudes from the upper surface CSt toward the lower surface CSb. Fig.16 The distance D1 and Fig.17 As the distance D2 shown increases, the amount (thickness in the Z direction) of the adhesive material BD1 interposed between the substrate CS1 and the frame body HS increases.

[0197] In addition, Fig.16 and Fig.17 In the X direction shown in FIG. 1 , as a method of increasing the amount (thickness) of the adhesive material BD1 sandwiched between the substrate CS1 and the frame body HS, there is also a method of increasing the amount (thickness) of the adhesive material BD1 sandwiched between the substrate CS1 and the frame body HS. Fig.16 The distance P1 and Fig.17 The method of increasing the distance P2 shown in FIG. Fig.16 As shown, the support portion HSF of the frame HS is connected to the lower surface Hf1 of the frame HS, and a part thereof has an inner side surface Hsi3 facing the side surface (short side surface) Css3 of the substrate CS1. Fig.16 In the example shown, the inner side surface Hsi3 is connected to the lower surface Hf1 and the step surface Hf6 respectively. Fig.17 As shown, the support portion HSF of the frame HS is connected to the lower surface Hf3 of the frame HS, and a part thereof has an inner side surface Hsi4 opposite to the side surface (short side surface) Css4 of the substrate CS1. Fig.17 In the example shown, the inner side surface Hsi4 is connected to the lower surface Hf3 and the step surface Hf8 respectively. Fig.16As shown in FIG. 1 , the distance P1 between the inner side surface Hsi3 and the side surface Css3 of the substrate CS1 increases, the amount of adhesive material BD1 can be increased between the inner side surface Hsi3 and the side surface Css3 of the substrate CS1. Fig.17 As shown, the distance P2 between the inner side surface Hsi4 and the side surface Css4 of the substrate CS1 increases, the amount of adhesive material BD1 can be increased between the inner side surface Hsi4 and the side surface Css4 of the substrate CS1. Fig.16 The distance P1 and Fig.17 When the distance P2 shown in FIG. 1 increases, the installation area of ​​the electronic device EA1 increases. Therefore, from the perspective of reducing the installation area, it is preferable that the distances P1 and P2 are small. Fig.16 The distance D1 shown is greater than the distance P1, Fig.17 The distance D2 shown is greater than the distance P2.

[0198] However, if Fig.18 As shown, step surfaces Hf5, Hf6, Hf7, and Hf8 are provided on the lower surface HSb side of the frame body HS in the present embodiment so as to surround the housing portion PKT. Fig.18 Yes means Fig.11 A bottom view of the lower surface side of the frame shown. Fig.19 and Fig. 20 It is along Fig.18 An enlarged cross-sectional view showing the periphery of the step difference surface in an enlarged manner in the cross-section taken along the line AA of FIG. Fig.18 In order to show the range of each surface of the support portion HSF of the frame HS, although it is a bottom view, different hatching lines are added to each of the multiple surfaces. Fig.18 Indicated by dotted line Fig.11 The outline of the substrate CS1 is shown.

[0199] like Fig.18 As shown, the frame HS has the following sides when viewed from above. First, the frame HS has, at its outermost periphery, a side (long side) HSe1 extending (extending) in the X direction, a side (long side) HSe2, and a side (long side) HSe3 intersecting the X direction ( Fig.18 The frame HS has a side (short side) HSe3 extending (extending) in the Y direction (orthogonal to the center), and a side (short side) HSe4. In addition, the frame HS has the following sides on the inner side of each side of the outermost periphery. That is, the frame HS has a side (long side) HSe5 extending in the X direction and located between the side HSe1 and the side HSe2, and a side (long side) HSe6 extending in the X direction and located between the side HSe5 and the side HSe2. In addition, the frame HS has a side (short side) HSe7 extending in the Y direction and located between the side HSe3 and the side HSe4, and a side (short side) HSe8 extending in the Y direction and located between the side HSe7 and the side HSe4.

[0200] In addition, in a top view, the substrate CS1 is accommodated in the accommodation portion PKT of the frame HS in the following manner. That is, the side (long side) CSe1 of the substrate CS1 extends along the side HSe1 of the frame HS and is arranged between the side HSe1 and the side HSe5. The side (long side) CSe2 of the substrate CS1 extends along the side HSe2 of the frame HS and is arranged between the side HSe2 and the side HSe6. The side (short side) CSe3 of the substrate CS1 extends along the side HSe3 of the frame HS and is arranged between the side HSe3 and the side HSe7. The side (short side) CSe4 of the substrate CS1 extends along the side HSe4 of the frame HS and is arranged between the side HSe4 and the side HSe8.

[0201] In addition, the frame HS has a lower surface (surface, mounted surface) Hf9 located between the side HSe1 and the side CSe1, a lower surface (surface, mounted surface) Hf10 located between the side HSe2 and the side CSe2, a lower surface Hf1 located between the side HSe3 and the side CSe3, and a lower surface Hf3 located between the side HSe4 and the side CSe4. These surfaces respectively constitute the lowermost surface of the frame HS, i.e., the lower surface HSb.

[0202] In addition, the frame HS has a step surface (surface, substrate holding surface) Hf5 extending along the X direction and having a portion located between the side HSe5 and the side CSe1; a step surface (surface, substrate holding surface) Hf7 extending along the X direction and having a portion located between the side HSe6 and the side CSe2. In addition, the frame HS has a step surface (surface, substrate holding surface) Hf6 extending along the Y direction and having a portion located between the side HSe7 and the side CSe3; and a step surface (surface, substrate holding surface) Hf8 extending along the Y direction and having a portion located between the side HSe8 and the side CSe4.

[0203] also, Fig.18 In the example shown, the frame HS has: step surfaces (surfaces, substrate holding surfaces) Hf11, Hf5 and Hf12 arranged in sequence along the X direction and each including an edge HSe5; and step surfaces (surfaces, substrate holding surfaces) Hf13, Hf7 and Hf14 arranged in sequence along the X direction and each including an edge HSe6. The step surfaces Hf5, Hf6, Hf7, Hf8, Hf11, Hf12, Hf13 and Hf14 each have a thickness direction of the substrate CS1 and a thickness direction of the substrate CS1 (see Fig.16 ) relative part.

[0204] In other words, the upper surface CSt of the substrate CS1 (see Fig.13) is opposite to any one of the step surfaces Hf5, Hf6, Hf7, Hf8, Hf11, Hf12, Hf13 and Hf14 over the entire circumference. In addition, an adhesive material BD1 (see Fig.16 ). In this way, when the outermost periphery of the substrate CS1 is opposite to the step difference surface throughout the entire periphery, the substrate CS1 can be stably held.

[0205] Here, as mentioned above Fig.16 and Fig.17 As shown, when the distance D1 and the distance D2 are increased, it can be considered to Fig.19 and Fig. 20 The distances D3 and D4 shown are also Fig.16 and Fig.17 However, when the distances D1, D2, D3, and D4 are set to equal large values, it is known that the position accuracy of the substrate CS1 is reduced due to the influence of the deviation of the coating amount of the adhesive material BD1. For example, Fig.18 In the embodiment, when the position of the substrate CS1 is too close to the side HSe3 of the frame HS as a whole, Fig.16 The distance P1 shown is narrowed, and the bonding material BD1 between the inner side surface Hsi3 and the side surface Css3 of the substrate CS1 is insufficient. In addition, for example, when the position of the substrate CS1 is too close to the side HSe4 of the frame HS as a whole, Fig.17 The distance P2 shown in the figure is narrowed, and the adhesive material BD1 between the inner side surface Hsi4 and the side surface Css4 of the substrate CS1 is insufficient. In addition, for example, if the amount of adhesive material BD1 applied is excessive at a portion between each of the step difference surfaces Hf5, Hf6, Hf7 and Hf8 and the upper surface CSt of the substrate CS1, it becomes Fig.18 The reason why the substrate CS1 shown is accommodated in the accommodation portion PKT in an inclined state. Fig.16 , Fig.17 , Fig.19 or Fig. 20 Each step surface Hf5, Hf6, Hf7 and Hf8 shown in any one of the above is ideally parallel to the upper surface CSt of the substrate CS1. However, when the substrate CS1 is tilted, each step surface is not parallel to the upper surface CSt of the substrate CS1.

[0206] As shown in the example, when the position accuracy of the substrate CS1 in the receiving portion PKT of the frame HS is reduced, it can be considered that the amount of the adhesive material BD1 is insufficient in a part of the peripheral area of ​​the substrate CS1. Fig.18In the vicinity of the through hole THH shown in FIG. 1 , an adhesive material BD1 (see Fig.16 ) is insufficient, it becomes a cause for applying a large external force to the substrate CS1.

[0207] Therefore, the inventors of the present application have studied a technique for suppressing damage to the substrate CS1 and improving the position accuracy of the substrate CS1 in the receiving portion PKT of the frame HS. Fig.14 The damage to the substrate CS1 caused by the screws BOL shown in the figure is likely to occur in the long side direction of the frame HS, that is, Fig.18 Therefore, for example, on the step surface Hf5 and the step surface Hf7 extending in the X direction, regardless of the adhesive material BD1 (refer to Fig.19 The inventors of the present application have focused on this point and invented the following technology: by intentionally reducing the amount of adhesive material BD1 in an area where it is difficult to damage the substrate CS1 even if the amount of adhesive material BD1 is small, the position accuracy of the substrate CS1 in the receiving portion PKT of the frame HS is improved.

[0208] That is, if we compare Fig.16 and Fig.19 It can be seen that in the electronic device EA1 of this embodiment, Fig.16 The distance D1 between the upper surface CSt of the substrate CS1 and the step surface Hf6 of the frame HS is shown in FIG. Fig.19 The distance D3 between the upper surface CSt of the substrate CS1 and the step surface Hf5 of the frame HS is large. Fig.16 The height (distance D1) from the upper surface CSt of the substrate CS1 to the step surface Hf6 of the frame HS is greater than that from Fig.19 The height (distance D3) from the upper surface CSt of the substrate CS1 to the step surface Hf5 of the frame HS is large. Fig.19 The distance D3 between the upper surface CSt of the substrate CS1 and the step surface Hf5 of the frame body HS is reduced. Fig.19 and Fig. 20 In the example shown, Fig.19 The distance D3 and Fig. 20 The distance D4 shown is respectively Fig.19 The distance P3 and Fig. 20 The distance P4 shown is about the same as that shown, for example, about 0.2 mm. Fig.19 The distance D3 and Fig. 20The distance D4 shown is smaller than the thickness of the substrate CS1 (the distance from one of the upper surface CSt and the lower surface CSb to the other). Therefore, when the substrate CS1 and the frame HS are bonded and fixed, the substrate CS1 is not easily tilted. Fig.19 and Fig. 20 In a modification of the example shown, the distance D3 and the distance D4 may be further reduced. For example, the distance D3 and the distance D4 may be less than 0.1 mm. In this case, the distance D3 and the distance D4 are smaller than the thickness of the metal pattern MP formed on the upper surface CSt of the substrate CS1.

[0209] Furthermore, Fig.19 The distance P3 and Fig. 20 The distance P4 shown can be defined as follows. Fig.19 As shown, the support portion HSF of the frame body HS is connected to the lower surface Hf9 of the frame body HS, and a part thereof has an inner side surface Hsi1 facing the side surface (long side surface) Css1 of the substrate CS1. Fig.19 In the example shown, the inner side surface Hsi1 is connected to the lower surface Hf9 and the step surface Hf5 respectively. Fig. 20 As shown, the support portion HSF of the frame body HS is connected to the lower surface Hf10 of the frame body HS, and a part thereof has an inner side surface Hsi2 facing the side surface (long side surface) Css2 of the substrate CS1. Fig. 20 In the example shown, the inner side surface Hsi2 is connected to the lower surface Hf10 and the step surface Hf7 respectively. Fig.19 The distance P3 shown is the distance between the inner side surface Hsi1 and the side surface Css1 of the substrate CS1. Fig. 20 The distance P4 shown is the distance between the inner side surface Hsi2 and the side surface Css2 of the substrate CS1. From the perspective of reducing the installation area of ​​the electronic device EA1, it is preferred that the distance P3 and the distance P4 are as small as possible. In this embodiment, the distance P3 and the distance P4 are respectively Fig.16 The distance P1 and Fig.17 The distance P2 is shown to have the same value.

[0210] In addition, if Fig.18 As shown, the step surface Hf5 is separated from the step surface Hf6 and the step surface Hf8. In other words, in the X direction, the step surface Hf11 is arranged between the step surface Hf6 and the step surface Hf5. Therefore, the step surface Hf5 is far away from the through hole THH. For example, Fig.19The cross section shown is a cross section obtained by cutting along an imaginary line connecting the center of the side HSe1 of the frame HS and the center of the side HSe5. Therefore, the step surface Hf5 is located in the middle of the two through holes THH in the X direction. In other words, the step surface Hf5 includes the midpoint of the side HSe5 of the frame HS. In this way, even at a position far from the through hole THH, Fig.19 If the distance D3 shown is smaller, use Fig.14 The influence of the external force EF1 is also small. Fig.19 Even when the distance D3 shown is small, damage to the substrate CS1 is unlikely to occur.

[0211] In addition, when configured at Fig.18 In the layer difference surface Hf6 near the through hole THH shown in FIG. Fig.16 As shown in FIG. 1 , the distance D1 between the upper surface CSt of the substrate CS1 and the step surface Hf6 of the frame HS is large. Fig.18 )Insert screw BOL (refer to Fig.14 ) and screwed in, it is also possible to Fig.16 The external force EF1 (see Fig.14 ) is dispersed, thereby being able to suppress damage to the substrate CS1.

[0212] In addition, in the above, for the comparison Fig.16 and Fig.19 The composition of Fig.16 The structure and Fig.17 The structure around the step difference surface Hf8 shown is the same. Fig.19 The structure and Fig. 20 The structure around the step difference surface Hf7 shown in FIG. 1 is the same. Therefore, repeated descriptions of all the structures are omitted. Fig.16 and Fig. 20 Comparison Fig.17 and Fig.19 comparison, or Fig.17 and Fig. 20 The same relationship holds true for comparisons of Fig.17 and Fig.19 It can be seen that in the electronic device EA1 of this embodiment, Fig.17 The distance D2 between the upper surface CSt of the substrate CS1 and the step surface Hf8 of the frame HS is Fig.19 The distance D3 between the upper surface CSt of the substrate CS1 and the step surface Hf5 of the frame HS is large. Fig.18) insert screw BOL (refer to Fig.14 ) and screw it in, it is also possible to Fig.17 The external force EF1 (see Fig.14 ) are dispersed, so the damage to the substrate CS1 can be suppressed.

[0213] In addition, for example, Fig.16 and Fig. 20 It can be seen that in the electronic device EA1 of this embodiment, Fig.16 The distance D1 between the upper surface CSt of the substrate CS1 and the step surface Hf6 of the frame HS is shown in FIG. Fig. 20 The distance D4 between the upper surface CSt of the substrate CS1 and the step surface Hf7 of the frame HS is large. Fig.18 ), the upper surface CSt of the substrate CS1 is Fig.18 The step surface Hf5 and the step surface Hf7 shown in the figure are both supported. In this way, since the substrate CS1 is supported at multiple positions separated from each other, the posture of the substrate CS1 is stable. In other words, the angle formed by the multiple step surfaces of the frame HS and the upper surface CSt of the substrate CS1 becomes easy to control. Therefore, the multiple step surfaces of the frame HS and the upper surface CSt of the substrate CS1 are arranged in a manner relative to each other in a roughly parallel state (a state that can be substantially regarded as parallel). In this case, as Fig.11 As shown, when viewed from the bottom surface CSb side of the substrate CS1, the center point of the bottom surface CSb of the substrate CS1 and the center point of the receiving portion PKT are roughly consistent. In addition, when viewed from the bottom surface CSb side of the substrate CS1, the interval between the substrate CS1 and the frame HS ( Fig.16 The distance P1, Fig.17 The distance P2, Fig.19 The distance P3 and Fig. 20 The distance P4 shown is substantially the same value, so that the variation in the amount of the adhesive material BD1 can be reduced.

[0214] also, Fig.18 Among the plurality of step surfaces shown, the step surfaces arranged in the long side direction become, for example, Fig.21 The structure shown. Fig.21 It is along Fig.18 The enlarged cross-sectional view showing the relationship between the step surface and the substrate in the cross section along the BB line of FIG. Fig.21 Is has Fig.18 The enlarged cross-sectional view of the layer difference surface of the edge HSe5 has Fig.18 The structure of the layer difference surface of the edge HSe6 shown is the same, so Fig.21The reference numerals of the step difference surfaces having the edge HSe6 are added in the following description. Fig.18 The structure of the layer difference surface of the edge HSe5 is described, and the structure of the layer difference surface having Fig.18 Illustration of the structure of the step surface of edge HSe6 shown.

[0215] like Fig.21 As shown, the frame HS has a step surface Hf11 (or step surface Hf13), which is located between the step surface Hf6 and the step surface Hf5 (or step surface Hf7) in the X direction, and is opposite to the upper surface CSt of the substrate CS1 via the adhesive material BD1 in the Z direction. In addition, the distance D5 between the upper surface CSt of the substrate CS1 and the step surface Hf11 (or step surface Hf13) of the frame HS is greater than the distance D3 (or distance D4) between the upper surface CSt of the substrate CS1 and the step surface Hf5 (or step surface Hf7) of the frame HS. In addition, Fig.21 In the example shown, the step surface Hf11 (or the step surface Hf13) is connected to the step surface Hf6, and the distance D5 is the same as the distance D1. Fig.18 A sufficient amount of adhesive material BD1 is arranged between the step surface Hf11 (or step surface Hf13) arranged closest to the step surface Hf6 on the short side among the multiple step surfaces of the side HSe5 (or side HSe6) shown and the upper surface CSt of the substrate CS1.

[0216] In addition, the frame HS has a step surface Hf12 (or step surface Hf14), which is located between the step surface Hf8 and the step surface Hf5 (or step surface Hf7) in the X direction, and is opposite to the upper surface CSt of the substrate CS1 via the adhesive material BD1 in the Z direction. In addition, the distance D6 between the upper surface CSt of the substrate CS1 and the step surface Hf12 (or step surface Hf14) of the frame HS is greater than the distance D3 (or distance D4) between the upper surface CSt of the substrate CS1 and the step surface Hf5 (or step surface Hf7) of the frame HS. In addition, Fig.21 In the example shown, the step surface Hf12 (or the step surface Hf14) is connected to the step surface Hf8, and the distance D6 is the same as the distance D2. Fig.18 A sufficient amount of adhesive material BD1 is arranged between the step surface Hf12 (or step surface Hf14) arranged closest to the step surface Hf8 on the short side among the multiple step surfaces of the side HSe5 (or side HSe6) shown and the upper surface CSt of the substrate CS1.

[0217] <Method for manufacturing electronic device>

[0218] Next, for the use Figure 1 to Figure 21 The manufacturing process of the electronic device EA1 described in the present invention is as follows: Fig. 22 The process flow shown is described below. Fig. 22 Yes means Fig.13 An explanatory diagram of the assembly process of the electronic device shown.

[0219] <Substrate preparation>

[0220] first, Fig. 22 In the substrate preparation step shown, Fig.23 The substrate CS1 is shown. Fig.23 is through Fig. 22 A cross-sectional view of a substrate prepared in the substrate preparation step shown. Fig.23 Along with Fig.11 The cross section shown corresponds to the A-A line.

[0221] The substrate CS1 prepared in this step has an upper surface (front surface, main surface, surface) CSt which is a chip mounting surface for mounting a plurality of semiconductor chips SC1 and a lower surface (rear surface, main surface, surface) CSb located on the opposite side of the upper surface CSt. The substrate CS1 is a ceramic substrate formed of a ceramic material.

[0222] In addition, a plurality of metal patterns MP are bonded to the upper surface CSt and the lower surface CSb of the substrate CS1. These plurality of metal patterns MP are, for example, a laminated film formed by laminating a nickel (Ni) film on the surface of a copper (Cu) film, and a copper film is directly bonded to the upper surface CSt or the lower surface CSb of the substrate CS1. When a copper film is bonded to a plate formed of ceramics such as alumina, bonding is performed using a eutectic reaction. In addition, a method of laminating a nickel film on the surface of a copper film can use, for example, an electroplating method.

[0223] In addition, since the types and layouts of the plurality of metal patterns MP are as described above, repeated descriptions will be omitted.

[0224] <Chip Mounting>

[0225] then, Fig. 22 In the chip mounting process shown in FIG. Fig.24 As shown in FIG. 1 , a plurality of semiconductor chips SC1 are mounted on the metal pattern MP of the substrate CS1 . Fig.24 It means in Fig.23 The cross-sectional view shows a state where a plurality of semiconductor chips are mounted on a substrate.

[0226] In this process, if you use Fig.13 As described above, the high-side potential E1 (see Figure 3) is provided with a plurality of (three in this embodiment) semiconductor chips SCH and a plurality of (three in this embodiment) semiconductor chips SC2. In addition, one semiconductor chip SC1 and one semiconductor chip SC2 are respectively provided on the metal patterns MPU, MPV, and MPW connected to the output terminal of the alternating current among the plurality of metal patterns MP. In addition, among the plurality of metal patterns MP, a low-side potential E2 (see Figure 3 ) The semiconductor chip SC1 is not mounted on the metal pattern MPL. In addition, the semiconductor chips SC1 and SC2 are not mounted on the plurality of metal patterns MPT for connecting the input / output terminals LD among the plurality of metal patterns MP.

[0227] In addition, if Fig.24 As shown, in this process, a plurality of semiconductor chips SC1, SC2 (refer to Fig.13 ) are mounted in a so-called face-up mounting manner with the back surface SCb of the semiconductor chips SC1 and SC2 facing the upper surface MPt of the metal pattern MP. In addition, a collector electrode CP (see Figure 5 ), a cathode CDP is formed on the back side SCb of the semiconductor chip SC2 (refer to Figure 8 ), in order to electrically connect the collector electrode CP and the cathode electrode CDP to the metal pattern MP, the semiconductor chips SC1 and SC2 are mounted via a conductive adhesive material (chip solder material, conductive member, connecting member, bonding material) SD. In this embodiment, an example in which solder is used as the conductive adhesive material SD is described.

[0228] The semiconductor chips SC1 and SC2 are mounted via the conductive adhesive material SD as solder (see Fig.13 ) is performed as follows. First, paste solder is applied to the area where the semiconductor chip is to be mounted. The paste solder contains solder components and flux components. Next, a plurality of semiconductor chips SC1, SC2 (see Fig.13 )( Fig. 22The semiconductor chip preparation step shown in the figure) is performed, and they are pressed respectively on the paste solder. In a state where a plurality of semiconductor chips SC1 are temporarily bonded to the metal pattern MP via the paste solder, the solder is subjected to a reflow treatment (heating treatment). The reflow treatment is performed, for example, in a heating furnace in a vacuum state (decompression state) (such a reflow treatment is called a vacuum reflow treatment). Through the reflow treatment, the solder melts, and one side is bonded to the metal pattern MP, and the other side is bonded to the electrode on the back side SCb of the semiconductor chips SC1 and SC2. Then, when the solder is cooled to solidify, the semiconductor chips SC1 are fixed on the metal pattern MP, respectively. In addition, afterwards, since there is a case where the residue of the flux component remains around the solidified conductive adhesive material SD, the substrate CS1 is cleaned to remove the residue.

[0229] In addition, when chip components (electronic components, functional elements) other than the semiconductor chip SC1 such as capacitors are mounted in addition to the semiconductor chips SC1 and SC2, they can be mounted together in this step.

[0230] The above is an example of the chip mounting process, and various modifications are applicable. For example, the state of the bonding portion between the semiconductor chips SC1 and SC2 and the metal pattern MP may be inspected by non-destructive inspection.

[0231] <Wire bonding>

[0232] Then, in Fig. 22 In the wire bonding process shown in FIG. Fig.25 As shown, the semiconductor chip SC1 and the metal pattern MP are electrically connected via a wire (conductive member) BW. Fig.25 It means in Fig.24 The cross-sectional view shows a semiconductor chip connected with wires.

[0233] If used Fig.13 As described above, in this process, the emitter EP (see Figure 4 ) is connected to one of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW via a plurality of wires BW. In addition, the emitter EP of the semiconductor chip SCL for the low side is connected to the metal pattern MPL via a plurality of wires BW. In addition, the semiconductor chip SCH for the high side and the semiconductor chip SCL for the low side each have a gate GP (refer to Figure 4 ) are electrically connected to the metal pattern MPT via wires BW.

[0234] In addition, the anode ADP (see Figure 7) is connected to the metal pattern MPU, the metal pattern MPV or one of the metal patterns MPW and the output metal pattern MPT via a plurality of wires BW. In addition, the anode ADP of the semiconductor chip SC2 for the low side is connected to the metal pattern MPL via a plurality of wires BW.

[0235] Fig.13 The multiple wires BW shown are metal wires, and in this embodiment, they are formed of aluminum, for example. However, there are various modifications of the material of the wires BW, and gold or copper can be used in addition to aluminum. Furthermore, in this embodiment, an example of using a wire as a component for electrically connecting the semiconductor chip SC1 and the metal pattern MP is shown, but as a modification, a metal formed in a strip shape (for example, an aluminum strip) can also be used. In addition, or alternatively, a metal plate (copper clip) formed with a pattern can also be used and connected via solder.

[0236] The above is an example of the wire bonding process, and various modifications are applicable. For example, the state of the bonding portion between the wire BW and the bonded portion may be inspected.

[0237] <Terminal mounting>

[0238] then, Fig. 22 In the terminal mounting process shown in FIG. Fig.26 As shown in FIG. 1 , terminals LD are mounted on a plurality of metal patterns MP. Fig.26 It means in Fig.25 The sectional view of the substrate shown in FIG. 1 is a state where a plurality of terminals are mounted on the substrate. The terminal LD ​​is a lead terminal for electrically connecting a plurality of metal patterns to an external device (not shown), and one end portion of the terminal LD ​​is connected to the metal pattern MP. Fig.25 In the example shown, the plurality of terminals LD are mounted on the metal pattern MP via a conductive adhesive material SD.

[0239] also, Fig.13 In the example shown, the metal pattern MPH supplied with a high potential and the metal pattern MPL supplied with a low potential among the plurality of metal patterns MP are provided with terminals LD at both ends in the long side direction (side CSe3 and side CSe4 as short sides). In addition, one terminal LD ​​is provided on each of the plurality of metal patterns MPT. In addition, the terminal LD ​​is not directly connected to each of the metal pattern MPU, the metal pattern MPV, and the metal pattern MPW.

[0240] Furthermore, although Fig.26Although the illustration is omitted, when connecting a plurality of terminals LD together, it is preferable to use a fixture (not shown) for holding the plurality of terminals LD. For example, if the plurality of terminals LD are connected to each other via a bracket frame (not shown), the plurality of terminals LD can be held together by using a fixture to hold the bracket frame. In this case, the plurality of terminals LD can be separated by cutting the bracket frame after connecting the plurality of terminals LD.

[0241] <Frame Installation>

[0242] then, Fig. 22 In the frame installation process shown in FIG. Fig. 27 As shown, the frame body HS is installed so as to surround the periphery of the substrate CS1, and the substrate CS1 and the frame body HS are fixed via an adhesive material BD1. Fig. 27 It is indicated schematically in Fig.26 2. A cross-sectional view of the process of mounting the frame on the substrate shown in FIG. In this process, the support portion HSF of the frame HS is bonded and fixed so as to cover the peripheral portion of the upper surface CSt of the substrate CS1. The peripheral portion of the upper surface CSt of the substrate CS1 and the support portion HSF of the frame HS are bonded and fixed via the adhesive material BD1.

[0243] In addition, in this process, Fig. 27 As shown, it is preferable to mount the substrate CS1 on the frame HS in a state where the substrate CS1 is turned upside down in the Z direction. Fig. 27 In the example shown, the frame HS is first fixed to the support stand STG with the step surfaces Hf5 and Hf7 of the frame HS facing upward. Next, the adhesive material BD1 is applied to the step surfaces Hf5 and Hf7 of the frame HS. Fig. 27 , a state where the adhesive material BD1 is applied to the step surfaces Hf5 and Hf7 of the frame body HS is representatively shown. However, in this process, Fig.18 The step difference surfaces Hf5, Hf6, Hf7, Hf8, Hf11, Hf12, Hf13 and Hf14 shown are each coated with an adhesive material BD1.

[0244] Then, if Fig. 27 As schematically indicated by the blank arrow in the figure, the upper surface CSt of the substrate CS1 is pressed against the support part HSF of the frame HS. As a result, the BD1 applied on each step surface is deformed and spreads between the step surface of the substrate CS1 and the frame HS. After the adhesive material BD1 is cured in this state, the peripheral portion of the upper surface CSt of the substrate CS1 and the step surface of the support part HSF of the frame HS are bonded and fixed via the adhesive material BD1.

[0245] According to the method of this embodiment, since the adhesive material BD1 is applied with each layer difference surface facing upward, even when the viscosity of the adhesive material BD1 is low, the adhesive material BD1 is not easy to spread to the surroundings. In other words, the degree of freedom in the material selection of the adhesive material BD1 is high. In addition, if the viscosity of the adhesive material BD1 before curing is low, the adhesive material BD1 is easy to infiltrate and spread when the substrate CS1 is pressed against the frame HS. In this case, Fig.18 It is difficult for gaps or voids to remain between the step surfaces and the substrate CS1. That is, according to this embodiment, it is easy to control the amount of the adhesive material BD1 interposed between the substrate CS1 and the frame body HS.

[0246] If used Fig.14 As described above, the adhesive material BD1 has the function of dispersing the external force EF1 transmitted from the frame HS to the substrate CS1 when the electronic device EA1 is mounted. Furthermore, by controlling the amount of the adhesive material BD1 interposed between the substrate CS1 and the frame HS, damage to the substrate CS1 can be stably suppressed.

[0247] <Sealing>

[0248] Then, in Fig. 22 In the sealing process shown in FIG. Fig.12 As shown, a sealing material MG is supplied into the space surrounded by the substrate CS1 and the frame HS to seal a portion of each of the plurality of terminals LD, the plurality of semiconductor chips SC1, and the plurality of wires BW. Fig.12 The sealing process is performed in the state of the cover portion (cover material, cover) HST shown. Fig. 27 As shown in FIG. 1 , an opening is provided inside the support portion HSF of the frame HS. Therefore, in this embodiment, a gel-like sealing material MG is filled from the opening to seal the frame HS. Fig.13 Shown are a plurality of semiconductor chips SC1, SC2 and a plurality of wires BW.

[0249] In addition, when a gel-like sealing material MG with relatively high fluidity is used as in the present embodiment, if there is a gap between the support portion HSF of the frame HS and the bonding portion of the substrate CS1 (the contact interface between the adhesive material BD1 and the substrate CS1 or the frame HS), the sealing material MG may leak out from the gap. Therefore, from the viewpoint of preventing leakage of the sealing material MG, it is preferable that the upper surface CSt of the substrate CS1 and the substrate CS1 are close to each other. Fig.18 The spacing between the different layers is small. Fig.18 Among the various step difference surfaces shown, the step difference surface with the largest distance from the upper surface CSt of the substrate CS1 is used. Fig.14 and Fig.15 As described above, the part with little damage to the substrate CS1, for example Fig.19 The distance D3 and Fig. 20 As shown in the figure, the distance D4 is reduced between the step surface and the substrate CS1.

[0250] In addition, as described above, in the frame installation process, if the viscosity of the adhesive material BD1 before curing is low, the adhesive material is easy to infiltrate and diffuse, so it is not easy to produce a gap in the bonding part between the supporting part HSF of the frame HS and the substrate CS1 (the contact interface between the adhesive material BD1 and the substrate CS1 or the frame HS).

[0251] <Cover Installation>

[0252] Then, in Fig. 22 In the sealing process shown in FIG. Fig.12 As shown in the figure, a cover HST is installed on the upper part of the frame HS to cover the area sealed by the sealing material MG. By covering the area sealed by the sealing material MG with the cover HST, it is possible to prevent foreign matter from intruding into the internal space of the frame HS. A plurality of through holes are formed in the cover HST of the frame HS, and a plurality of terminals LD are respectively inserted into the plurality of through holes (not shown).

[0253] The cover HST and the support HSF are fixed, for example, via an adhesive material (not shown). Alternatively, the cover HST may be placed on the receiving portion PKT (see FIG. 1 ) of the support HSF without using an adhesive material. Fig.12 As long as the position of the cover HST is not misaligned on the support portion HSF, even if it is not completely fixed, it is possible to prevent foreign matter from intruding into the internal space of the frame body HS.

[0254] Through the above processes, it can be used Figure 3 to Figure 21 After that, necessary inspections and tests such as appearance inspection and electrical test are carried out before shipment. Fig.14 As shown on the substrate BP1. Fig. 22 A variation of the invention may also include the following: Fig.14 The steps on the substrate BP1 shown above are used as a method for manufacturing an electronic device.

[0255] The invention completed by the inventor is specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the scope of the gist thereof. Furthermore, several modified examples are described in the above embodiments, and representative modified examples other than the modified examples described in the above embodiments are described below.

[0256] <Variation 1>

[0257] For example, in the above embodiment, using Fig.21Describes the Fig.18 The structure example of the step surface along the side HSe5 and the step surface along the side HSe6 is shown, but there are various modifications. Fig.28 and Fig.29 Respectively, they represent Fig.21 An enlarged cross-sectional view of a modified example.

[0258] Fig.28 The electronic device EA2 and Fig.29 The shape of the step surface extending along the long side direction of the frame HS of each of the electronic devices EA3 shown in the figure is similar to Fig.21 The electronic arrangement EA1 shown is different.

[0259] Fig.28 The frame HS of the electronic device EA2 shown has a step surface Hf11 (or step surface Hf13), which is located between the step surface Hf5 (or step surface Hf7) and the step surface Hf6 in the X direction and is opposite to the upper surface CSt of the substrate CS1 via the adhesive material BD1 in the Z direction. The step surface Hf11 (or step surface Hf13) is a curved surface extending in the X direction in a manner connecting the step surface Hf5 (or step surface Hf7) and the step surface Hf6.

[0260] In addition, the frame HS has a step surface Hf12 (or a step surface Hf14), which is located between the step surface Hf8 and the step surface Hf5 (or the step surface Hf7) in the X direction and is opposite to the upper surface CSt of the substrate CS1 via the adhesive material BD1 in the Z direction. The step surface Hf12 (or the step surface Hf14) is a curved surface extending in the X direction in a manner connecting the step surface Hf5 (or the step surface Hf7) and the step surface Hf8.

[0261] In the case of the electronic device EA2, the values ​​of the distance D5 and the distance D6 change gradually. In other words, there is no inflection point where the distance D5 (or the distance D6) changes sharply in the path from the step surface Hf6 (or the step surface Hf8) to the step surface Hf5 (or the step surface Hf7). Therefore, at the flange portion FLG of the frame body HS (refer to Fig.14 )When deformation occurs, it is difficult to create a location where strong force is applied locally.

[0262] Furthermore, although the illustration is omitted, as a relative Fig.28 In a modified example, the step surfaces Hf11, Hf12, Hf13 and Hf14 may be inclined surfaces inclined relative to a reference plane parallel to the step surface Hf5. Fig.21 Compared with the electronic device EA1 shown in FIG. 1 , the flange portion FLG (refer to FIG. 1 ) of the frame body HS is Fig.14) is deformed, it is difficult to generate a location where a strong force is applied locally. However, since a stronger force may be applied to the portion where the inclined surface and the horizontal surface intersect than to other portions, it is preferred to Fig.28 The surface shown is a curved surface.

[0263] Although not shown in the figure, Fig.21 The same is true for the electronic device EA1 shown. Fig.28 In the case of the electronic device EA2 shown in FIG. 1 , the step surface Hf5 (or the step surface Hf7) is also located between the two through holes THH (see FIG. 1 ) in the X direction. Fig.18 ). In other words, Fig.18 The step surface Hf5 (or the step surface Hf7 ) shown includes the midpoint of the side HSe5 (or the side HSe6 ) of the frame HS.

[0264] also, Fig.29 The electronic device EA3 shown in the figure has a frame HS having a plurality of step surfaces Hf5 and a step surface (surface, substrate holding surface) Hf15 arranged in a manner sandwiched between the plurality of step surfaces Hf5. The plurality of step surfaces Hf5 are arranged in the Y direction (refer to Fig.18 ) is located on the edge HSe5 (refer to Fig.18 ) and the edge CSe1 of the substrate CS1 (refer to Fig.18 ) and is opposite to the upper surface CSt of the substrate CS1 via the adhesive material BD1 in the Z direction. In addition, the frame body HS has a plurality of step surfaces Hf7 and step surfaces (surfaces, substrate holding surfaces) Hf16 arranged in a manner sandwiched between the plurality of step surfaces Hf7. The plurality of step surfaces Hf7 extend in the Y direction (refer to Fig.18 ) is located on the edge HSe6 (refer to Fig.18 ) and the edge CSe2 of the substrate CS1 (refer to Fig.18 ) and is opposite to the upper surface CSt of the substrate CS1 via the adhesive material BD1 in the Z direction. In addition, the interval between the upper surface CSt of the substrate CS1 and the step surface Hf15 (or the step surface Hf16) of the frame HS, that is, the distance D7, is greater than the interval between the upper surface CSt of the substrate CS1 and the step surface Hf5 (or the step surface Hf7) of the frame HS, that is, the distance D3 (or the distance D4).

[0265] In other words, in the case of the electronic device EA3, among the step surfaces provided along the long sides of the frame HS, convex portions (step surfaces Hf5 or step surfaces Hf7) are provided at multiple locations. In this case, since the substrate CS1 is supported by the convex portions at multiple locations in the above-mentioned frame installation process, the posture of the substrate CS1 is stable. In other words, it is easy to control the angles formed by the multiple step surfaces of the frame HS and the upper surface CSt of the substrate CS1.

[0266] like Fig.29 As shown, the frame HS has a step surface Hf11 (or step surface Hf13), and the step surface Hf11 (or step surface Hf13) is located between the step surface Hf5 (or step surface Hf7) and the step surface Hf6 that are closest to the step surface Hf6 among the multiple step surfaces Hf5 (or step surface Hf7) in the X direction, and is opposite to the upper surface CSt of the substrate CS1 via the adhesive material BD1 in the Z direction. In addition, the distance D5 between the upper surface CSt of the substrate CS1 and the step surface Hf11 (or step surface Hf13) of the frame HS is greater than the distance D3 (or distance D4) between the upper surface CSt of the substrate CS1 and the step surface Hf5 (or step surface Hf7) of the frame HS. In addition, Fig.29 In the example shown, the step surface Hf11 (or the step surface Hf13) is connected to the step surface Hf6, and the distance D5 is the same as the distance D1. Fig.18 A sufficient amount of adhesive material BD1 is arranged between the step surface Hf11 (or step surface Hf13) arranged closest to the step surface Hf6 on the short side among the multiple step surfaces of the side HSe5 (or side HSe6) shown and the upper surface CSt of the substrate CS1.

[0267] In addition, the frame HS has a step surface Hf12 (or step surface Hf14), which is located between the step surface Hf5 (or step surface Hf7) and the step surface Hf8 that are closest to the step surface Hf8 among the multiple step surfaces Hf5 (or step surface Hf7) in the X direction, and is opposite to the upper surface CSt of the substrate CS1 via the adhesive material BD1 in the Z direction. In addition, the distance D6 between the upper surface CSt of the substrate CS1 and the step surface Hf12 (or step surface Hf14) of the frame HS is greater than the distance D3 (or distance D4) between the upper surface CSt of the substrate CS1 and the step surface Hf5 (or step surface Hf7) of the frame HS. In addition, Fig.29 In the example shown, the step surface Hf12 (or the step surface Hf14) is connected to the step surface Hf8, and the distance D6 is the same as the distance D2. Fig.18 A sufficient amount of adhesive material BD1 is arranged between the step surface Hf12 (or step surface Hf14) arranged closest to the step surface Hf8 on the short side among the multiple step surfaces of the side HSe5 (or side HSe6) shown and the upper surface CSt of the substrate CS1.

[0268] also, Fig.29 The step surface Hf15 (or the step surface Hf16) shown is provided at the middle point of the step surface provided along the long side of the frame body HS. In other words, the step surface Hf15 (or the step surface Hf16) includes Fig.18 The midpoint of the side HSe5 (or the side HSe6) of the frame HS shown in the figure. In this case, since the convex parts are arranged on both sides of the midpoint of the side HSe5 (or the side HSe6), it is easy to stabilize the posture of the substrate CS1.

[0269] also, Fig.29 In the example shown, the distance D7 of the step surface Hf15 (or the step surface Hf16) is the same value as the distance D1. Therefore, in the Z direction, the step surface Hf15 (or the step surface Hf16) is located at Fig.12 The height between the front surface SCt and the back surface SCb of the semiconductor chip SC1 is shown.

[0270] <Variation 2>

[0271] In addition, for example, in the above embodiment, an example using an IGBT as the transistor Q1 constituting the switching element is described. However, as a modified example, a power MOSFET may be used as the switching element of the inverter circuit. In the case of a power MOSFET, a body diode as a parasitic diode is formed in the semiconductor element constituting the transistor. This body diode plays a role in Fig. 9 The diode (flywheel diode) FWD shown in FIG. 1 has the function of a freewheeling diode. Therefore, if a semiconductor chip having a power MOSFET is used, a body diode is built into the semiconductor chip. Therefore, when a power MOSFET is used, one semiconductor chip can be used as a switching element.

[0272] When a power MOSFET is used as a switching element of the inverter circuit, the description of the above embodiment can be applied by replacing the emitter with the source and the collector with the drain. Therefore, repeated descriptions are omitted.

[0273] <Variation 3>

[0274] In addition, for example, in the above embodiment, the size examples of the components of the electronic device EA1 are described as an example, but in addition to the examples described in the above embodiment, various modifications can be applied. Fig.11 The opening diameter (diameter of the circular opening) of the through hole THH shown in the figure is described, and an embodiment in which the opening diameter is larger than the distance between the side HSe1 of the frame HS and the side CSe1 of the substrate CS1 is described. In addition, in the above embodiment, an embodiment in which the shortest distance from the edge of a through hole THH to the sides CSe3 and CSe4 of the substrate CS1 is smaller than the opening diameter of the through hole THH is described. From the viewpoint of improving the fixing strength of the electronic device EA1, it is preferred to Fig.14The diameter of the screw BOL shown is large. Therefore, the above relationship is easily established when the insertion position of the screw BOL is close to the substrate CS1, thereby easily damaging the substrate CS1. However, even in the case of an electronic device with a small opening diameter of the through hole THH, the technology described in the above embodiment and modified example can be applied.

[0275] <Variation 4>

[0276] Furthermore, for example, various modified examples have been described as above, but the modified examples described above can be combined and applied.

[0277] Furthermore, if the technical ideas of the electronic device and the method for manufacturing the electronic device described in the above embodiments are extracted, they can be embodied in the following manner.

[0278] [Supplementary Note 1]

[0279] A method for manufacturing an electronic device, comprising:

[0280] (a) preparing a first substrate having a first surface on which a plurality of semiconductor chips are mounted and on which a first pattern made of metal is formed, and a first back surface located on the opposite side of the first surface and on which a second pattern made of metal is formed;

[0281] (b) fixing the housing via an adhesive material so as to surround the peripheral edge of the first substrate;

[0282] (c) after the step (b), a step of filling the housing with a sealing material to seal the plurality of semiconductor chips; and

[0283] (d) after the step (c), the step of screwing the housing onto the second substrate in a state where the first back surface of the first substrate and the second substrate face each other with a heat conductive material interposed therebetween,

[0284] When viewed from above from the first back side of the first substrate, the shell has: a first long side extending in a first direction; a second long side extending in the first direction and located on the opposite side of the first long side; a third long side extending in the first direction and located between the first long side and the second long side; a fourth long side extending in the first direction and located between the third long side and the second long side; a first short side extending in a second direction intersecting the first direction; a second short side extending in the second direction and located on the opposite side of the first short side; a third short side extending in the second direction and located between the first short side and the second short side; and a fourth short side extending in the second direction and located between the third short side and the second short side.

[0285] The first substrate has: a fifth long side extending in the first direction and located between the first long side and the third long side; a sixth long side extending along the fifth long side and located between the second long side and the fourth long side; a fifth short side extending along the second direction and located between the first short side and the third short side; a sixth short side extending along the fifth short side and located between the second short side and the fourth short side,

[0286] The shell comprises: a first surface located between the first short side and the fifth short side of the first substrate in a plan view; a second surface located on the opposite side of the first surface in a third direction from one of the first surface and the first back side of the first substrate toward the other; a third surface located between the second short side and the sixth short side of the first substrate in a plan view; a fourth surface located on the opposite side of the third surface in the third direction; a fifth surface located between the third long side and the fifth long side in a plan view and opposite to the first surface of the first substrate across the adhesive material in the third direction; and a sixth surface located between the third short side and the fifth short side in a plan view and opposite to the first surface of the first substrate across the adhesive material in the third direction.

[0287] In the first direction, a first hole is formed between the first short side and the third short side, the first hole extending from one of the first surface and the second surface to the other, and a screw is inserted in the step (d).

[0288] In the first direction, a second hole is formed between the second short side and the fourth short side, the second hole extending from one of the third surface and the fourth surface to the other, and a screw is inserted in the step (d).

[0289] In the third direction, the first surface of the housing is located at a height between the first surface of the first substrate and the back surface of the second pattern.

[0290] A distance between the first surface of the first substrate and the sixth surface of the housing is larger than a distance between the first surface of the first substrate and the fifth surface of the housing.

Claims

1. An electronic device, characterized in that: include: A substrate having a first surface on which a first pattern composed of metal is formed and a first back surface located on the opposite side of the first surface and on which a second pattern composed of metal is formed; a plurality of semiconductor chips mounted on the second surface of the first pattern; a housing fixed to the first surface of the substrate via an adhesive material; and a sealing material that seals the first surface of the substrate and the plurality of semiconductor chips, The second pattern of the substrate has a second back surface facing the same side as the first back surface of the substrate, In a plan view, the shell has: a first long side extending in a first direction; a second long side extending in the first direction and located on the opposite side of the first long side; a third long side extending in the first direction and located between the first long side and the second long side; a fourth long side extending in the first direction and located between the third long side and the second long side; a first short side extending along a second direction intersecting the first direction; a second short side extending in the second direction and located on the opposite side of the first short side; a third short side extending in the second direction and located between the first short side and the second short side; and a fourth short side extending in the second direction and located between the third short side and the second short side. The substrate has: a fifth long side extending in the first direction and located between the first long side and the third long side; a sixth long side extending along the fifth long side and located between the second long side and the fourth long side; a fifth short side extending along the second direction and located between the first short side and the third short side; and a sixth short side extending along the fifth short side and located between the second short side and the fourth short side, The shell comprises: a first surface located between the first short side and the fifth short side of the substrate in a plan view; a second surface located on the opposite side of the first surface in a third direction from one of the first surface and the first back side of the substrate toward the other; a third surface located between the second short side and the sixth short side of the substrate in a plan view; a fourth surface located on the opposite side of the third surface in the third direction; a fifth surface located between the third long side and the fifth long side of the substrate in a plan view and opposite to the first surface of the substrate via the adhesive material in the third direction; a sixth surface located between the third short side and the fifth short side of the substrate in a plan view and opposite to the first surface of the substrate via the adhesive material in the third direction, In the first direction, a first hole is formed between the first short side and the third short side, extending from one of the first surface and the second surface to the other. In the first direction, a second hole is formed between the second short side and the fourth short side, extending from one of the third surface and the fourth surface to the other. In the third direction, the first surface of the housing is located at a height between the first surface of the substrate and the second back surface of the second pattern. A distance between the first surface of the substrate and the sixth surface of the housing is larger than a distance between the first surface of the substrate and the fifth surface of the housing.

2. The electronic device according to claim 1, wherein: In the third direction, a distance between the first surface of the substrate and the sixth surface of the housing is larger than a thickness of the first pattern on which the semiconductor chip is mounted.

3. The electronic device according to claim 1, wherein: A distance between the first surface of the substrate and the fifth surface of the housing is smaller than a thickness of the substrate.

4. The electronic device according to claim 1, wherein: The plurality of semiconductor chips each have a third surface and a third back surface located on an opposite side of the third surface and facing the second surface of the first pattern, In the third direction, the sixth surface of the housing is located at a height between the third surface and the third back surface of the semiconductor chip.

5. The electronic device according to claim 1, wherein: A diameter of the first hole is larger than a length from the first long side of the housing to the fifth long side of the substrate.

6. The electronic device as claimed in claim 1, wherein: The shortest distance from the edge of the first hole to the fifth short side of the substrate is smaller than a diameter of the first hole.

7. The electronic device as claimed in claim 1, wherein: The housing has a seventh surface, the seventh surface is located between the fifth surface and the sixth surface in the first direction, and is opposite to the first surface of the substrate via the adhesive material in the third direction. A distance between the first surface of the substrate and the seventh surface of the housing is larger than a distance between the first surface of the substrate and the fifth surface of the housing.

8. The electronic device as claimed in claim 7, wherein: The shell has an eighth surface and a ninth surface, the eighth surface is located between the fourth short side and the sixth short side in the first direction, and is opposite to the first surface of the substrate in the third direction via the adhesive material; the ninth surface is located between the fifth surface and the eighth surface in the first direction, and is opposite to the first surface of the substrate in the third direction via the adhesive material. The distance between the first surface of the substrate and the eighth surface of the housing is larger than the distance between the first surface of the substrate and the fifth surface of the housing. A distance between the first surface of the substrate and the ninth surface of the housing is larger than a distance between the first surface of the substrate and the fifth surface of the housing.

9. The electronic device as claimed in claim 1, wherein: The housing has a seventh surface, the seventh surface is located between the fifth surface and the sixth surface in the first direction, and is opposite to the first surface of the substrate via the adhesive material in the third direction. The seventh surface is a curved surface extending in the first direction in a manner connecting the fifth surface and the sixth surface.

10. The electronic device as claimed in claim 9, wherein: The shell has an eighth surface and a ninth surface, the eighth surface is located between the fourth short side and the sixth short side in the first direction, and is opposite to the first surface of the substrate via the adhesive material in the third direction; the ninth surface is located between the fifth surface and the eighth surface in the second direction, and is opposite to the first surface of the substrate via the adhesive material in the third direction, The distance between the first surface of the substrate and the eighth surface of the housing is larger than the distance between the first surface of the substrate and the fifth surface of the housing. The ninth surface is a curved surface extending in the second direction in a manner connecting the fifth surface and the eighth surface.

11. The electronic device according to any one of claims 7 to 10, characterized in that: The fifth surface includes a midpoint of the third long side of the housing.

12. The electronic device as claimed in claim 1, wherein: The housing has: a plurality of fifth surfaces, which are located between the third long side and the fifth long side in the second direction and are opposite to the first surface of the substrate via the adhesive material in the third direction; and a tenth surface, which is arranged in a manner of being sandwiched between a plurality of said fifth surfaces, A distance between the first surface of the substrate and the tenth surface of the housing is larger than a distance between the first surface of the substrate and each of the plurality of fifth surfaces of the housing.

13. The electronic device as claimed in claim 12, wherein: The housing has a seventh surface, the seventh surface is located between the fifth surface closest to the sixth surface among the plurality of fifth surfaces in the first direction and the sixth surface, and is opposite to the first surface of the substrate via the adhesive material in the third direction. A distance between the first surface of the substrate and the seventh surface of the housing is larger than a distance between the first surface of the substrate and the fifth surface of the housing.

14. The electronic device according to claim 12 or 13, characterized in that: The tenth face includes a midpoint of the third long side of the shell.

15. The electronic device as claimed in claim 12, wherein: The plurality of semiconductor chips each have a third surface and a third back surface located on an opposite side of the third surface and facing the second surface of the first pattern, In the third direction, the tenth surface of the housing is located at a height between the third surface and the third back surface of the semiconductor chip.

16. The electronic device as claimed in claim 1, wherein: In a plan view viewed from the first rear surface side of the substrate, a first imaginary line connecting a center point of the first hole and a center point of the second hole passes through a center point of the first rear surface of the substrate.

17. The electronic device as claimed in claim 1, wherein: In a plan view from the first back side of the substrate, a portion of the adhesive material is exposed in a gap between the fifth short side of the substrate and the first surface of the housing. A distance between the first surface of the substrate and the sixth surface of the housing is larger than a distance of the gap in which a portion of the adhesive material is exposed.

18. The electronic device as claimed in claim 1, wherein: The housing has an eighth surface, the eighth surface being located between the fourth short side and the sixth short side of the substrate in the first direction and facing the first surface of the substrate via the adhesive material in the third direction. A distance between the first surface of the substrate and the eighth surface of the housing is larger than a distance between the first surface of the substrate and the fifth surface of the housing.

19. The electronic device as claimed in claim 1, wherein: The housing has an eleventh surface, the eleventh surface is located between the fourth long side and the sixth long side of the substrate in the second direction, and is opposite to the first surface of the substrate via the adhesive material in the third direction. A distance between the first surface of the substrate and the sixth surface of the housing is larger than a distance between the first surface of the substrate and the eleventh surface of the housing.

20. An electronic device, characterized in that: include: A substrate having a first surface on which a first pattern composed of metal is formed, a first back surface located on the opposite side of the first surface and on which a second pattern composed of metal is formed, and a plurality of side surfaces located between the first surface and the first back surface; a plurality of semiconductor chips mounted on the second surface of the first pattern; a housing fixed to the first surface of the substrate via an adhesive material; and a sealing material that seals the first surface of the substrate and the plurality of semiconductor chips, The second pattern of the substrate has a second back surface facing the same side as the first back surface of the substrate, In a top view observed from the first back side of the substrate, the shell has: a first long side extending in a first direction; a second long side extending in the first direction and located on the opposite side of the first long side; a third long side extending in the first direction and located between the first long side and the second long side; a fourth long side extending in the first direction and located between the third long side and the second long side; a first short side extending along a second direction intersecting the first direction; a second short side extending in the second direction and located on the opposite side of the first short side; a third short side extending in the second direction and located between the first short side and the second short side; and a fourth short side extending in the second direction and located between the third short side and the second short side. The substrate comprises: a fifth long side extending in the first direction and located between the first long side and the third long side; a sixth long side extending along the fifth long side and located between the second long side and the fourth long side; a fifth short side extending along the second direction and located between the first short side and the third short side; and a sixth short side extending along the fifth short side and located between the second short side and the fourth short side. The shell comprises: a first surface located between the first short side and the fifth short side of the substrate in a plan view; a second surface located on the opposite side of the first surface in a direction from one of the first surface and the first back side of the substrate toward the other, that is, in a third direction; a third surface located between the second short side and the sixth short side of the substrate in a plan view; a fourth surface located on the opposite side of the third surface in the third direction; a fifth surface located between the third long side and the fifth long side in a plan view and opposite to the first surface of the substrate via the adhesive material in the third direction; a sixth surface located between the third short side and the fifth short side in a plan view and opposite to the first surface of the substrate via the adhesive material in the third direction; and a first side surface intersecting the sixth surface and the first surface and connected to the sixth surface and the first surface, In the first direction, a first hole is formed between the first short side and the third short side, extending from one of the first surface and the second surface to the other. In the first direction, a second hole is formed between the second short side and the fourth short side, extending from one of the third surface and the fourth surface to the other. In the first direction, the first side surface of the housing and a second side surface among the plurality of surfaces of the substrate are opposite to each other, A height from the first surface of the substrate to the sixth surface of the housing is greater than a height from the first surface of the substrate to the fifth surface of the housing.

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