electronic devices

Abstract

The present invention provides an electronic device, the purpose of which is to improve the performance of the electronic device. The wiring substrate (10) of the electronic device (EDV1) includes a substrate terminal (12A) connected to a semiconductor device (semiconductor component) (20), a wiring (11A) formed in a first wiring layer and electrically connected to the substrate terminal (12A), a conductor pattern (MPc) formed in a second wiring layer and electrically connected to the wiring (11A) via a via wiring (VWA), and a conductor pattern (MPg) formed in a third wiring layer and supplied with a first fixed potential. The conductor pattern (MPc) and the conductor pattern (MPg) are opposed to each other via an insulating layer, and the area of ​​the region where the conductor pattern (MPc) and the conductor pattern MPg are opposed to each other is larger than the area of ​​the wiring (11A).

Description

Technical Field

[0001] The present invention relates to an electronic device (semiconductor module), and for example, to a technology that is effectively applied to an electronic device in which a semiconductor component is mounted on a wiring substrate. Background Art

[0002] Japanese Patent Application Laid-Open No. 2005-183790 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2005-294528 (Patent Document 2) describe stacking a ground pattern and a wiring pattern with an insulating layer interposed therebetween, and utilizing the layout of the ground pattern to reduce high-frequency noise. Japanese Patent Application Laid-Open No. 2009-21747 (Patent Document 3) describes a bandpass filter comprising a plurality of open-circuit stubs connected to a coplanar line and a capacitor provided at the input end, forming an impedance matching circuit.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2005-183790

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2005-294528

[0007] Patent Document 3: Japanese Patent Application Laid-Open No. 2009-21747 Summary of the Invention

[0008] Semiconductor devices are used in a variety of applications. To ensure stable operation of these devices, technologies are needed to reduce the noise that affects their operation. One method for reducing noise that affects semiconductor device operation is to mount noise suppression components such as capacitors on the wiring substrate on which the semiconductor device is mounted. However, it is known that there is still room for improvement in terms of efficient noise reduction.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] A wiring substrate for an electronic device according to one embodiment includes: a first substrate terminal connected to a semiconductor component; a first wiring formed in a first wiring layer and electrically connected to the first substrate terminal; a first conductor pattern formed in a second wiring layer different from the first wiring layer and electrically connected to the first wiring via a first via wiring; and a second conductor pattern formed in a third wiring layer different from the first and second wiring layers and supplied with a first fixed potential. The first and second conductor patterns are opposed to each other via an insulating layer, and the area of ​​the region where the first and second conductor patterns oppose each other is larger than the area of ​​the first wiring.

[0011] Effects of the Invention

[0012] According to the embodiment described above, the performance of an electronic device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is an enlarged plan view showing a structural example of an electronic device according to one embodiment.

[0014] Figure 2 It will Figure 1 The equivalent circuit diagram shows the electrical connection path of the sensor and the amplifier circuit.

[0015] Figure 3 It is along Figure 1 An enlarged cross-sectional view of line AA is shown.

[0016] Figure 4 is extracted Figure 1 The diagram is an overlaid top view showing wiring connected to the sensor, substrate terminals, and a conductor pattern connected to the wiring.

[0017] Figure 5 It means relative to Figure 4 Overlapping top view of a modified example of .

[0018] Figure 6 is relative to Figure 3 An enlarged cross-sectional view of an electronic device according to a modified example of FIG.

[0019] Figure 7 It means in Figure 6 The electronic device shown is relative to Figure 4 Overlapping top view of a modified example of .

[0020] Figure 8 It means relative to Figure 4 Overlapping top views of other variations of .

[0021] Figure 9 It means relative to Figure 1 An enlarged top view of a structural example of an electronic device according to a modified example.

[0022] Figure 10 It will Figure 9 The equivalent circuit diagram shows the path where the amplifier circuit and the analog conversion circuit are electrically connected.

[0023] Figure 11 This is an enlarged plan view showing a configuration example of an electronic device in which EMI countermeasures are implemented for power semiconductor components.

[0024] Figure 12 It will Figure 11 The equivalent circuit diagram shows a path electrically connecting a semiconductor component including an amplifier circuit and a power semiconductor component that supplies power to the semiconductor component.

[0025] Figure 13 It is along Figure 11 An enlarged cross-sectional view of line AA is shown.

[0026] Figure 14 This is an enlarged plan view showing a structural example of an electronic device including a connector and a semiconductor component connected to the connector.

[0027] Figure 15 It is along Figure 14 An enlarged cross-sectional view of line AA is shown.

[0028] Figure 16 It is mounted on Figure 14 An enlarged top view of the capacitor periphery on the opposite side of the lower surface.

[0029] Figure 17 It is along Figure 16 An enlarged cross-sectional view of line A-A.

[0030] Figure 18 yes Figure 14 The equivalent circuit diagram of the electronic device shown.

[0031] Figure 19 This is an enlarged plan view showing a configuration example of an electronic device in which a bandpass filter is connected between a transmitting circuit and a receiving circuit.

[0032] Figure 20 yes Figure 19 The equivalent circuit diagram of the electronic device shown.

[0033] Figure 21 It is along Figure 19 An enlarged cross-sectional view of line AA is shown.

[0034] Figure 22 This is an enlarged plan view showing a configuration example of an electronic device in which a high-pass filter is connected between a transmitting circuit and a receiving circuit.

[0035] Figure 23 yes Figure 22 The equivalent circuit diagram of the electronic device shown.

[0036] Figure 24 It is along Figure 22 An enlarged cross-sectional view of line AA is shown.

[0037] Figure 25 Is to use Figures 1 to 24 An enlarged cross-sectional view of a modified example of the capacitor described.

[0038] Description of Reference Numerals

[0039] 10, 10A wiring substrate

[0040] 10b Lower surface (front, main surface, back surface)

[0041] 10t top surface (face, main surface, surface)

[0042] 11, 11A, 11B, 11D, 11G, 11L, 11P, 11R, 11T, 11T1, 11T2, 11W1, 11W2 wiring

[0043] 11BP resistor connection

[0044] 11L1, 11L2, 11L3, 11L4, 11L5, 11L6, 11L7, 11L8, 11L9, 11L10, 11L11 extensions

[0045] 11VP, 11VP1, 11VP2, VP3 channel junction

[0046] 12, 12A, 12B, 12N, 12P, 12T, 13, 13A, 13H, 13L, 13R1, 13R2, 15, 15T, 16, 16P, 17, 17D, 17G, 18, 18D, 18G, 19, 19D, 19G, 111R, 211T Substrate terminals (bonding wires, bonding fingers, pads, lands)

[0047] 14, 14A, 14B, 14C insulation layer

[0048] 20, 50, 60, 70, 100, 200 Semiconductor devices (semiconductor parts, electronic parts)

[0049] 21 semiconductor chips

[0050] 22, 22A, 22B, 22N, 22P, 22T, 51T, 61, 61P, 71, 71D, 71G, 81, 81D, 81G, 101R, 201T terminals (leads)

[0051] 30 Sensors (electronic components)

[0052] 30E1, 30E2 electrodes

[0053] 40 Resistor parts (electronic parts)

[0054] 40E1, 40E2, 40E3, 40E4, 40E5, 40E6 electrodes

[0055] 72 Circuit

[0056] 80 Connectors (electronic components)

[0057] 90 Capacitors (capacitor parts, chip capacitors)

[0058] 91, 91D, 91G electrodes

[0059] 92 Main body

[0060] 93 Insulation layer (dielectric layer)

[0061] 94 Conductor Plate

[0062] 102 Receiving Circuit

[0063] 202 Transmitting Circuit

[0064] AC1, AC2, AC3, AC4, AC5, AC6 capacitors

[0065] ADC1AD conversion circuit (analog-to-digital conversion circuit, AD converter)

[0066] AL1, AL2, AL3, AL4, AL5, AL6 inductors

[0067] AR1, AR2, AR3, AR4, AR5, AR6 resistors

[0068] EDV1, EDV2, EDV3, EDV4, EDV5, EDV6, EDV7, EDV8, EDV9, EDV10 electronic devices

[0069] INV inverter (power conversion circuit)

[0070] LE1 Length

[0071] MP1, MP2, MPc, MPc1, MPc2, MPg, MPG, MPG1, MPG2, MPr, MPt conductor pattern

[0072] MPh opening (through hole)

[0073] MPs1, MPs2 long side (side)

[0074] MPs3, MPs4, MPs5 short side (side)

[0075] MPs6 Edge

[0076] MWD2 channel routing

[0077] NF1, NF2, NF3, NF4 noise filters (low-pass filters)

[0078] NF5 Noise Filter (Bandpass Filter)

[0079] NF6 Noise Filter (High Pass Filter)

[0080] OP1 amplifier circuit (operational amplifier)

[0081] OWR area

[0082] PS external power supply

[0083] R1, R2 resistor elements

[0084] SD solder

[0085] VW, VW1, VW2, VWA, VWB, VWD, VWD1, VWD2, VWG, VWH, VWL, VWLG, VWP, VWR, VWT Via wiring (interlayer conductive circuit)

[0086] W1, W2 width

[0087] WL1, WL2, WL3, WL4, WL5, WL6, WL7 wiring layers DETAILED DESCRIPTION

[0088] (Description format, basic terms, and usage of this application)

[0089] In this application, the description of the embodiments may be divided into multiple parts for ease of description as needed, but unless otherwise expressly stated, these parts are not independent of each other. Regardless of the preceding or following position of the description, one part of a single example may be a detailed description of another part or a partial or complete modification. In principle, repeated descriptions of the same parts are omitted. In addition, the various structural elements in the embodiments are not required, unless otherwise expressly stated, theoretically not limited to the number, or clearly not required from the context.

[0090] Similarly, in the description of the embodiments, etc., regarding materials, composition, etc., even if "X composed of A" is mentioned, unless it is specifically stated otherwise or it is clear from the context that it is not the case, it does not exclude the inclusion of elements other than A. For example, in terms of composition, it means "X containing A as a main component" etc. For example, even if "silicon components" are mentioned, it is not limited to pure silicon, and of course includes SiGe (silicon germanium) alloys or other multi-component alloys with silicon as the main component, and materials containing other additives. In addition, even if gold plating, Cu layer, nickel plating, etc. are mentioned, unless it is specifically stated otherwise or it is specifically stated that it is not the case, it includes not only pure plating materials but also materials with gold, Cu, nickel, etc. as the main components.

[0091] Moreover, when referring to a specific numerical value or quantity, the numerical value may be a value exceeding the specific numerical value or a value less than the specific numerical value, except where it is specifically stated otherwise, where it is not theoretically limited to the quantity, or where it is clear from the context that it is not the case.

[0092] In addition, in each drawing of the embodiment, the same or similar parts are denoted by the same or similar symbols or reference numerals, and in principle, the description thereof will not be repeated.

[0093] In the accompanying drawings, hatching and other lines may be omitted even for cross-sections when the illustration is cumbersome or when the distinction from voids is clear. Relatedly, when this is clear from the description, the outline of the background may be omitted even for a hole that is closed on a plane. Furthermore, hatching or dot patterns may be added even for non-cross-sections to clearly indicate that the hole is not a void or to clearly indicate the boundaries of a certain area.

[0094] Noise Countermeasures

[0095] As semiconductor devices (semiconductor parts) become smaller and more sophisticated, they are being incorporated into various electronic devices (equipment) and used as control components. For example, in automobiles and motorcycles with engines, these devices are used to control various components, including drive control of powertrains such as engines and motors, operation control of various components that transmit power to tires, control of optical components such as lighting and signal lights, and control of sensors that monitor the operating status of various components.

[0096] Control systems using semiconductor devices like those described above are constructed by mounting multiple electronic components, including the semiconductor device, on a substrate and electrically connecting them to each other. In this case, it is crucial to implement noise suppression measures for the electronic devices so that the electronic components mounted on the substrate do not interfere with each other's operations.

[0097] Noise countermeasures for electronic devices can be roughly divided into the following two categories. One is to reduce the degree to which the operation of the target electronic component is affected by electromagnetic waves generated by circuits located around the target electronic component or outside the electronic device (EMS: Electro Magnetic Susceptibility). This EMS countermeasure can be said to be a measure to improve the noise resistance of the target electronic component. The other is to reduce the degree to which the operation of other circuits is hindered (obstructed) by the operation of the target electronic component (EMI: Electro Magnetic Interference). EMI countermeasures can be said to be a measure to reduce the impact of noise originating from the target electronic component.

[0098] In the following embodiments, for the purpose of EMS countermeasures or EMI countermeasures, embodiments in which a filter circuit for filtering noise is formed on a wiring board on which electronic components are mounted will be described in order by giving a plurality of specific examples.

[0099] (Implementation 1)

[0100] In this first embodiment, as an example of EMS countermeasures, a low-pass filter is connected to the transmission path electrically connecting an electronic component (sensor component) including a sensor and a semiconductor component including an amplifier circuit that amplifies the output signal from the sensor. Furthermore, the following description illustrates an embodiment using a thermistor that measures temperature changes as a sensor. However, electronic components such as sensor components that transmit input signals to circuits such as amplifier circuits include a variety of other components besides thermistors.

[0101] Figure 1 It is an enlarged plan view showing a structural example of an electronic device according to one embodiment. Figure 2 yes Figure 1 The equivalent circuit diagram of the electronic device shown. Figure 3 It is along Figure 1 An enlarged cross-sectional view of line AA is shown.

[0102] Figure 1 In FIG, the conductor pattern MPc, the conductor pattern MPg, and the via wiring VW as the interlayer conductive circuit formed on a wiring layer different from the wiring layer on which the wiring 11 is formed are indicated by dotted lines. Figure 1 In FIG, the semiconductor chip 21 built into the semiconductor device 20 is indicated by a dotted line. Figure 1 A portion of the wiring connected to the plurality of substrate terminals 12 is shown, and the other portion is omitted. Figure 1 In FIG. 1 , a circuit diagram of the amplifier circuit OP1 included in the semiconductor device 20 is schematically shown by a two-dot chain line. Figure 2 , a simplified non-inverting amplifier circuit is shown as an example of an amplifier circuit. However, there are various modified examples of the amplifier circuit, such as an inverting amplifier circuit and a differential amplifier circuit.

[0103] like Figure 1As shown, the electronic device EDV1 of this embodiment is a structure in which a plurality of components (electronic components) such as a semiconductor device 20, a sensor 30, and a resistor component 40 are mounted on a wiring substrate 10 serving as a base material, and the components are electrically connected via conductive members such as wiring 11. The electronic device EDV1 includes the semiconductor device (semiconductor component, electronic component) 20, the sensor (electronic component) 30, and the resistor component (electronic component) 40 mounted on the upper surface 10t of the wiring substrate 10.

[0104] In the present embodiment, the sensor 30 is, for example, a temperature sensor (thermistor), an electronic component having a sensor element whose resistance value changes according to the ambient temperature. Furthermore, the semiconductor device 20 is an electronic component having an amplifier circuit (operational amplifier) ​​OP1 that receives and amplifies the signal (temperature detection signal) output from the sensor 30. The amplifier circuit OP1 is an integrated circuit formed on the semiconductor chip 21 included in the semiconductor device 20. Furthermore, the sensor 30 and the resistor component 40 are each a sheet-like component having two electrodes located on opposite sides of each other. The sensor 30 has an electrode 30E1 and an electrode 30E2 located on opposite sides of each other. The resistor component 40 has an electrode 40E1 and an electrode 40E2 located on opposite sides of each other.

[0105] The semiconductor device 20 also includes a plurality of terminals 22 serving as external terminals. The plurality of terminals (leads) 22 include a terminal 22A to which the signal output from the sensor 30 is input. Terminal 22A is connected to the non-inverting input terminal of the amplifier circuit OP1. Furthermore, the plurality of terminals 22 include a terminal 22B connected to the inverting input terminal of the amplifier circuit OP1. Furthermore, the plurality of terminals 22 include a terminal 22T connected to the output terminal of the amplifier circuit OP1. Furthermore, the plurality of terminals 22 include a terminal 22P that forms a transmission path for supplying a high-side potential (e.g., a positive potential) to the amplifier circuit OP1. Furthermore, the plurality of terminals 22 include a terminal 22N that forms a transmission path for supplying a low-side potential (e.g., a negative potential or ground potential) lower than the high-side potential to the amplifier circuit OP1.

[0106] The semiconductor device 20 is mounted on the upper surface 10t of the wiring substrate 10. The plurality of terminals 22 of the semiconductor device 20 and the plurality of substrate terminals 12 of the wiring substrate 10 are electrically connected to each other.

[0107] The wiring substrate 10 has an upper surface (surface, main surface, top surface) 10t and a lower surface (surface, main surface, back surface) 10b (see FIG. 1 ) located on the opposite side of the upper surface 10t. Figure 3 ).also, Figure 1 and Figure 3, a plurality of wirings 11 and a plurality of substrate terminals 12 and 13 are formed on the upper surface 10t of the wiring substrate 10, and their conductor patterns are exposed. However, an insulating film (protective film, solder resist film) covering the conductor patterns such as the plurality of wirings 11 may be formed on the upper surface 10t. In this case, an opening is formed in the insulating film covering the upper surface 10t, and a part or the whole of each of the plurality of substrate terminals 12 and 13 is exposed from the insulating film. Similarly, Figure 3 As shown, the conductor pattern MPG is formed and exposed on the lower surface 10b of the wiring substrate 10. However, an insulating film (protective film, solder resist film) may be formed on the lower surface 10b to cover the conductor pattern MPG.

[0108] Furthermore, the wiring substrate 10 includes a plurality of substrate terminals (bonding wires, bonding fingers, pads, lands) 12 connected to the plurality of terminals 22 of the semiconductor device 20. The plurality of substrate terminals 12 include a substrate terminal 12A to which a signal output from the sensor 30 is input. Figure 3 In the example shown, terminal 22A of semiconductor device 20 is bonded and electrically connected to substrate terminal 12A via solder SD. Furthermore, the plurality of substrate terminals 12 include substrate terminal 12B connected to the inverting input terminal of amplifier circuit OP1. Furthermore, the plurality of substrate terminals 12 include substrate terminal 12T connected to the output terminal of amplifier circuit OP1. Furthermore, the plurality of substrate terminals 12 include substrate terminal 12P, which forms a transmission path for supplying a high-side potential (e.g., a positive potential) to amplifier circuit OP1. Furthermore, the plurality of substrate terminals 12 include substrate terminal 12N, which forms a transmission path for supplying a low-side potential (e.g., a negative potential or ground potential) lower than the high-side potential to amplifier circuit OP1.

[0109] The wiring substrate 10 also includes a plurality of substrate terminals 13 on which the sensor 30 or the resistor component 40 is mounted. The plurality of substrate terminals 13 include a substrate terminal 13A to which the electrode 30E1 of the sensor 30 and the electrode 40E1 of the resistor component 40 are connected. The output-side electrode 30E1 of the sensor 30 is bonded to the substrate terminal 13A via a bonding material such as solder (not shown). The electrode 40E1 of the resistor component is bonded to the substrate terminal 13A via a bonding material such as solder (not shown). Furthermore, the plurality of substrate terminals 13 include a substrate terminal 13L, which is connected to the electrode 30E2 of the sensor 30 and supplies a low-side reference potential to the sensor 30. A reference potential, such as ground potential (GRAND potential), is supplied to the substrate terminal 13L via a via wiring VWL. Furthermore, the plurality of substrate terminals 13 include a substrate terminal 13H, which is connected to the electrode 40E2 of the resistor component 40 and supplies a high-side reference potential to the resistor component 40. A reference potential, such as a potential higher than ground potential, is supplied to the substrate terminal 13H via a via wiring VWH.

[0110] Furthermore, the wiring substrate 10 includes a plurality of wirings 11 connected to a plurality of substrate terminals 12. The plurality of wirings 11 include a wiring 11A connected to the substrate terminal 12A. The signal output from the sensor 30 is input to the amplifier circuit OP1 of the semiconductor device 20 via the electrode 30E1 serving as the output terminal, the substrate terminal 13A, the wiring 11A, the substrate terminal 12A, and the terminal 22A. Furthermore, the plurality of wirings 11 include a wiring 11B connected to the substrate terminal 12B. The wiring 11B is connected to the substrate terminal 12B via the electrode 30E1 serving as the output terminal, the substrate terminal 13A, the wiring 11A, the substrate terminal 12A, and the terminal 22A. Figure 2 The resistor element R2 is electrically connected to the substrate terminal 12T. The plurality of wirings 11 include a wiring 11T connected to the substrate terminal 12T. The output signal of the amplifier circuit OP1 is input to the wiring 11T via the terminal 22T, which is an external terminal of the semiconductor device 20, and the substrate terminal 12T of the wiring substrate 10.

[0111] When a signal is amplified by the amplifier circuit OP1 as in the electronic device EDV1, it is preferable to filter the noise of the signal before amplification, that is, the signal before input to the amplifier circuit OP1. Figure 2 As shown, the electronic device EDV1 has a noise filter (low-pass filter) NF1 including a resistor AR1, an inductor AL1, and a capacitor AC1 connected between a substrate terminal 13A, which is an output terminal of the sensor 30, and a substrate terminal 12A, which is an input terminal of the amplifier circuit OP1.

[0112] When connecting a filter circuit such as the noise filter NF1, it is necessary to prepare Figure 2 In the method shown, electronic components corresponding to resistor AR1, inductor AL1, and capacitor AC1 are mounted on wiring substrate 10. However, as the number of electronic components mounted on wiring substrate 10 increases, the layout constraints of the components and wiring become greater, which increases the area of ​​wiring substrate 10. In addition, when discrete devices (components with a single function) are aggregated, since the interference between each component and other components is not considered, interference between components may become a new source of noise.

[0113] Therefore, the inventors of the present application have studied a technique for forming the noise filter NF1 using a conductor pattern formed on the wiring substrate 10. First, Figure 2 The resistor AR1 and inductor AL1 shown can be used Figure 1The wiring 11A shown in the figure can be replaced. Specifically, by adjusting the length (extension distance) and width (length in a direction perpendicular to the extension direction, which is the longitudinal direction) of the wiring 11A, the wiring 11A can be given the functions of the resistor AR1 and the inductor AL1. However, the function of the capacitor AC1 is difficult to give to the wiring 11A because it affects the planar area of ​​the electrodes arranged opposite each other through the dielectric.

[0114] For example, as relative to Figure 1 In this study example, where via wiring VWA and conductor pattern MPc are not connected to wiring 11A, and wiring 11A itself is considered an RLC filter circuit, the values ​​of the components of the RLC filter circuit are as follows. Specifically, under the calculation conditions described below, the resistance value of substrate terminal 12A of the RLC filter circuit is 32.82 mΩ (milliohms), the inductance value is 2.62 nH (nanohenry), and the capacitance value is 0.53 pF (picofarad). The calculation conditions for these values ​​are as follows. Figure 1 The length of the wiring 11A shown (path distance from the substrate terminal 13A to the substrate terminal 12A) is 5 mm, the width (length in the Y direction of the extension 11L1) is 0.4 mm, and the thickness ( Figure 3 The length in the Z direction shown) is 60 μm.

[0115] In the case of the aforementioned RLC circuit, the output power is half the frequency of the passband, i.e., the cutoff frequency is approximately 4.25 GHz (gigahertz). However, in automotive electronic devices, for example, the frequency of noise that could affect the signal output from sensor 30 is approximately between 150 kHz (kilohertz) and 2 GHz. Therefore, an RLC filter circuit with a cutoff frequency of approximately 4.25 GHz is difficult to use as a noise filter for frequencies between 150 kHz and 2 GHz. In other words, a noise filter used in the frequency band between 150 kHz and 2 GHz requires a cutoff frequency of at least 2 GHz.

[0116] As a method to lower the cutoff frequency, increase Figure 2 However, in order to increase the value of capacitor AC1, it is necessary to increase the plane area of ​​the electrodes arranged opposite to each other through the dielectric. Figure 1 If the plurality of wirings 11 shown are provided on the same layer as the conductor pattern constituting the capacitor AC1 , the area of ​​the wiring board 10 will increase.

[0117] In the case of the electronic device EDV1, as Figure 3 As shown, the wiring substrate 10 is a multilayer wiring substrate having a plurality of wiring layers WL1, WL2, WL3, and WL4. Figure 2 The conductor patterns MPc and MPg of the capacitor AC1 shown are formed on wiring layers WL2 and WL3 that are different from the wiring layer WL1 on which the wiring 11A is formed.

[0118] like Figure 3 As shown, the wiring substrate 10 has a wiring layer WL1 provided with wirings 11A. Figure 1 The plurality of wirings 11 shown are also formed on the wiring layer WL1 in the same manner as the wiring 11A. Thus, by providing the plurality of wirings 11 on the same wiring layer WL1, the wiring path distance can be shortened. Figure 3 In the example shown, substrate terminals 12A and 13A are also formed on the wiring layer WL1. In other words, the wiring 11A is formed on the top layer among the plurality of wiring layers provided on the wiring substrate 10. However, as a modification, Figure 1 The substrate terminals 12 and 13 are provided on the uppermost layer, and the wirings 11 are provided on the wiring layer below the uppermost layer. In this case, the wirings 11 and the substrate terminals 12 are connected via via wirings VW serving as interlayer conductive circuits.

[0119] Furthermore, the electronic device EDV1 includes a conductor pattern MPc formed on a wiring layer WL3 different from the wiring layer WL1 and electrically connected to the wiring 11A via the via wiring VWA. Furthermore, the electronic device EDV1 includes a conductor pattern MPg formed on a wiring layer WL2 different from the wiring layer WL1 and the wiring layer WL3 and supplied with a fixed potential. Figure 3 In the example shown, a conductor pattern (ground plane) MPG is provided for supplying a ground potential to the wiring layer WL4, and the conductor pattern MPg is electrically connected to the conductor pattern MPG via the via wiring VWG. Therefore, a ground potential (ground potential) is supplied to the conductor pattern MPg. The conductor pattern MPG covers substantially the entire lower surface 10b of the wiring substrate 10. In addition, the conductor pattern MPc and the conductor pattern MPg are opposed to each other via the insulating layer 14. In the region where the conductor pattern MPc and the conductor pattern MPg are opposed to each other, an insulating layer 14 is formed. Figure 2 Capacitor AC1 is shown.

[0120] In addition, the conductor patterns MPc and MPg are formed in wiring layers other than the wiring layer WL1, and therefore are not easily affected. Figure 1 Therefore, the area of ​​the conductor patterns MPc and MPg can be increased. Figure 1 As shown, the area of ​​the region where the conductor pattern MPc and the conductor pattern MPg face each other is larger than the area of ​​the wiring 11A. Figure 1 In the example shown, the conductor pattern MPc is a quadrilateral (more specifically, a rectangle) with an area of ​​20.16 mm.2 In addition, the conductor pattern MPg is formed in most of the wiring layer WL2 except for the opening MPh provided for the passage of the via wiring VW and the peripheral edge of the wiring substrate 10. Therefore, even taking into account the area of ​​the opening MPh, the area of ​​the region where the conductor pattern MPc and the conductor pattern MPg face each other is approximately 20 mm. 2 On the other hand, since the length of the wiring 11A (the path distance from the substrate terminal 13A to the substrate terminal 12A) is 5 mm and the width (the length of the extension 11L1 in the Y direction) is about 0.4 mm, the area of ​​the wiring 11A is about 2 mm. 2 . Thus, it is possible to increase Figure 2 The capacitance value of capacitor AC1 is shown.

[0121] For example, in Figure 1 and Figure 3 In the case of the layout shown, Figure 2 The resistance value of substrate terminal 12A of noise filter NF1 shown is 36.34 mΩ, the inductance value is 2.73 nH, and the capacitance value is 9.60 pF. These values ​​are calculated under the following conditions. Wiring 11A has a length of 5 mm, a width of 0.4 mm, and a thickness of 60 μm. Furthermore, the thickness of the conductor patterns formed on wiring layers WL2 and WL3 is 35 μm, and the thickness of the conductor pattern formed on wiring layer WL4 is 60 μm. Furthermore, the thickness of insulating layer 14A between wiring layers WL1 and WL2, and the thickness of insulating layer 14B between wiring layers WL3 and WL4 are 600 μm, and the thickness of insulating layer 14C between wiring layers WL2 and WL3 is 100 μm.

[0122] According to the above calculation conditions, Figure 2 The cutoff frequency of the noise filter NF1 shown is 0.98 GHz. With this cutoff frequency, it can be fully utilized as a noise filter in the frequency band of about 150 kHz to 2 GHz. Figure 1 The cutoff frequency can be easily adjusted by adjusting the length, width, thickness of the wiring 11A and the area of ​​the region where the conductor pattern MPc and the conductor pattern MPg face each other.

[0123] For example, Figure 1 The width of the wiring 11A shown is 0.4 mm as described above, but when it is set to 0.1 mm, the noise filter NF1 (see Figure 2 ) The resistance value of the substrate terminal 12A is 69.86 [mΩ], the inductance value is 3.78 [nH], and the capacitance value is 9.56 [pF]. In this case, the cutoff frequency is 0.85 GHz.

[0124] Thus, according to this embodiment, Figure 2 Of the resistor AR1, inductor AL1, and capacitor AC1 constituting the noise filter NF1 shown in FIG. 1 , the conductor pattern MPc constituting the capacitor AC1 (see FIG. 1 ) Figure 3 ) and conductor pattern MPg (refer to Figure 3 ) is formed on the wiring 11A (refer to Figure 1 ) different wiring layers. Therefore, even if the capacitance value of capacitor AC1 is increased to the extent that it can be used as a noise filter, the wiring layer WL1 (refer to Figure 3 ) wiring layout is not easy to cause restrictions. In addition, if Figure 3 As shown, in the case of the electronic device EDV1, the noise filter NF1 is formed by the conductor pattern (including the wiring 11A) of the wiring substrate 10 without adding electronic components for the noise filter (see Figure 2 This reduces the increase in the area of ​​wiring board 10 caused by connecting noise filter NF1. Furthermore, when noise filter NF1 is formed within the conductor pattern of wiring board 10, the design can take into account the electromagnetic influence between noise filter NF1 and other wiring. This prevents the generation of new noise due to unintentional electromagnetic interference between components.

[0125] In addition, as in this embodiment, in suppressing Figure 2 In the example shown, to reduce noise contained in the input signal of amplifier circuit OP1, it is preferable to connect capacitor AC1, which functions as a low-pass filter (noise filter NF1), to the input terminal of amplifier circuit OP1. Shortening the distance between capacitor AC1 and the input terminal of amplifier circuit OP1 can prevent additional noise from being added to the filtered signal.

[0126] In the case of this embodiment, Figure 1 The signal transmitted by the substrate terminal 12A shown is an input signal input to the amplifier circuit OP1 of the semiconductor device 20 via the terminal 22A. In addition, the wiring 11A has an extension portion 11L1 extending along the X direction, and a via junction portion 11VP connected to the via wiring VWA. The via junction portion 11VP is located between the extension portion 11L1 and the substrate terminal 12A when viewed from above. In addition, when viewed from above, the separation distance between the substrate terminal 12A and the via junction portion 11VP is shorter than the extension distance (length) of the extension portion 11L1. That is, the connection Figure 2 The via junction portion 11VP of the capacitor AC1 shown is arranged near the substrate terminal 12A, which is the input end of the amplifier circuit OP1.

[0127] In addition, the structure of this embodiment can also be expressed as follows. That is, a sensor 30 connected to the wiring 11A is mounted on the wiring substrate 10. The signal transmitted to the substrate terminal 12A is a signal output from the sensor 30 and input to the amplifier circuit OP1 of the semiconductor device 20 via the terminal 22A. In addition, the wiring 11A has an extension portion 11L1 extending along the X direction, and a via junction portion 11VP connected to the via wiring VWA. The via junction portion 11VP is located between the extension portion 11L1 and the substrate terminal 12A when viewed from above. In addition, when viewed from above, the separation distance between the sensor 30 and the via junction portion 11VP is longer than the separation distance between the substrate terminal 12A and the via junction portion 11VP. That is, the sensor 30 is connected to the substrate terminal 12A. Figure 2 The via junction portion 11VP of the capacitor AC1 shown is arranged closer to the substrate terminal 12A, which is the input terminal of the amplifier circuit OP1 , than to the substrate terminal 13A, which is the output terminal of the sensor 30 .

[0128] in addition, Figure 2 The capacitance value of capacitor AC1 shown is based on Figure 3 The area of ​​the region where the conductor pattern MPc and the conductor pattern MPg face each other is defined, but for example, Figure 1 When the planar shape of the conductor pattern MPc is a long and narrow shape like the wiring 11A shown, the resistance component and the inductance component given to the conductor pattern MPc increase. From the viewpoint of reducing the resistance component and the inductance component given to the conductor pattern MPc, the conductor pattern MPc is preferably a pattern with a small aspect ratio (length-to-width ratio) when viewed from above. For example, in the case of this embodiment, Figure 4 As shown, the conductor pattern MPc has a long side (side) MPs1 extending in the X direction and a long side MPs2 located on the opposite side of the long side MPs1. Figure 4 is extracted Figure 1 11A is an overlapping top view showing the wiring connected to the sensor, the substrate terminal, and the conductor pattern connected to the wiring. Furthermore, the conductor pattern MPc has a short side MPs3 extending in the Y direction intersecting the X direction, and a short side MPs4 located opposite the short side MPs3. The lengths of the long sides MPs1 and MPs2 are each longer than the lengths of the short sides MPs3 and MPs4. Furthermore, in the Y direction, the separation distance (width W1) between the long sides MPs1 and MPs2 is longer than the width W2 of the extension portion 11L1 of the wiring 11A. In other words, the conductor pattern MPc is wider than the wiring 11A. This reduces the resistance and inductance components imparted to the conductor pattern MPc.

[0129] On the other hand, the wiring 11A has both Figure 2 The functions of resistor AR1 and inductor AL1 are shown, so it is preferred Figure 4 The extension portion 11L1 shown is an elongated shape with a large aspect ratio. Figure 4 In the illustrated example, the length LE1 of the extending portion 11L1 of the wiring 11A in the X direction is longer than the distance (width W1 ) between the long side MPs1 and the long side MPs2 . Figure 4 In the embodiment, the entire length of the wiring 11A is, for example, 5 mm. On the other hand, the width (length in the Y direction) of the extension portion 11L1 of the wiring 11A is 0.4 mm. Therefore, the length of the wiring 11A is at least 10 times the width of the extension portion 11L1 of the wiring 11A.

[0130] In addition, if Figure 4 As shown in FIG. 1 , the conductor pattern MPc overlaps the wiring 11 in a plan view. Specifically, the wiring 11A includes an extension portion 11L1 extending in the X direction and a via wiring VWA (see FIG. 1 ). Figure 3 ) is connected to a via joint portion 11VP. In a plan view, the conductor pattern MPc overlaps with the extension portion 11L1 of the wiring 11A. Thus, when the extension portion 11L1 of the wiring 11A overlaps with the conductor pattern MPc, the layout flexibility is increased when forming conductor patterns other than the conductor pattern MPc on the wiring layer WL2.

[0131] However, if Figure 4 As shown in FIG. 1 , the conductor pattern MPc overlaps the substrate terminal 12P and the wiring 11P connected to the substrate terminal 12P when viewed from above. Figure 1 The amplifier circuit OP1 shown in FIG. 1 provides a transmission path for a high-side potential (eg, a positive potential). Therefore, when other conductor patterns are not interposed between the conductor pattern MPc and the wiring layer WL1 (see FIG. 2 ), the conductor pattern MPc is connected to the wiring layer WL1. Figure 6 ), the potential supplied to the substrate terminal 12P and the wiring 11P sometimes causes an electromagnetic influence on the conductor pattern MPc.

[0132] However, in the case of this embodiment, Figure 3 As shown, a conductor pattern MPg supplied with a fixed potential is interposed between the conductor pattern MPc and the wiring layer WL1. In this case, the conductor pattern MPg functions as a shielding conductor layer that reduces electromagnetic waves directed toward the conductor pattern MPc. When the conductor pattern MPg functions as a shielding conductor layer, as in this embodiment, it is particularly preferable that the potential supplied to the conductor pattern MPg is a ground potential.

[0133] When the conductor pattern MPg as a shield conductor layer is interposed between the wiring layer WL1 and the wiring layer WL3, the degree of freedom of the planar shape of the conductor pattern MPc is improved. Figure 4 As shown, when the planar shape of the conductor pattern MPc is a quadrilateral, Figure 2 The design of the capacitance of the capacitor AC1 shown becomes easy. Figure 4In the example shown, the conductor pattern MPc overlaps with the substrate terminal 12P and the wiring 11P connected to the substrate terminal 12P when viewed from above. However, there is a gap between the substrate terminal 12P and the wiring 11P and the conductor pattern MPc. Figure 3 Therefore, the electromagnetic influence of the substrate terminal 12 and the wiring 11P on the conductor pattern MPc is greatly reduced.

[0134] Furthermore, as in this embodiment, when wiring 11A and conductor pattern MPg are arranged facing each other with insulating layer 14A interposed therebetween, capacitance is formed between wiring 11A and conductor pattern MPg. As described above, the capacitance formed by wiring 11A is not very large. However, as in this embodiment, when capacitance is formed by both conductor pattern MPc and wiring 11A, fine adjustment of the capacitance value becomes easy.

[0135] In addition, when the conductor pattern MPg as a shield conductor layer is interposed between the wiring layer WL1 and the wiring layer WL3, it is also conceivable that Figure 5 A modified example of the electronic device EDV2 is shown. Figure 5 It means relative to Figure 4 The electronic device EDV2 is similar to the modified example in that the conductor pattern MPc overlaps with the substrate terminal 12B and the wiring 11B when viewed from above. Figure 4 The electronic device EDV1 shown is different.

[0136] The substrate terminals 12B and the wiring 11B are formed with Figure 1 The inverting input terminal of the amplifier circuit OP1 shown in FIG. 1 is connected to the transmission path of the input signal. Therefore, a signal current different from that of the substrate terminal 12A and the wiring 11A connected to the non-inverting input terminal flows through the substrate terminal 12B. In the case of the electronic device EDV2, Figure 3 The electronic device EDV1 shown is the same as the one shown in FIG. 1 , in which the conductor pattern MPg is arranged on the wiring layer WL2 and the conductor pattern MPc is arranged on the wiring layer WL3. Figure 5 The conductor pattern MPc shown and the substrate terminal 12B are interposed therebetween. Figure 3 The conductor pattern MPg shown. Figure 5 As shown, even when the conductor pattern MPc overlaps the substrate terminal 12B in a plan view, the electromagnetic influence between the conductor pattern MPc and the substrate terminal 12B can be reduced. In this way, when the wiring layer WL2 in which the conductor pattern MPg is arranged is provided between the wiring layer WL3 in which the conductor pattern MPc is arranged and the wiring layer WL1 in which the wiring 11A is arranged, Figure 1 The layout freedom of the wiring 11 and the conductor pattern MPc shown is improved.

[0137] In addition, as other modified examples of the electronic device EDV1, the following can be exemplified: Figure 6 and Figure 7 The structure of the electronic device EDV3 is shown. Figure 6 is relative to Figure 3 An enlarged cross-sectional view of an electronic device according to a modified example of FIG. Figure 7 It means in Figure 6 The electronic device shown is relative to Figure 4 Overlapping top view of a modified example of .

[0138] Figure 6 The electronic device EDV3 shown in the figure is different from the electronic device EDV3 in that the conductor pattern MPc is arranged between the conductor pattern MPg and the wiring 11A. Figure 3 The electronic device EDV1 shown is different. Figure 7 As shown, the electronic device EDV3 is different from the electronic device EDV3 in that the substrate terminal 12P and the conductor pattern MPc do not overlap when viewed from above. Figure 4 The electronic device EDV1 shown is different. Figure 4 In the case of the electronic device EDV1 shown, the planar shape of the conductor pattern MPc is a rectangle, but there are various modifications of the planar shape of the conductor pattern MPc. Figure 7 In the case of the conductor pattern MPc of the electronic device EDV3 shown, short sides MPs4 and MPs5 are provided on the opposite side of the short side MPs3, and a side MPs6 is provided between the short sides MPs4 and MPs5 in the X direction and between the long sides MPs1 and MPs2 in the Y direction. Figure 7 The conductor pattern MPc shown does not overlap with the substrate terminal 12P when viewed from above. Figure 6 On the other hand, the wiring 11P extends from the substrate terminal 12P in the X direction in the direction opposite to the wiring 11A (in other words, away from the substrate terminal 13A). Figure 6 In the case of the electronic device EDV3, the conductor pattern layout is as described above, so the conductor pattern MPc does not overlap with the wiring 11P connected to the substrate terminal 12P in a plan view.

[0139] As described above, the substrate terminals 12P form a Figure 1 The amplifier circuit OP1 shown in the figure provides a transmission path for a high-side potential (for example, a positive potential). In the case of the substrate terminal 12P for power supply, the substrate terminal 12B for signal (see Figure 1 ) compared to the conductor pattern MPc, the electromagnetic influence is relatively small even when it overlaps with the conductor pattern MPc. Figure 4The electronic device EDV1 shown in FIG. 1 is the same as the one shown in FIG. 1 . In a plan view, the substrate terminal 12P and the wiring 11P may overlap with the conductor pattern MPc. However, from the perspective of further reducing the influence of the potential supplied to the substrate terminal 12P and the wiring 11P on the conductor pattern MPc, as shown in FIG. Figure 7 As shown, it is preferable that the substrate terminals 12P and the wirings 11P do not overlap with the conductor pattern MPc in a plan view.

[0140] In addition, if Figure 3 As shown, in the case of the electronic device EDV1, the via wiring VWA connects the wiring substrate 10 in the thickness direction ( Figure 3 On the other hand, in the Z direction Figure 6 In the case of the electronic device EDV3 shown, the via wiring VWA is not made to penetrate the wiring substrate 10 but is arranged between the wiring layer WL2 and the wiring layer WL1.

[0141] like Figure 3 As shown, the via wiring VWA penetrating the wiring substrate 10 in the thickness direction is formed as follows: after laminating the wiring layers of the wiring substrate 10, a through hole penetrating the wiring substrate 10 in the thickness direction is formed, and a conductor material is embedded in the through hole. Figure 6 As shown, the via wiring VWA that does not penetrate the wiring substrate 10 is formed by, for example, a buildup method.

[0142] like Figure 3 As shown, in the case of via wiring VWA that penetrates the wiring substrate 10 in the thickness direction, the lower end portion of via wiring VWA (the portion between wiring layer WL3 and wiring layer WL4) may function as a stub. In other words, depending on the length of the lower end portion of via wiring VWA, the transmission of signals in a specific frequency band may be hindered by resonance of the stub of via wiring VWA. Figure 2 As shown in FIG, this does not usually become a problem in a transmission path with a low-pass filter inserted. However, when the frequency of the signal is high, from the perspective of suppressing the obstruction of the transmission of the necessary signal, as shown in FIG. Figure 6 As shown in FIG. 1 , it is preferable to use a via wiring VWA that does not penetrate the wiring substrate 10. On the other hand, from the viewpoint of ease of manufacturing, as shown in FIG. Figure 3 As shown, the via wiring VWA penetrating the wiring substrate 10 can be easily formed.

[0143] Hereinafter, in this specification, various via wirings VW will be described, but the shape of the via wiring VW may be as follows. Figure 3 The via wiring VWA shown in FIG. 1 penetrates the wiring substrate 10, or the via wiring VWA shown in FIG. Figure 6The via wiring VWA shown in FIG. 1 does not penetrate the wiring substrate 10. However, in the case of the via wiring VW constituting the bandpass filter or highpass filter described later in the fourth embodiment, the via wiring VW may function as a stub. For example, if Figure 3 In the via wiring VWA shown, if the length of the portion from the wiring layer WL3 to the wiring layer WL4 is 1 / 4 of the wavelength of the frequency to be passed, it will be difficult to pass the frequency band due to resonance. When a bandpass filter or a high-pass filter is connected, it is used to transmit high-frequency signals, so there is a possibility that a stub resonance will occur. Therefore, in the case of via wiring VW constituting a bandpass filter or a high-pass filter, as shown in FIG. Figure 6 The via wiring VWA shown preferably does not penetrate the wiring substrate 10 .

[0144] in addition, Figure 1 In the embodiment described above, the wiring 11A as one of the signal input paths and the conductor pattern MPc are electrically connected. However, as a modified example, Figure 8 In the illustrated electronic device EDV4 , the wiring 11A and the wiring 11B serving as signal input paths may be connected to separate conductor patterns MPc. Figure 8 It means relative to Figure 4 Overlapping top views of other variations of .

[0145] exist Figure 8 In the case of the electronic device EDV4 shown, with the amplifier circuit OP1 (refer to Figure 1 ) is electrically connected to the conductor pattern MPc1 via a via wiring VWA. Furthermore, the wiring 11B connected to the inverting input terminal of the amplifier circuit OP1 is electrically connected to the conductor pattern MPc2 via a via wiring VWB. The conductor patterns MPc1 and MPc2 are separated from each other, for example, Figure 3 The wiring layer WL2 shown. In addition, on the wiring layer WL2, Figure 3 The electronic device EDV1 shown in the figure is similarly formed with a conductor pattern MPg. The conductor patterns MPc1 and MPc2 are opposed to the conductor pattern MPg via the insulating layer 14C. The conductor pattern MPc1 constitutes a transmission path connected to the non-inverting input terminal of the amplifier circuit OP1. Figure 2 The conductor pattern MPc2 forms a part of the capacitor AC1 of the noise filter NF1 shown. In addition, the conductor pattern MPc2 forms a part of the capacitor of the noise filter (low-pass filter) in the transmission path connected to the inverting input terminal of the amplifier circuit OP1.

[0146] In the case of the electronic device EDV4, noise filters are installed in each input path of the signal to the amplifier circuit, reducing the influence of noise on each transmission path. The structure of the electronic device EDV4 is particularly effective for differential amplifier circuits that receive independent signals at the inverting input terminal and the non-inverting input terminal and amplify the difference between the two input signals based on the differential gain.

[0147] (Implementation Method 2)

[0148] In the first embodiment described above, as an example of EMS countermeasures, an embodiment in which a low-pass filter is connected to filter the noise of the output signal from the sensor before it is input to the amplifier circuit is described. In the second embodiment, as an example of EMI countermeasures (and other examples of EMS countermeasures), an embodiment in which a noise filter is connected to filter the analog signal output from an analog circuit such as an amplifier circuit before it is input to the analog circuit of other electronic components is described. In addition, the noise filter described below is for Figure 9 The semiconductor device 20 including the amplifier circuit OP1 shown in the figure is an embodiment of EMI countermeasures, and the semiconductor device 50 including the AD conversion circuit (analog-to-digital conversion circuit, AD converter) ADC1 is an embodiment of EMS countermeasures. Figure 9 It means relative to Figure 1 An enlarged top view of a structural example of an electronic device according to a modified example. Figure 10 It will Figure 9 1. An equivalent circuit diagram of the path electrically connected to the amplifier circuit and the analog conversion circuit is shown. In the following description, overlapping descriptions of portions identical to those described in Embodiment 1 are omitted in principle. However, portions identical to those described in Embodiment 1 may be described with reference to the drawings described in the above embodiment.

[0149] exist Figure 9 In FIG, the conductor pattern MPc, the conductor pattern MPg, and the via wiring VW as an interlayer conductive circuit formed in a wiring layer different from the wiring layer in which the wiring 11 is formed are indicated by dashed lines. Figure 9 In FIG, the semiconductor chip 21 built into the semiconductor device 20 is indicated by a dotted line. Figure 9 1 and 2 show a portion of the wiring connected to the plurality of substrate terminals 12 and the plurality of substrate terminals 15, and the other portions are omitted. Figure 9 2 , schematically shown are a circuit diagram of the amplifier circuit OP1 included in the semiconductor device 20 and an AD converter circuit ADC1 included in the semiconductor device 50 .

[0150] Figure 9 and Figure 10The electronic device EDV5 shown includes a semiconductor device 20 and a semiconductor device (electronic component) 50 electrically connected via a wiring 11T. Wiring 11T is connected to the output terminal of amplifier circuit OP1. Semiconductor device 50 also includes an A / D converter circuit ADC1 electrically connected to wiring 11T via a terminal (lead) 51T and substrate terminal 15T. The A / D converter circuit ADC1 converts analog signals into digital signals.

[0151] like Figure 10 As shown, in the case of the electronic device EDV5, the analog signal output from the terminal 22T, which is the output terminal of the semiconductor device 20, is input to the AD conversion circuit ADC1 of the semiconductor device 50 via the wiring 11T, the substrate terminal 15T, and the terminal 51T. In addition, in the case of the electronic device EDV5, a noise filter NF2 is connected to the transmission path that electrically connects the substrate terminal 15T and the substrate terminal 12T. Figure 10 In the example shown, the noise filter NF2 is a low-pass filter including a resistor AR2 , an inductor AL2 , and a capacitor AC2 .

[0152] Connecting noise filter NF2 before the output terminal (terminal 22T) of semiconductor device 20 reduces the impact of noise components in the analog signal transmission path (wiring 11T, etc.) on other circuits. Furthermore, connecting noise filter NF2 before the input terminal (terminal 51T) of analog converter circuit ADC1, which includes analog circuits, reduces noise contained in the input signal to analog converter circuit ADC1.

[0153] Figure 10 The resistor AR2, inductor AL2, and capacitor AC2 shown are respectively used Figure 2 The noise filter NF1 described above is similarly formed by the conductor pattern of the wiring board 10 included in the electronic device EDV5. Figure 9 The extension portion 11L2 of the wiring 11T shown is composed of Figure 10 The resistor AR2, inductor AL2, and capacitor AC2 that constitute the noise filter NF2 are shown as follows. Figure 9 The conductor pattern MPc and the conductor pattern MPg shown in FIG. Figure 10 The capacitor AC2 is shown. Although not shown in the figure, the conductor pattern MPc is connected to Figure 3 The electronic device EDV1 shown is similarly formed in the wiring layer WL3. In addition, the conductor pattern MPg is formed in Figure 3 The wiring layer WL2 shown. In addition, as a modification example of the electronic device EDV5, Figure 6Similarly, in the electronic device EDV3 shown, the conductor pattern MPc may be formed in the wiring layer WL2 , and the conductor pattern MPg may be formed in the wiring layer WL3 .

[0154] Here, in the case of the electronic device EDV5, the signal flowing through the wiring 11T constituting the noise filter NF2 is a signal output from the amplifier circuit OP1 via the terminal 22T and input to the AD converter circuit ADC1 of the semiconductor device 50. Thus, when a low-pass filter is connected to the transmission path of the output signal, as shown in FIG. Figure 10 As shown in FIG. 1 , a resistor AR2 and an inductor AL2 are connected between the capacitor AC2 and the substrate terminal 12T serving as the output terminal. Therefore, in the case of the electronic device EDV5, the layout becomes as follows. Figure 9 As shown, the wiring 11T includes an extension portion 11L2 extending in the Y direction and a via junction portion 11VP connected to the via wiring VWT. The extension portion 11L2 is located between the via junction portion 11VP and the terminal 22T (substrate terminal 12T) in a plan view.

[0155] The structure of the electronic device EDV5 can also be expressed as follows: in a plan view, the distance between the terminal 22T (substrate terminal 12T) and the via-joint portion 11VP is longer than the distance between the semiconductor device 50 and the via-joint portion 11VP.

[0156] Furthermore, the wiring 11 constituting a part of the noise filter may be Figure 1 It is preferable to arrange the wiring 11A in a straight line in one direction so as to facilitate the design. Figure 9 As shown in FIG. 11T, the wiring path may be bent in the middle. For example, Figure 9 The illustrated wiring 11T has an extension portion 11L2 extending in the Y direction and an extension portion 11L3 extending in the X direction intersecting the Y direction. In this case, the separation distance between the terminal 22T (substrate terminal 12T) and the via junction portion 11VP is the separation distance along the wiring path of the wiring 11T, that is, the sum of the extension distances of the extension portion 11L2 and the extension distances of the extension portion 11L3. Furthermore, the phrase "in a plan view, the extension portion 11L2 is located between the via junction portion 11VP and the terminal 22T (substrate terminal 12T)" means that "on the wiring path of the wiring 11T, the extension portion 11L2 is located between the via junction portion 11VP and the terminal 22T (substrate terminal 12T)."

[0157] Figure 9 and Figure 10 The electronic device EDV5 shown is similar to Figures 1 to 3The electronic device EDV1 shown is the same as that shown in FIG. Therefore, repeated descriptions are omitted. In addition, in the electronic device EDV5 of this second embodiment, each modification described in the first embodiment can also be applied in combination.

[0158] (Implementation 3)

[0159] In the first and second embodiments described above, as examples of EMI or EMS countermeasures, methods for noise suppression in signal transmission paths by connecting a noise filter to the signal transmission path are primarily described. EMS or EMI countermeasures are sometimes also effective for power supply paths, such as power supply potentials, in addition to signal transmission paths. This third embodiment describes an embodiment of EMS or EMI countermeasures by connecting a noise filter to the power supply path.

[0160] Figure 11 This is an enlarged plan view showing a configuration example of an electronic device in which EMI countermeasures are implemented for power semiconductor components. Figure 12 It will Figure 11 The equivalent circuit diagram shows the paths electrically connected to the semiconductor components of the amplifier circuit and the power semiconductor components that supply power to the semiconductor components. Figure 13 It is along Figure 11 An enlarged cross-sectional view of line AA is shown.

[0161] Figure 11 The electronic device EDV6 shown includes a semiconductor device 20, a semiconductor device (semiconductor component, electronic component) 60 that supplies a power supply potential to the semiconductor device 20, and a wiring substrate 10 on which the semiconductor device 20 and the semiconductor device 60 are mounted. The semiconductor device 60 includes an inverter INV as a power conversion circuit. In the inverter INV, power input from the outside is processed and the processed power is output. As an example of the above-mentioned processing, a process of boosting or lowering the potential supplied from the outside and outputting a potential different from the input potential can be cited. In addition, as another example of the above-mentioned processing, a process of converting the input DC power supply into AC power supply and outputting it can be cited. The semiconductor device 60 is a semiconductor device for power management that controls the power supplied to the electronic components of the electronic device EDV6.

[0162] Figure 11 : Schematic diagram of a terminal (lead) 61P, which is an output terminal for outputting a processed potential, among a plurality of terminals (leads) 61 included in the semiconductor device 60 . The terminal 61P is electrically connected to the inverter INV inside the semiconductor device 60 .

[0163] The transmission path (power transmission path) connected to the output terminal of a power semiconductor device such as semiconductor device 60 carries a larger amount of current than the signal transmission path described in the first and second embodiments. Therefore, if noise is included in the power transmission path, it is likely to have an electromagnetic effect on the circuits surrounding the power transmission path. Therefore, in the electronic device EDV6, a noise filter NF3 (see FIG. 1 ) is connected to the power transmission path connected to the output terminal of the semiconductor device 60, that is, the terminal 61P. Figure 12 ), reducing the noise contained in the power transmission path.

[0164] exist Figure 12 In the example shown, the noise filter NF3 is connected to Figure 2 The noise filter NF1 shown and Figure 10 The noise filter NF2 shown is similar to the one shown in FIG. 1 , and is a low-pass filter comprising a resistor AR3, an inductor AL3, and a capacitor AC3. Figure 12 In the example shown, high-frequency noise included in the current flowing through the wiring 11P is reduced.

[0165] In the case of a low-pass filter, a capacitor AC3 is connected near the semiconductor device 20 that consumes power (see Figure 12 Therefore, when a capacitor chip as a sheet component is mounted as capacitor AC3 near the semiconductor device 20, signal wiring connected to the semiconductor device 20 (for example, Figure 12 Therefore, in the case of the electronic device EDV6, Figure 12 The resistor AR3 , the inductor AL3 , and the capacitor AC3 constituting the noise filter NF3 are each formed by a conductor pattern provided on the wiring board 10 .

[0166] like Figure 11 and Figure 13 As shown, the wiring substrate 10 includes a substrate terminal 16P connected to the terminal 61P and a wiring layer WL1 (see FIG. Figure 13 ) and is connected to the substrate terminal 16P. In addition, the wiring substrate 10 includes a wiring layer WL3 formed on a layer different from the wiring layer WL1 (see Figure 13 ) and electrically connected to the wiring 11P via the via wiring VWP, and the conductor pattern MPc formed on a wiring layer WL2 (see FIG. 1 ) which is different from the wiring layers WL1 and WL3. Figure 13 ) and is supplied with a fixed potential (for example, a ground potential) of the conductor pattern MPg. In addition, the conductor pattern MPc and the conductor pattern MPg are separated by an insulating layer 14C (see Figure 13) face each other. Furthermore, the area of ​​the region where the conductor pattern MPc and the conductor pattern MPg face each other is larger than the area of ​​the wiring 11P. The wiring 11P includes an extension portion 11L4 extending in the Y direction and a via-joint portion 11VP connected to the via wiring VWP. The extension portion 11L4 is located between the via-joint portion 11VP and the substrate terminal 16P in a plan view.

[0167] In the case of electronic device EDV6, connecting a noise filter NF3 to the power transmission path reduces noise along the power transmission path. This reduces the electromagnetic impact of noise along the power transmission path on peripheral circuits of semiconductor device 20. Furthermore, the resistor AR3, inductor AL3, and capacitor AC3 that comprise noise filter NF3 are each formed using a conductor pattern on wiring substrate 10. This reduces the risk of unintended electromagnetic impact on peripheral circuits caused by noise filter NF3.

[0168] In addition, the electronic device EDV5 formed in the above-mentioned embodiment 2 (see Figure 9 ) Similarly, the noise filter NF3 (refer to Figure 12 ) is bent midway along the wiring path. Wiring 11P has an extension portion 11L4 extending in the Y direction and an extension portion 11L5 extending in the X direction intersecting the Y direction. Extension portion 11L5 is located between via junction 11VP and substrate terminal 12P. In the case of a low-pass filter connected to the output terminal, a resistor and an inductor are connected between the output terminal and the capacitor. Figure 12 The values ​​of the resistor AR3 and inductor AL3 shown are determined by the extension length of the extension portion 11L4. Therefore, if the length of the extension portion 11L4 is long enough, it is easier to control the values ​​of the resistor AR3 and inductor AL3. On the other hand, if the length of the extension portion 11L5 is long, the risk of new noise being mixed in after passing through the noise filter NF3 increases. Therefore, the length of the extension portion 11L5 is preferably short. Therefore, in this embodiment, as shown in FIG. Figure 11 As shown, the length of the extension portion 11L4 is longer than the length of the extension portion 11L5.

[0169] The relationship between the extension portion 11L4 and the extension portion 11L5 is also equivalent to Figure 9 The relationship between the extension portion 11L2 and the extension portion 11L3 is shown.

[0170] Figures 11 to 13 The electronic device EDV6 shown has the same function as the one used in the Figure 9 and Figure 10The electronic device EDV5 described above is the same. Therefore, repeated descriptions are omitted. In addition, in the electronic device EDV6 of this third embodiment, each modification described in the first embodiment can also be combined and applied.

[0171] Next, in the third embodiment, an embodiment in which EMS countermeasures are taken by connecting a noise filter to a power supply path will be described. Figure 14 This is an enlarged plan view showing a structural example of an electronic device including a connector and a semiconductor component connected to the connector. Figure 15 It is along Figure 14 An enlarged cross-sectional view of line AA is shown. Figure 16 It is mounted on Figure 14 An enlarged top view of the capacitor periphery on the opposite side of the lower surface. Figure 17 It is along Figure 16 The enlarged cross-sectional view of the A-A line. In addition, Figure 18 yes Figure 14 The equivalent circuit diagram of the electronic device shown.

[0172] Figures 14 to 18 The electronic device EDV7 shown has: a circuit 72 with a power supply (see Figure 14 ) of the semiconductor device 70, and a connector 80 that relays the power supply potential and ground potential supplied from the outside to the semiconductor device 70.

[0173] The circuit 72 included in the semiconductor device (semiconductor component, electronic component) 70 is not particularly limited in type, as long as it supplies power supply potential and ground potential. For example, it can be a logic circuit that consumes power to process data, such as a processing circuit, or a power supply buffer circuit. The semiconductor device 70 includes a plurality of terminals (leads) 71 connected to the circuit 72. Figure 14 , among the plurality of terminals 71, a terminal 71D serving as an input terminal for a power supply potential and a terminal (lead) 71G serving as an input terminal for a ground potential are shown.

[0174] Furthermore, the connector (electronic component) 80 is a relay component (external connection component) that electrically connects the electronic device EDV7 and external equipment. Figure 18 1 shows an example of connecting the connector 80 to the external power supply PS. Figure 14 8 shows, among the plurality of terminals 81 included in the connector 80 , a terminal (lead) 81D serving as an output terminal for a power supply potential and a terminal (lead) 81G serving as an output terminal for a ground potential.

[0175] In addition, the semiconductor device 70 and the connector 80 are mounted on the wiring substrate 10 and are electrically connected to each other. The wiring substrate 10 of the electronic device EDV7 has an upper surface (surface, main surface, top surface) 10t and a lower surface (surface, main surface, back surface) 10b located on the opposite side of the upper surface 10t. The semiconductor device 70 and the connector 80 are respectively mounted on the upper surface 10t. The semiconductor device 70 and the connector 80 are connected to each other via the wiring layer WL1 (see FIG. Figure 15 ) are electrically connected to each other via wiring 11. Specifically, terminal 71D of semiconductor device 70, which constitutes a supply path for the power supply potential, and terminal 81D of connector 80 are electrically connected to each other via substrate terminal 17D, wiring 11D, and substrate terminal 18D. Furthermore, terminal 71G of semiconductor device 70, which constitutes a supply path for the ground potential, and terminal 81G of connector 80 are electrically connected to each other via substrate terminal 17G, wiring 11G, and substrate terminal 18G.

[0176] In addition, the semiconductor device 70 includes a capacitor (capacitor component, chip capacitor) 90 mounted on the wiring substrate 10. Figure 15 In the example shown, the capacitor 90 is mounted on the lower surface 10b of the wiring substrate 10. Figure 16 As shown, the capacitor 90 forms a quadrilateral when viewed from above. In addition, the capacitor 90 has two long sides (long sides) and two short sides (short sides). In addition, the capacitor 90 has an electrode 91D and an electrode 91G provided at ends on opposite sides of each other. In the example of this embodiment, the two electrodes 91 (refer to Figure 17 ) are located at opposite ends of the capacitor 90 in the direction of extension of the long side. In addition, the capacitor 90 has a main body 92 sandwiched between the electrode 91D and the electrode 91G. For example, Figure 17 As shown, the main body has a plurality of conductor plates 94 stacked with insulating layers (dielectric layers) 93 interposed therebetween. Each of the plurality of conductor plates 94 is connected to one of electrodes 91D and 91G. Electrodes 91D and 91G function as external electrode terminals for extracting the capacitance formed between the plurality of conductor plates facing each other to the outside.

[0177] Figure 17 The capacitor 90 of the structure shown in FIG. 1 often uses a ceramic insulating layer 93 and is called a ceramic capacitor. Figure 17 As shown, capacitor 90 is a surface-mount electronic component that can be mounted on the surface of wiring board 10. Surface-mount electronic components are also called chip components (in the case of capacitor 90, a chip capacitor).

[0178] The capacitor 90 is connected in parallel to the path for supplying the power supply potential to the semiconductor device 70 and the path for supplying the ground potential to the semiconductor device 70. In other words, the capacitor 90 is connected in parallel to the path for supplying the driving voltage to the semiconductor device 70 (see Figures 15 to 18 ). In detail, the electrode 91D of the capacitor 90 is formed on the wiring layer WL4 (see Figure 15 ) substrate terminal 19D, via junction VP3, via wiring VWD2 penetrating the wiring substrate 10 in the thickness direction, and via junction 11VP2 are electrically connected to substrate terminal 17D. In addition, electrode 91G of capacitor 90 is connected to wiring layer WL4 (see FIG. Figure 15 ) of the substrate terminal 19G and the via wiring VWG (see Figure 14 、 Figure 16 ,and Figure 18 ) is electrically connected to the substrate terminal 17G. When the capacitor 90 is connected in parallel to the path for supplying the driving voltage to the semiconductor device 70, it is possible to suppress the voltage drop caused by the instantaneous increase in power consumption of the semiconductor device 70. That is, the capacitor 90 acts as a bypass capacitor. By Figure 18 ) is connected near the circuit 72, so that the circuit 72 can operate stably, thereby improving the reliability of the electronic device EDV7.

[0179] However, if high-frequency noise is introduced into the supply path of the driving voltage, the capacitor 90 as a bypass capacitor may not operate accurately.

[0180] Therefore, in the electronic device EDV7, a noise filter NF4 as a low-pass filter is connected to the path that supplies a relatively high power supply potential among the two transmission paths that supply the driving voltage to the semiconductor device 70 (see FIG. Figure 18 ). This reduces high-frequency noise in the transmission path connected to wiring 11D. Furthermore, ground potential is supplied to wiring 11G. Therefore, high-frequency noise is less likely to enter the transmission path including wiring 11G. Therefore, in the case of electronic device EDV7, connecting noise filter NF4 to wiring 11D reduces high-frequency noise in the path supplying the drive voltage to semiconductor device 70, allowing capacitor 90, which functions as a bypass capacitor, to operate accurately.

[0181] in addition, Figure 18 The noise filter NF4 included in the illustrated electronic device EDV7 is formed by a conductor pattern included in the wiring substrate 10 .

[0182] like Figure 14 As shown, the wiring substrate 10 includes a substrate terminal 18D connected to the terminal 81D and a wiring layer WL1 (see FIG. Figure 15 ) and connected to the substrate terminal 18D. In addition, the wiring substrate 10 includes a wiring layer WL3 formed on a layer different from the wiring layer WL1 (see Figure 15 ) and electrically connected to the wiring 11D via the via wiring VWD, and formed in a wiring layer WL2 (see Figure 15 ) and supplying a fixed potential (for example, a ground potential) to the conductor pattern MPg. In addition, the conductor pattern MPc and the conductor pattern MPg are connected via the insulating layer 14C (see Figure 15 ) are opposed to each other. In addition, the area of ​​the region where the conductor pattern MPc and the conductor pattern MPg are opposed to each other is larger than the area of ​​the wiring 11D. The wiring 11D has an extension portion 11L6 extending along the Y direction and a via junction portion 11VP1 connected to the via wiring VWD1. When viewed from above, the extension portion 11L6 is located between the via junction portion 11VP1 and the substrate terminal 18D, and the via junction portion 11VP1 is located between the capacitor 90 (see FIG. 1 ). Figure 15 ) between the electrode 91D and the extending portion 11L6 of the wiring 11D.

[0183] in addition, Figure 15 The conductor pattern MPc and the via wiring VWD2 shown are connected to the wiring 11D. Therefore, the conductor pattern MPc and the via wiring MWD2 may also be in contact. Figure 15 In the example shown, the via wiring VWD2 does not contact the conductor pattern MPc. Thus, the via wiring VWD2 can be connected to the noise filter NF4 (see FIG. Figure 18 ) is connected to the path and the path connected to the capacitor 90 as a bypass capacitor is distinguished, so that the mutual interference between the operations can be suppressed. In addition, from the perspective of suppressing the interference between the capacitor 90 and the noise filter NF4, as shown in FIG. Figure 15 As shown, it is preferable that the conductor pattern MPc and the capacitor 90 do not overlap.

[0184] In addition, from the viewpoint of shortening the path connected to the capacitor 90 as a bypass capacitor, as shown in FIG. Figure 15 As shown, the path distance of the wiring path connecting the terminal 71D to the via-wiring VWD2 is preferably the same as or shorter than the path distance of the wiring path connecting the terminal 71D to the via-wiring VWD1 .

[0185] In the case of electronic device EDV7, connecting a noise filter NF4, acting as a low-pass filter, to the power transmission path reduces high-frequency noise in the path. This ensures reliable operation of bypass capacitor 90. Furthermore, the resistor AR4, inductor AL4, and capacitor AC4 that comprise noise filter NF4 are each formed by a conductor pattern on wiring board 10. This prevents unintended electromagnetic interference on peripheral circuits caused by noise filter NF4.

[0186] In addition, the electronic device EDV7 also has various modifications. For example, Figure 15 In the embodiment shown, capacitor 90 is mounted on lower surface 10b of wiring substrate 10, but capacitor 90 may be mounted on upper surface 10t. In this case, substrate terminal 19D connected to electrode 91D of capacitor 90 is arranged between substrate terminal 17D and via wiring VWD1 (via junction 11VP1) in a plan view. In this modified embodiment, capacitor 90 and circuit 72 (see FIG. 1 ) can be connected. Figure 18 ) path distance ratio Figure 15 However, the chip capacitor and the semiconductor device 70 are close to each other, which may cause unexpected electromagnetic interference between the components. Therefore, from the perspective of suppressing interference between components, as shown in the example Figure 15 As shown, capacitor 90 is preferably mounted on lower surface 10 b of wiring substrate 10 .

[0187] In addition, for example, in this embodiment 3, an example of a capacitor component is shown. Figure 17 1 , a ceramic capacitor including electrodes 91D and 91G provided at opposite ends is used as an example of capacitor 90. However, as a modified example, an electrolytic capacitor may also be used.

[0188] In addition, the electronic device EDV5 formed in the above-mentioned embodiment 2 (see Figure 9 ) is the same as the noise filter NF4 (refer to Figure 18 ) A portion of the wiring 11D may be bent in the middle of the wiring path. In this case, when the wiring 11D includes a plurality of extensions extending in a plurality of directions intersecting each other, it is preferred that the extension 11L6 be the longest.

[0189] Figures 14 to 18 The electronic device EDV7 shown is similar to the one used in the Figure 9 and Figure 10 The electronic device EDV5 described above is the same. Therefore, repeated descriptions are omitted. In addition, in the electronic device EDV7 of this third embodiment, each modification described in the first embodiment can also be combined and applied.

[0190] (Implementation 4)

[0191] For example, in Embodiments 1 through 3 above, a low-pass filter composed of resistors, inductors, and capacitors was used as an example of a noise filter. However, noise filters include not only low-pass filters that primarily block the passage of high-frequency noise, but also high-pass filters that primarily block the passage of low-frequency noise, and band-pass filters that block the passage of high-frequency noise and low-frequency noise outside the intended frequency band. In this embodiment, as a variation of the low-pass filter, an embodiment in which a portion of the band-pass filter and high-pass filter is formed using a conductor pattern on a wiring substrate will be described.

[0192] Figure 19 This is an enlarged plan view showing a configuration example of an electronic device in which a bandpass filter is connected between a transmitting circuit and a receiving circuit. Figure 20 yes Figure 19 The equivalent circuit diagram of the electronic device shown. Figure 21 It is along Figure 19 An enlarged cross-sectional view of line AA is shown. Figure 19 This is a top view, and the area OWR where the conductor pattern MPr and the conductor pattern MPt face each other is shaded. Figure 21 In FIG. 1 , a via wiring VWG that exists in another cross section and electrically connects the conductor pattern MPG1 and the conductor pattern MPG2 is indicated by a two-dot chain line.

[0193] Figure 19 The electronic device EDV8 shown in FIG. 1 includes: a receiving circuit 102 (see FIG. Figure 20 ) of a semiconductor device (semiconductor component, electronic component) 100, including a transmission circuit 202 (see Figure 20 ) of a semiconductor device (semiconductor component, electronic component) 200, and a wiring substrate 10 on which the semiconductor devices 100 and 200 are mounted. Figure 20 A high-frequency communication circuit for transmitting a high-frequency signal of, for example, approximately 5 GHz is provided between the transmitting circuit 202 and the receiving circuit 102 .

[0194] When transmitting high-frequency signals, it is preferable to reduce noise in frequency bands other than the frequency band used for communication. In this case, noise outside the specified frequency band can be reduced by connecting a bandpass filter to the transmission path between the transmitting circuit 202 and the receiving circuit 102. Furthermore, as described later, noise at frequencies lower than the specified frequency band can also be reduced by connecting a highpass filter to the transmission path between the transmitting circuit 202 and the receiving circuit 102.

[0195] In the case of bandpass filters and high-pass filters, such as Figure 20As shown, the capacitor AC5 is connected in series with the transmission path. Figure 2 The low-pass filter shown in FIG. 1 is different. One electrode of capacitor AC5 ( Figure 21 The conductor pattern MPt shown is connected to the transmission circuit 202. In addition, the other electrode of the capacitor AC5 ( Figure 21 The conductor pattern MPr) shown is connected to the receiving circuit 102.

[0196] In the electronic device EDV8, a portion of the noise filter NF5 as a bandpass filter is formed by the wiring substrate 10 (see FIG. Figure 19 ) is formed by a conductor pattern. In detail, Figure 20 Of the inductor AL5, capacitor AC5, and resistor AR5 that constitute noise filter NF5, inductor AL5 and capacitor AC5 are formed by the conductor pattern of wiring board 10. Meanwhile, resistor AR5 is largely contributed by the resistance value of resistor component 40, which is a chip component (chip resistor).

[0197] like Figure 19 As shown, semiconductor device 100 includes terminals (leads) 101R for inputting communication signals, and semiconductor device 200 includes terminals (leads) 201T for outputting communication signals. Furthermore, resistor component 40 includes electrodes 40E3 and 40E4 located on opposite sides of each other. Semiconductor devices 100, 200, and resistor component 40 are each mounted on top surface 10t of wiring substrate 10.

[0198] Furthermore, the wiring substrate 10 includes a substrate terminal 111R connected to the terminal 101R of the semiconductor device 100, and a substrate terminal 211T connected to the terminal 201T of the semiconductor device 200. Furthermore, the wiring substrate 10 includes a wiring 11R electrically connected to the substrate terminal 111R, and a wiring 11T electrically connected to the substrate terminal 211T. The substrate terminals 111R and 211T, and the wirings 11R and 11T, are formed in the wiring layer WL1 (see FIG. 1 ) of the wiring substrate 10. Figure 21 The wiring 11R includes a via-joint portion 11VP connected to the via wiring VWR and an extension portion 11L7 located between the substrate terminal 111R and the via-joint portion 11VP. Furthermore, the wiring 11T includes a via-joint portion 11VP connected to the via wiring VWT and an extension portion 11L8 located between the substrate terminal 211T and the via-joint portion 11VP.

[0199] In addition, the wiring substrate 10 includes a wiring layer WL2 formed on a substrate different from the wiring layer WL1 (see Figure 21) and electrically connected to the wiring 11R via the via wiring VWR, and the conductor pattern MPr formed in the wiring layer WL3 different from the wiring layers WL1 and WL2 and electrically connected to the wiring 11T via the via wiring VWT. The conductor pattern MPr and the conductor pattern MPt are connected via the insulating layer 14C (see Figure 21 ) are opposed to each other. In addition, the area of ​​the region OWR where the conductor pattern MPr and the conductor pattern MPt are opposed to each other is larger than the area of ​​the wiring 11R. In addition, the area of ​​the region OWR is larger than the area of ​​the wiring 11T. The portion where the conductor pattern MPr and the conductor pattern MPt are opposed to each other via the insulating layer 14C constitutes Figure 20 Therefore, in a plan view, the region OWR is located between the via wiring VWR and the via wiring VWT.

[0200] In addition, the wiring 11T and the via wiring VWT are equivalent to Figure 20 The inductor AL5 shown can be adjusted by adjusting the length of the wiring 11T and the via wiring VWT. Figure 20 The value of inductor AL5 is shown.

[0201] Wiring board 10 includes conductor pattern MPG1 formed in wiring layer WL4 and conductor pattern MPG2 formed in wiring layer WL1. Conductor patterns MPG1 and MPG2 are each supplied with a ground potential and are electrically connected via via wiring VWG.

[0202] In addition, if Figure 19 As shown, multiple via wirings VWG are connected to the conductor pattern MPG2, which supplies a ground potential. Via wirings VWG are arranged on both sides of the via wiring VWR and on both sides of the via wiring VWT. In other words, the via wiring VWR is arranged between the multiple via wirings VWG. Furthermore, the via wiring VWT is arranged between the multiple via wirings VWG. By arranging via wirings VWG, which supply a ground potential, on both sides of the via wiring VWR and via wiring VWT, which serve as signal transmission paths, it is possible to reduce electromagnetic interference from other circuits on the signal transmission paths of the via wirings VWR and VWT.

[0203] In addition, the wiring 11R is connected to the electrode 40E4, which is one electrode of the resistor component 40. In detail, the wiring 11R has a via junction 11VP connected to the via wiring VWR and a resistor connection portion 11BP connected to the electrode 40E4 of the resistor component 40. The resistor connection portion 11BP is located between the substrate terminal 111R and the via junction 11VP. An extension portion 11L7 extending along the X direction is present between the substrate terminal 111R and the via junction 11VP, and the resistor connection portion 11BP is located midway through the extension portion 11L7. The electrode 40E4 is bonded to the resistor connection portion 11BP via solder SD and is electrically connected. When viewed from above, the resistor connection portion 11BP is located between the substrate terminal 111R and the via wiring VWR (via junction 11VP). In addition, the other electrode of the resistor component 40, namely the electrode 40E3, is connected to the conductor pattern MPG2.

[0204] In the case of the electronic device EDV8, Figure 20 Of the inductor AL5, capacitor AC5, and resistor AR5 that constitute the noise filter NF5 shown, the inductor AL5 and capacitor AC5 are formed by the conductor pattern of the wiring substrate 10. Therefore, electromagnetic interference between the inductor AL5 and capacitor AC5 and other electronic components can be suppressed. Furthermore, in the case of the electronic device EDV8, a sheet-like component is used as the resistor AR5. However, the resistance value of the resistor AR5, which constitutes part of the bandpass filter, is, for example, more than tens of Ω, and the current flowing through it is small. Therefore, compared to the case of incorporating a low-pass filter, even if a sheet-like component is used for the resistor AR5, the electromagnetic impact is smaller. Furthermore, in the case of a resistor element with a large resistance formed by a conductor pattern, the extension distance of the conductor pattern needs to be extended, and therefore, the planar area of ​​the wiring substrate 10 may be increased. Therefore, in the case of the electronic device EDV8, by using a sheet-like component as the resistor AR5, the planar area of ​​the wiring substrate 10 can be reduced.

[0205] Next, a configuration example of an electronic device including a high-pass filter will be described. Figure 22 This is an enlarged plan view showing a configuration example of an electronic device in which a high-pass filter is connected between a transmitting circuit and a receiving circuit. Figure 23 yes Figure 22 The equivalent circuit diagram of the electronic device shown. Figure 24 It is along Figure 22 An enlarged cross-sectional view of line AA is shown. Figure 22 2 is a top view, and the area OWR where the conductor pattern MPr and the conductor pattern MPt face each other is hatched. Figure 24 In FIG. 1 , a via wiring VWG that exists in another cross section and electrically connects the conductor pattern MPG1 and the conductor pattern MPG2 is indicated by a two-dot chain line.

[0206] about Figures 22 to 24The semiconductor device 100 or the semiconductor device 200 in the electronic device EDV9 shown in FIG. Figures 19 to 21 The common parts of the electronic device EDV8 described above will be omitted from repeated description.

[0207] In the case of a high-pass filter, Figure 23 As shown, the capacitor AC6 is connected in series in the transmission path. Figure 2 The low-pass filter shown in FIG. 1 is different. One electrode of capacitor AC6 ( Figure 24 The conductor pattern MPt shown is connected to the transmission circuit 202. In addition, the other electrode of the capacitor AC6 ( Figure 24 The conductor pattern MPr) shown is connected to the receiving circuit 102.

[0208] In addition, in the electronic device EDV9, a portion of the noise filter NF6 as a high-pass filter is passed through the wiring substrate 10 (see Figure 22 ) is formed by a conductor pattern. In detail, Figure 23 Of the inductor AL6, capacitor AC6, and resistor AR6 that constitute noise filter NF6, inductor AL6 and capacitor AC6 are formed by the conductor pattern of wiring board 10. Meanwhile, resistor AR6 is largely contributed by resistor component 40, which is a chip component (chip resistor).

[0209] like Figure 22 As shown, semiconductor device 100 includes terminals (leads) 101R to which communication signals are input, and semiconductor device 200 includes terminals (leads) 201T to which communication signals are input. Furthermore, resistor component 40 includes electrodes 40E5 and 40E6 located on opposite sides of each other. Semiconductor devices 100, 200, and resistor component 40 are each mounted on top surface 10t of wiring substrate 10.

[0210] In addition, the wiring substrate 10 includes a substrate terminal 111R connected to the terminal 101R of the semiconductor device 100, and a substrate terminal 211T connected to the terminal 201T of the semiconductor device 200. In addition, the wiring substrate 10 of the electronic device EDV9 includes a substrate terminal 13R1 connected to the electrode 40E5 of the resistor component 40, and a substrate terminal 13R2 connected to the electrode 40E6 of the resistor component 40. In addition, the wiring substrate 10 includes a wiring 11R electrically connected to the substrate terminal 111R, and a wiring 11T2 electrically connected to the substrate terminal 211T. In addition, the wiring substrate 10 of the electronic device EDV9 includes a wiring 11T1 connected to the substrate terminal 13R1, and a wiring 11L connected to the wiring 11R. The substrate terminals 111R, 211T, 13R1, 13R2, and the wirings 11R, 11T1, 11T2, 11L are respectively formed on the wiring layer WL1 (see FIG. 1 ) of the wiring substrate 10. Figure 24 ).

[0211] In addition, the wiring substrate 10 includes a wiring layer WL2 formed on a substrate different from the wiring layer WL1 (see Figure 24 ) and electrically connected to the wiring 11R via the via wiring VWR, and the conductor pattern MPr formed in the wiring layer WL3 different from the wiring layers WL1 and WL2 and electrically connected to the wiring 11T1 via the via wiring VWT. The conductor pattern MPr and the conductor pattern MPt are connected via the insulating layer 14C (see Figure 24 ) are opposed to each other. In addition, the area of ​​the region OWR where the conductor pattern MPr and the conductor pattern MPt are opposed to each other is larger than the area of ​​the wiring 11R. In addition, the area of ​​the region OWR is larger than the area of ​​the wiring 11T1. The portion where the conductor pattern MPr and the conductor pattern MPt are opposed to each other via the insulating layer 14C constitutes Figure 23 Therefore, in a plan view, the region OWR is located between the via wiring VWR and the via wiring VWT.

[0212] Furthermore, the wiring 11L connected to the wiring 11R and the via wiring VWLG connected to the wiring 11L correspond to Figure 23 The inductor AL6 is shown. The wiring 11R has an extension portion 11L9 extending in the X direction and a via junction portion 11VP connected to the via wiring VWR. In a plan view, the wiring 11L has an extension portion 11L10 connected between the substrate terminal 111R and the via junction portion 11VP of the wiring 11R and longer than the extension portion 11L9. Figure 24 The via wiring VWG shown is similarly an interlayer conductive circuit that penetrates the wiring substrate 10 in the thickness direction and is electrically connected to the conductor pattern MPG1 that supplies the ground potential on the wiring layer WL4. Figure 23 ), by adjusting Figure 22 The length of the extension portion 11L10 of the wiring 11L shown can be adjusted. Figure 23 The value of inductor AL6 is shown.

[0213] Wiring board 10 includes conductor pattern MPG1 formed in wiring layer WL4 and conductor pattern MPG2 formed in wiring layer WL1. Conductor patterns MPG1 and MPG2 are each supplied with a ground potential and are electrically connected via via wiring VWG.

[0214] In addition, if Figure 22 As shown, multiple via wirings VWG are connected to the conductor pattern MPG2, which supplies a ground potential. Via wirings VWG are arranged on both sides of the via wiring VWR and on both sides of the via wiring VWT. In other words, the via wiring VWR is arranged between the multiple via wirings VWG. Furthermore, the via wiring VWT is arranged between the multiple via wirings VWG. By arranging via wirings VWG, which supply a ground potential, on both sides of the via wiring VWR and via wiring VWT, which serve as signal transmission paths, it is possible to reduce electromagnetic interference from other circuits on the signal transmission paths of the via wirings VWR and VWT.

[0215] in addition, Figure 23 The resistor AR6 constituting the high-pass filter needs a resistance value of, for example, several tens of Ω or more. Therefore, in order to reduce the plane area of ​​the wiring board 10, the electronic device EDV9 uses a chip-shaped resistor component 40 as the resistor AR6.

[0216] Regarding the resistor component 40, the electrode 40E5 is connected via solder SD (see Figure 24 ) is mounted on the substrate terminal 13R1, and the electrode 40E6 is connected to the substrate terminal 13R1 via the solder SD (see Figure 24 ) is mounted on substrate terminal 13R2. Substrate terminal 13R1 of wiring substrate 10 is electrically connected to via wiring VWT via wiring 11T1. Wiring 11T1 includes via junction 11VP connected to via wiring VWT and extending portion 11L11 located between via junction 11VP and substrate terminal 13R1. Furthermore, substrate terminal 13R2 of wiring substrate 10 is electrically connected to substrate terminal 211T via wiring 11T2.

[0217] In this embodiment, as a modification of the low-pass filter, an embodiment in which a portion of a band-pass filter and a portion of a high-pass filter are formed by a conductor pattern of a wiring substrate is described with reference to each example. Figure 19 The electronic device EDV8 shown and Figure 22 The electronic device EDV9 shown has various modifications.

[0218] For example, Figure 21 and Figure 24 In the example described above, a conductor pattern MPr is formed on wiring layer WL2, and a conductor pattern MPt is formed on wiring layer WL3. However, as long as the conductor pattern MPr and the conductor pattern MPt are opposed to each other via an insulating layer, the wiring layers in which they are formed are not limited. For example, the conductor pattern MPt may be formed on wiring layer WL2, and the conductor pattern MPr may be formed on wiring layer WL3.

[0219] In addition, for example, in this embodiment, Figure 20 or Figure 23 As shown in the figure, the electronic devices EDV8 and EDV9 are described as including both the transmitting circuit 202 and the receiving circuit 102, but it is also possible to use an electronic device including only one of the transmitting and receiving circuits. In this case, as long as either the semiconductor device 200 including the transmitting circuit 202 or the semiconductor device 100 including the receiving circuit 102 is, for example, Figure 14 A relay component (electronic component) such as the illustrated connector 80 may be used. The relay component has a function of transmitting or receiving a signal output from the transmission circuit 202 or a signal input to the reception circuit 102 with or from an external device.

[0220] Furthermore, a plurality of modified examples described in the above-mentioned Embodiments 1 to 3 may be applied in combination.

[0221] Other Modifications

[0222] The invention proposed by the inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments and can be modified in various ways without departing from the scope of its purpose. In addition, several modifications have been described in the above embodiments, but representative modifications other than those described in the above embodiments will be described below.

[0223] For example, in the above-mentioned embodiments 1 to 4, as an example of the structure of the conductor pattern constituting the capacitor, for example, Figure 3 As shown in FIG. 1 , a structure in which one conductor pattern MPc and one conductor pattern MPg are opposed to each other via the insulating layer 14C has been described. In this case, Figure 3 As shown, since the capacitor can be formed by the wiring layer WL2 and the wiring layer WL3 which are different from the wiring layer WL1 , the number of wiring layers of the wiring substrate 10 can be reduced.

[0224] However, the number of wiring layers of the wiring substrate 10 may be four or more. Figure 25 In the case of a wiring board 10A included in the illustrated electronic device EDV10 , the wiring board 10A includes seven wiring layers, namely, wiring layers WL1 to WL7 . Figure 25 Is to use Figures 1 to 24 Enlarged cross-sectional view of a modified example of the capacitor described below. A modified example in which the number of wiring layers is large will be described below using the electronic device EDV10 as an example.

[0225] In the case of electronic device EDV10, because it has a large number of wiring layers, the conductor patterns MP1 and MP2 that constitute the capacitor can be arranged on multiple wiring layers. Electronic device EDV10 differs from electronic devices EDV1 to EDV9 described in Embodiments 1 to 3 above in that the conductor patterns MP1 and MP2 that constitute the capacitor are stacked in multiple layers. Specifically, the structure of wiring board 10A can be expressed as follows.

[0226] Wiring substrate 10A includes multiple conductor patterns MP1 connected to wiring 11W1 via via wiring VW1 and formed on different wiring layers. Furthermore, wiring substrate 10A includes multiple conductor patterns MP2 connected to wiring 11W2 or conductor pattern MPG via via wiring VW2 and formed on different wiring layers. The multiple conductor patterns MP1 and the multiple conductor patterns MP2 are formed on different wiring layers. Furthermore, each of the multiple conductor patterns MP1 faces one of the multiple conductor patterns MP2 via insulating layer 14.

[0227] The multiple conductor patterns MP1 are electrically connected to each other via via wiring VW1. Furthermore, the multiple conductor patterns MP2 are electrically connected to each other via via wiring VW2. Thus, in a structure where multiple conductor patterns MP1 and multiple conductor patterns MP2 are stacked, the capacitance of the capacitor can be increased even if the area of ​​each conductor pattern MP1 and MP2 is small. Therefore, in the case of a capacitor having a stacked structure, such as in the electronic device EDV10, the area occupied by the capacitor when viewed from above can be reduced compared to a case where there are only one conductor pattern MP1 and one conductor pattern MP2. As a result, the planar area of ​​the wiring board 10A can be reduced.

[0228] Furthermore, the capacitors included in electronic device EDV10 can be replaced with the capacitors included in electronic devices EDV1 to EDV9 described in the above embodiments. Therefore, conductor pattern MP1 corresponds to conductor pattern MPc or MPr described in the above embodiments. Furthermore, conductor pattern MP2 corresponds to conductor pattern MPg or MPt described in the above embodiments. Furthermore, via wiring VW1 corresponds to via wiring VWA, VWP, VWD1, or VWR described in the above embodiments. Furthermore, via wiring VW2 corresponds to via wiring VWG or VWT described in the above embodiments.

[0229] In the above-mentioned first to third embodiments, the embodiment in which most of the wiring 11 connecting the conductor pattern MPc overlaps with the conductor pattern MPc in a plan view has been described. Figure 19 In the example shown, most of the wiring 11 connected to the conductor pattern MPr may not overlap with the conductor pattern MPc in a plan view.

[0230] In addition, in the above embodiment, for example, Figure 3 As shown, the example in which the plurality of substrate terminals 12 and 13 and the wiring 11 are formed in the wiring layer WL1 is described. However, the wiring 11 may be formed in a layer below the substrate terminals (a wiring layer on the lower surface 10b side).

[0231] In the above embodiment, the structure of a noise filter is described. However, if Figure 8 The electronic device EDV4 described above can simply connect a noise filter to each of the multiple transmission paths. Furthermore, if there are multiple circuits operating in multiple channels (e.g., amplifier circuits), a noise filter can also be connected to each of the transmission paths of the multiple circuits. In this case, multiple conductor patterns MPc can be formed on multiple wiring layers, depending on the layout.

[0232] Furthermore, for example, various modified examples have been described above, but the modified examples described above may be applied in combination with each other.

[0233] Furthermore, if the technical concept of the electronic device described in the above embodiment is extracted, it can be expressed as follows.

[0234] [Note 1]

[0235] An electronic device comprising:

[0236] an electronic component having a first terminal to which a first signal is input;

[0237] a wiring substrate on which the above-mentioned electronic component is mounted; and

[0238] A resistor component mounted on the wiring substrate and having two electrodes located on opposite sides of each other,

[0239] The wiring substrate includes:

[0240] a first substrate terminal connected to the first terminal;

[0241] a second substrate terminal;

[0242] a first wiring formed in the first wiring layer and electrically connected to the first substrate terminal;

[0243] a second wiring formed in the first wiring layer and electrically connected to the second substrate terminal;

[0244] a first conductor pattern formed in a second wiring layer different from the first wiring layer and electrically connected to the first wiring via a first via wiring; and

[0245] a second conductor pattern formed in a third wiring layer different from the first wiring layer and the second wiring layer and electrically connected to the second wiring via a second via wiring;

[0246] The first conductor pattern and the second conductor pattern are opposed to each other via an insulating layer.

[0247] The area of ​​the first region where the first conductor pattern and the second conductor pattern face each other is larger than the area of ​​the first wiring.

[0248] The first wiring includes a first via junction portion connected to the first via wiring, and a resistor connection portion connected to one of the two electrodes of the resistor component.

[0249] In a plan view, the resistive connection portion is located between the first substrate terminal and the first via wiring, and the first region is located between the first via wiring and the second via wiring.

[0250] [Note 2]

[0251] An electronic device comprising:

[0252] an electronic component having a first terminal to which a first signal is input;

[0253] a wiring substrate on which the above-mentioned electronic component is mounted; and

[0254] a resistor component mounted on the wiring substrate and including a first electrode and a second electrode located on opposite sides of each other,

[0255] The wiring substrate includes:

[0256] a first substrate terminal connected to the first terminal;

[0257] a second substrate terminal connected to the first electrode of the resistor component;

[0258] a third substrate terminal connected to the second electrode of the resistor component;

[0259] a first wiring formed in the first wiring layer and electrically connected to the first substrate terminal;

[0260] a second wiring formed in the first wiring layer and electrically connected to the second substrate terminal;

[0261] a third wiring formed in the first wiring layer and connected to the first wiring;

[0262] a first conductor pattern formed in a second wiring layer different from the first wiring layer and electrically connected to the first wiring via a first via wiring; and

[0263] a second conductor pattern formed in a third wiring layer different from the first wiring layer and the second wiring layer and electrically connected to the second wiring via a second via wiring;

[0264] The first conductor pattern and the second conductor pattern are opposed to each other via an insulating layer.

[0265] The area of ​​the first region where the first conductor pattern and the second conductor pattern face each other is larger than the area of ​​the first wiring.

[0266] The first wiring has a first extending portion extending along a first direction and a first via junction portion connected to the first via wiring.

[0267] In a plan view, the third wiring has a second extension portion connected between the first substrate terminal and the first via joint portion and longer than the first extension portion.

[0268] In a plan view, the second via wiring is located between the first region and the second substrate terminal, and the first region is located between the first via wiring and the second via wiring.

Claims

1. An electronic device, characterized in that: have: an electronic component comprising a first terminal for outputting a first potential and a second terminal for outputting a second potential different from the first potential; a semiconductor component to which the first potential and the second potential are input; a first capacitor component including a first electrode electrically connected to the first terminal and a second electrode electrically connected to the second terminal; as well as a wiring substrate on which the electronic component, the semiconductor component, and the first capacitor component are mounted, The wiring substrate comprises: a first substrate terminal connected to the first terminal; a first wiring formed in a first wiring layer and electrically connected to the first substrate terminal; a first conductor pattern formed in a second wiring layer different from the first wiring layer and electrically connected to the first wiring via a first via wiring; The second conductor pattern is formed in a third wiring layer different from the first wiring layer and the second wiring layer and is supplied with a first fixed potential. The first conductor pattern and the second conductor pattern are opposed to each other via an insulating layer. The area of ​​the region where the first conductor pattern and the second conductor pattern face each other is larger than the area of ​​the first wiring. The first wiring has a first extending portion extending along a first direction and a first via joint portion connected to the first via wiring. In a plan view, the first extending portion is located between the first via-joint portion and the first substrate terminal, and the first via-joint portion is located between the first electrode of the first capacitor component and the first extending portion of the first wiring.

2. The electronic device according to claim 1, wherein: The wiring substrate has an upper surface and a lower surface opposite to the upper surface. The electronic components and the semiconductor components are respectively mounted on the upper surface of the wiring substrate. The first capacitor component is mounted on the lower surface of the wiring substrate. The first substrate terminal is formed in the first wiring layer and is electrically connected to the first terminal. When viewed from above, the first wiring layer is located closer to the upper surface than to the lower surface. In a plan view, the second wiring layer is located between the first wiring layer and the lower surface.

3. The electronic device according to claim 1, wherein: The first wiring electrically connects the semiconductor component and the electronic component so that the first potential is supplied from the electronic component to the semiconductor component via the first wiring.

4. The electronic device according to claim 2 or 3, characterized in that: A separation distance between the semiconductor component and the first via joint portion is shorter than an extension distance of the first extension portion.

5. The electronic device according to claim 2 or 3, characterized in that: A separation distance between the first substrate terminal and the first via-joint portion is longer than a separation distance between the semiconductor component and the first via-joint portion.

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