Hardware watchdog self-start circuit

Abstract

The invention discloses a hardware watchdog self-starting circuit, comprising a main chip, a pulse detection circuit, an OR gate circuit, a first NOR gate circuit, a delay circuit, a second NOR gate circuit, and a self-starting circuit. When a pulse signal is detected, the OR gate circuit outputs a low level, the first NOR gate circuit outputs a high level, the second NOR gate circuit outputs a low level, the self-starting circuit does not work, and the output voltage is normal; when no pulse signal is detected, the OR gate circuit outputs a high level, the first NOR gate circuit outputs a low level, the second NOR gate outputs a high level first, the self-starting circuit works, stops outputting the voltage, the main chip suspends work, and after a certain delay, the second NOR gate circuit outputs a low level again, outputs a normal voltage, and the main chip continues to work. The circuit structure of the invention is simple, the gate circuit design is adopted, the anti-interference ability is strong, the application range is wide, the power consumption is reduced, the program runaway fault caused by interference is effectively solved, and the overall reliability of the system is improved.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, in particular to a hardware watchdog self-starting circuit. Background Art

[0002] The equipment commonly used in the field of power electronics is, to a certain extent, subject to the possibility of CPU program errors caused by external electromagnetic interference and other reasons. The main chip in an abnormal working state may sometimes output abnormalities, causing malfunctions and even safety hazards.

[0003] At present, in response to the failure of the main chip, the first is to strengthen the anti-interference processing of the MUC power supply, and the second is to add an external watchdog circuit. Once the MUC is found to be in a dead state, it will be reset within the specified time to reduce the time of the uncontrollable state.

[0004] Existing external watchdog circuits usually use watchdog chips. One type is for power-on reset, and the other is for MCU program runaway. These watchdog chips either have simple functions and can only solve a single problem, or are too expensive. Summary of the invention

[0005] In order to solve the above technical problems, the present invention proposes a hardware watchdog self-starting circuit, which solves the power-on reset problem and the program runaway fault problem while reducing the cost.

[0006] The technical solution of the present invention is achieved in this way:

[0007] A hardware watchdog self-starting circuit comprises a main chip, a pulse detection circuit, an OR gate circuit, a first NOR gate circuit, a delay circuit, a second NOR gate circuit and a self-starting circuit, wherein the output end of the main chip is connected to the input end of the pulse detection circuit, the output end of the pulse detection circuit is connected to the input end of the OR gate circuit, the output end of the OR gate circuit is connected to the first input end of the first NOR gate circuit and the input end of the delay circuit, the output end of the first NOR gate circuit is connected to the first input end of the second NOR gate circuit, the output end of the delay circuit is connected to the second input end of the second NOR gate circuit, the output end of the second NOR gate circuit is connected to the input end of the self-starting circuit, and the output voltage of the self-starting circuit is fed back to the main chip; when the pulse detection circuit detects a pulse signal from the main chip, the OR gate circuit outputs a low level to the first NOR gate circuit, the first NOR gate circuit outputs a high level to the second NOR gate circuit, the second NOR gate circuit outputs a low level to the self-start circuit, the self-start circuit does not work, and feeds back the normal output voltage to the main chip, and the main chip works normally; when the pulse detection circuit does not detect the pulse signal from the main chip, the OR gate circuit outputs a high level to the first NOR gate circuit, the first NOR gate circuit outputs a low level to the second NOR gate circuit, the second NOR gate first outputs a high level to the self-start circuit, the self-start circuit works, stops feeding back the output voltage to the main chip, the main chip pauses and resets, after a certain delay, the delay circuit controls the second NOR gate circuit to output a low level to the self-start circuit again, the self-start circuit works, feeds back the normal output voltage to the main chip, and the main chip continues to work.

[0008] Furthermore, the pulse detection circuit includes a first resistor, a first capacitor, a second resistor, a third resistor and a first NMOS tube, one end of the first capacitor is connected to one end of the first resistor, the other end of the first capacitor is connected to one end of the second resistor, the other end of the first resistor is grounded, the other end of the second resistor is connected to the gate of the first NMOS tube, the drain of the first NMOS tube is connected to one end of the third resistor, the other end of the third resistor is connected to a power supply, and the source of the first NMOS tube is grounded; the intersection of one end of the first capacitor and one end of the first resistor is connected to the main chip as the input end of the pulse detection circuit, and the drain and source of the first NMOS tube are connected to the OR gate circuit as the first output end and the second output end of the pulse detection circuit.

[0009] Furthermore, the OR gate circuit includes an OR gate, a fourth resistor, a first NPN transistor, a fifth resistor and a sixth resistor; input pin 1 of the OR gate is connected to the first output end of the pulse detection circuit, input pin 2 of the OR gate is connected to the second output end of the pulse detection circuit, output pin 3 of the OR gate is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the base of the first NPN transistor, the collector of the first NPN transistor is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to a power supply, the emitter of the first NPN transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is grounded; the emitter of the first NPN transistor is connected to the first NOR gate circuit and the delay circuit as the output end of the OR gate circuit.

[0010] Furthermore, the first NOR gate circuit includes a seventh resistor and a first NOR gate, one end of the seventh resistor is connected to the 2 input pin of the first NOR gate, the other end of the seventh resistor is grounded, the 1 input pin of the first NOR gate is connected to the output end of the OR gate circuit, and the 3 output pin of the first NOR gate is connected to the first input end of the second NOR gate circuit.

[0011] Furthermore, the delay circuit includes a ninth resistor, a diode and a second capacitor, one end of the ninth resistor is connected to the output end of the OR gate circuit and the cathode of the diode, the other end of the ninth resistor is connected to the anode of the diode and one end of the second capacitor, the other end of the second capacitor is grounded, and the intersection of the other end of the ninth resistor and the anode of the diode is connected as the output end of the delay circuit and the second input end of the second NOR gate circuit.

[0012] Furthermore, the second NOR gate circuit includes a second NOR gate and a tenth resistor, input pin 1 of the second NOR gate is connected to output pin 3 of the first NOR gate, input pin 2 of the second NOR gate is connected to the output end of the delay circuit, output pin 3 of the second NOR gate is connected to one end of the tenth resistor, and the other end of the tenth resistor is connected to the self-start circuit as the output end of the second NOR gate circuit.

[0013] Furthermore, the self-starting circuit includes a second NPN transistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a light-emitting diode, a second NMOS transistor and a third NPN diode, the base of the second NPN transistor is connected to the other end of the tenth resistor, the collector of the second NPN transistor is connected to one end of the eleventh resistor, one end of the thirteenth resistor and the drain of the second NMOS transistor, the emitter of the second NPN transistor is connected to one end of the twelfth resistor and the anode of the light-emitting diode, the other end of the eleventh resistor is connected to the input voltage, the other end of the twelfth resistor is connected to the base of the third NPN transistor, the collector of the third NPN transistor is connected to the other end of the thirteenth resistor and the gate of the second NMOS transistor, the emitter of the third NPN transistor is grounded, the source of the second NMOS tube is connected to the output voltage, and the cathode of the light-emitting diode is grounded.

[0014] The beneficial effects of the present invention are as follows: the present invention provides a hardware watchdog self-starting circuit, which detects the pulse signal sent by the main chip through the pulse detection circuit, controls the output of the OR gate circuit to be high or low by means of the presence or absence of the pulse signal, and then controls the output of the first OR gate circuit to be high or low, and then controls the output of the second OR gate circuit to be high or low by the high or low level output by the first OR gate circuit and the delay circuit, thereby realizing the control of the self-starting circuit to work or not work, because the self-starting circuit can feedback the normal output voltage or stop feedback of the output voltage to the main chip when it works or not, so that it can be judged whether the system works normally, solves the problem of program running away, controls the self-starting circuit to start automatically at a certain delay time through the delay circuit, realizes the function of resetting the system, solves the problem of power-on reset, and thus ensures the reliable operation of the system. The present invention has a simple circuit structure, adopts a gate circuit design, has strong anti-interference ability, has a wide range of application, reduces power consumption, effectively solves the program running away fault caused by interference, and improves the overall reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a principle block diagram of the hardware watchdog self-starting circuit of the present invention;

[0016] Figure 2 The present invention is a circuit diagram of the hardware watchdog self-starting circuit. DETAILED DESCRIPTION

[0017] In order to more clearly understand the technical content of the present invention, the following embodiments are described in detail, the purpose of which is only to better understand the content of the present invention but not to limit the scope of protection of the present invention. The components in the structure of the embodiment drawings are not scaled according to normal proportions, so they do not represent the actual relative sizes of the structures in the embodiments. The above or upper side of the structure or surface mentioned therein includes the situation where there are other layers in the middle.

[0018] like Figure 1 and Figure 2 As shown, a hardware watchdog self-starting circuit includes a main chip, a pulse detection circuit, an OR gate circuit, a first NOR gate circuit, a delay circuit, a second NOR gate circuit and a self-starting circuit, the output end of the main chip is connected to the input end of the pulse detection circuit, the output end of the pulse detection circuit is connected to the input end of the OR gate circuit, the output end of the OR gate circuit is connected to the first input end of the first NOR gate circuit and the input end of the delay circuit, the output end of the first NOR gate circuit is connected to the first input end of the second NOR gate circuit, the output end of the delay circuit is connected to the second input end of the second NOR gate circuit, the output end of the second NOR gate circuit is connected to the input end of the self-starting circuit, and the output voltage of the self-starting circuit is fed back to the main chip; when the pulse detection circuit detects a pulse signal from the main chip, the OR gate circuit outputs a low When the pulse detection circuit does not detect the pulse signal from the main chip, the OR gate circuit outputs a high level to the first NOR gate circuit, the first NOR gate circuit outputs a high level to the second NOR gate circuit, the second NOR gate circuit outputs a low level to the self-start circuit, the self-start circuit does not work, and feeds back the normal output voltage to the main chip, and the main chip works normally; when the pulse detection circuit does not detect the pulse signal from the main chip, the OR gate circuit outputs a high level to the first NOR gate circuit, the first NOR gate circuit outputs a low level to the second NOR gate circuit, the second NOR gate first outputs a high level to the self-start circuit, the self-start circuit works, stops feeding back the output voltage to the main chip, the main chip suspends work and resets, after a certain delay, the delay circuit controls the second NOR gate circuit to output a low level to the self-start circuit again, the self-start circuit works, feeds back the normal output voltage to the main chip, and the main chip continues to work.

[0019] In the above structure, the pulse detection circuit detects whether the main chip sends a pulse signal, and controls the output of the OR gate circuit to be high or low by means of the presence or absence of the pulse signal, thereby controlling the output of the first OR gate circuit to be high or low, and then controlling the output of the second OR gate circuit to be high or low by the high or low level output of the first OR gate circuit and the delay circuit, thereby realizing the control of the self-starting circuit to work or not work. Since the self-starting circuit works or not, it can feedback the normal output voltage or stop feedback of the output voltage to the main chip, so that it can be judged whether the system works normally, and the problem of program running away is solved. The self-starting circuit is controlled to start automatically at a certain delay time by the delay circuit, and the function of resetting the system is realized, and the problem of power-on reset is solved, thereby ensuring the reliable operation of the system. The circuit structure of the present invention is simple, the gate circuit design is adopted, the anti-interference ability is strong, the application range is wide, the power consumption is reduced, the program running away fault caused by interference is effectively solved, and the overall reliability of the system is improved.

[0020] The pulse detection circuit is used to detect the pulse signal from the main chip MCU, and its output is used to control the OR gate circuit to output a high level or a low level. Preferably, the pulse detection circuit includes a first resistor R1, a first capacitor C1, a second resistor R2, a third resistor R3 and a first NMOS tube Q1, one end of the first capacitor is connected to one end of the first resistor, the other end of the first capacitor is connected to one end of the second resistor, the other end of the first resistor is grounded, the other end of the second resistor is connected to the gate of the first NMOS tube, the drain of the first NMOS tube is connected to one end of the third resistor, the other end of the third resistor is connected to the power supply VCC, and the source of the first NMOS tube is grounded; the intersection of one end of the first capacitor and one end of the first resistor is connected to the main chip as the input end of the pulse detection circuit, and the drain and source of the first NMOS tube are connected to the OR gate circuit as the first output end and the second output end of the pulse detection circuit. The first resistor R1 plays a role in absorbing clutter, and the first capacitor C1 and the second resistor R2 play a role in detecting whether the chip sends out a pulse signal. Only when a pulse signal is detected, the first NMOS tube Q1 is turned on, otherwise it is not turned on.

[0021] The output of the OR gate circuit is used to control the first OR gate circuit to output a high level or a low level. Preferably, the OR gate circuit includes an OR gate U1, a fourth resistor R4, a first NPN transistor Q2, a fifth resistor R5 and a sixth resistor R6; the input pin 1 of the OR gate is connected to the first output end of the pulse detection circuit, the input pin 2 of the OR gate is connected to the second output end of the pulse detection circuit, the output pin 3 of the OR gate is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the base of the first NPN transistor, the collector of the first NPN transistor is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the power supply VCC, the emitter of the first NPN transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is grounded; the emitter of the first NPN transistor is connected to the first OR gate circuit and the delay circuit as the output end of the OR gate circuit.

[0022] The output of the first NOR gate circuit is used to control the second NOR gate circuit to output a high level or a low level together with the delay circuit. Preferably, the first NOR gate circuit includes a seventh resistor R7 and a first NOR gate U2, one end of the seventh resistor is connected to the 2 input pin of the first NOR gate, the other end of the seventh resistor is grounded, the 1 input pin of the first NOR gate is connected to the output end of the NOR gate circuit, and the 3 output pin of the first NOR gate is connected to the first input end of the second NOR gate circuit. The seventh resistor R7 is a pull-down resistor, so that the 2 input pin of the first NOR gate U2 is always at a low level.

[0023] The output of the delay circuit is used to control the output of the second NOR gate circuit with the first NOR gate circuit to be high level or low level. Preferably, the delay circuit includes a ninth resistor R9, a diode D1 and a second capacitor C2. One end of the ninth resistor is connected to the output end of the NOR gate circuit and the cathode of the diode. The other end of the ninth resistor is connected to the anode of the diode and one end of the second capacitor. The other end of the second capacitor is grounded. The intersection of the other end of the ninth resistor and the anode of the diode is connected as the output end of the delay circuit and is connected to the second input end of the second NOR gate circuit. The expected delay time can be obtained by changing the values ​​of the ninth resistor R9 and the second capacitor C2. The diode D1 plays a discharging role.

[0024] The output of the second NOR gate circuit is used to control the on and off of the NPN transistor Q3, thereby controlling whether the self-starting circuit works or not. Preferably, the second NOR gate circuit includes a second NOR gate U3 and a tenth resistor R10, wherein the 1 input pin of the second NOR gate is connected to the 3 output pin of the first NOR gate, the 2 input pin of the second NOR gate is connected to the output end of the delay circuit, the 3 output pin of the second NOR gate is connected to one end of the tenth resistor, and the other end of the tenth resistor is connected to the self-starting circuit as the output end of the second NOR gate circuit. The tenth resistor R10 serves to limit the current and protect the transistor Q3.

[0025] The self-start circuit can feed back normal output voltage or stop feeding back output voltage to the main chip when it is working or not, so as to judge whether the main chip MCU is working normally or not, and realize the self-start function. Preferably, the self-start circuit includes a second NPN transistor Q3, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a light-emitting diode D2, a second NMOS tube Q4 and a third NPN diode Q5, the base of the second NPN transistor is connected to the other end of the tenth resistor, and the collector of the second NPN transistor is connected to one end of the eleventh resistor and one end of the thirteenth resistor. and the drain of the second NMOS tube, the emitter of the second NPN transistor is connected to one end of the twelfth resistor and the anode of the light emitting diode, the other end of the eleventh resistor is connected to the input voltage VIN, the other end of the twelfth resistor is connected to the base of the third NPN transistor, the collector of the third NPN transistor is connected to the other end of the thirteenth resistor and the gate of the second NMOS tube, the emitter of the third NPN transistor is grounded, the source of the second NMOS tube is connected to the output voltage VOUT, and the cathode of the light emitting diode is grounded.

[0026] The working principle of the hardware watchdog self-starting circuit of the present invention is:

[0027] When the circuit is powered on, the main chip sends a pulse signal to the pulse detection circuit through the GPIO port. When the pulse detection circuit detects the pulse signal, the first NMOS tube Q1 is turned on, the 3rd output pin of the OR gate U1 of the OR gate circuit outputs a low level, the first NPN transistor Q2 is not turned on, the 3rd output pin of the first NOR gate U2 of the first NOR gate circuit outputs a high level, the 3rd output pin of the second NOR gate U3 of the second NOR gate circuit outputs a low level, the second NPN transistor Q3 is not turned on, the self-start circuit does not work, the light-emitting diode D2 does not emit light, the input voltage VIN is equal to the normal output voltage VOUT, and the main chip MCU continues to work normally.

[0028] When no pulse signal is detected, the first NMOS tube Q1 is not turned on, the 3rd output pin of the OR gate U1 outputs a high level, the first NPN transistor Q2 is turned on, the 3rd output pin of the first NOR gate U2 outputs a low level, the 3rd output pin of the second NOR gate U3 outputs a high level first, the second NPN transistor Q3 is turned on, the self-start circuit works, the light-emitting diode emits light, VOUT=0, the output voltage stops, the main chip MCU pauses working, after a certain delay, the 3rd output pin of the second NOR gate U3 outputs a low level again, the second PN transistor Q3 is not turned on, the self-start circuit does not work, the light-emitting diode D2 does not emit light, the output voltage is normal VIN=VOUT, and the main chip MCU continues to work normally.

[0029] The above embodiments are to describe the preferred embodiments of the present invention in detail with reference to the accompanying drawings. Those skilled in the art may make various modifications or changes to the above embodiments without departing from the essence of the present invention, which shall fall within the protection scope of the present invention.

Claims

1. A hardware watchdog self-starting circuit, characterized in that: The invention comprises a main chip, a pulse detection circuit, an OR gate circuit, a first NOR gate circuit, a delay circuit, a second NOR gate circuit and a self-starting circuit, wherein the output end of the main chip is connected to the input end of the pulse detection circuit, the output end of the pulse detection circuit is connected to the input end of the OR gate circuit, the output end of the OR gate circuit is connected to the first input end of the first NOR gate circuit and the input end of the delay circuit, the output end of the first NOR gate circuit is connected to the first input end of the second NOR gate circuit, the output end of the delay circuit is connected to the second input end of the second NOR gate circuit, the output end of the second NOR gate circuit is connected to the input end of the self-starting circuit, and the output voltage of the self-starting circuit is fed back to the main chip; when the pulse detection circuit detects a pulse signal from the main chip, the OR gate circuit outputs a low level to the first OR gate circuit. NOT gate circuit, the first NOR gate circuit outputs a high level to the second NOR gate circuit, the second NOR gate circuit outputs a low level to the self-start circuit, the self-start circuit does not work, and feeds back the normal output voltage to the main chip, and the main chip works normally; when the pulse detection circuit does not detect the pulse signal from the main chip, the OR gate circuit outputs a high level to the first NOR gate circuit, the first NOR gate circuit outputs a low level to the second NOR gate circuit, the second NOR gate first outputs a high level to the self-start circuit, the self-start circuit works, stops feeding back the output voltage to the main chip, the main chip suspends work and resets, after a certain delay time, the delay circuit controls the second NOR gate circuit to output a low level to the self-start circuit again, the self-start circuit works, feeds back the normal output voltage to the main chip, and the main chip continues to work.

2. The hardware watchdog self-starting circuit according to claim 1, characterized in that: The pulse detection circuit comprises a first resistor (R1), a first capacitor (C1), a second resistor (R2), a third resistor (R3) and a first NMOS transistor (Q1), one end of the first capacitor is connected to one end of the first resistor, the other end of the first capacitor is connected to one end of the second resistor, the other end of the first resistor is grounded, the other end of the second resistor is connected to the gate of the first NMOS transistor, the drain of the first NMOS transistor is connected to one end of the third resistor, the other end of the third resistor is connected to a power supply (VCC), and the source of the first NMOS transistor is grounded; the intersection of one end of the first capacitor and one end of the first resistor is connected to the main chip as the input end of the pulse detection circuit, and the drain and source of the first NMOS transistor are connected to the OR gate circuit as the first output end and the second output end of the pulse detection circuit.

3. The hardware watchdog self-starting circuit according to claim 2, characterized in that: The OR gate circuit comprises an OR gate (U1), a fourth resistor (R4), a first NPN transistor (Q2), a fifth resistor (R5) and a sixth resistor (R6); input pin 1 of the OR gate is connected to the first output end of the pulse detection circuit, input pin 2 of the OR gate is connected to the second output end of the pulse detection circuit, output pin 3 of the OR gate is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the base of the first NPN transistor, the collector of the first NPN transistor is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to a power supply (VCC), the emitter of the first NPN transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is grounded; the emitter of the first NPN transistor is connected to the first NOR gate circuit and the delay circuit as the output end of the OR gate circuit.

4. The hardware watchdog self-starting circuit according to claim 3, characterized in that: The first NOR gate circuit comprises a seventh resistor (R7) and a first NOR gate (U2), one end of the seventh resistor is connected to the 2 input pin of the first NOR gate, the other end of the seventh resistor is grounded, the 1 input pin of the first NOR gate is connected to the output end of the OR gate circuit, and the 3 output pin of the first NOR gate is connected to the first input end of the second NOR gate circuit.

5. The hardware watchdog self-starting circuit according to claim 4, characterized in that: The delay circuit comprises a ninth resistor (R9), a diode (D1) and a second capacitor (C2), one end of the ninth resistor is connected to the output end of the OR gate circuit and the cathode of the diode, the other end of the ninth resistor is connected to the anode of the diode and one end of the second capacitor, the other end of the second capacitor is grounded, and the intersection of the other end of the ninth resistor and the anode of the diode is connected as the output end of the delay circuit and the second input end of the second NOR gate circuit.

6. The hardware watchdog self-starting circuit according to claim 5, characterized in that: The second NOR gate circuit includes a second NOR gate (U3) and a tenth resistor (R10), wherein input pin 1 of the second NOR gate is connected to output pin 3 of the first NOR gate, input pin 2 of the second NOR gate is connected to the output end of the delay circuit, output pin 3 of the second NOR gate is connected to one end of the tenth resistor, and the other end of the tenth resistor is connected to the self-starting circuit as the output end of the second NOR gate circuit.

7. The hardware watchdog self-starting circuit according to claim 6, characterized in that: The self-starting circuit comprises a second NPN transistor (Q3), an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13), a light emitting diode (D2), a second NMOS transistor (Q4) and a third NPN diode (Q5), wherein the base of the second NPN transistor is connected to the other end of the tenth resistor, the collector of the second NPN transistor is connected to one end of the eleventh resistor, one end of the thirteenth resistor and the drain of the second NMOS transistor, the emitter of the second NPN transistor is connected to one end of the twelfth resistor and the anode of the light emitting diode, the other end of the eleventh resistor is connected to an input voltage (VIN), the other end of the twelfth resistor is connected to the base of the third NPN transistor, the collector of the third NPN transistor is connected to the other end of the thirteenth resistor and the gate of the second NMOS transistor, the emitter of the third NPN transistor is grounded, the source of the second NMOS transistor is connected to an output voltage (VOUT), and the cathode of the light emitting diode is grounded.

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