A time-sharing startup module

Abstract

The present invention provides a time-sharing startup module, relating to the field of load driving technology. The time-sharing startup module includes a startup circuit, a delay circuit, and multiple drive circuits. The delay circuit is electrically connected to the startup circuit and the multiple drive circuits. The startup circuit is configured to generate a clock signal and a reset signal, and transmit the clock signal and the reset signal to the delay circuit. After receiving the clock signal and the reset signal, the delay circuit is configured to sequentially generate multiple startup signals at preset time intervals. The delay circuit is further configured to transmit the multiple startup signals to the drive circuits corresponding to each startup signal. The multiple drive circuits are configured to be turned on in response to the corresponding startup signals, so that multiple loads electrically connected to the multiple drive circuits are sequentially started at preset time intervals. Since the delayed startup of the loads is achieved without using a single-chip microcomputer, the cost of manufacturing the time-sharing startup module is reduced, making it more suitable for practical applications.

Description

Technical Field

[0001] The present invention relates to the technical field of load driving, and in particular to a time-sharing starting module. Background Art

[0002] Currently, the startup of heavy-loaded, high-power equipment such as fans and pumps is mainly divided into direct startup and other startup methods that reduce the starting current. However, in some cases, the startup of multiple power equipment can be carried out in time periods. This can avoid the impact of simultaneous startup on the power grid and avoid affecting the normal operation of other equipment when starting at the same time.

[0003] However, in the existing technology, a multi-channel timed start module can start a group of electrical equipment in time periods and ensure the same start interval, but most of them use single-chip microcomputer control to achieve soft start of the electrical equipment; however, in a strong electromagnetic environment, the single-chip microcomputer is more susceptible to interference, which may cause start-up failure. At the same time, the cost of using a single-chip microcomputer is high, resulting in high cost of the entire start module and uneconomical. Summary of the Invention

[0004] The object of the present invention is to provide a time-sharing startup module to solve the above-mentioned problem.

[0005] The present invention provides a time-sharing starting module, which includes a starting circuit, a delay circuit, and a plurality of driving circuits, wherein the delay circuit is electrically connected to the starting circuit and the plurality of driving circuits;

[0006] The startup circuit is used to generate a clock signal and a reset signal, and transmit the clock signal and the reset signal to the delay circuit;

[0007] The delay circuit is configured to generate a plurality of start signals in sequence according to a preset time interval after receiving the clock signal and the reset signal, wherein the plurality of start signals correspond one to one to the plurality of drive circuits;

[0008] The delay circuit is further configured to transmit the plurality of start signals to the drive circuit corresponding to each start signal respectively;

[0009] The plurality of driving circuits are configured to be turned on in response to the corresponding starting signals, so that the plurality of loads electrically connected to the plurality of driving circuits are started in sequence according to preset time intervals.

[0010] Furthermore, the delay circuit includes a frequency dividing unit and a shifting unit, the starting circuit is electrically connected to the frequency dividing unit and the shifting unit, the frequency dividing unit is electrically connected to the shifting unit, and the shifting unit is electrically connected to the plurality of driving circuits;

[0011] The frequency dividing unit is configured to generate a data input clock signal and an output latch clock signal after receiving the clock signal, and transmit the data input clock signal and the output latch clock signal to the shift unit; wherein the data input clock signal and the output latch clock signal have the same period and opposite levels;

[0012] The shift unit is configured to generate the plurality of start signals in sequence according to the data input clock signal and the output latch clock signal after receiving the reset signal.

[0013] Furthermore, the frequency dividing unit includes a frequency divider, a timing resistor, a timing capacitor, a first switching tube, a second switching tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first signal output terminal, and a second signal output terminal. The first pin of the frequency divider is electrically connected to the timing resistor, the second pin of the frequency divider is electrically connected to the timing capacitor, the timing resistor is electrically connected to the timing capacitor, the output pin of the frequency divider is electrically connected to the base of the first switching tube, the collector of the first switching tube is connected in series with the first resistor and then electrically connected to the power supply circuit, the emitter of the first switching tube is grounded, the second switching tube is connected in parallel with the first switching tube, the base of the second switching tube is connected in series with the third resistor and the second resistor in sequence and then electrically connected to the power supply circuit, the collector of the second switching tube is connected in series with the fourth resistor and then electrically connected to the power supply circuit, the emitter of the second switching tube is grounded, the first signal output terminal is electrically connected between the collector of the first switching tube and the first resistor, and is electrically connected to the connection point between the second resistor and the third resistor, and the second signal output terminal is electrically connected between the collector of the second switching tube and the fourth resistor.

[0014] The first signal output terminal is used to output the data input clock signal;

[0015] The second signal output terminal is used to output the output latch clock signal.

[0016] Furthermore, the frequency dividing unit is used to clear the output latch clock signal after receiving the reset signal.

[0017] Furthermore, the frequency division unit also includes a first capacitor, a first diode, a second diode, a third switch tube, a fifth resistor and a sixth resistor. The startup circuit is connected in series with the first capacitor and the fifth resistor and then electrically connected to the base of the third switch tube. The first diode and the fifth resistor are connected in reverse parallel. The base of the third switch tube is connected in reverse series with the second diode and then grounded. The emitter of the third switch tube is grounded. The collector of the third switch tube is connected in series with the sixth resistor and then electrically connected to the power supply circuit. The second signal output end is also electrically connected between the collector of the third switch tube and the sixth resistor.

[0018] Furthermore, the shift unit includes a shift register and multiple signal output units, the multiple signal output units correspond one-to-one to the multiple driving circuits, the data input clock pin of the shift register is electrically connected to the first signal output end, the output latch clock pin of the shift register is electrically connected to the second signal output end, the reset pin of the shift register is electrically connected to one of the multiple signal output units, and the multiple data output pins of the shift register are respectively electrically connected to one of the signal output units.

[0019] Furthermore, the startup circuit includes a first power signal access terminal, a rectifier bridge, an optocoupler, a seventh resistor, an eighth resistor, a third diode, a fourth switch tube, a clock signal output terminal, and a reset signal output terminal. The first power signal access terminal is sequentially connected in series with the rectifier bridge and the optocoupler, the first output terminal of the optocoupler is reversely connected in series with the third diode and the eighth resistor and then electrically connected to the power circuit, the first output terminal of the optocoupler is connected in series with the seventh resistor and then electrically connected to the base of the fourth switch tube, the emitter of the fourth switch tube is electrically connected to the power circuit, the second output terminal of the optocoupler and the collector of the fourth switch tube are grounded, the clock signal output terminal is electrically connected to the first output terminal of the optocoupler, and the reset signal output terminal is electrically connected to the collector of the fourth switch tube;

[0020] The clock signal output terminal is used to output the clock signal;

[0021] The reset signal output terminal is used to output the reset signal.

[0022] Furthermore, each of the driving circuits includes a fifth switching tube, a relay, a second capacitor, a third capacitor, a ninth resistor, a tenth resistor and a fourth diode. The base of the fifth switching tube is electrically connected to the shift register, the emitter of the fifth switching tube is grounded, the collector of the fifth switching tube is connected in series with the ninth resistor and the relay and then electrically connected to the power supply circuit, the second capacitor is connected in forward series with the fourth diode and then connected in parallel with the ninth resistor and the relay, and the third capacitor is connected in series with the tenth resistor and then connected in parallel with the contacts of the relay.

[0023] Furthermore, the time-sharing startup module further includes a power supply circuit, and the power supply circuit is electrically connected to the startup circuit, the delay circuit, and the plurality of drive circuits.

[0024] Furthermore, the power supply circuit includes a second power signal input terminal, a first voltage conversion unit, and a second voltage conversion unit, and the second power signal input terminal, the first voltage conversion unit, and the second voltage conversion unit are electrically connected in sequence;

[0025] The first voltage conversion unit is used to convert the power voltage connected to the second power signal input terminal into a first DC voltage;

[0026] The second voltage conversion unit is configured to convert the first DC voltage into a second DC voltage.

[0027] Compared with the prior art, the present invention has the following beneficial effects: a time-sharing start-up module provided by the present invention includes a start-up circuit, a delay circuit and multiple drive circuits, the delay circuit is electrically connected to the start-up circuit and the multiple drive circuits, the start-up circuit is used to generate a clock signal and a reset signal, and transmit the clock signal and the reset signal to the delay circuit, the delay circuit is used to generate multiple start-up signals in sequence according to a preset time interval after receiving the clock signal and the reset signal, the multiple start-up signals correspond one-to-one to the multiple drive circuits, the delay circuit is also used to transmit the multiple start-up signals to the drive circuit corresponding to each start-up signal, the multiple drive circuits are used to respond to the corresponding start signals and be turned on, so that the multiple loads electrically connected to the multiple drive circuits are started in sequence according to the preset time interval; since the delayed start-up of the load is achieved without using a single-chip microcomputer, the cost of manufacturing the time-sharing start-up module is reduced, and it is more suitable for practical applications.

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0031] Figure 1 This is a circuit structure block diagram of the time-sharing startup module provided by the present invention.

[0032] Figure 2 This is a circuit diagram of the power supply circuit provided by the present invention.

[0033] Figure 3 This is a circuit diagram of the starting circuit provided by the present invention.

[0034] Figure 4 This is a further circuit structure block diagram of the time-sharing startup module provided by the present invention.

[0035] Figure 5 This is a circuit diagram of the frequency division unit provided by the present invention.

[0036] Figure 6 This is a circuit diagram of the shift unit provided by the present invention.

[0037] Figure 7 This is a circuit diagram of the driving circuit provided by the present invention.

[0038] Icon: 100-time-sharing start module; 110-power supply circuit; 120-start circuit; 130-delay circuit; 132-frequency division unit; 134-shift unit; 140-drive circuit. DETAILED DESCRIPTION

[0039] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely intended to represent selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0041] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0042] The present invention provides a time-sharing starting module 100 for starting multiple loads in a time-sharing manner. Figure 1 , which is a circuit block diagram of a time-sharing startup module 100 provided by the present invention. The time-sharing startup module 100 includes: a power supply circuit 110, a startup circuit 120, a delay circuit 130, and multiple drive circuits 140. The power supply circuit 110 is electrically connected to the startup circuit 120, the delay circuit 130, and the multiple drive circuits 140. The delay circuit 130 is electrically connected to the startup circuit 120 and the multiple drive circuits 140.

[0043] The power supply circuit 110 is used to provide voltage to the startup circuit 120, the delay circuit 130, and the plurality of drive circuits 140. Specifically, the power supply circuit 110 includes a second power signal access terminal J2, a first voltage conversion unit, and a second voltage conversion unit, which are electrically connected in sequence.

[0044] The first voltage conversion unit is used to convert the power voltage connected to the second power signal access terminal J2 into a first DC voltage; the second voltage conversion unit is used to convert the first DC voltage into a second DC voltage.

[0045] See also Figure 2 , which is a circuit diagram of the power supply circuit 110 provided by the present invention. The power supply circuit 110 includes a first voltage conversion chip U5, a second voltage conversion chip U6, a fuse F, a current limiting resistor RX, a first electrolytic capacitor CX1, a second electrolytic capacitor CX2, a varistor RV, a high-frequency transistor CY0, a transient suppression diode TVS, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a light-emitting diode L1.

[0046] The L end of the second power signal access terminal J2 is connected in series with the fuse F, the current limiting resistor RX and the third pin of the voltage conversion chip U5, the N end of the second power signal access terminal J2 is electrically connected to the first pin of the voltage conversion chip U5, one end of the varistor RV is electrically connected between the series fuse F and the current limiting resistor RX, the other end of the varistor RV is electrically connected to the first pin of the voltage conversion chip U5, the first electrolytic capacitor CX1 is connected in parallel with the varistor RV, the fifth pin of the voltage conversion chip U5 is connected in series with the second electrolytic capacitor CX2 and then electrically connected to the seventh pin of the voltage conversion chip U5, the seventh pin of the voltage conversion chip U5 is connected in series with the high-frequency tube CY0 and then electrically connected to the twelfth pin of the voltage conversion chip U5, the voltage conversion chip The twelfth pin of the chip U5 is electrically connected to the fourteenth pin of the voltage conversion chip U5 after being connected in series with the fourth capacitor C4. The transient suppression diode TVS, the fifth capacitor C5, the sixth capacitor C6 and the seventh capacitor C7 are all connected in parallel with the fourth capacitor C4 and grounded. The eleventh resistor R11 and the twelfth resistor R12 are connected in parallel and then connected in series between the fifth capacitor C5 and the sixth capacitor C6. One end of the seventh capacitor C7 is electrically connected to the signal input end of the second voltage conversion chip U6. The ground end of the second voltage conversion chip U6 is grounded. The signal output end of the second voltage conversion chip U6 is connected in series with the eighth capacitor C8 and then grounded. The ninth capacitor C9 is connected in parallel with the eighth capacitor C8. The light-emitting diode L1 is connected in series with the thirteenth resistor R13 and then connected in parallel with the eighth capacitor C8.

[0047] Among them, the fuse F is used for overcurrent and overheating protection, and automatically recovers when the current in the loop returns to normal; the current-limiting resistor RX is used to limit the current output from the second power signal access terminal J2 to the voltage conversion chip U5; the varistor RV can effectively suppress surges in the loop; when the loop is working normally, the transient suppression diode TVS is in a high-resistance state, and once the loop is abnormal, the transient suppression diode TVS quickly changes to a low-resistance state and clamps the abnormal high voltage within a safe voltage, thereby protecting the chip and the loop.

[0048] In addition, the first DC voltage is output by the fourteenth pin of the voltage conversion chip U5. In this embodiment, the first DC voltage is 12V. The second DC voltage is output by the signal output terminal of the second voltage conversion chip U6. In this embodiment, the second DC voltage is 5V.

[0049] Therefore, when the power circuit 110 operates normally, the light emitting diode L1 is lit, indicating that the power circuit 110 outputs a 5V voltage normally.

[0050] In an optional embodiment, the model of the voltage conversion chip U5 is LD03-10B12R2, which is used to convert alternating current into direct current; the second voltage conversion chip U6 is a 7805 voltage regulator.

[0051] The startup circuit 120 is configured to generate a clock signal, a reset signal, and an enable signal, and transmit the clock signal, the reset signal, and the enable signal to the delay circuit 130 .

[0052] See also Figure 3 , which is a circuit diagram of the startup circuit 120 provided by the present invention. The startup circuit 120 includes a first power signal input terminal J1, a rectifier bridge U3, an optocoupler U4, a seventh resistor R7, an eighth resistor R8, a third diode D3, a fourth switch Q4, a clock signal output terminal clock, a reset signal output terminal MR, and an enable signal output terminal OE. The first power signal input terminal J1 is connected in series with the rectifier bridge U3 and the optocoupler U4 in sequence. The first output terminal of the optocoupler U4 is connected in reverse series with the third diode D3 and the eighth resistor R8 and then electrically connected to the power circuit 110. The first output terminal of the optocoupler U4 is connected in series with the seventh resistor R7 and then electrically connected to the base of the fourth switch Q4. The emitter of the fourth switch Q4 is electrically connected to the power circuit 110. The second output terminal of the optocoupler U4 and the collector of the fourth switch Q4 are grounded. The clock signal output terminal clock is electrically connected to the first output terminal of the optocoupler U4. The reset signal output terminal MR is electrically connected to the collector of the fourth switch Q4. The enable signal output terminal OE is electrically connected between the eighth resistor R8 and the third diode D3. The fourth switch tube Q4 is a PNP transistor.

[0053] The clock signal output terminal clock is used to output a clock signal, the reset signal output terminal MR is used to output a reset signal, and the enable signal output terminal OE is used to output an enable signal.

[0054] It can be understood that when the first power signal input terminal J1 is connected to the power supply voltage, the optocoupler U4 is turned on, the level of the clock signal output terminal clock is pulled low, and the third diode D3 is turned on, so that the level of the enable signal output terminal OE is pulled low. At the same time, the base of the fourth switch tube Q4 is pulled low like the level of the clock signal output terminal clock, the fourth switch tube Q4 is turned on, and the level of the reset signal output terminal MR is pulled high by the power supply circuit 110.

[0055] Therefore, when the first power signal input terminal J1 is connected to the power voltage, the clock signal output terminal clock and the enable signal output terminal OE output low levels, and the reset signal output terminal MR outputs high levels.

[0056] The delay circuit 130 is configured to generate a plurality of start signals in sequence at preset time intervals after receiving a clock signal and a reset signal, and transmit the plurality of start signals to the driving circuit 140 corresponding to each start signal.

[0057] The plurality of start-up signals correspond one-to-one to the plurality of driving circuits 140 .

[0058] See also Figure 4 The delay circuit 130 includes a frequency dividing unit 132 and a shifting unit 134 . The starting circuit 120 is electrically connected to the frequency dividing unit 132 and the shifting unit 134 . The frequency dividing unit 132 is electrically connected to the shifting unit 134 . The shifting unit 134 is electrically connected to the plurality of driving circuits 140 .

[0059] The frequency dividing unit 132 is used to generate a data input clock signal and an output latch clock signal after receiving the clock signal, and transmit the data input clock signal and the output latch clock signal to the shift unit 134; wherein the data input clock signal and the output latch clock signal have the same period and opposite levels.

[0060] The frequency dividing unit 132 is further configured to clear the output latched clock signal after receiving a reset signal.

[0061] See also Figure 5, which is a circuit diagram of the frequency division unit 132 provided by the present invention. The frequency dividing unit 132 includes a frequency divider U1, a timing resistor Rtc, a timing capacitor Ctc, a first switch Q1, a second switch Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first signal output terminal SH_CP, a second signal output terminal ST_CP, a first capacitor C1, a first diode D1, a second diode D2, a third switch Q3, a fifth resistor R5, and a sixth resistor R6. A first pin of the frequency divider U1 is electrically connected to the timing resistor Rtc, a second pin of the frequency divider U1 is electrically connected to the timing capacitor Ctc, the timing resistor Rtc is electrically connected to the timing capacitor Ctc, a sixth pin of the frequency divider U1 is electrically connected to the clock signal output terminal clock, an output pin of the frequency divider U1 is electrically connected to the base of the first switch Q1, a collector of the first switch Q1 is connected in series with the first resistor R1, and then is electrically connected to the power supply circuit 110, an emitter of the first switch Q1 is grounded, the second switch Q2 is connected in parallel with the first switch Q1, and the base of the second switch Q2 is connected in series with the first switch Q1. The third resistor R3 and the second resistor R2 are connected in series, and then electrically connected to the power circuit 110. The collector of the second switch Q2 is connected in series with the fourth resistor R4, and then electrically connected to the power circuit 110. The emitter of the second switch Q2 is grounded. The first signal output terminal SH_CP is electrically connected between the collector of the first switch Q1 and the first resistor R1, and is also electrically connected to the connection point between the second resistor R2 and the third resistor R3. The second signal output terminal ST_CP is electrically connected between the collector of the second switch Q2 and the fourth resistor R4. The reset signal output terminal MR is connected in series with the first capacitor C1 and the fifth resistor R5, and then electrically connected to the base of the third switch Q3. The first diode D1 is connected in antiparallel to the fifth resistor R5. The base of the third switch Q3 is connected in antiparallel series with the second diode D2, and then grounded. The emitter of the third switch Q3 is grounded. The collector of the third switch Q3 is connected in series with the sixth resistor R6, and then electrically connected to the power circuit 110. The second signal output terminal ST_CP is also electrically connected between the collector of the third switch Q3 and the sixth resistor R6.

[0062] The first signal output terminal SH_CP is used to output a data input clock signal; the second signal output terminal ST_CP is used to output a latch clock signal.

[0063] In an optional embodiment, the frequency divider U1 is a CD4541 frequency divider. The CD4541 frequency divider is a programmable frequency divider whose oscillation frequency can be matched through the timing resistor Rtc and the timing capacitor Ctc.

[0064] Among them, the oscillation period satisfies the formula: T = 2.3nRtc*Ctc, and the oscillation frequency satisfies the formula: n is the frequency division coefficient.

[0065] The frequency division coefficient is determined by the voltage level U1.A at the 12th pin of the frequency divider U1 and the voltage level U1.B at the 13th pin. Specifically, if U1.A = 0 and U1.B = 0, then n = 4096; if U1.A = 0 and U1.B = 1, then n = 512; if U1.A = 1 and U1.B = 0, then n = 128; and if U1.A = 1 and U1.B = 1, then n = 32768.

[0066] For example, if the timing resistor Rtc is 22 kilo-ohms, the timing capacitor Ctc is 10nF, and the frequency division coefficient n is 32768, then the oscillation period T = 2.3 × 32768 × 22 × 10 × 10 -6 ≈16s.

[0067] Furthermore, the sixth pin of the frequency divider U1 is a reset pin, which is active high. That is, when the sixth pin of the frequency divider U1 is high, the frequency divider U1 is reset; when the sixth pin of U1 is low, the frequency divider U1 operates normally. Thus, when the startup circuit 120 operates normally, its clock signal output terminal "clock" provides a low-level signal to the sixth pin of the frequency divider U1, enabling the frequency divider U1 to operate normally.

[0068] When the divider U1 is operating normally, its output pin outputs a different level signal every oscillation cycle. Taking an oscillation cycle of 15 seconds as an example, the output pin of the divider U1 outputs a high level at 15 seconds, a low level at 30 seconds, a high level at 45 seconds, and so on.

[0069] When the output pin of the frequency divider U1 outputs a high level, the first switch tube Q1 is turned on, and the level of the first signal output terminal SH_CP is pulled down to ground by the first switch tube Q1. At the same time, the base of the second switch tube Q2 is at a low level, the second switch tube Q2 is turned off, and the level of the second signal output terminal ST_CP is pulled up by the power supply circuit 110; when the output pin of the frequency divider U1 outputs a low level, the first switch tube Q1 is turned off, and the level of the first signal output terminal SH_CP is pulled up by the power supply circuit 110, so that the second switch tube Q2 is turned on, and the level of the second signal output terminal ST_CP is pulled down to ground by the second switch tube Q2.

[0070] Thus, when the output pin of the frequency divider U1 outputs a high level, the first signal output terminal SH_CP outputs a low level signal, and the second signal output terminal ST_CP outputs a high level signal. When the output pin of the frequency divider U1 outputs a low level, the first signal output terminal SH_CP outputs a high level signal, and the second signal output terminal ST_CP outputs a low level signal. In other words, the level signal of the second signal output terminal ST_CP is opposite to the level signal of the second signal output terminal ST_CP, and the period of each signal is twice the oscillation period.

[0071] In addition, when the startup circuit 120 is just started, the reset signal output terminal MR outputs a high level signal to the base of the third switch tube Q3, so that the third switch tube Q3 is turned on, so that the level of the second signal output terminal ST_CP is pulled low, completing a reset operation.

[0072] It should be noted that by setting the first capacitor C1, the effect of passing AC and blocking DC is achieved, so that the third switch tube Q3 can be turned on only when the startup circuit 120 is just started and the output signal of the reset signal output terminal MR contains an AC signal; and after the startup circuit 120 is started, the reset signal output terminal MR outputs a high-level DC signal, which cannot pass through the first capacitor C1, thereby ensuring that the second signal output terminal ST_CP can output signals normally.

[0073] The shift unit 134 is configured to generate a plurality of start signals in sequence according to the data input clock signal and the output latch clock signal after receiving the reset signal.

[0074] See also Figure 6 , which is a circuit diagram of the shift unit 134 provided by the present invention. The shift unit 134 includes a shift register U2 and multiple signal output units. The multiple signal output units correspond one-to-one to the multiple driving circuits 140. The data input clock pin SHCP of the shift register U2 is electrically connected to the first signal output terminal SH_CP, the output latch clock pin STCP of the shift register U2 is electrically connected to the second signal output terminal ST_CP, the reset pin of the shift register U2 is electrically connected to one of the multiple signal output units, the multiple data output pins of the shift register U2 are respectively electrically connected to one of the signal output units, the enable pin of the shift register U2 is electrically connected to the enable signal output terminal OE of the startup circuit 120, and the reset pin of the shift register U2 is electrically connected to the reset signal output terminal MR of the startup circuit 120.

[0075] In this embodiment, the shift register U2 is a 74HC595, which is an 8-bit serial input / output or parallel output shift register. The data input clock pin SHCP of the shift register U2 shifts the data in the shift register when it rises, and holds the data in the shift register when it falls. The output latch clock pin STCP of the shift register U2 shifts the data in the shift register into the data storage register when it rises, and remains unchanged when it falls.

[0076] Therefore, when the startup circuit 120 is started, the reset signal output terminal MR outputs a high level, and outputs a high level signal to a driving circuit 140 through a signal output unit among multiple signal output units; at the same time, the enable signal output terminal OE outputs a low level, and the shift register U2 works normally. At the same time, the first signal output terminal SH_CP and the second signal output terminal ST_CP input reverse high and low levels every oscillation cycle of the frequency dividing unit 132, so that after a preset time interval, the Q0 pin of the shift register U2 outputs a high level signal and maintains it, and after another preset time interval, the Q1 pin outputs a high level signal and maintains it, and after another preset time interval, the Q2 pin outputs a high level signal and maintains it, thereby achieving the effect of generating multiple startup signals in sequence according to the preset time interval.

[0077] The plurality of driving circuits 140 are configured to be turned on in response to corresponding start-up signals, so that the plurality of loads electrically connected to the plurality of driving circuits 140 are sequentially started at preset time intervals.

[0078] See also Figure 7 , which is a circuit diagram of the drive circuit 140 provided by the present invention. Each drive circuit 140 includes a fifth switch tube Q5, a relay KM, a second capacitor C2, a third capacitor C3, a ninth resistor R9, a tenth resistor R10, and a fourth diode D4. The base of the fifth switch tube Q5 is electrically connected to the shift register, the emitter of the fifth switch tube Q5 is grounded, the collector of the fifth switch tube Q5 is connected in series with the ninth resistor R9 and the relay KM, and then electrically connected to the power circuit 110. The second capacitor C2 is connected in forward direction in series with the fourth diode D4, and then connected in parallel with the ninth resistor R9 and the relay KM. The third capacitor C3 is connected in series with the tenth resistor R10, and then connected in parallel with the contact of the relay KM.

[0079] When the driving circuit 140 receives the start signal, the base of the fifth switch tube Q5 is connected to the high level signal, the fifth switch tube Q5 is turned on, the coil of the relay KM is energized, and the contacts of the relay KM are closed, so that the load works.

[0080] Among them, the fourth diode D4 is a freewheeling diode, which has a freewheeling function when the coil of the relay KM is turned off; the ninth resistor R9 and the second capacitor C2 can reduce the voltage when the relay KM is energized, thereby reducing the power consumption of the relay KM; the tenth resistor R10 and the third capacitor C3 form an RC circuit and are connected in parallel with the contacts of the relay KM, which can absorb sparks from the contacts of the relay KM.

[0081] At the same time, since different drive circuits 140 receive the start signal at different times, each drive circuit 140 makes the load work according to the above principle after receiving the start signal, thereby realizing time-sharing start of multiple loads and avoiding the impact of simultaneous start on the power grid.

[0082] In addition, in the present invention, the chips such as the divider U1 and the shift register U2 are all CMOS chips, which have stronger anti-interference capabilities than single-chip microcomputers and are not easily interfered with in strong electromagnetic environments; more importantly, the cost is low, making the manufactured time-sharing startup module 100 competitive in the market.

[0083] In summary, an embodiment of the present invention provides a time-sharing startup module, including a startup circuit, a delay circuit, and multiple drive circuits. The delay circuit is electrically connected to the startup circuit and the multiple drive circuits. The startup circuit is used to generate a clock signal and a reset signal, and transmit the clock signal and the reset signal to the delay circuit. After receiving the clock signal and the reset signal, the delay circuit is used to generate multiple startup signals in sequence according to a preset time interval. The multiple startup signals correspond one-to-one to the multiple drive circuits. The delay circuit is also used to transmit the multiple startup signals to the drive circuit corresponding to each startup signal respectively. The multiple drive circuits are used to be turned on in response to the corresponding startup signals, so that the multiple loads electrically connected to the multiple drive circuits are started in sequence according to the preset time interval. Since the delayed startup of the load is achieved without using a single-chip microcomputer, the cost of manufacturing the time-sharing startup module is reduced, and it is more suitable for practical applications.

[0084] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A time-sharing startup module, characterized in that: The time-sharing startup module includes a startup circuit, a delay circuit, and multiple drive circuits, wherein the delay circuit is electrically connected to the startup circuit and the multiple drive circuits; the delay circuit includes a frequency division unit and a shift unit, wherein the startup circuit is electrically connected to the frequency division unit and the shift unit, wherein the frequency division unit is electrically connected to the shift unit, and wherein the shift unit is electrically connected to the multiple drive circuits; The startup circuit is used to generate a clock signal and a reset signal, and transmit the clock signal and the reset signal to the delay circuit; The delay circuit is configured to generate a plurality of start signals in sequence according to a preset time interval after receiving the clock signal and the reset signal, wherein the plurality of start signals correspond one to one to the plurality of drive circuits; The delay circuit is further configured to transmit the plurality of start signals to the drive circuit corresponding to each start signal respectively; The plurality of driving circuits are configured to be turned on in response to the corresponding starting signals, so that the plurality of loads electrically connected to the plurality of driving circuits are started in sequence according to a preset time interval; The frequency dividing unit is configured to generate a data input clock signal and an output latch clock signal after receiving the clock signal, and transmit the data input clock signal and the output latch clock signal to the shift unit; wherein the data input clock signal and the output latch clock signal have the same period and opposite levels; The shift unit is configured to generate the plurality of start signals in sequence according to the data input clock signal and the output latch clock signal after receiving the reset signal; The frequency division unit includes a frequency divider, a timing resistor, a timing capacitor, a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first signal output end, and a second signal output end. The first pin of the frequency divider is electrically connected to the timing resistor, the second pin of the frequency divider is electrically connected to the timing capacitor, the timing resistor is electrically connected to the timing capacitor, the output pin of the frequency divider is electrically connected to the base of the first switch tube, the collector of the first switch tube is connected in series with the first resistor and then electrically connected to the power supply circuit, the emitter of the first switch tube is grounded, and the second switch tube is connected in parallel with the first switch tube. The base of the second switching tube is sequentially connected in series with the third resistor and the second resistor, and then electrically connected to the power circuit. The collector of the second switching tube is connected in series with the fourth resistor, and then electrically connected to the power circuit. The emitter of the second switching tube is grounded. The first signal output end is electrically connected between the collector of the first switching tube and the first resistor, and is electrically connected to the connection point between the second resistor and the third resistor. The second signal output end is electrically connected between the collector of the second switching tube and the fourth resistor. When the frequency divider is operating normally, the output pin of the frequency divider outputs a signal of a different level every other oscillation cycle. The first signal output terminal is used to output the data input clock signal; The second signal output terminal is used to output the output latch clock signal.

2. The time-sharing startup module according to claim 1, characterized in that: The frequency dividing unit is used to clear the output latch clock signal after receiving the reset signal.

3. The time-sharing startup module according to claim 2, characterized in that: The frequency division unit also includes a first capacitor, a first diode, a second diode, a third switch tube, a fifth resistor and a sixth resistor. The startup circuit is connected in series with the first capacitor and the fifth resistor and then electrically connected to the base of the third switch tube. The first diode and the fifth resistor are connected in reverse parallel. The base of the third switch tube is connected in reverse series with the second diode and then grounded. The emitter of the third switch tube is grounded. The collector of the third switch tube is connected in series with the sixth resistor and then electrically connected to the power supply circuit. The second signal output end is also electrically connected between the collector of the third switch tube and the sixth resistor.

4. The time-sharing startup module according to claim 1, characterized in that: The shift unit includes a shift register and multiple signal output units, the multiple signal output units correspond one-to-one to the multiple driving circuits, the data input clock pin of the shift register is electrically connected to the first signal output end, the output latch clock pin of the shift register is electrically connected to the second signal output end, the reset pin of the shift register is electrically connected to one of the multiple signal output units, and the multiple data output pins of the shift register are respectively electrically connected to one of the signal output units.

5. The time-sharing startup module according to claim 4, characterized in that: The startup circuit includes a first power signal input terminal, a rectifier bridge, an optocoupler, a seventh resistor, an eighth resistor, a third diode, a fourth switch tube, a clock signal output terminal, and a reset signal output terminal. The first power signal input terminal is sequentially connected in series with the rectifier bridge and the optocoupler. The first output terminal of the optocoupler is reversely connected in series with the third diode and the eighth resistor and then electrically connected to the power circuit. The first output terminal of the optocoupler is connected in series with the seventh resistor and then electrically connected to the base of the fourth switch tube. The emitter of the fourth switch tube is electrically connected to the power circuit. The second output terminal of the optocoupler and the collector of the fourth switch tube are grounded. The clock signal output terminal is electrically connected to the first output terminal of the optocoupler. The reset signal output terminal is electrically connected to the collector of the fourth switch tube. The clock signal output terminal is used to output the clock signal; The reset signal output terminal is used to output the reset signal.

6. The time-sharing startup module according to claim 4, characterized in that: Each of the driving circuits includes a fifth switching tube, a relay, a second capacitor, a third capacitor, a ninth resistor, a tenth resistor, and a fourth diode. The base of the fifth switching tube is electrically connected to the shift register, the emitter of the fifth switching tube is grounded, the collector of the fifth switching tube is connected in series with the ninth resistor and the relay, and then electrically connected to the power supply circuit. The second capacitor is connected in forward series with the fourth diode and then connected in parallel with the ninth resistor and the relay. The third capacitor is connected in series with the tenth resistor and then connected in parallel with the contacts of the relay.

7. The time-sharing startup module according to any one of claims 1 to 6, characterized in that: The time-sharing startup module further includes a power supply circuit, which is electrically connected to the startup circuit, the delay circuit, and the plurality of drive circuits.

8. The time-sharing startup module according to claim 7, characterized in that: The power supply circuit includes a second power signal input terminal, a first voltage conversion unit and a second voltage conversion unit, wherein the second power signal input terminal, the first voltage conversion unit and the second voltage conversion unit are electrically connected in sequence; The first voltage conversion unit is used to convert the power voltage connected to the second power signal input terminal into a first DC voltage; The second voltage conversion unit is configured to convert the first DC voltage into a second DC voltage.

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