Wordline bridges in 3D memory arrays

Abstract

The present invention discloses a wordline bridge in a 3D memory array. The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number of wordline steps in a 3D memory array. A device may include a memory array having memory cells. The memory array includes a first block of pages of memory cells in a first tile and a second block of pages of memory cells in a second tile. The device may also include a polysilicon wordline bridge that couples a first wordline of the first block to a second wordline of the second block for coupling the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of the polysilicon connecting the first tile to the second tile.

Description

Technical Field

[0001] The present disclosure relates to using word line bridges in memory arrays. Background Art

[0002] In a 3D flash memory array, memory cells and word lines are stacked vertically in tiers of memory cells. To access and control the word lines, the sides of the memory array terminate in one or more staircase structures to allow connecting metal contact structures to be connected to the word lines. The staircase structures include steps or landings for each word line to connect each word line to a metal contact. To increase the density of the memory array, memory manufacturers have attempted to add additional tiers of memory cells to the memory array. An undesirable side effect of more tiers is the increase in the size of the stairs used to electrically connect to, access, and control the word lines of the memory array. The stairs, while functionally important, consume silicon real estate and hinder the goals of shrinking die size or increasing die density. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Features and advantages of the claimed subject matter will be apparent from the following detailed description of embodiments consistent therewith, which description should be considered with reference to the accompanying drawings, in which:

[0004] Figure 1 illustrates a system block diagram consistent with several embodiments of the present disclosure;

[0005] Figure 2 illustrates an example side view diagram of a memory die consistent with one embodiment of the present disclosure;

[0006] Figure 3 illustrates an example perspective view illustration of a wordline bridge system consistent with one embodiment of the present disclosure;

[0007] Figure 4 illustrates a simplified example top view of a memory array implementing wordline bridges between tiles of memory cells consistent with one embodiment of the present disclosure;

[0008] Figure 5 An embodiment consistent with the present disclosure is shown. Figure 4 a simplified example top view of a memory array masked to define and maintain word line bridges between tiles of the memory array; and

[0009] Figure 6 Illustrated is a flow diagram of operations for fabricating wordline bridges between tiles in a memory array, consistent with various embodiments of the present disclosure.

[0010] While the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications, and variations therein will be apparent to those skilled in the art. DETAILED DESCRIPTION

[0011] Embodiments of the present disclosure enable memory manufacturers to reclaim portions of silicon real estate that have been lost to wordline access structures. In 3D flash memory arrays, memory cells, and the wordlines that control the memory cells, are stacked vertically in levels. In some memory arrays, the wordlines are stacked 32 levels high (or more), so obtaining access to individual wordlines becomes complicated. In particular, access to individual wordlines is required to couple the wordlines to wordline control circuitry, which is fabricated below the memory array, and access to individual wordlines is required to couple the wordlines to metal levels formed above the memory array. Existing solutions for providing wordline access to both the lower control circuitry and the upper metal levels include using wordline access structures in each tile of a memory block.

[0012] A tile of memory blocks includes several memory blocks, for example, 200 blocks, and each block includes a stack of memory cell pages (e.g., a 32-level stack). The memory array has been partitioned into tiles of memory blocks to reduce the length of any one wordline. Longer wordlines have higher parasitic capacitance and higher resistance, which slows the transmission of control signals and alters their voltage levels. In conventional tiles of memory blocks, each memory block includes a wordline access structure that couples the block's wordlines to lower control circuitry and to upper metal levels.

[0013] Wordline access structures include through-array vias (TAVs) and wordline ladders. Array vias couple the upper metal level to the lower control circuitry. Wordline ladders couple the wordline blocks of memory cells to the upper metal level, for example, via metal contacts. These wordline access structures occupy space that could otherwise be used for additional memory cells (e.g., increased memory cell density). Furthermore, as more levels are added to future memory arrays to achieve greater memory density, the size of the wordline access structures will likely also have to increase, further depleting the real estate of the memory cells (within a fixed size).

[0014] Embodiments of the present disclosure include a wordline bridge that enables a block of memory cells from one tile to share the wordline access structure of another tile. By sharing the wordline access structure between the two tiles, one of the tiles does not need to be manufactured with a duplicate wordline access structure. In addition, by sharing the wordline access resource that is located approximately in the center of the two tiles, the effective length of the driven wordline remains approximately the same as the wordline length of the individual tiles. In exchange for the wordline bridge, the space saved from eliminating redundant wordline access structures can achieve increased memory cell density in both current and future memory product offerings. For example, for a 62.2 mm 2 Process of Record (“POR”), the disclosed wordline bridge implementation can release an estimated 0.8mm 2 , which is approximately 1.2%. For 175.8 mm 2 The POR, word line bridge implementation can release 3.2 mm 2 , which is approximately 1.8%.Thus, implementation of the disclosed embodiments of the word line bridge may provide 1-2% (or more) increased availability of silicon real estate, which may be used for additional memory cell density.

[0015] According to one embodiment, a memory array is provided. According to one embodiment, the memory array includes a plurality of memory cells. According to one embodiment, the memory array includes a first tile of a first plurality of memory cells (first ones) of the plurality of memory cells, wherein the first tile includes a first block of the first plurality of memory cells of the plurality of memory cells. According to one embodiment, the memory array includes a second tile of a second plurality of memory cells (second ones) of the plurality of memory cells, wherein the second tile includes a second block of the second plurality of memory cells of the plurality of memory cells. According to one embodiment, the memory array includes a word line bridge coupled between the first block of the first plurality of memory cells of the plurality of memory cells and the second block of the second plurality of memory cells of the plurality of memory cells.

[0016] According to one embodiment, a system is provided. According to one embodiment, the system includes a memory controller and a memory array. According to one embodiment, the memory array includes a plurality of memory cells. According to one embodiment, the memory array includes a first tile of a first plurality of memory cells in the plurality of memory cells, wherein the first tile includes a first block of the first plurality of memory cells in the plurality of memory cells. According to one embodiment, the memory array includes a second tile of a second plurality of memory cells in the plurality of memory cells, wherein the second tile includes a second block of the second plurality of memory cells in the plurality of memory cells. According to one embodiment, the memory array includes a word line bridge coupled between the first block of the first plurality of memory cells in the plurality of memory cells and the second block of the second plurality of memory cells in the plurality of memory cells.

[0017] According to one embodiment, a method is provided. According to one embodiment, the method includes forming a first tile of a memory cell block of a memory array. According to one embodiment, the method includes forming a second tile of the memory cell block of the memory array. According to one embodiment, the method includes forming a word line bridge that electrically couples the first tile of the memory cell block to the second tile of the memory cell block.

[0018] Figure 1 A system block diagram 100 consistent with several embodiments of the present disclosure is illustrated. The system 100 may correspond to a computing device, including but not limited to a server, a workstation computer, a desktop computer, a laptop computer, a tablet computer (e.g., iPad®, Galaxy Tab®, etc.), an ultraportable computer, an ultramobile computer, a netbook computer, and / or a small notebook computer; a mobile phone, including but not limited to a smartphone (e.g., iPhone®, an Android®-based phone, a Blackberry®, a Symbian®-based phone, a Palm®-based phone, etc.), and / or a feature phone.

[0019] According to one embodiment, system 100 may include a processor 102 communicatively coupled to a chipset 104, peripheral device(s) 106, and memory 108. According to one embodiment, processor 102, chipset 104, peripheral device(s) 106, and memory 108 are communicatively and / or physically coupled to each other via one or more buses 110. According to one embodiment, processor 102 may correspond to a single-core or multi-core general-purpose processor, such as those provided by Intel® Corporation, among others. According to one embodiment, chipset 104 may include, for example, a set of electronic components including the one or more buses 110 for facilitating communication between components of the system, and the set of electronic components manages data flow between processor 102, memory 108, and peripheral device(s) 106. According to one embodiment, the peripheral device(s) 106 may include, for example: user interface device(s) including a display, a touch screen display, a printer, a keypad, a keyboard, etc., communication logic, wired and / or wireless, storage device(s) including a hard drive, a solid-state drive, removable storage media, etc. It should be noted that the system 100 is simplified for ease of illustration and description.

[0020] According to one embodiment, the memory 108 is coupled to the processor 102 and is configured to receive instructions, receive addresses, receive data, and provide data to the processor 102 and the bus 110 in response to one or more instructions received from the processor 102. According to one embodiment, the memory 108 may include one or more memory controllers and one or more memory arrays, which are provided in one or more packages or dices. According to one embodiment, the memory 108 may be a non-volatile memory, such as a storage medium that does not require power to maintain the state of the data stored in the storage medium. The non-volatile memory may include, but is not limited to, NAND flash memory (e.g., single-level cell ("SLC"), multi-level cell ("MLC"), triple-level cell ("TLC"), quad-level cell ("QLC"), or some other NAND), NOR memory, solid-state memory (e.g., planar or three-dimensional (3D) NAND flash memory or NOR flash memory), a memory device using a chalcogenide phase change material (e.g., chalcogenide glass), a byte-addressable non-volatile memory device, a ferroelectric memory, a silicon-oxide-nitride-oxide-silicon (SONOS) memory, a polymer memory (e.g., a ferroelectric polymer memory), a byte-addressable random access memory (BAM ... The present invention relates to 3D cross-point memory, ferroelectric transistor random access memory (Fe-TRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM, PRAM), resistive memory, ferroelectric memory (F-RAM, FeRAM), spin transfer torque memory (STT), thermally assisted switching memory (TAS), millipede memory, floating junction gate memory (FJGRAM), magnetic tunnel junction (MTJ) memory, electrochemical cell (ECM) memory, binary oxide filament cell memory, interface switching memory, battery-backed RAM, Austenite memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), etc. In some embodiments, the byte-addressable random access 3D cross-point memory may include a transistor-free, stackable cross-point architecture in which memory cells are located at the intersection of word lines and bit lines and are individually addressable, and in which bit storage is based on changes in bulk resistance, according to various embodiments.

[0021] According to one embodiment, the memory 108 includes a memory controller 112 configured to address, write to, and read from a memory array 114. According to one embodiment, the memory controller 112 is configured to perform memory access operations, such as reading from and / or writing to a target memory cell, ECC checking operations, and memory cell recovery operations. According to one embodiment, the memory array 114 includes a plurality of memory cells organized in one or more strings (e.g., columns), pages (e.g., word lines or rows), blocks, tiles, and planes of memory cells.

[0022] According to one embodiment, memory controller 112 uses bitline control logic and wordline control logic to address and access memory array 114. According to one embodiment, memory controller 112 includes bitline control logic 116. According to one embodiment, bitline control logic 116 controls a first plurality of bitlines 118 (individually, for example, bitline 118a) of a first tile 120 of memory array 114 and controls a second plurality of bitlines 122 (individually, for example, bitline 122a) of a second tile 123 of memory array 114. According to one embodiment, bitline control logic 116 includes control logic for suppressing voltages of the first and second pluralities of bitlines 118 and 122.

[0023] According to one embodiment, the memory controller 112 includes wordline control logic 124. According to one embodiment, the wordline control logic 124 applies voltage levels to a first plurality of wordlines 126 (individually, for example, wordline 126a) of the first tile 120 and applies voltage levels to a second plurality of wordlines 134 (individually, for example, wordline 134a) of the second tile 123. According to one embodiment, the wordline control logic 124 includes a voltage regulator that generates one or more read voltage levels and write voltage levels for accessing memory cells (e.g., memory cells 130, 138) within the first tile 120 and the second tile 123 of the memory array 114.

[0024] According to one embodiment, wordline control logic 124 is configured to receive target wordline address(es) from memory controller 112 and select or access a wordline for a read (or write) operation. For example, wordline control logic 124 can be configured to select a target wordline by coupling a wordline select bias voltage from a voltage regulator to the target wordline. According to one embodiment, wordline control logic 124 can be configured to deselect a target wordline by decoupling the target wordline from the wordline select bias voltage and / or by coupling a wordline deselect bias voltage to the wordline. According to one embodiment, wordline control logic 124 includes a global wordline driver. According to one embodiment, wordline control logic 124 includes a select gate source ("SGS") and a select gate drain ("SGD") driver. According to one embodiment, the voltage regulator is a wordline ("WL") regulator. According to one embodiment, wordline control logic 124 is fabricated at least partially below memory array 114, for example, using under-array CMOS ("CUA") fabrication technology.

[0025] According to one embodiment, memory controller 112 may include additional logic to facilitate memory array operations and communications with one or more of processor 102, chipset 104, and peripheral device(s) 106. According to one embodiment, memory controller 112 may include one or more of the following: memory controller logic 140, an error repository 142, sense circuitry 144, ECC logic 146, recovery logic 148, a parameter repository 150, and a current source 152. Memory controller logic 140 may be configured to perform operations associated with memory controller 112. For example, memory controller logic 140 may manage communications with processor 102 and may be configured to identify one or more target word lines associated with each received memory address (e.g., in a read request). According to one embodiment, error repository 142 includes failure types for memory read or access failures. According to one embodiment, sense circuitry 144 may be configured to detect, for example, the amount of current passed through a memory cell during a read operation. According to one embodiment, ECC logic 146 may be configured to provide error checking functionality for memory controller 112. According to one embodiment, the recovery logic 148 is configured to manage the recovery of failed reads / writes of associated memory cells identified by the ECC logic 146 and / or the memory controller logic 140. The parameter repository 150 is configured to store the number of adjacent memory cells to be selected, as well as parameters associated with the sequence of recovery pulses. According to one embodiment, the number of adjacent memory cells to be selected can be based at least in part on the type of failure (e.g., read / write), the memory array density, and / or the maximum current available from the current source 152. According to one embodiment, the current source 152 supplies current to one or more portions of the memory 108.

[0026] The memory array 114 can be physically and / or logically organized into two or more tiles of memory cells to improve access (e.g., read / write) speed to the memory cells (e.g., memory cells 130, 138). A wordline can be a conductive length of silicon (e.g., polysilicon) that electrically couples the control gates of a physical page of memory cells to wordline control logic 124 (e.g., which can include one or more voltage regulators). The longer the wordline length, the greater the effect of parasitic capacitance and wordline resistance on the transmission of control signals to the memory cells. For example, if the entire length of the memory array 114 is driven by a single wordline (assuming a single-page memory array), the voltage level at the control gates of the memory cells farthest from the wordline control logic 124 can be significantly lower (e.g., due to voltage drops) than the voltage level at the control gates of the memory cells closest to the wordline control logic 124. Similarly, voltage levels at the control gates of memory cells farthest from wordline control logic 124 may propagate or arrive significantly later (eg, due to capacitive time delays) than voltage levels at the control gates of memory cells closest to wordline control logic 124 .

[0027] In order to reduce wordline length and thereby reduce the effects of parasitic capacitance and wordline resistance, the memory array 114 can be broken up or physically divided into a number of tiles. According to one embodiment, the first tile 120 and the second tile 123 are examples of tiles that may comprise the memory array 114. Although dividing the memory array 114 into tiles provides the benefits of reduced overall wordline resistance and reduced parasitic capacitance, this benefit comes at the expense of increased silicon real estate being used to provide access to the wordlines. According to one embodiment, because dedicating more silicon to wordline access (e.g., wordline exit) generally results in less silicon available for memory cells, the improved performance obtained from reduced wordline resistance and parasitic capacitance comes at the potential expense of increased memory cell density in the memory array 114.

[0028] According to one embodiment, the memory array 114 includes a wordline bridge 136 to enable the first tile 120 to share a wordline access structure with the second tile 123. According to one embodiment, the wordline control logic 124 provides control voltages or signals to the first tile 120 or to the second tile 123 at least in part through the wordline bridge 136. According to one embodiment, the wordline bridge 136 electrically couples at least some of the wordlines 126 of the first tile 120 with at least some of the wordlines 134 of the second tile 123. According to one embodiment, the wordline bridge 136 electrically couples a block of the wordlines 126 of the first tile 120 with a block of the wordlines 134 of the second tile 123. According to one embodiment, the wordline bridge 136 can electrically couple all of the wordlines 126 of the first tile 120 with all of the wordlines 134 of the second tile 123. According to one embodiment, the wordline bridge 136 can span the physical distance between the first tile 120 and the second tile 123, thereby physically coupling the first tile 120 to the second tile 123. According to one embodiment, the wordline bridge 136 can represent a single wordline bridge or can represent multiple wordline bridges between the first tile 120 and the second tile 123. According to one embodiment, by physically coupling the first tile 120 to the second tile 123, and by having the first tile 120 and the second tile 123 share wordline access structures, the wordline access structures of the first tile (e.g., wordline ladders and / or through array vias (TAVs)) can be reduced or eliminated. Thus, according to one embodiment, including the wordline bridge 136 in the memory array 114 can achieve increased memory cell density within the memory 108 while approximately maintaining the tile-based performance of the memory array 114.

[0029] Figure 2 A simplified example side view illustration of a memory die 200 consistent with one embodiment of the present disclosure is illustrated. According to one embodiment, the memory die 200 includes a 3D flash memory architecture and utilizes a wordline bridge to share wordline access structures between two tiles of a memory array. According to one embodiment, the memory die 200 may correspond to Figure 1 Memory 108.

[0030] According to one embodiment, memory die 200 includes a memory array 202 and peripheral circuitry 204. According to one embodiment, memory array 202 includes memory cells 205 and memory cells 206 that are accessed (e.g., read / written) using peripheral circuitry 204. According to one embodiment, peripheral circuitry 204 is fabricated at least partially below memory array 202 in memory die 200, such as by using under-array CMOS fabrication technology.

[0031] According to one embodiment, the memory array 202 is partitioned into a first tile 208 and a second tile 210. Although two tiles are shown and described, according to one embodiment, the memory array 202 can be partitioned into tens or hundreds of tiles to facilitate access and operation of the memory array 202. According to one embodiment, the first tile 208 includes a memory block 212, which includes memory cells 205 and a word line access structure 218. According to one embodiment, the word line access structure 218 represents a word line access structure that can be partially or completely eliminated from the first tile 208 by sharing the word line access structure between the first tile 208 and the second tile 210. According to one embodiment, the word line access structure 218 includes reduced array vias 220 and eliminated word line stairs 222. According to one embodiment, the reduced array vias 220 represent a reduced or eliminated number of array vias connecting the word lines for the memory cells 205 to the peripheral circuitry 204 below the memory array 202. In accordance with one embodiment, the eliminated wordline ladder 222 represents a wordline ladder structure that (in the absence of the present disclosure) could be used to connect the wordline of the memory cell 205 to a metal contact for connection to an upper metal level. In accordance with one embodiment, the eliminated wordline ladder 222 need not be included in the memory block 212 because the memory block 212 shares the wordline access structure with the second tile 210. For purposes of illustration, the wordline access structure 218 is shown disproportionately larger than the memory cell 205. In practice, the memory cell 205 can occupy a significantly larger area in the memory array than the wordline access structure 218, in accordance with one embodiment.

[0032] According to one embodiment, the second tile 210 includes a memory block 224 that includes memory cells 206 and a wordline access structure 226. According to one embodiment, the wordline access structure 226 includes an array via 228 and a wordline ladder 230. According to one embodiment, the array via 228 passes through the memory block 224 to couple the upper metal level to the peripheral circuitry 204. According to one embodiment, the wordline ladder 230 provides a step and / or a structure for metal contacts to connect the wordline of the memory cell 206 to the upper metal level at the top or above the memory array 202.

[0033] According to one embodiment, the second tile 210 is electrically coupled to the first tile 208 via a wordline bridge 232 to facilitate sharing of wordline access structures between the memory block 212 and the memory block 224. According to one embodiment, the wordline bridge 232 enables the memory block 212 to be manufactured without the wordline access structures 218, or with a reduced set of wordline access structures 218. In one embodiment, the eliminated wordline ladder 222 is not manufactured in the memory block 212 because the memory block 212 utilizes the wordline ladder 230. In one embodiment, the reduced array vias 220 include fewer array vias than the array vias 228. In one embodiment, the reduced array vias 220 are eliminated from the memory block 212 because the memory block 212 utilizes the array vias 228. According to one embodiment, the wordline bridge 232 enables the memory block 212 to utilize the array vias 228 of the memory block 224 to access the peripheral circuit 204. According to one embodiment, wordline bridge 232 enables memory block 212 to access upper metal levels through wordline ladder 230 of memory block 224. Thus, according to one embodiment, wordline bridge 232 reduces the silicon real estate occupied by wordline access structure 218 by enabling memory block 212 to access circuitry above and / or below memory array 202 by sharing wordline access structure 226 of memory block 224.

[0034] According to one embodiment, peripheral circuitry 204 includes a word line driver 234 and a bit line driver 236 that drive word lines and bit lines of memory array 202 .

[0035] Figure 3 An example perspective diagram of a wordline bridge system 300 consistent with one embodiment of the present disclosure is illustrated. According to one embodiment, the wordline bridge system 300 includes a first tile 302 of memory cells and a second tile 304 of memory cells electrically coupled together using a wordline bridge 306. According to one embodiment, the wordline bridge 306 may be coupled to a first tile 302 of memory cells and a second tile 304 of memory cells. Figure 1 The word line bridge 133 and / or Figure 2 Corresponding to the word line bridge 232.

[0036] According to one embodiment, the memory cell block of the first tile 302 includes word lines 308a, dielectrics 310a, 308b, 310b, 308c, 310c, 308d, and 310d (collectively, word line stack 312). According to one embodiment, word lines 308a, 308b, 308c, and 308d (collectively, word lines 308) are a simplified representation of many word lines (e.g., 32 word lines) that may be included in a 3D flash memory array. According to one embodiment, word lines 308 are conductive layers, such as silicon or polysilicon layers. According to one embodiment, dielectrics 310a, 310b, 310c, and 310d (collectively, dielectric 310) are a simplified representation of many dielectric layers that may be used to separate word lines 308. According to one embodiment, dielectric 310 is an oxide layer. According to one embodiment, dielectric 310 is a silicon dioxide layer. According to one embodiment, the memory cell block of the first tile 302 includes a memory cell string 314 of memory cells 316 included in the memory cell block of the first tile 302. According to one embodiment, the memory cell string 314 is a simplified illustration representing, for example, 2 kb of memory cells.

[0037] According to one embodiment, the memory cell block of the second tile 304 includes word lines 318a, dielectrics 320a, 318b, 320b, 318c, 320c, 318d, and 320d (collectively, word line stack 322). According to one embodiment, word lines 318a, 318b, 318c, and 318d (collectively, word lines 318) are a simplified representation of many word lines (e.g., 32 word lines) that may be included in a 3D flash memory array. According to one embodiment, word lines 318 are conductive layers, such as silicon or polysilicon layers. According to one embodiment, dielectrics 320a, 320b, 320c, and 320d (collectively, dielectric 320) are a simplified representation of many dielectric layers that may be used to separate word lines 318. According to one embodiment, dielectric 320 is an oxide layer. According to one embodiment, dielectric 320 is a silicon dioxide layer. According to one embodiment, the memory cell block of the second tile 304 includes memory cells 324 (not shown) included in the memory cell block of the second tile 304 .

[0038] According to one embodiment, the memory cell block of the second tile 304 includes a word line access structure 326 that provides access to the word line 318 to the upper metal level and the lower peripheral circuitry. According to one embodiment, the word line access structure 326 is connected to Figure 2328 . The wordline access structure 326 corresponds to the wordline access structure 226 of the second tile 304. According to one embodiment, the wordline access structure 326 includes an array via 328. According to one embodiment, the array via 328 provides access to the wordline 318 to the metal levels and circuitry fabricated below the memory cell block of the second tile 304. According to one embodiment, the array via 328 individually includes holes 328a, 328b, 328c, and 328d, which couple the upper metal levels to the circuitry below the memory cell array and which couple the metal contacts 334 to the circuitry below the memory cell array.

[0039] According to one embodiment, the word line access structure 326 includes a word line ladder 330. According to one embodiment, the word line ladder 330 provides access to the word line 318 to the metal levels and circuitry fabricated above the memory cell block of the second tile 304. According to one embodiment, the word line ladder 330 includes a word line ladder step 332a that provides access to the word line 318a, a word line ladder step 332b that provides access to the word line 318b, a word line ladder step 332c that provides access to the word line 318c, and a word line ladder step 332d that provides access to the word line 318d. Although the word line ladder 330 is illustrated as having only four steps for simplicity, according to one embodiment, the word line ladder 330 may include as many steps as there are word lines included in the word line stack 322. According to one embodiment, word line staircase 330 provides metal contacts 334 (individually metal contacts 334 a , 334 b , 334 c , and 334 d ) with access to word line 318 .

[0040] According to one embodiment, wordline bridge 306 electrically couples wordline 308 to wordline 318 to enable wordline access structure 326 to access wordline 308. According to one embodiment, wordline bridge 306 comprises the same layers as wordline stacks 312, 322. According to one embodiment, wordline bridge 306 comprises a width 336, a height 338, and a length 340. According to one embodiment, width 336 is a percentage or fraction of height 338. According to one embodiment, width 336 is one-quarter of the height 338 of wordline bridge 306. According to one embodiment, width 336 may be some other fraction of the height 338 of wordline bridge 306. According to one embodiment, length 340 spans the distance between a memory cell block of a first tile 302 and a memory cell block of a second tile 304.

[0041] According to one embodiment, an advantage of the wordline bridge 306 is that the area consumed by the wordline access structure 326 is not duplicated, either for the blocks of memory cells of the second tile 304 and the four-memory cell blocks of the first tile 302. Although the wordline bridge system 300 illustrates a single instance of the wordline bridge 306, in an implementation, according to one embodiment, a wordline bridge is fabricated to connect each block of the first tile to each block of the second tile, sharing each of the wordline ladders of the second tile with blocks of the first tile.

[0042] Figure 4 A simplified example top view of a memory array 400 implementing word line bridges between tiles of memory cells consistent with various embodiments of the present disclosure is illustrated. The memory array 400 may be connected to Figure 1 The memory array 114 and / or Figure 2 4. Memory array 400 includes a first memory plane 402 and a second memory plane 404. Memory plane 402 includes a first tile 406 (tile 0), a second tile 408 (tile 2), a third tile 410 (tile 4), and a fourth tile 412 (tile 6). Second memory plane 404 includes a fifth tile 414 (tile 1), a sixth tile 416 (tile 3), a seventh tile 418 (tile 5), and an eighth tile 420 (tile 7).

[0043] According to one embodiment, the first tile 406 includes a plurality of blocks 422 of memory cells (individually, such as block 422a). According to one embodiment, the plurality of blocks 422 of memory cells include memory cell regions 424 (individually, such as memory cell region 424a) and reduced array vias 426 (individually, such as reduced array via 426a).

[0044] According to one embodiment, the second tile 408 includes a plurality of blocks 428 of memory cells (individually, such as block 428a). According to one embodiment, the plurality of blocks 428 of memory cells include a memory cell region 430 (individually, such as memory cell region 430a), array vias 432 (individually, such as reduced array via 432a), and word line ladders 434 (individually, such as word line ladder 434a).

[0045] According to one embodiment, the plurality of blocks 422 of memory cells (first tile 406) are electrically coupled to the plurality of blocks 428 of memory cells (second tile 408) using a plurality of wordline bridges 436 (individually, for example, wordline bridge 436a). According to one embodiment, the configuration of wordline bridges coupling a block of memory cells of one tile to a block of memory cells of another tile is repeated throughout the first memory plane 402 and throughout the second memory plane 404. Although two memory planes 402, 404 are illustrated, the memory array 400 may include fewer memory planes or more memory planes according to various embodiments.

[0046] Figure 5 Illustrated are various embodiments consistent with the present disclosure. Figure 4 A simplified example top view of a memory array 400 masked to define and maintain word line bridges between tiles of the memory array 400. According to one embodiment, to define Figure 4 In order to form word line bridges, the memory array 400 can be covered with multiple word line bridge masks to maintain the silicon layer connecting the blocks of one tile to the blocks of another tile. According to one embodiment, the word line bridge masks can include a first word line bridge tile mask 502, a second word line bridge tile mask 504, a third word line bridge tile mask 506, and a fourth word line bridge tile mask 508. According to one embodiment, the word line bridge tile masks 502, 504, 506 and 508 can be applied after the first word line ladder mask 510 and the second word line ladder mask 512 are deposited. According to one embodiment, the first word line ladder mask 510 and the second word line ladder mask 512 can be repeatedly modified to individually form each word line ladder step of the word line ladder. According to one embodiment, by applying the word line bridge tile masks on top of the word line ladder masks, the word line bridges connecting the blocks of one tile to the blocks of another tile can be defined and maintained during the manufacture of the memory array 400. According to one embodiment, the word line bridge tile masks 502 , 504 , 506 , and 508 are hard masks and may be formed of Alox, HDP carbon, or other hard mask materials as known in the art.

[0047] Figure 6 Illustrated is a flowchart 600 of operations for fabricating wordline bridges between tiles in a memory array consistent with various embodiments of the present disclosure. According to one embodiment, operations may be performed to fabricate wordline bridges that may enable reduced silicon real estate to be dedicated to wordline exit circuitry and which may enable increased memory cell density in a 3D flash memory array.

[0048] The operations of flowchart 600 may begin at operation 602. A first tile of a block of memory cells of a memory array may be formed at operation 604. A second tile of a block of memory cells of the memory array may be formed at operation 606. A word line bridge may be formed at operation 608, the word line bridge electrically coupling the first tile of the block of memory cells to the second tile of the block of memory cells. According to one embodiment, the word line bridge may be formed by growing or depositing a hard mask (e.g., Alox or HDP carbon) over the first tile of the block, the second tile of the block, and a silicon (e.g., polysilicon) strip connecting the word lines of the first tile of the block to the word lines of the second tile of the block. According to one embodiment, the width of the word line bridge may be 1 / 4, 1 / 3, 1 / 2, or some other fraction of the height of the word line bridge, which may be the same as the height of the word line stack for the block of the first tile or for the block of the second tile. When the width of the word line bridge decreases, the resistance of the word line bridge increases. When the width of the word line bridge increases, the capacitance of the word line bridge increases. According to one embodiment, when designing or determining the width of the word line bridge, the resistance and capacitance characteristics of the word line bridge are taken into account. The operations of flowchart 600 may end at operation 610. Thus, according to various embodiments, the operations of flowchart 600 are configured to form a word line bridge to at least partially replace the word line ladder in certain memory tiles and achieve increased memory cell density in a 3D flash memory array.

[0049] Although Figure 6 Various operations are illustrated, but according to one embodiment, it is understood that instead of Figure 6 All operations described in are necessary for other embodiments. In fact, it is fully contemplated herein that in other embodiments of the present disclosure, Figure 6 The operations depicted in the drawings and / or other operations described herein may be combined in a manner or order not specifically shown in any of the drawings, but still be fully consistent with the present disclosure. Therefore, claims related to features and / or operations that are not specifically shown in a single drawing are deemed to be within the scope and content of the present disclosure.

[0050] This application provides the following technical solutions:

[0051] 1. A memory array comprising:

[0052] a plurality of memory cells;

[0053] a first tile of a first plurality of memory cells in the plurality of memory cells, wherein the first tile comprises a first block of the first plurality of memory cells in the plurality of memory cells;

[0054] a second tile of a second plurality of memory cells in the plurality of memory cells, wherein the second tile comprises a second block of the second plurality of memory cells in the plurality of memory cells; and

[0055] A word line bridge is coupled between the first block of the first plurality of memory cells in the plurality of memory cells and the second block of the second plurality of memory cells in the plurality of memory cells.

[0056] 2. The memory array according to technical solution 1, wherein the word line bridge comprises multiple polysilicon layers and multiple oxide layers.

[0057] 3. The memory array according to technical solution 2, wherein every two of the multiple polysilicon layers are separated by one of the multiple oxide layers.

[0058] 4. The memory array according to technical solution 2, wherein each of the multiple polysilicon layers is connected to a word line of the first block of the first plurality of memory cells among the multiple memory cells, and is connected to a word line of the second block of the second plurality of memory cells among the multiple memory cells.

[0059] 5. The memory array according to claim 1 , wherein the width of the word line bridge is in a range from 1 / 8 to 3 / 8 of the height of the word line bridge, wherein the height of the word line bridge is the height of the word line stack of the first block of the first plurality of memory cells among the plurality of memory cells.

[0060] 6. The memory array of claim 1, wherein the first tile comprises a first plurality of blocks of the first plurality of memory cells in the plurality of memory cells, wherein the second tile comprises a second plurality of blocks of the second plurality of memory cells in the plurality of memory cells, and wherein the memory array further comprises:

[0061] A plurality of word line bridges are used to couple the first plurality of blocks to the second plurality of blocks.

[0062] 7. The memory array according to claim 1, further comprising:

[0063] a word line ladder formed in the second block of the second plurality of memory cells in the plurality of memory cells to provide access to the second block of the second plurality of memory cells in the plurality of memory cells and to the first block of the first plurality of memory cells in the plurality of memory cells from one or more metal levels through the word line bridge.

[0064] 8. The memory array according to technical solution 7, wherein the word line ladder is formed in the word line of the second block of the second plurality of memory cells in the plurality of memory cells, wherein the ladder provides a plurality of steps for coupling to a conductive contact portion.

[0065] 9. The memory array according to claim 1, further comprising:

[0066] a set of array vias in the second block of the second plurality of memory cells of the plurality of memory cells, the array vias coupling an upper metal level to a word line driver disposed below the memory array,

[0067] Wherein word lines of the first block of a first plurality of memory cells in the plurality of memory cells are electrically coupled to a word line driver through a word line bridge and through the set of array vias.

[0068] 10. The memory array of claim 1 , wherein the word line bridge is defined at least in part by forming a hard mask over the first tile and over the second tile during fabrication of a word line staircase structure in the word lines of the second block of a second plurality of memory cells in the plurality of memory cells.

[0069] 11. The memory array according to technical solution 1, wherein the memory array includes a plurality of tiles, and each of the plurality of tiles includes a plurality of blocks of the plurality of memory cells, wherein the first tile and the second tile are two of the plurality of tiles.

[0070] 12. A system comprising:

[0071] a memory controller; and

[0072] A memory array, the memory array comprising:

[0073] a plurality of memory cells;

[0074] a first tile of a first plurality of memory cells in the plurality of memory cells, wherein the first tile comprises a first block of the first plurality of memory cells in the plurality of memory cells;

[0075] a second tile of a second plurality of memory cells in the plurality of memory cells, wherein the second tile comprises a second block of the second plurality of memory cells in the plurality of memory cells; and

[0076] A word line bridge is coupled between the first block of the first plurality of memory cells in the plurality of memory cells and the second block of the second plurality of memory cells in the plurality of memory cells.

[0077] 13. The system according to technical solution 12, wherein the word line bridge comprises multiple polysilicon layers and multiple oxide layers.

[0078] 14. A system according to technical solution 13, wherein every two of the multiple polysilicon layers are separated by one of the multiple oxide layers.

[0079] 15. A system according to technical solution 13, wherein the multiple polysilicon layers are connected to the first multiple word lines of the first block of the first plurality of memory cells among the multiple memory cells, and are connected to the second multiple word lines of the second block of the second plurality of memory cells among the multiple memory cells.

[0080] 16. The system according to technical solution 12, wherein the height of the word line bridge is the height of the word line stack of the first block of the first plurality of memory cells in the plurality of memory cells.

[0081] 17. The system of claim 12, wherein the first tile comprises a first plurality of blocks of the first plurality of memory cells in the plurality of memory cells, wherein the second tile comprises a second plurality of blocks of the second plurality of memory cells in the plurality of memory cells, and the memory array further comprises:

[0082] A plurality of word line bridges are used to couple the first plurality of blocks to the second plurality of blocks.

[0083] 18. The system according to technical solution 12 further comprises:

[0084] a word line ladder formed in the second block of the second plurality of memory cells in the plurality of memory cells to provide access to the second block of the second plurality of memory cells in the plurality of memory cells and to the first block of the first plurality of memory cells in the plurality of memory cells from one or more metal levels through the word line bridge.

[0085] 19. The system according to technical solution 12 further comprises:

[0086] a set of array vias in the second block of a second plurality of memory cells in the plurality of memory cells, the array vias coupling an upper metal level to a word line driver disposed below the memory array,

[0087] Wherein word lines of the first block of a first plurality of memory cells in the plurality of memory cells are electrically coupled to a word line driver through a word line bridge and through the set of array vias.

[0088] 20. The system of claim 12, wherein the word line bridge is defined at least in part by forming a hard mask over the first tile and over the second tile during fabrication of a word line staircase structure in the word lines of the second block of a second plurality of memory cells in the plurality of memory cells.

[0089] 21. A method comprising:

[0090] forming a first tile of a block of memory cells of a memory array;

[0091] forming a second tile of a block of memory cells of the memory array; and

[0092] A word line bridge is formed that electrically couples the first tile of a block of memory cells to the second tile of the block of memory cells.

[0093] 22. The method according to technical solution 21, wherein forming a word line bridge includes forming a hard mask over the first tile, the second tile, and a polysilicon layer between the first tile and the second tile of a memory cell block of a memory array.

[0094] 23. The method according to technical solution 22 further comprises:

[0095] forming a step mask adjacent to said second tile of the block before forming the hard mask;

[0096] forming a staircase structure in word lines of the second tile of the memory cell block; and

[0097] A metal contact structure is formed on the staircase structure to enable the second tile of the block and the first tile of the block to receive a control signal through the metal contact structure and through the word line bridge.

[0098] 24. The method according to technical solution 21 further comprises:

[0099] A plurality of array vias are formed through the second tile and between an upper metal level and word line control logic to couple the first tile of the memory cell block to the word line control logic through a word line bridge.

[0100] As used in any embodiment herein, the term "logic" may refer to an app, software, firmware, and / or circuitry configured to perform any of the aforementioned operations. Software may be embodied as a software package, code, instructions, an instruction set, and / or data that is recorded on a non-transitory computer-readable storage medium. Firmware may be embodied as code, instructions, an instruction set, and / or data that is hard-coded (e.g., non-volatile) in a memory device.

[0101] "Circuitry," as used in any embodiment herein, may include, for example, individually or in any combination, hardwired circuitry, programmable circuitry such as a computer processor including one or more separate instruction processing cores, state machine circuitry, and / or firmware storing instructions executed by programmable circuitry. Logic may collectively or individually be embodied as circuitry forming part of a larger system, such as an integrated circuit (IC), an application specific integrated circuit (ASIC), a system on a chip (SoC), a desktop computer, a laptop computer, a tablet computer, a server, a smartphone, or the like.

[0102] In some embodiments, a hardware description language can be used to specify circuit and / or logic implementations for various logic and / or circuits described herein. For example, in one embodiment, the hardware description language can conform to or be compatible with the Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), which can implement semiconductor fabrication of one or more circuits and / or logic described herein. VHDL can conform to or be compatible with IEEE Standard 1076-1987, IEEE Standard 1076.2, IEEE 1076.1, IEEE Draft 3.0 of VHDL-2006, IEEE Draft 4.0 of VHDL-2008, and / or other versions of the IEEE VHDL standard and / or other hardware description standards.

[0103] Example

[0104] Examples of the present disclosure include subject matter related to wordline bridges in memory arrays, such as methods, means for performing acts of methods, memory arrays, or systems, as discussed below.

[0105] Example 1. According to this example, a memory array is provided. The memory array includes a plurality of memory cells, and a first tile of a first plurality of memory cells in the plurality of memory cells. The first tile includes a first block of the first plurality of memory cells in the plurality of memory cells. The memory array includes a second tile of a second plurality of memory cells in the plurality of memory cells, and the second tile includes a second block of the second plurality of memory cells in the plurality of memory cells. The memory array includes a word line bridge coupled between the first block of the first plurality of memory cells in the plurality of memory cells and the second block of the second plurality of memory cells in the plurality of memory cells.

[0106] Example 2. This example includes elements of Example 1, wherein the word line bridge includes multiple polysilicon layers and multiple oxide layers.

[0107] Example 3. This example includes elements of Example 2, wherein every two of the plurality of polysilicon layers are separated by one of the plurality of oxide layers.

[0108] Example 4. This example includes the elements of Example 2, wherein each of the plurality of polysilicon layers is connected to a word line of the first block of the first plurality of memory cells in the plurality of memory cells and to a word line of the second block of the second plurality of memory cells in the plurality of memory cells.

[0109] Example 5. This example includes the elements of Example 1, wherein the width of the word line bridge is approximately 1 / 4 (e.g., between 1 / 8 and 3 / 8) the height of the word line bridge, wherein the height of the word line bridge is the height of the word line stack of the first block of the first plurality of memory cells in the plurality of memory cells.

[0110] Example 6. This example includes elements of Example 1, wherein the first tile includes a first plurality of blocks of the first plurality of memory cells in the plurality of memory cells, wherein the second tile includes a second plurality of blocks of the second plurality of memory cells in the plurality of memory cells, and wherein the memory array further includes a plurality of word line bridges for coupling the first plurality of blocks to the second plurality of blocks.

[0111] Example 7. This example includes the elements of Example 1, further comprising a word line ladder formed in the second block of the second plurality of memory cells in the plurality of memory cells to provide access to the second block of the second plurality of memory cells in the plurality of memory cells and to the first block of the first plurality of memory cells in the plurality of memory cells from one or more metal levels through the word line bridge.

[0112] Example 8. This example includes the elements of Example 7, wherein the word line staircase is formed in a word line of the second block of the second plurality of memory cells in the plurality of memory cells, wherein the staircase provides a plurality of steps for coupling to conductive contacts.

[0113] Example 9. This example includes the elements of Example 1, further comprising a set of array vias in the second block of the second plurality of memory cells in the plurality of memory cells, the array vias coupling an upper metal level to a word line driver disposed below the memory array, wherein word lines of the first block of the first plurality of memory cells in the plurality of memory cells are electrically coupled to the word line driver through a word line bridge and through the set of array vias.

[0114] Example 10. This example includes the elements of Example 1, wherein the word line bridge is defined at least in part by forming a hard mask over the first tile and over the second tile during fabrication of a word line staircase structure in word lines of the second block of a second plurality of memory cells in the plurality of memory cells.

[0115] Example 11. This example includes the elements of Example 1, wherein the memory array comprises a plurality of tiles, and each of the plurality of tiles comprises a plurality of blocks of the plurality of memory cells, wherein the first tile and the second tile are two of the plurality of tiles.

[0116] Example 12. This example includes elements of Example 1, wherein a width of the word line bridge is between 1 / 8 and 1 / 4 of a height of the word line bridge.

[0117] Example 13. This example includes the elements of Example 1, wherein the width of the wordline bridge is between ¼ and ½ of the height of the wordline bridge.

[0118] Example 14. This example includes the elements of Example 1, wherein the word line bridge includes at least 32 polysilicon layers.

[0119] Example 15. According to this example, a system is provided. The system includes a memory controller and a memory array. The memory array includes a plurality of memory cells, and a first tile of a first plurality of memory cells in the plurality of memory cells. The first tile includes a first block of the first plurality of memory cells in the plurality of memory cells. The memory array includes a second tile of a second plurality of memory cells in the plurality of memory cells. The second tile includes a second block of the second plurality of memory cells in the plurality of memory cells. The memory array includes a word line bridge coupled between the first block of the first plurality of memory cells in the plurality of memory cells and the second block of the second plurality of memory cells in the plurality of memory cells.

[0120] Example 16. This example includes elements of Example 15, wherein the word line bridge includes multiple polysilicon layers and multiple oxide layers.

[0121] Example 17. This example includes elements of Example 16, wherein every two of the plurality of polysilicon layers are separated by one of the plurality of oxide layers.

[0122] Example 18. This example includes the elements of Example 16, wherein the plurality of polysilicon layers are connected to a first plurality of word lines of the first block of the first plurality of memory cells in the plurality of memory cells and to a second plurality of word lines of the second block of the second plurality of memory cells in the plurality of memory cells.

[0123] Example 19. This example includes the elements of Example 15, wherein the height of the word line bridge is a height of the word line stacks of the first block of the first plurality of memory cells in the plurality of memory cells.

[0124] Example 20. This example includes the elements of Example 15, wherein the first tile includes first blocks of the first plurality of memory cells in the plurality of memory cells, and wherein the second tile includes second blocks of the second plurality of memory cells in the plurality of memory cells. The memory array further includes a plurality of wordline bridges for coupling the first blocks to the second blocks.

[0125] Example 21. This example includes the elements of Example 15, further comprising a word line ladder formed in the second block of the second plurality of memory cells in the plurality of memory cells to provide access to the second block of the second plurality of memory cells in the plurality of memory cells and to the first block of the first plurality of memory cells in the plurality of memory cells from one or more metal levels through the word line bridge.

[0126] Example 22. This example includes the elements of Example 15, further comprising a set of array vias in the second block of a second plurality of memory cells in the plurality of memory cells, the array vias coupling an upper metal level to a word line driver disposed below the memory array, wherein word lines of the first block of a first plurality of memory cells in the plurality of memory cells are electrically coupled to the word line driver through a word line bridge and through the set of array vias.

[0127] Example 23. This example includes the elements of Example 15, wherein the word line bridge is defined at least in part by forming a hard mask over the first tile and over the second tile during fabrication of a word line staircase structure in word lines of the second block of a second plurality of memory cells in the plurality of memory cells.

[0128] Example 24. This example includes the elements of Example 15, further comprising word line circuitry for executing word line control logic, the word line circuitry being disposed at least partially beneath the memory array; and bit line circuitry for executing bit line control logic, the bit line control logic being disposed at least partially beneath the memory array.

[0129] Example 25. This example includes the elements of Example 15, wherein the second block of the second plurality of memory cells in the plurality of memory cells includes one or more word line access structures shared with the first block of the first plurality of memory cells in the plurality of memory cells via a word line bridge.

[0130] Example 26. According to this example, a method is provided. The method includes forming a first tile of a memory cell block of a memory array; forming a second tile of the memory cell block of the memory array; and forming a word line bridge that electrically couples the first tile of the memory cell block to the second tile of the memory cell block.

[0131] Example 27. This example includes the elements of Example 26, wherein forming a word line bridge includes forming a hard mask over the first tile, the second tile, and a polysilicon layer between the first tile and the second tile of a memory cell block of a memory array.

[0132] Example 28. This example includes the elements of Example 27, and further includes: forming a step mask adjacent to the second tile of the block before forming the hard mask; forming a step structure in the word line of the second tile of the memory cell block; and forming a metal contact structure on the step structure to enable the second tile of the block and the first tile of the block to receive control signals through the metal contact structure and through the word line bridge.

[0133] Example 29. This example includes the elements of Example 26, further comprising forming a plurality of array vias through the second tile and between the upper metal level and the wordline control logic to couple the first tile of the memory cell block to the wordline control logic through a wordline bridge.

[0134] Example 30. According to this example, there is provided a system according to any one of Examples 15 to 25, the system further comprising a processor circuit.

[0135] Example 31. According to this example, there is provided a memory system comprising a plurality of memory arrays, wherein each of the memory arrays comprises the memory array according to any one of Examples 1 to 14.

[0136] Example 32. According to this example, there is provided an apparatus comprising means for performing the method according to any one of Examples 26 to 29.

[0137] Example 33. According to this example, there is provided a computer readable storage device having stored thereon instructions that, when executed by one or more processors, result in operations including the method according to any one of Examples 26 to 29.

[0138] Various features, aspects, and embodiments have been described herein. As will be appreciated by those skilled in the art, the features, aspects, and embodiments are susceptible to combination with one another and to variations and modifications. Therefore, this disclosure should be considered to encompass such combinations, variations, and modifications.

Claims

1. A memory array comprising: a first tile comprising a first block of memory cells, the first block of memory cells comprising a first plurality of memory cells and a first word line access structure for providing access to a first plurality of word lines associated with the first plurality of memory cells; a second tile comprising a second memory cell block including a second plurality of memory cells and a second word line access structure, the second word line access structure comprising a word line ladder structure including a plurality of steps for providing access to a second plurality of word lines associated with the second plurality of memory cells; as well as a wordline bridge for selectively coupling the first plurality of wordlines to the second plurality of wordlines; Among the first word line access structure and the second word line access structure coupled together via the word line bridge, only the second word line access structure includes the word line ladder structure. 2 . The memory array of claim 1 , wherein the word line bridge comprises a plurality of polysilicon layers and a plurality of oxide layers. 3 . The memory array of claim 2 , wherein every two of the plurality of polysilicon layers are separated by one of the plurality of oxide layers. 4 . The memory array of claim 2 , wherein each of the plurality of polysilicon layers is connected to one word line of the first plurality of word lines and one word line of the second plurality of word lines.

5. The memory array of claim 1, wherein the width of the word line bridge is ¼ the height of the word line bridge, wherein the height of the word line bridge is the height of the word line stacks of the first block in the first plurality of memory cells.

6. The memory array of claim 1 , wherein the first tile comprises a first plurality of blocks of first memory cells, wherein the second tile comprises a second plurality of blocks of second memory cells, the memory array further comprising: A plurality of word line bridges are provided for coupling a first plurality of blocks of the first memory cells to a second plurality of blocks of the second memory cells.

7. The memory array of claim 1 , further comprising: a set of array vias in the second memory cell block, the array vias coupling an upper metal level to a word line driver disposed below the memory array, Wherein the first plurality of word lines are electrically coupled to a word line driver through a word line bridge and through the set of array vias.

8. The memory array of claim 1, wherein the word line bridge is defined at least in part by forming a hard mask over the first tile and over the second tile during fabrication of the word line staircase structure. 9 . The memory array of claim 1 , wherein the memory array comprises a plurality of tiles, and each of the plurality of tiles comprises a plurality of memory cell blocks, wherein the first tile and the second tile are two of the plurality of tiles.

10. The memory array of claim 1, wherein a width of the word line bridge is between 1 / 8 and 1 / 4 of a height of the word line bridge.

11. The memory array of claim 1, wherein a width of the word line bridge is between ¼ and ½ of a height of the word line bridge.

12. The memory array of claim 1, wherein the word line bridge comprises at least 32 polysilicon layers.

13. A word line bridge system comprising: Memory controller; as well as A memory array, the memory array comprising: a first tile comprising a first block of memory cells, the first block of memory cells comprising a first plurality of memory cells and a first word line access structure for providing access to a first plurality of word lines associated with the first plurality of memory cells; a second tile comprising a second memory cell block including a second plurality of memory cells and a second word line access structure including a word line ladder structure including a plurality of steps for providing access to a second plurality of word lines associated with the second plurality of memory cells; and a wordline bridge for selectively coupling the first plurality of wordlines to the second plurality of wordlines; Among the first word line access structure and the second word line access structure coupled together via the word line bridge, only the second word line access structure includes the word line ladder structure.

14. The system of claim 13, wherein the word line bridge comprises a plurality of polysilicon layers and a plurality of oxide layers. 15 . The system of claim 14 , wherein the plurality of polysilicon layers are connected to the first plurality of first word lines and to the plurality of second word lines.

16. The system of any one of claims 13 to 15, further comprising a processor circuit.

17. A method for manufacturing a word line bridge, comprising: forming a first tile of memory cell blocks of a memory array, the first tile comprising a first memory cell block, the first memory cell block comprising a first plurality of memory cells and a first word line access structure for providing access to a first plurality of word lines associated with the first plurality of memory cells; forming a second tile of memory cell blocks of the memory array, the second tile comprising a second memory cell block, the second memory cell block comprising a second plurality of memory cells and a second word line access structure, the second word line access structure comprising a word line ladder structure including a plurality of steps for providing access to a second plurality of word lines associated with the second plurality of memory cells; as well as forming a wordline bridge for selectively coupling the first plurality of wordlines to the second plurality of wordlines; Among the first word line access structure and the second word line access structure coupled together via the word line bridge, only the second word line access structure includes the word line ladder structure. 18 . The method of claim 17 , wherein forming a word line bridge comprises forming a hard mask over the first tile, the second tile, and a polysilicon layer between the first memory cell block and the second memory cell block.

19. The method of claim 18, further comprising: forming a step mask of the second tile adjacent to a memory cell block of the memory array before forming the hard mask; forming a staircase structure in the second plurality of word lines of the second memory cell block; as well as A metal contact structure is formed on the staircase structure to enable the second memory cell block and the first memory cell block to receive a control signal through the metal contact structure and the word line bridge.

20. The method of claim 17, further comprising: A plurality of array vias are formed through the second tile and between the upper metal level and the wordline control logic to couple the first plurality of wordlines to the wordline control logic through wordline bridges.

21. A memory system comprising a plurality of memory arrays, wherein each of the memory arrays comprises a memory array according to any one of claims 1 to 12.

22. A word line bridge arrangement comprising means for performing the method according to any one of claims 17 to 20.

23. A computer-readable storage device having stored thereon instructions that, when executed by one or more processors, result in operations comprising: A method according to any one of claims 17 to 20.

24. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method according to any one of claims 17 to 20.

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