A single-phase photovoltaic grid-connected power generation system

Abstract

The present invention provides a single-phase photovoltaic grid-connected power generation system, which relates to the technical field of photovoltaic grid-connected power generation. The system comprises a first photovoltaic module, a first boost circuit, a first DC / DC converter, a first MPPT controller, a first drive circuit, a second photovoltaic module, a second boost circuit, a second DC / DC converter, a second MPPT controller, a second drive circuit, an inverter circuit, and a grid-connected controller. The single-phase photovoltaic grid-connected power generation system of the present invention utilizes the first photovoltaic module, the first boost circuit, a first LLC resonant converter, the second photovoltaic module, the second boost circuit, and the second LLC resonant converter to form a series DC / DC boost circuit, thereby stabilizing the DC bus voltage at 400V, facilitating the same-frequency and same-phase control of the inverter circuit, and thus reducing losses in the grid-connected power generation system and improving grid-connected power generation efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic grid-connected power generation, and in particular to a single-phase photovoltaic grid-connected power generation system. Background Art

[0002] Energy, environment, and development are pressing issues facing the world today. To reduce air pollution, protect the human ecological environment, and ensure a long-term, stable energy supply, it is imperative to implement a sustainable development strategy, gradually transform the existing energy structure, and vigorously develop and utilize new energy sources. Solar energy, as an inexhaustible, renewable energy source, offers advantages such as unlimited reserves, ubiquity, clean development and utilization, and increasingly cost-effectiveness. Its development and utilization can effectively address energy shortages and environmental pollution caused by conventional energy sources, particularly fossil fuels, making it an ideal alternative energy source. The development and utilization of solar energy is bound to see significant growth in the 21st century and will ultimately play a significant role in the global energy transition, becoming one of the dominant energy sources in the latter half of the century.

[0003] Grid-connected power generation systems are the primary form of solar energy utilization. Their characteristic is that they directly convert the direct current (DC) generated by solar arrays into alternating current (AC) through controlled inverters, which are then transmitted to the grid. There are two main types of grid-connected power generation systems. One is a large, centralized, networked photovoltaic power station. These require complex control and transmission and distribution equipment, occupy large tracts of land, and are currently much more expensive than utility power. Consequently, the development of these large-scale photovoltaic power stations has been slow. The other is a decentralized, small-scale, grid-connected photovoltaic power generation system, particularly household photovoltaic grid-connected systems, which have seen rapid growth in recent years. Existing household photovoltaic grid-connected power generation systems consist of photovoltaic modules, boost circuits, inverter circuits, drive circuits, and control circuits. The boost circuit can suffer from duty cycle distortion when the PV module output voltage varies widely. Furthermore, the direct connection of the boost circuit to the inverter circuit results in high losses and low efficiency in the grid-connected power generation system. Summary of the Invention

[0004] (1) Technical problems solved

[0005] In order to overcome the problem that the duty cycle distortion of the above-mentioned Boost circuit occurs when the output voltage of the photovoltaic module varies widely, the Boost circuit is directly connected to the inverter circuit, resulting in large losses and low efficiency in the grid-connected power generation system, the present invention provides a single-phase photovoltaic grid-connected power generation system.

[0006] (2) Technical solution

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0008] A single-phase photovoltaic grid-connected power generation system includes a first photovoltaic module, a first boost circuit, a first DC / DC converter, a first MPPT controller, a first drive circuit, a second photovoltaic module, a second boost circuit, a second DC / DC converter, a second MPPT controller, a second drive circuit, an inverter circuit, and a grid-connected controller;

[0009] The output end of the first photovoltaic assembly is connected to the input end of the first Boost circuit, the output end of the first Boost circuit is connected to the input end of the first DC / DC converter, the output end of the first DC / DC converter is connected to the input end of the inverter circuit, the output end of the second photovoltaic assembly is connected to the input end of the second Boost circuit, the output end of the second Boost circuit is connected to the input end of the second DC / DC converter, and the output end of the second DC / DC converter is connected to the input end of the inverter circuit and the output end of the first DC / DC converter;

[0010] The output end of the inverter circuit is connected to the grid-connected controller, the grid-connected inverter is connected to the first DC / DC converter through a first drive circuit for driving the power tube of the first DC / DC converter, the grid-connected inverter is connected to the second DC / DC converter through a second drive circuit for driving the power tube of the second DC / DC converter, the grid-connected controller and the first photovoltaic assembly are connected to the first Boost circuit through a first MPPT controller for driving the power tube of the first Boost circuit, and the grid-connected controller and the second photovoltaic assembly are connected to the second Boost circuit through a second MPPT controller for driving the power tube of the second Boost circuit;

[0011] The first DC / DC converter and the second DC / DC converter are connected in series, and the first DC / DC converter and the second DC / DC converter are LLC resonant converters.

[0012] According to one embodiment of the present invention, the first Boost circuit includes an inductor L1, a diode D1, a power transistor VT1, and a capacitor C1. An output end of the first photovoltaic module is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the anode of the diode D1 and the collector of the power transistor VT1, the cathode of the diode D1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the emitter of the power transistor VT1 and the other output end of the first photovoltaic module.

[0013] The first DC / DC converter includes power tubes Q1 and Q2, a resonant capacitor Cr1, a resonant inductor Lr1, an excitation inductor Lm1, a transformer T1, rectifier diodes D2 and D3, and a capacitor Co1. The drain of the power tube Q1 is connected to the cathode of the diode D1, the emitter of the power tube Q1 is connected to the drain of the power tube Q2 and one end of the resonant capacitor Cr1, the other end of the resonant capacitor Cr1 is connected to one end of the resonant inductor Lr1, the other end of the resonant inductor Lr1 is connected to one end of the primary winding of the transformer T1, the other end of the primary winding of the transformer T1 is connected to the emitter of the power tube Q2, the excitation inductor Lm1 is connected in parallel to both ends of the primary winding of the transformer T1, the two ends of the secondary winding of the transformer T1 are respectively connected to the anodes of the rectifier diodes D2 and D3, the cathodes of the rectifier diodes D2 and D3 are respectively connected to one end of the capacitor Co1, and the other end of the capacitor Co1 is connected to the middle tap of the secondary winding of the transformer T1;

[0014] The second Boost circuit includes an inductor L2, a diode D4, a power tube VT2, and a capacitor C2. One output end of the second photovoltaic module is connected to one end of the inductor L2, the other end of the inductor L2 is connected to the anode of the diode D4 and the collector of the power tube VT2, the cathode of the diode D4 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the emitter of the power tube VT2 and the other output end of the second photovoltaic module;

[0015] The second DC / DC converter includes power tubes Q3 and Q4, a resonant capacitor Cr2, a resonant inductor Lr2, an excitation inductor Lm2, a transformer T2, rectifier diodes D5 and D6, and a capacitor Co2. The drain of the power tube Q3 is connected to the cathode of the diode D4, the emitter of the power tube Q3 is connected to the drain of the power tube Q4 and one end of the resonant capacitor Cr2, the other end of the resonant capacitor Cr2 is connected to one end of the resonant inductor Lr2, the other end of the resonant inductor Lr2 is connected to one end of the primary winding of the transformer T2, the other end of the primary winding of the transformer T2 is connected to the emitter of the power tube Q4, the excitation inductor Lm2 is connected in parallel to both ends of the primary winding of the transformer T2, both ends of the secondary winding of the transformer T2 are connected to the anodes of the rectifier diodes D5 and D6, respectively, the cathodes of the rectifier diodes D5 and D6 and one end of the capacitor Co1 connected to the middle tap of the secondary winding of the transformer T1 are respectively connected to one end of the capacitor Co2, and the other end of the capacitor Co2 is connected to the middle tap of the secondary winding of the transformer T2 and is grounded;

[0016] The inverter circuit includes a capacitor Cd c , power tubes VT3, VT4, VT5, VT6, inductor L3, isolation transformer T3, relay normally open contact K1, power grid, capacitor Cd c One end is connected to the cathode of rectifier diodes D2 and D3, the collector of power tubes VT3 and VT4, and the capacitor Cd cThe other end is grounded, the emitter of the power tube VT3 is connected to the collector of the power tube VT5 and one end of the inductor L3, the other end of the inductor L3 is connected to one end of the primary winding of the isolation transformer T3, the other end of the primary winding of the isolation transformer T3 is connected to the emitter of the power tube VT4 and the collector of the power tube VT6, the emitters of the power tubes VT5 and VT6 are grounded, one end of the secondary winding of the isolation transformer T3 is connected to one end of the normally open contact K1 of the relay, the other end of the normally open contact K1 of the relay is connected to one end of the power grid, and the other end of the power grid is connected to the other end of the secondary winding of the isolation transformer T3.

[0017] According to an embodiment of the present invention, the inductor L1 and the resonant inductor Lr1 are coupled inductors, and the inductor L2 and the resonant inductor Lr2 are coupled inductors.

[0018] According to an embodiment of the present invention, the first driving circuit adopts a control mode combining PWM and PFM, and the second driving circuit adopts a control mode combining PWM and PFM.

[0019] According to one embodiment of the present invention, the first driving circuit includes a first voltage sampling circuit, a first current sampling circuit, a first comparison circuit, a second comparison circuit, a third comparison circuit, a first oscillator, a first clock pulse generating circuit, and a first logic gate circuit; the output of the first voltage sampling circuit is connected to the input of the first comparison circuit, the output of the first current sampling circuit is connected to the input of the second comparison circuit, the output of the first comparison circuit is connected to the input of the third comparison circuit and the second comparison circuit respectively, the output of the second comparison circuit is connected to the input of the first clock pulse generating circuit, the output of the first clock pulse generating circuit is connected to the first logic gate circuit, the output of the third comparison circuit is connected to the first logic gate circuit through the first oscillator, and the first logic gate circuit is used to drive power tubes Q1 and Q2.

[0020] According to one embodiment of the present invention, the first driving circuit includes resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, and R11, capacitors C3, C4, C5, and C6, diodes D7 and D8, operational amplifiers U1, U2, and U3, a clock pulse generating chip U4, and a transistor VT7;

[0021] The clock pulse generating chip U4 includes an error amplifier non-inverting input terminal EAP, an error amplifier inverting input terminal EAN, an error amplifier output terminal EAOUT, a PWM comparator non-inverting input terminal EAMP, an oscillator timing capacitor access terminal CT, an oscillator timing resistor access terminal RT, and pulse output terminals OUTA and OUTB. The error amplifier inverting input terminal EAN is connected to the error amplifier output terminal EAOUT, the PWM comparator non-inverting input terminal EAMP is connected to the oscillator timing capacitor access terminal CT and is grounded through a capacitor C6, and the pulse output terminals OUTA and OUTB are connected to the gates of the power tubes Q1 and Q2 through resistors R10 and R11, respectively.

[0022] One end of the resistors R1 and R2 is respectively connected to the output voltage Va1 of the first voltage sampling circuit, the other end of the resistor R1 is connected to the inverting input terminal of the operational amplifier U1, the non-inverting input terminal of the operational amplifier U1 is connected to the reference voltage Vref1, the other end of the resistor R2 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the output terminal of the operational amplifier U1, the output terminal of the operational amplifier U1 is connected to the anode of the diode D7, the cathode of the diode D7 is respectively connected to one end of the resistors R3 and R7, the other end of the resistor R3 is connected to one end of the resistor R4 and the inverting input terminal of the operational amplifier U2, the non-inverting input terminal of the operational amplifier U2 is connected to the reference voltage Vref2, the other end of the resistor R4 is connected to the output terminal of the operational amplifier U2, the output terminal of the operational amplifier U2 is connected to the base of the transistor VT7, the collector of the transistor VT7 is connected to the access terminal RT of the oscillator timing resistor, the emitter of the transistor VT7 is grounded through the resistor R6, and the resistor R5 is connected in series with the capacitor C4 and then connected in parallel to the collector and emitter of the transistor VT7;

[0023] The other end of the resistor R7 is respectively connected to the non-inverting input terminal EAP of the error amplifier and the anode of the diode D8. The cathode of the diode D8 is connected to the output terminal of the operational amplifier U3. The inverting input terminal of the operational amplifier U3 is connected to one end of the resistor R8. The other end of the resistor R8 is connected to one end of the resistor R9 and the output current Ia1 of the first current sampling circuit. The non-inverting input terminal of the operational amplifier U3 is connected to the short-circuit protection current upper limit Im. The other end of the resistor R9 is connected to one end of the capacitor C5. The other end of the capacitor C5 is connected to the output terminal of the operational amplifier U3.

[0024] According to one embodiment of the present invention, the second driving circuit includes a second voltage sampling circuit, a second current sampling circuit, a fourth comparison circuit, a fifth comparison circuit, a sixth comparison circuit, a second oscillator, a second clock pulse generating circuit, and a second logic gate circuit; the output of the second voltage sampling circuit is connected to the input of the fourth comparison circuit, the output of the second current sampling circuit is connected to the input of the fifth comparison circuit, the output of the fourth comparison circuit is connected to the input of the sixth comparison circuit and the fifth comparison circuit respectively, the output of the fifth comparison circuit is connected to the input of the second clock pulse generating circuit, the output of the second clock pulse generating circuit is connected to the second logic gate circuit, the output of the sixth comparison circuit is connected to the second logic gate circuit through the second oscillator, and the second logic gate circuit is used to drive power tubes Q3 and Q4.

[0025] According to one embodiment of the present invention, the second driving circuit includes resistors R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, and R22, capacitors C7, C8, C9, and C10, diodes D9 and D10, operational amplifiers U5, U6, and U7, a clock pulse generating chip U8, and a transistor VT8;

[0026] The clock pulse generating chip U8 includes an error amplifier non-inverting input terminal EAP, an error amplifier inverting input terminal EAN, an error amplifier output terminal EAOUT, a PWM comparator non-inverting input terminal EAMP, an oscillator timing capacitor access terminal CT, an oscillator timing resistor access terminal RT, and pulse output terminals OUTC and OUTD. The error amplifier inverting input terminal EAN is connected to the error amplifier output terminal EAOUT, the PWM comparator non-inverting input terminal EAMP is connected to the oscillator timing capacitor access terminal CT and is grounded through a capacitor C10, and the pulse output terminals OUTC and OUTD are connected to the gates of the power tubes Q3 and Q4 through resistors R21 and R22, respectively.

[0027] One end of the resistors R12 and R13 is respectively connected to the output voltage Va2 of the second voltage sampling circuit, the other end of the resistor R12 is connected to the inverting input terminal of the operational amplifier U5, the non-inverting input terminal of the operational amplifier U5 is connected to the reference voltage Vref3, the other end of the resistor R13 is connected to one end of the capacitor C7, the other end of the capacitor C7 is connected to the output terminal of the operational amplifier U5, the output terminal of the operational amplifier U5 is connected to the anode of the diode D9, the cathode of the diode D9 is respectively connected to one end of the resistors R14 and R18, the other end of the resistor R14 is connected to one end of the resistor R15 and the inverting input terminal of the operational amplifier U6, the non-inverting input terminal of the operational amplifier U6 is connected to the reference voltage Vref4, the other end of the resistor R15 is connected to the output terminal of the operational amplifier U6, the output terminal of the operational amplifier U6 is connected to the base of the transistor VT8, the collector of the transistor VT8 is connected to the access terminal RT of the oscillator timing resistor, the emitter of the transistor VT8 is grounded through the resistor R17, and the resistor R16 is connected in series with the capacitor C8 and then connected in parallel to the collector and emitter of the transistor VT8;

[0028] The other end of the resistor R18 is respectively connected to the non-inverting input terminal EAP of the error amplifier and the anode of the diode D10. The cathode of the diode D10 is connected to the output terminal of the operational amplifier U7. The inverting input terminal of the operational amplifier U7 is connected to one end of the resistor R19. The other end of the resistor R19 is connected to one end of the resistor R20 and the output current Ia2 of the second current sampling circuit. The non-inverting input terminal of the operational amplifier U7 is connected to the short-circuit protection current upper limit Im. The other end of the resistor R20 is connected to one end of the capacitor C9. The other end of the capacitor C9 is connected to the output terminal of the operational amplifier U7.

[0029] According to an embodiment of the present invention, the grid-connected controller adopts a TMS320F28335 digital signal processor.

[0030] (3) Beneficial effects

[0031] The beneficial effects of the present invention are as follows: a single-phase photovoltaic grid-connected power generation system, which adopts a first photovoltaic module, a first Boost circuit, a first LLC resonant converter, a second photovoltaic module, a second Boost circuit, and a second LLC resonant converter to form a series DC / DC boost circuit, so that the DC bus voltage is stabilized at 400V, which is convenient for the same-frequency and same-phase control of the inverter circuit, can reduce the loss of the grid-connected power generation system and improve the grid-connected power generation efficiency; the LLC resonant converter adopts a PWM and PFM hybrid control working mode, PFM control is performed under heavy load and normal operation, and PWM control is performed under light load and no-load, and the two control modes can be freely switched; a Boost circuit is set in the front stage to facilitate The maximum power point tracking control of photovoltaic modules, the MPPT controller adopts a control algorithm that combines the interference observation method with fuzzy control. Under the premise of smoothly tracking the maximum power point, this algorithm reduces the power loss caused by the oscillation of the photovoltaic array at the maximum power point, effectively improving the speed and accuracy of photovoltaic array tracking; the grid-connected controller adopts the TMS320F28335 digital signal processor and adopts dual-loop control, with the inner loop being the current loop and the outer loop being the power loop. The error between the given current and the inductor current is adjusted through PI, and the closed-loop control makes the inductor current of the inverter circuit track the sinusoidal current instruction to realize current tracking control, so that the output inductor current of the inverter circuit is in the same frequency and phase as the grid voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 This is a principle block diagram of the present invention;

[0034] Figure 2 This is the main circuit schematic diagram of the grid-connected power generation system;

[0035] Figure 3 is a block diagram of a first driving circuit;

[0036] Figure 4 is a block diagram of the second driving circuit;

[0037] Figure 5 is a schematic diagram of the first driving circuit;

[0038] Figure 6 is a schematic diagram of the second driving circuit;

[0039] Figure 7 This is a schematic diagram of the mode control switching transition;

[0040] Figure 8 is the membership function of dP;

[0041] Figure 9 is the membership function of dS;

[0042] Figure 10 This is the simulation curve of the MPPT control algorithm of the present invention;

[0043] Figure 11 This is the inverter circuit control block diagram.

[0044] Description of reference numerals:

[0045] 10. First photovoltaic module; 11. First boost circuit; 12. First DC / DC converter; 13. Inverter circuit; 20. Second photovoltaic module; 21. Second boost circuit; 22. Second DC / DC converter.

[0046] Resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, Cr1, Cr2, Co1, Co2, Cdc, diodes D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, inductors L1, L2, L3, Lr1, Lr2, Lm1, Lm2, power tubes VT1, VT2, VT3, VT4, VT5, VT6, Q1, Q2, Q3, Q4, transistors VT7, VT8, transformers T1, T2, T3, operational amplifiers U1, U2, U3, U5, U6, U7, clock pulse generating chips U4, U8, relay normally open contact K1. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0048] Combine Figure 1A single-phase photovoltaic grid-connected power generation system includes a first photovoltaic component, a first Boost circuit, a first DC / DC converter, a first MPPT controller, a first drive circuit, a second photovoltaic component, a second Boost circuit, a second DC / DC converter, a second MPPT controller, a second drive circuit, an inverter circuit, and a grid-connected controller; the output end of the first photovoltaic component is connected to the input end of the first Boost circuit, the output end of the first Boost circuit is connected to the input end of the first DC / DC converter, the output end of the first DC / DC converter is connected to the input end of the inverter circuit, the output end of the second photovoltaic component is connected to the input end of the second Boost circuit, the output end of the second Boost circuit is connected to the input end of the second DC / DC converter, the output end of the second DC / DC converter is connected to the input end of the inverter circuit, the first DC / The output end of the DC converter is connected; the output end of the inverter circuit is connected to the grid-connected controller, the grid-connected inverter is connected to the first DC / DC converter through a first drive circuit for driving the power tube of the first DC / DC converter, the grid-connected inverter is connected to the second DC / DC converter through a second drive circuit for driving the power tube of the second DC / DC converter, the grid-connected controller and the first photovoltaic component are connected to the first Boost circuit through a first MPPT controller for driving the power tube of the first Boost circuit, the grid-connected controller and the second photovoltaic component are connected to the second Boost circuit through a second MPPT controller for driving the power tube of the second Boost circuit; the first DC / DC converter and the second DC / DC converter are connected in series, and the first DC / DC converter and the second DC / DC converter are LLC resonant converters.

[0049] The first and second DC / DC converters are LLC resonant converters. The first and second Boost circuits use BOOST boost circuits. The inverter circuit uses a full-bridge inverter.

[0050] Combine Figure 2 The main circuit of the single-phase photovoltaic grid-connected power generation system includes a first photovoltaic module 10, a first Boost circuit 11, a first DC / DC converter 12, a second photovoltaic module 20, a second Boost circuit 21, a second DC / DC converter 22, and an inverter circuit 13.

[0051] The first Boost circuit 11 includes an inductor L1, a diode D1, a power tube VT1, and a capacitor C1. One output end of the first photovoltaic module is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the anode of the diode D1 and the collector of the power tube VT1, the cathode of the diode D1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the emitter of the power tube VT1 and the other output end of the first photovoltaic module.

[0052] The first DC / DC converter 12 includes power tubes Q1 and Q2, a resonant capacitor Cr1, a resonant inductor Lr1, a magnetizing inductor Lm1, a transformer T1, rectifier diodes D2 and D3, and a capacitor Co1. The drain of the power tube Q1 is connected to the cathode of the diode D1, the emitter of the power tube Q1 is connected to the drain of the power tube Q2 and one end of the resonant capacitor Cr1, the other end of the resonant capacitor Cr1 is connected to one end of the resonant inductor Lr1, the other end of the resonant inductor Lr1 is connected to one end of the primary winding of the transformer T1, the other end of the primary winding of the transformer T1 is connected to the emitter of the power tube Q2, the magnetizing inductor Lm1 is connected in parallel across the primary winding of the transformer T1, the two ends of the secondary winding of the transformer T1 are connected to the anodes of the rectifier diodes D2 and D3, respectively, the cathodes of the rectifier diodes D2 and D3 are connected to one end of the capacitor Co1, and the other end of the capacitor Co1 is connected to the middle tap of the secondary winding of the transformer T1.

[0053] The second boost circuit 21 includes an inductor L2, a diode D4, a power transistor VT2, and a capacitor C2. One output terminal of the second photovoltaic module is connected to one end of the inductor L2. The other end of the inductor L2 is connected to the anode of the diode D4 and the collector of the power transistor VT2. The cathode of the diode D4 is connected to one end of the capacitor C2. The other end of the capacitor C2 is connected to the emitter of the power transistor VT2 and the other output terminal of the second photovoltaic module.

[0054] The second DC / DC converter 22 includes power tubes Q3 and Q4, a resonant capacitor Cr2, a resonant inductor Lr2, a magnetizing inductor Lm2, a transformer T2, rectifier diodes D5 and D6, and a capacitor Co2. The drain of the power tube Q3 is connected to the cathode of the diode D4, the emitter of the power tube Q3 is connected to the drain of the power tube Q4 and one end of the resonant capacitor Cr2, the other end of the resonant capacitor Cr2 is connected to one end of the resonant inductor Lr2, the other end of the resonant inductor Lr2 is connected to one end of the primary winding of the transformer T2, the other end of the primary winding of the transformer T2 is connected to the emitter of the power tube Q4, the magnetizing inductor Lm2 is connected in parallel across the primary winding of the transformer T2, the two ends of the secondary winding of the transformer T2 are connected to the anodes of the rectifier diodes D5 and D6, respectively, the cathodes of the rectifier diodes D5 and D6, and one end of the capacitor Co1 connected to the middle tap of the secondary winding of the transformer T1 are respectively connected to one end of the capacitor Co2, and the other end of the capacitor Co2 is connected to the middle tap of the secondary winding of the transformer T2 and is grounded.

[0055] The inverter circuit 13 includes a capacitor Cdc, power tubes VT3, VT4, VT5, VT6, an inductor L3, an isolation transformer T3, a normally open contact K1 of a relay, and a power grid. One end of the capacitor Cdc is connected to the cathodes of the rectifier diodes D2 and D3 and the collectors of the power tubes VT3 and VT4. The other end of the capacitor Cdc is grounded. The emitter of the power tube VT3 is connected to the collector of the power tube VT5 and one end of the inductor L3. The other end of the inductor L3 is connected to one end of the primary winding of the isolation transformer T3. The other end of the primary winding of the isolation transformer T3 is connected to the emitter of the power tube VT4 and the collector of the power tube VT6. The emitters of the power tubes VT5 and VT6 are grounded. One end of the secondary winding of the isolation transformer T3 is connected to one end of the normally open contact K1 of the relay. The other end of the normally open contact K1 of the relay is connected to one end of the power grid. The other end of the power grid is connected to the other end of the secondary winding of the isolation transformer T3.

[0056] In order to save circuit space, the inductor L1 and the resonant inductor Lr1 are designed as coupled inductors, and the inductor L2 and the resonant inductor Lr2 are designed as coupled inductors.

[0057] The first driving circuit adopts a control mode combining PWM and PFM, and the second driving circuit adopts a control mode combining PWM and PFM.

[0058] Combine Figure 3 The first driving circuit includes a first voltage sampling circuit, a first current sampling circuit, a first comparison circuit, a second comparison circuit, a third comparison circuit, a first oscillator, a first clock pulse generating circuit, and a first logic gate circuit; the output of the first voltage sampling circuit is connected to the input of the first comparison circuit, the output of the first current sampling circuit is connected to the input of the second comparison circuit, the output of the first comparison circuit is respectively connected to the input of the third comparison circuit and the second comparison circuit, the output of the second comparison circuit is connected to the input of the first clock pulse generating circuit, the output of the first clock pulse generating circuit is connected to the first logic gate circuit, the output of the third comparison circuit is connected to the first logic gate circuit through the first oscillator, and the first logic gate circuit is used to drive power tubes Q1 and Q2.

[0059] Combine Figure 4The second driving circuit includes a second voltage sampling circuit, a second current sampling circuit, a fourth comparison circuit, a fifth comparison circuit, a sixth comparison circuit, a second oscillator, a second clock pulse generating circuit, and a second logic gate circuit; the output of the second voltage sampling circuit is connected to the input of the fourth comparison circuit, the output of the second current sampling circuit is connected to the input of the fifth comparison circuit, the output of the fourth comparison circuit is connected to the input of the sixth comparison circuit and the fifth comparison circuit respectively, the output of the fifth comparison circuit is connected to the input of the second clock pulse generating circuit, the output of the second clock pulse generating circuit is connected to the second logic gate circuit, the output of the sixth comparison circuit is connected to the second logic gate circuit through the second oscillator, and the second logic gate circuit is used to drive power tubes Q3 and Q4.

[0060] Combine Figure 5 The first driving circuit includes resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, capacitors C3, C4, C5, C6, diodes D7, D8, operational amplifiers U1, U2, U3, clock pulse generating chip U4, and transistor VT7.

[0061] Clock pulse generation chip U4 includes an error amplifier non-inverting input terminal EAP, an error amplifier inverting input terminal EAN, an error amplifier output terminal EAOUT, a PWM comparator non-inverting input terminal EAMP, an oscillator timing capacitor access terminal CT, an oscillator timing resistor access terminal RT, and pulse output terminals OUTA and OUTB. The error amplifier inverting input terminal EAN is connected to the error amplifier output terminal EAOUT, and the PWM comparator non-inverting input terminal EAMP is connected to the oscillator timing capacitor access terminal CT and grounded via capacitor C6. Pulse generation chip U4 can be a phase shift control chip UCC3895. Pulse output terminals OUTA and OUTB are connected to the gates of power transistors Q1 and Q2 respectively through resistors R10 and R11.

[0062] One end of the resistors R1 and R2 is respectively connected to the output voltage Va1 of the first voltage sampling circuit, the other end of the resistor R1 is connected to the inverting input terminal of the operational amplifier U1, the non-inverting input terminal of the operational amplifier U1 is connected to the reference voltage Vref1, the other end of the resistor R2 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the output terminal of the operational amplifier U1, the output terminal of the operational amplifier U1 is connected to the anode of the diode D7, the cathode of the diode D7 is respectively connected to one end of the resistors R3 and R7, the other end of the resistor R3 is connected to one end of the resistor R4 and the inverting input terminal of the operational amplifier U2, the non-inverting input terminal of the operational amplifier U2 is connected to the reference voltage Vref2, the other end of the resistor R4 is connected to the output terminal of the operational amplifier U2, the output terminal of the operational amplifier U2 is connected to the base of the transistor VT7, the collector of the transistor VT7 is connected to the access terminal RT of the oscillator timing resistor, the emitter of the transistor VT7 is grounded through the resistor R6, and the resistor R5 and the capacitor C4 are connected in series and then connected in parallel to the collector and emitter of the transistor VT7;

[0063] The other end of the resistor R7 is respectively connected to the non-inverting input terminal EAP of the error amplifier and the anode of the diode D8. The cathode of the diode D8 is connected to the output terminal of the operational amplifier U3. The inverting input terminal of the operational amplifier U3 is connected to one end of the resistor R8. The other end of the resistor R8 is connected to one end of the resistor R9 and the output current Ia1 of the first current sampling circuit. The non-inverting input terminal of the operational amplifier U3 is connected to the short-circuit protection current upper limit Im. The other end of the resistor R9 is connected to one end of the capacitor C5. The other end of the capacitor C5 is connected to the output terminal of the operational amplifier U3.

[0064] Combine Figure 6 The second driving circuit includes resistors R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, capacitors C7, C8, C9, C10, diodes D9, D10, operational amplifiers U5, U6, U7, clock pulse generating chip U8, and transistor VT8.

[0065] Clock pulse generation chip U8 includes an error amplifier non-inverting input terminal EAP, an error amplifier inverting input terminal EAN, an error amplifier output terminal EAOUT, a PWM comparator non-inverting input terminal EAMP, an oscillator timing capacitor access terminal CT, an oscillator timing resistor access terminal RT, and pulse output terminals OUTC and OUTD. The error amplifier inverting input terminal EAN is connected to the error amplifier output terminal EAOUT, and the PWM comparator non-inverting input terminal EAMP is connected to the oscillator timing capacitor access terminal CT and grounded via capacitor C10. Pulse generation chip U8 can be a phase shift control chip UCC3895. Pulse output terminals OUTC and OUTD are connected to the gates of power transistors Q3 and Q4 respectively via resistors R21 and R22.

[0066] One end of the resistors R12 and R13 is respectively connected to the output voltage Va2 of the second voltage sampling circuit, the other end of the resistor R12 is connected to the inverting input terminal of the operational amplifier U5, the non-inverting input terminal of the operational amplifier U5 is connected to the reference voltage Vref3, the other end of the resistor R13 is connected to one end of the capacitor C7, the other end of the capacitor C7 is connected to the output terminal of the operational amplifier U5, the output terminal of the operational amplifier U5 is connected to the anode of the diode D9, the cathode of the diode D9 is respectively connected to one end of the resistors R14 and R18, the other end of the resistor R14 is connected to one end of the resistor R15 and the inverting input terminal of the operational amplifier U6, the non-inverting input terminal of the operational amplifier U6 is connected to the reference voltage Vref4, the other end of the resistor R15 is connected to the output terminal of the operational amplifier U6, the output terminal of the operational amplifier U6 is connected to the base of the transistor VT8, the collector of the transistor VT8 is connected to the access terminal RT of the oscillator timing resistor, the emitter of the transistor VT8 is grounded through the resistor R17, and the resistor R16 is connected in series with the capacitor C8 and then connected in parallel to the collector and emitter of the transistor VT8;

[0067] The other end of the resistor R18 is respectively connected to the non-inverting input terminal EAP of the error amplifier and the anode of the diode D10. The cathode of the diode D10 is connected to the output terminal of the operational amplifier U7. The inverting input terminal of the operational amplifier U7 is connected to one end of the resistor R19. The other end of the resistor R19 is connected to one end of the resistor R20 and the output current Ia2 of the second current sampling circuit. The non-inverting input terminal of the operational amplifier U7 is connected to the short-circuit protection current upper limit Im. The other end of the resistor R20 is connected to one end of the capacitor C9. The other end of the capacitor C9 is connected to the output terminal of the operational amplifier U7.

[0068] PFM and PWM hybrid control is achieved through a fixed-frequency and variable-frequency hybrid control circuit consisting of a subtractor composed of an operational amplifier, a transistor, and the UCC3895. The voltage signal Va is compared with the voltage reference Vref1. The error is passed through a voltage regulator to generate a control level Vb. One path of this control level Vb is connected to the non-inverting input of the UCC3895's error amplifier, the EAP pin. This control level intersects with the sawtooth waveform within the UCC3895 chip to generate the PWM drive signal. Another path passes through a subtractor to generate a voltage signal Vc, which is then connected to the UCC3895's RT pin through a transistor. The voltage-controlled oscillator (VCO) in PFM control, composed of the transistor, subtractor, and UCC3895, controls the switching frequency. The two control modes in PWM and PFM hybrid control are independent and can be switched freely. The internal sawtooth wave of UCC3895 is 3.15V. When the control level Vb is higher than 3.15V, the transistor is turned on, the converter operates at full duty cycle, and enters the variable frequency control mode. When the control level Vb is lower than 3.15V, the transistor is cut off and the converter enters the PWM control mode.

[0069] In specific operation, when the sawtooth wave voltage value inside the UCC3895 rises to equal the control level Vb, the variable frequency clock pulse generator generates a narrow pulse. At the same time, the sawtooth wave generator voltage signal will rise from zero and be compared with the control level Vb, and the control signal will be output. This is repeated to form a clock pulse signal sequence. Figure 7 The waveform diagram for the transition between PWM and PFM control is shown below. PWM control is used before t, and PFM control is used after t. The LLC resonant converter uses a hybrid PWM and PFM control mode. PFM control is used during heavy load and normal operation, and PWM control is used during light load and no-load operation. The two control modes can be switched freely.

[0070] To implement overcurrent protection for the LLC resonant converter, the sampling current Ia1 of the first current sampling circuit is connected to resistor R8, and the sampling current Ia2 of the second current sampling circuit is connected to resistor R19. When no overcurrent occurs, after comparing with the short-circuit protection current upper limit Im, operational amplifiers U3 and U7 output a high level. Since diodes D8 and D10 conduct unidirectionally, the sampling current has no effect on the UCC3895. When an overcurrent occurs, operational amplifier U3 or U7 outputs a low level, diodes D8 or D10 conduct, and the voltage at the non-inverting input terminal EAP of the UCC3895 error amplifier decreases. The UCC3895 operates in PWM mode, outputting a PWM signal with a minimum duty cycle, thus implementing overcurrent protection for the LLC resonant converter.

[0071] Photovoltaic arrays have corresponding operating curves under changes in temperature and light intensity. Through a self-optimization process, they achieve maximum power output. Maximum power point tracking (MPPT) control methods include the fixed voltage method, the straight line approximation method, the interference observation method, and the conductance increment method. The fixed voltage method achieves maximum power tracking by setting the maximum power point voltage to 0.71-0.78 of the open-circuit voltage when the environment changes. This method is simple to control and easy to implement, but has poor environmental adaptability and cannot complete maximum power tracking when the ambient temperature and light intensity change drastically. The straight line approximation method, based on the maximum power point of the photovoltaic array under different light intensities being approximately on a straight line, uses the power and voltage changes equal to 0 to determine, and controls the photovoltaic array operating point to change along the approximate straight line to achieve maximum power tracking. This method has simple tracking control, but the tracking accuracy is not high. The conductance increment method utilizes the fact that the slope of the PV array's PU curve at its maximum power point is zero, and the derivative of power with respect to voltage is zero, i.e., ΔI / ΔV = -I / V. This method uses the calculated admittance I / V and the admittance increment ΔI / ΔV to achieve maximum power tracking of the PV array. This method maintains a stable output voltage at the PV array terminal when light intensity changes suddenly, but it places high demands on the sensor and system response speed. Existing solar photovoltaic maximum power tracking generally uses the disturbance observation method. This method periodically perturbs the PV array output voltage, observes the output power changes before and after the perturbation, and uses the output power change to determine the direction of the voltage perturbation. This method is simple in structure and easy to control, but it can cause oscillation near maximum power, resulting in significant power loss. To reduce power losses caused by oscillations near the maximum power point (MPT) using the interference observation method, the first and second MPPT controllers incorporate fuzzy control based on the interference observation method. A MPPT control algorithm combining a fixed-step interference observation method with variable-step fuzzy control is designed. The interference observation algorithm is first used to set a large step size to quickly approach the maximum power point. Fuzzy control is then used to further approach the maximum power point and achieve stability, meeting the fast and high-precision tracking requirements of the photovoltaic system. This effectively reduces power losses caused by oscillations of photovoltaic cells at the maximum power point.

[0072] The fuzzy control algorithm transforms the output signal error of the photovoltaic array into a fuzzy quantity through fuzzification. This fuzzy quantity is then input into the fuzzy inference module to generate a fuzzy set. The defuzzification module then converts this into a clear digital quantity to control the controlled object. The PV characteristic curve of the photovoltaic array shows that at the maximum power point (MPP), dP / dV = 0. dP / dV is the slope of the PV curve. The absolute value of the PV curve slope determines the distance of the operating point from the MPP. The two inputs of the fuzzy control are the error change e and the power change dP, where e = dP / dV and dP = P(k) - P(k-1). The perturbation step change dS serves as the output of the fuzzy controller. If the perturbation step dS is too small, the power tracking time will be too long. If it is too large, the power loss will increase. By selecting an appropriate perturbation step dS, the circuit duty cycle can be adjusted to keep the photovoltaic array operating at its MPP.

[0073] Combined with the changes in power and disturbance step length, the domain of input and output variables is defined as -6 to +6. A fuzzy controller is established in MATLAB, and the fuzzy rule table 1 is given. dP / dV, dP and dS are defined as 7 identical fuzzy subsets {NB, NM, NS, Z, PS, PM, PB}, which represent negative large, negative medium, negative small, zero, positive small, positive medium, and positive large, respectively. A suitable membership function is selected for each fuzzy subset, and the domain of fuzzy input and output is {-6, -5, -4, -3, -2, -1, 0, +1, +2, +3, +4, +5, +6}. dS = (-0.05, 0.05), dP = (-30, 30), which is the range of variation of the actual measured values. Then, they are divided into their respective fuzzy domains through quantization factors. In view of the inherent characteristics of photovoltaic cells, the membership function is represented by a triangle shape. The membership function is as follows: Figure 8 、 Figure 9 As shown, Figure 8 is the membership function of dP, Figure 9 is the membership function of dS. Figure 10 This is the simulation curve of the MPPT control algorithm of the present invention. The improved algorithm not only reduces the power oscillation near the maximum power point, but also can achieve stable, fast and accurate tracking of the maximum power.

[0074] Table 1: Fuzzy rules

[0075]

[0076] The grid-connected controller uses the TMS320F28335 digital signal processor. The TMS320F28335 is a floating-point DSP controller from the TMS320C28X series. Compared to fixed-point DSPs, it offers advantages such as higher precision, lower cost, lower power consumption, higher performance, higher peripheral integration, larger data and program storage, and more accurate and faster A / D conversion. The TMS320F28335 boasts a 150MHz high-speed processing capability, a 32-bit floating-point processing unit, six DMA channels supporting ADCs, McBSP, and EMIF, and up to 18 PWM outputs, six of which are TI's unique, higher-precision PWM outputs (HRPWM). It also features a 12-bit, 16-channel ADC.

[0077] The photovoltaic grid-connected power generation system of the present invention adopts dual-loop control, the inner loop is the current loop, and the outer loop is the power loop. The inverter circuit outputs AC current synchronous with the grid voltage by detecting the grid voltage zero point. The specific work is to generate a synchronous square wave signal after filtering and conditioning the sampling signal of the grid voltage. The rising edge of the synchronous square wave signal corresponds to the moment when the grid voltage crosses zero point. The synchronous square wave signal is input into the external CAP capture port of the DSP to capture the zero point of the grid voltage. When the DSP detects the rising edge signal of the zero point, a synchronous interrupt is generated, and the sine pointer is reset to zero in the synchronous interrupt. The sine pointer is consistent with the reference current instruction I out Multiplication generates a sinusoidal given current command Whenever the timer T1 underflows, the sine pointer increases by 1, and the synchronization signal synchronizes the sine table pointer with the grid voltage, thereby achieving synchronization of the grid-connected current and the grid voltage. Figure 11 As shown, the given current The error with the inductor current is adjusted by PI, and the inductor current of the inverter circuit is controlled by closed loop to track the sinusoidal current instruction to realize current tracking control, so that the output inductor current of the inverter circuit is in the same frequency and phase with the grid voltage.

[0078] Two sets of photovoltaic panels are controlled and boosted using a boost circuit with maximum power point tracking. The boost circuit's output voltage serves as the input voltage for two LLC resonant converters, which, through series boost control, achieve a stable 400V DC output. Digital control technology is implemented using the TMS320F28335. The grid-connected current is required to track both the reference current and the mains phase. Grid-connected current control multiplies the grid-connected current amplitude reference by the grid voltage phase reference signal, obtained through phase-locked control. This is then used as the grid-connected current reference. Current loop control is then used to ensure that the grid-connected current tracks the reference current. Finally, SPWM is generated to drive the inverter circuit's power transistors, ensuring that the grid-connected current and grid voltage are in phase and frequency.

[0079] In summary, in an embodiment of the present invention, a single-phase photovoltaic grid-connected power generation system employs a first photovoltaic module, a first boost circuit, a first LLC resonant converter, a second photovoltaic module, a second boost circuit, and a second LLC resonant converter to form a series DC / DC boost circuit. The DC bus voltage is stabilized at 400V, facilitating the same-frequency and same-phase control of the inverter circuit, thereby reducing losses in the grid-connected power generation system and improving grid-connected power generation efficiency. The LLC resonant converter employs a hybrid PWM and PFM control operating mode, employing PFM control under heavy load and normal operation, and PWM control under light load and no-load conditions. The two control modes can be freely switched. The MPPT controller adopts a control algorithm that combines the interference observation method with fuzzy control. Under the premise of smoothly tracking the maximum power point, this algorithm reduces the power loss caused by the oscillation of the photovoltaic array at the maximum power point, effectively improving the speed and accuracy of photovoltaic array tracking; the grid-connected controller adopts the TMS320F28335 digital signal processor and adopts dual-loop control, with the inner loop being the current loop and the outer loop being the power loop. The error between the given current and the inductor current is adjusted through PI, and the closed-loop control makes the inductor current of the inverter circuit track the sinusoidal current instruction to realize current tracking control, so that the output inductor current of the inverter circuit is in the same frequency and phase as the grid voltage.

[0080] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A single-phase photovoltaic grid-connected power generation system, characterized by: It includes a first photovoltaic component, a first Boost circuit, a first DC / DC converter, a first MPPT controller, a first drive circuit, a second photovoltaic component, a second Boost circuit, a second DC / DC converter, a second MPPT controller, a second drive circuit, an inverter circuit, and a grid-connected controller; The output end of the first photovoltaic assembly is connected to the input end of the first Boost circuit, the output end of the first Boost circuit is connected to the input end of the first DC / DC converter, the output end of the first DC / DC converter is connected to the input end of the inverter circuit, the output end of the second photovoltaic assembly is connected to the input end of the second Boost circuit, the output end of the second Boost circuit is connected to the input end of the second DC / DC converter, and the output end of the second DC / DC converter is connected to the input end of the inverter circuit and the output end of the first DC / DC converter; The output end of the inverter circuit is connected to the grid controller, which is connected to the first DC / DC converter through a first drive circuit to drive the power tube of the first DC / DC converter. The grid controller is connected to the second DC / DC converter through a second drive circuit to drive the power tube of the second DC / DC converter. The grid controller and the first photovoltaic assembly are connected to the first Boost circuit through a first MPPT controller to drive the power tube of the first Boost circuit. The grid controller and the second photovoltaic assembly are connected to the second Boost circuit through a second MPPT controller to drive the power tube of the second Boost circuit. The first DC / DC converter and the second DC / DC converter are connected in series, and the first DC / DC converter and the second DC / DC converter are LLC resonant converters; The LLC resonant converter adopts a mixed control mode of PWM and PFM. PFM control is performed under heavy load and normal operation, and PWM control is performed under light load and no-load. The two control modes can be switched freely. The first MPPT controller and the second MPPT controller introduce fuzzy control on the basis of the interference observation method, and adopt an MPPT control algorithm that combines the fixed-step interference observation method with the variable-step fuzzy control. A larger step size is set by the interference observation algorithm to quickly approach the maximum power point, and fuzzy control is used to further approach the maximum power point and achieve stability, thereby reducing the power loss caused by the oscillation of the photovoltaic cell at the maximum power point. The fuzzy control algorithm converts the output signal error of the photovoltaic array into a fuzzy quantity through fuzzification processing, inputs the fuzzy set into the fuzzy reasoning module, and converts it into a clear digital quantity using the anti-fuzzy module to control the controlled object. The single-phase photovoltaic grid-connected power generation system generates a synchronous square wave signal after filtering and conditioning the sampling signal of the grid voltage. The rising edge of the synchronous square wave signal corresponds to the moment when the grid voltage crosses zero. The synchronous square wave signal is input into the external CAP capture port of the DSP to capture the zero crossing point of the grid voltage. When the DSP detects the rising edge signal of the zero crossing point, it generates a synchronous interrupt, and the sine pointer is reset to zero during the synchronous interrupt. The sine pointer is multiplied by a reference current command to generate a sinusoidal given current command.

2. A single-phase photovoltaic grid-connected power generation system according to claim 1, characterized in that: The first Boost circuit includes an inductor L1, a diode D1, a power tube VT1, and a capacitor C1. One output end of the first photovoltaic module is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the anode of the diode D1 and the collector of the power tube VT1, the cathode of the diode D1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the emitter of the power tube VT1 and the other output end of the first photovoltaic module. The first DC / DC converter includes power tubes Q1 and Q2, a resonant capacitor Cr1, a resonant inductor Lr1, an excitation inductor Lm1, a transformer T1, rectifier diodes D2 and D3, and a capacitor Co1. The drain of the power tube Q1 is connected to the cathode of the diode D1, the emitter of the power tube Q1 is connected to the drain of the power tube Q2 and one end of the resonant capacitor Cr1, the other end of the resonant capacitor Cr1 is connected to one end of the resonant inductor Lr1, the other end of the resonant inductor Lr1 is connected to one end of the primary winding of the transformer T1, the other end of the primary winding of the transformer T1 is connected to the emitter of the power tube Q2, the excitation inductor Lm1 is connected in parallel to both ends of the primary winding of the transformer T1, the two ends of the secondary winding of the transformer T1 are respectively connected to the anodes of the rectifier diodes D2 and D3, the cathodes of the rectifier diodes D2 and D3 are respectively connected to one end of the capacitor Co1, and the other end of the capacitor Co1 is connected to the middle tap of the secondary winding of the transformer T1; The second Boost circuit includes an inductor L2, a diode D4, a power tube VT2, and a capacitor C2. One output end of the second photovoltaic module is connected to one end of the inductor L2, the other end of the inductor L2 is connected to the anode of the diode D4 and the collector of the power tube VT2, the cathode of the diode D4 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the emitter of the power tube VT2 and the other output end of the second photovoltaic module; The second DC / DC converter includes power tubes Q3 and Q4, a resonant capacitor Cr2, a resonant inductor Lr2, an excitation inductor Lm2, a transformer T2, rectifier diodes D5 and D6, and a capacitor Co2. The drain of the power tube Q3 is connected to the cathode of the diode D4, the emitter of the power tube Q3 is connected to the drain of the power tube Q4 and one end of the resonant capacitor Cr2, the other end of the resonant capacitor Cr2 is connected to one end of the resonant inductor Lr2, the other end of the resonant inductor Lr2 is connected to one end of the primary winding of the transformer T2, the other end of the primary winding of the transformer T2 is connected to the emitter of the power tube Q4, the excitation inductor Lm2 is connected in parallel to both ends of the primary winding of the transformer T2, both ends of the secondary winding of the transformer T2 are connected to the anodes of the rectifier diodes D5 and D6 respectively, one end of the capacitor Co2 is connected to the cathodes of the rectifier diodes D5 and D6 and the middle tap of the secondary winding of the transformer T1, and the other end of the capacitor Co2 is connected to the middle tap of the secondary winding of the transformer T2 and is grounded. The inverter circuit includes a capacitor Cdc, power tubes VT3, VT4, VT5, VT6, an inductor L3, an isolation transformer T3, a relay normally open contact K1, and a power grid. One end of the capacitor Cdc is connected to the cathodes of the rectifier diodes D2 and D3 and the collectors of the power tubes VT3 and VT4. The other end of the capacitor Cdc is grounded. The emitter of the power tube VT3 is connected to the collector of the power tube VT5 and one end of the inductor L3. The other end of the inductor L3 is connected to one end of the primary winding of the isolation transformer T3. The other end of the primary winding of the isolation transformer T3 is connected to the emitter of the power tube VT4 and the collector of the power tube VT6. The emitters of the power tubes VT5 and VT6 are grounded. One end of the secondary winding of the isolation transformer T3 is connected to one end of the relay normally open contact K1. The other end of the relay normally open contact K1 is connected to one end of the power grid. The other end of the power grid is connected to the other end of the secondary winding of the isolation transformer T3.

3. A single-phase photovoltaic grid-connected power generation system according to claim 2, characterized in that: The inductor L1 and the resonant inductor Lr1 are coupled inductors, and the inductor L2 and the resonant inductor Lr2 are coupled inductors.

4. A single-phase photovoltaic grid-connected power generation system according to claim 2, characterized in that: The first driving circuit adopts a control mode combining PWM and PFM, and the second driving circuit adopts a control mode combining PWM and PFM.

5. A single-phase photovoltaic grid-connected power generation system according to claim 4, characterized in that: The first driving circuit includes a first voltage sampling circuit, a first current sampling circuit, a first comparison circuit, a second comparison circuit, a third comparison circuit, a first oscillator, a first clock pulse generating circuit, and a first logic gate circuit; the output of the first voltage sampling circuit is connected to the input of the first comparison circuit, the output of the first current sampling circuit is connected to the input of the second comparison circuit, the output of the first comparison circuit is connected to the input of the third comparison circuit and the second comparison circuit respectively, the output of the second comparison circuit is connected to the input of the first clock pulse generating circuit, the output of the first clock pulse generating circuit is connected to the first logic gate circuit, the output of the third comparison circuit is connected to the first logic gate circuit through the first oscillator, and the first logic gate circuit is used to drive power tubes Q1 and Q2.

6. A single-phase photovoltaic grid-connected power generation system according to claim 5, characterized in that: The first driving circuit includes resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, and R11, capacitors C3, C4, C5, and C6, diodes D7 and D8, operational amplifiers U1, U2, and U3, a clock pulse generating chip U4, and a transistor VT7; the clock pulse generating chip U4 includes an error amplifier non-inverting input terminal EAP, an error amplifier inverting input terminal EAN, an error amplifier output terminal EAOUT, a PWM comparator non-inverting input terminal EAMP, an oscillator timing capacitor access terminal CT, an oscillator timing resistor access terminal RT, and pulse output terminals OUTA and OUTB, the error amplifier inverting input terminal EAN is connected to the error amplifier output terminal EAOUT, the PWM comparator non-inverting input terminal EAMP is connected to the oscillator timing capacitor access terminal CT and is grounded through a capacitor C6, and the pulse output terminals OUTA and OUTB are connected to the gates of the power tubes Q1 and Q2 through resistors R10 and R11, respectively; One end of the resistors R1 and R2 is respectively connected to the output voltage Va1 of the first voltage sampling circuit, the other end of the resistor R1 is connected to the inverting input terminal of the operational amplifier U1, the non-inverting input terminal of the operational amplifier U1 is connected to the reference voltage Vref1, the other end of the resistor R2 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the output terminal of the operational amplifier U1, the output terminal of the operational amplifier U1 is connected to the anode of the diode D7, the cathode of the diode D7 is respectively connected to one end of the resistors R3 and R7, the other end of the resistor R3 is connected to one end of the resistor R4 and the inverting input terminal of the operational amplifier U2, the non-inverting input terminal of the operational amplifier U2 is connected to the reference voltage Vref2, the other end of the resistor R4 is connected to the output terminal of the operational amplifier U2, the output terminal of the operational amplifier U2 is connected to the base of the transistor VT7, the collector of the transistor VT7 is connected to the access terminal RT of the oscillator timing resistor, the emitter of the transistor VT7 is grounded through the resistor R6, and the resistor R5 is connected in series with the capacitor C4 and then connected in parallel to the collector and emitter of the transistor VT7; The other end of the resistor R7 is respectively connected to the non-inverting input terminal EAP of the error amplifier and the anode of the diode D8. The cathode of the diode D8 is connected to the output terminal of the operational amplifier U3. The inverting input terminal of the operational amplifier U3 is connected to one end of the resistor R8. The other end of the resistor R8 is connected to one end of the resistor R9 and the output current Ia1 of the first current sampling circuit. The non-inverting input terminal of the operational amplifier U3 is connected to the short-circuit protection current upper limit Im. The other end of the resistor R9 is connected to one end of the capacitor C5. The other end of the capacitor C5 is connected to the output terminal of the operational amplifier U3.

7. The single-phase photovoltaic grid-connected power generation system according to claim 4, characterized in that: The second driving circuit includes a second voltage sampling circuit, a second current sampling circuit, a fourth comparison circuit, a fifth comparison circuit, a sixth comparison circuit, a second oscillator, a second clock pulse generating circuit, and a second logic gate circuit; the output of the second voltage sampling circuit is connected to the input of the fourth comparison circuit, the output of the second current sampling circuit is connected to the input of the fifth comparison circuit, the output of the fourth comparison circuit is connected to the input of the sixth comparison circuit and the fifth comparison circuit respectively, the output of the fifth comparison circuit is connected to the input of the second clock pulse generating circuit, the output of the second clock pulse generating circuit is connected to the second logic gate circuit, the output end of the sixth comparison circuit is connected to the second logic gate circuit through the second oscillator, and the second logic gate circuit is used to drive power tubes Q3 and Q4.

8. The single-phase photovoltaic grid-connected power generation system according to claim 7, characterized in that: The second driving circuit includes resistors R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, capacitors C7, C8, C9, C10, diodes D9, D10, operational amplifiers U5, U6, U7, a clock pulse generating chip U8, and a transistor VT8; The clock pulse generating chip U8 includes an error amplifier non-inverting input terminal EAP, an error amplifier inverting input terminal EAN, an error amplifier output terminal EAOUT, a PWM comparator non-inverting input terminal EAMP, an oscillator timing capacitor access terminal CT, an oscillator timing resistor access terminal RT, and pulse output terminals OUTC and OUTD. The error amplifier inverting input terminal EAN is connected to the error amplifier output terminal EAOUT, the PWM comparator non-inverting input terminal EAMP is connected to the oscillator timing capacitor access terminal CT and is grounded through a capacitor C10, and the pulse output terminals OUTC and OUTD are connected to the gates of the power tubes Q3 and Q4 through resistors R21 and R22, respectively. One end of the resistors R12 and R13 is respectively connected to the output voltage Va2 of the second voltage sampling circuit, the other end of the resistor R12 is connected to the inverting input terminal of the operational amplifier U5, the non-inverting input terminal of the operational amplifier U5 is connected to the reference voltage Vref3, the other end of the resistor R13 is connected to one end of the capacitor C7, the other end of the capacitor C7 is connected to the output terminal of the operational amplifier U5, the output terminal of the operational amplifier U5 is connected to the anode of the diode D9, the cathode of the diode D9 is respectively connected to one end of the resistors R14 and R18, the other end of the resistor R14 is connected to one end of the resistor R15 and the inverting input terminal of the operational amplifier U6, the non-inverting input terminal of the operational amplifier U6 is connected to the reference voltage Vref4, the other end of the resistor R15 is connected to the output terminal of the operational amplifier U6, the output terminal of the operational amplifier U6 is connected to the base of the transistor VT8, the collector of the transistor VT8 is connected to the access terminal RT of the oscillator timing resistor, the emitter of the transistor VT8 is grounded through the resistor R17, and the resistor R16 is connected in series with the capacitor C8 and then connected in parallel to the collector and emitter of the transistor VT8; The other end of the resistor R18 is respectively connected to the non-inverting input terminal EAP of the error amplifier and the anode of the diode D10. The cathode of the diode D10 is connected to the output terminal of the operational amplifier U7. The inverting input terminal of the operational amplifier U7 is connected to one end of the resistor R19. The other end of the resistor R19 is connected to one end of the resistor R20 and the output current Ia2 of the second current sampling circuit. The non-inverting input terminal of the operational amplifier U7 is connected to the short-circuit protection current upper limit Im. The other end of the resistor R20 is connected to one end of the capacitor C9. The other end of the capacitor C9 is connected to the output terminal of the operational amplifier U7.

9. The single-phase photovoltaic grid-connected power generation system according to claim 1, characterized in that: The grid-connected controller adopts a TMS320F28335 digital signal processor.

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