Pulse generating device and chip including the same

Abstract

The embodiment of the present application discloses a pulse generating device and a chip including the pulse generating device, and the pulse generating device may include: a first logic circuit, which includes a first input terminal for receiving a trigger signal, a first reset terminal, a first output terminal for outputting a pulse signal generated in response to the trigger signal, and a second output terminal, wherein when the first logic circuit is in a stable state, the level state of the first output terminal is opposite to that of the second output terminal; a multi-bit counter, which includes a second input terminal for receiving a clock signal, a second reset terminal connected to the second output terminal, and a plurality of third output terminals; and a second logic circuit, which includes a third input terminal connected to at least one third output terminal and a fourth output terminal connected to the first reset terminal. By utilizing the technical solution provided in the embodiment of the present application, the control accuracy of the width of the pulse signal can be improved, and the chip area occupied can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a pulse generating device and a chip including the pulse generating device. Background Art

[0002] The description in this section merely provides background information related to the disclosure of this application and does not constitute prior art.

[0003] Monostable triggers are commonly used in existing integrated circuits to generate pulse signals with fixed widths. A monostable trigger is a basic pulse unit circuit with two operating states: stable and transient. It can be widely used for pulse shaping, delaying, timing, and time measurement, making it an indispensable circuit module in modern integrated circuit design.

[0004] A monostable trigger is generally composed of a logic gate circuit and an RC circuit, and can control the width of the generated pulse signal by charging or discharging the capacitor. Figure 1 As shown, the monostable trigger can be composed of a NOR gate G1, a NOT gate G2, a capacitor (C, C d ) and resistors (R, R d ), where the capacitor C and the resistor R form an RC circuit, the capacitor C d and resistor R d A differential circuit with a very small time constant is formed. This differential circuit is mainly used to convert V I The rectangular trigger pulse signal with a wider end is converted into V d The working principle of the monostable trigger is as follows: When the monostable trigger is in the steady state, V I The voltage at the end is equal to 0, V d The voltage at is equal to 0, V 12 The voltage at V DD , V o The voltage at is equal to 0, V o1 The voltage at V DD , the voltage difference between the two ends of capacitor C is equal to 0; when the trigger pulse signal is received, V I The voltage at the terminal and V d The voltage at both ends is greater than the threshold voltage V TH , V o1 The voltage at is equal to 0, V 12 The voltage at is equal to 0, V o The voltage at V DD , at this time the monostable trigger enters the quasi-stable state; when the capacitor C is charged so that the voltage across it rises to V TH When V 12 The voltage at V TH When Vo The voltage at is equal to 0, at this time the monostable trigger exits the quasi-stable state, and the pulse width of its output is equal to the duration of the quasi-stable state; after the monostable trigger exits the quasi-stable state, V d The voltage at the point returns to 0, V o1 The voltage at V DD , V 12 The voltage at V DD +V TH , the voltage across capacitor C is V TH ; When the capacitor C is discharged to make V 12 The voltage at V DD When , the monostable trigger returns to the stable state.

[0005] In the process of implementing this application, the inventors discovered that the prior art has at least the following problems:

[0006] The width of the pulse signal generated by a monostable trigger depends on the time constant formed by the capacitors and resistors in the charging circuit. However, the precision of capacitors and resistors manufactured using integrated circuit processes is poor. This causes the width of the pulse signal generated by the manufactured monostable trigger to deviate significantly from the design target value, thereby reducing the control accuracy of the pulse signal width and affecting the performance of the chip integrated with the monostable trigger. Moreover, due to the inevitable fluctuations in existing integrated circuit manufacturing processes, this may cause the driving capability of the transistors in the discharge circuit and the threshold voltage of the gate circuit to vary, further deteriorating the control accuracy of the generated pulse width. In addition, when a pulse with a larger width needs to be generated, manufacturing larger capacitors and resistors in the integrated circuit will occupy a larger chip area, which may reduce the integration density of the integrated circuit and increase the manufacturing cost of the chip. Summary of the Invention

[0007] The purpose of the embodiments of the present application is to provide a pulse generating device and a chip including the pulse generating device, so as to improve the control accuracy of the width of the pulse signal and reduce the occupied chip area.

[0008] In order to solve the above technical problems, an embodiment of the present application provides a pulse generating device, which may include:

[0009] a first logic circuit comprising a first input terminal for receiving a trigger signal, a first reset terminal, a first output terminal for outputting a pulse signal generated in response to the trigger signal, and a second output terminal, wherein when the first logic circuit is in a stable state, the first output terminal and the second output terminal have opposite voltage levels;

[0010] a multi-bit counter comprising a second input terminal for receiving a clock signal, a second reset terminal connected to the second output terminal, and a plurality of third output terminals, and configured to count the clock signal when the pulse signal outputted from the first output terminal is at a valid level; and

[0011] a second logic circuit, comprising a third input terminal connected to at least one of the third output terminals and a fourth output terminal connected to the first reset terminal, and configured to feed back a reset signal to the first logic circuit through the fourth output terminal according to a counting state of the multi-bit counter.

[0012] Optionally, the first logic circuit includes an SR latch or a logic gate circuit composed of a D latch and having a function equivalent to that of the SR latch.

[0013] Optionally, the SR latch includes two CMOS NOR gate circuits or two CMOS NAND gate circuits, and the second logic circuit includes a multi-input AND gate circuit or a multi-input NOT gate circuit.

[0014] Optionally, the multi-bit counter includes a multi-bit binary counter, a multi-bit decimal counter, a multi-bit ring counter or a shift register type counter.

[0015] Optionally, at least two of the third input terminals are connected to corresponding at least two of the third output terminals of the multi-bit counter.

[0016] Optionally, the second logic circuit also includes a reference terminal corresponding to the third input terminal, and when a first preset base value corresponding to the level of the third input terminal is greater than or equal to a second preset base value corresponding to the level of the reference terminal, the reset signal generated by the second logic circuit is a valid level.

[0017] The present application also provides another pulse generating device, which may include:

[0018] a first logic circuit comprising a first input terminal for receiving a trigger signal, a first reset terminal, a first output terminal for outputting a pulse signal generated in response to the trigger signal, and a second output terminal, wherein when the first logic circuit is in a stable state, the first output terminal and the second output terminal have opposite voltage levels; and

[0019] A multi-bit counter is configured to count a received clock signal when a pulse signal outputted from the first output terminal is at a valid level, and comprises a second input terminal for receiving the clock signal, a second reset terminal connected to the second output terminal, and a plurality of third output terminals, wherein one of the plurality of third output terminals is connected to the first reset terminal, and a level state of one of the third output terminals is consistent with the valid level of the first reset terminal.

[0020] Optionally, the first logic circuit includes an SR latch or a logic gate circuit composed of a D latch and having a function equivalent to that of the SR latch.

[0021] An embodiment of the present application also provides a chip, in which the above-mentioned pulse generating device can be integrated.

[0022] Optionally, the chip includes a single photon avalanche diode array, a silicon photomultiplier or a time-to-digital converter.

[0023] It can be seen from the technical solutions provided by the above embodiments of the present application that the embodiments of the present application generate a pulse signal of fixed width by utilizing logic circuits such as a first logic circuit, a multi-bit counter and a second logic circuit. The pulse signal can retain the time information of the trigger signal, and the width of the pulse signal is determined by the period of the clock signal and the counting state of the multi-bit counter. This eliminates the influence of the precision errors of capacitors and resistors manufactured using integrated circuit technology on the width control of the pulse signal, thereby improving the control accuracy of the width of the pulse signal and reducing the occupied chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0025] Figure 1 It is a structural diagram of a monostable trigger in the prior art;

[0026] Figure 2 1 is a schematic structural diagram of a pulse generating device provided in an embodiment of the present application;

[0027] Figure 3 is a structural schematic diagram of another pulse generating device provided in an embodiment of the present application;

[0028] Figure 4 is a structural schematic diagram of another pulse generating device provided in an embodiment of the present application;

[0029] Figure 5 is a structural schematic diagram of another pulse generating device provided in an embodiment of the present application;

[0030] Figure 6 is a structural schematic diagram of another pulse generating device provided in an embodiment of the present application;

[0031] Figure 7 yes Figure 4 The pulse generating device shown in the figure generates a timing diagram of a pulse signal;

[0032] Figure 8 yes Figure 5 The pulse generating device shown in the figure generates a timing diagram of a pulse signal;

[0033] Figure 9 is a structural schematic diagram of another pulse generating device provided in an embodiment of the present application;

[0034] Figure 10 is a structural schematic diagram of another pulse generating device provided in an embodiment of the present application;

[0035] Figure 11 yes Figure 10 The pulse generating device shown in the figure generates a timing diagram of a pulse signal. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only used to illustrate some embodiments of the present application, not all embodiments, and are not intended to limit the scope of the present application or the claims. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application.

[0037] It should be noted that when an element is referred to as being "set on" another element, it may be directly set on the other element or there may also be an intermediate element. When an element is referred to as being "connected / coupled" to another element, it may be directly connected / coupled to the other element or there may be an intermediate element at the same time. The term "connection / coupling" as used herein may include electrical and / or mechanical physical connections / couplings. The term "includes / comprising" as used herein refers to the presence of a feature, step or element, but does not exclude the presence or addition of one or more other features, steps or elements. The term "and / or" as used herein includes any and all combinations of one or more relevant listed items.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0039] In addition, in the description of this application, the terms "first," "second," "third," etc. are used only for descriptive purposes and to distinguish similar objects. There is no order of precedence between the two, and they should not be understood to indicate or imply relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0040] In addition, in the embodiments of the present application, the effective level can be a high level or a low level, which corresponds to a high level or a low level being effective, and whether the effective level of each circuit is a high level or a low level can be preset or controlled in real time. Correspondingly, the ineffective level can be a low level or a high level, which is opposite to the effective level. The level state can also include a high level or a low level.

[0041] The pulse generating device and the chip including the pulse generating device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0042] like Figure 2 As shown, an embodiment of the present application provides a pulse generating device, which may include a first logic circuit 210, a multi-bit counter 220, and a second logic circuit 230 connected to each other. The first logic circuit 210 may be configured to receive a trigger signal (i.e., a signal that triggers the first logic circuit 210 to start operating, such as a trigger pulse signal) and output a pulse signal with a specified width in response to the trigger signal; the multi-bit counter 220 may be controlled by the first logic circuit 210 and configured to count the received clock signal when the pulse signal output by the first logic circuit 210 is at a valid level, and reset when the pulse signal output by the first logic circuit 210 is at an invalid level; the second logic circuit 230 may generate a reset signal for resetting the first logic circuit 210 according to the counting state of the multi-bit counter 220, so as to control the width of the pulse signal generated by the first logic circuit 210.

[0043] The first logic circuit 210 may include a first input terminal I1 for receiving a trigger signal, a first reset terminal R1 for receiving a reset input, a first output terminal O1 for outputting a pulse signal generated in response to the trigger signal, and a second output terminal O2. When the first logic circuit 210 is in a stable state, the voltage levels of the first output terminal O1 and the second output terminal O2 are opposite, i.e., when the first output terminal O1 outputs a high voltage level, the second output terminal O2 outputs a low voltage level, or vice versa. It should be noted that the first logic circuit 210 only changes state upon receiving a rising or falling edge of the trigger signal. Prior to receiving a rising or falling edge of the trigger signal, the first logic circuit 210 may maintain its current state, i.e., be in a stable state. Furthermore, the first output terminal O1 may serve as the output terminal of the pulse generating device.

[0044] The first logic circuit 210 may include a latch, for example, an SR latch, or may include a logic circuit composed of a D latch having a function equivalent to that of an SR latch. Figure 3 and Figure 4 As shown, when the first logic circuit 210 is an SR latch, the first output terminal O1 and the second output terminal O2 can be a non-inverting output terminal Q and an inverting output terminal Q with opposite level states. Specifically, when the first output terminal O1 outputs a high level, it can be the in-phase output terminal Q, and the second output terminal O2 can be the inverting output terminal When the first output terminal O1 outputs a low level, it can be an inverting output terminal. The second output terminal O2 may be a non-inverting output terminal Q. The SR latch may be formed by a logic gate circuit, for example, by two complementary metal oxide semiconductor (CMOS) or NOT gate circuits, such as Figure 3 As shown, or it can be composed of two CMOS NAND gate circuits, such as Figure 4 As shown; it can also be directly composed of transistors, but is not limited to this.

[0045] The logical function of the SR latch is as follows: when the first input terminal S is high and the first reset terminal R1 is low, the in-phase output terminal Q outputs a high level and the inverting output terminal Output low level; when the first input terminal S is low level and the first reset terminal R1 is high level, the in-phase output terminal Q outputs low level, and the inverting output terminal Output high level; when the first input terminal S and the first reset terminal R1 are both high level, the in-phase output terminal Q and the inverting output terminal Maintain the previous level state; when the first input terminal S and the first reset terminal R1 are simultaneously converted to low level, the SR latch is in a functional failure state, and the in-phase output terminal Q and the inverting output terminal The level state cannot be determined; when the first input terminal S and the first reset terminal R1 are successively changed to low level, the in-phase output terminal Q and the inverting output terminal The level state when the first input terminal S and the first reset terminal R1 are both at low levels remains consistent with the level state immediately before the first input terminal S and the first reset terminal R1 are both at low levels.

[0046] The multi-bit counter 220 may include a second input terminal CP for receiving a clock signal, a second reset terminal R2 for receiving a reset input, and a plurality of third output terminals (eg, Q0, Q1, Q2, Q3, ..., Q n-1 , n is a positive integer greater than 1), wherein the second reset terminal R2 can be connected to the second output terminal (for example, the inverting output terminal) of the first logic circuit 210. The multi-bit counter 220 may be a multi-bit binary counter, a multi-bit decimal counter, or a multi-bit counter of another base, or may be a multi-bit ring counter or a shift register type counter, but is not limited thereto, and may employ a synchronous triggering method or an asynchronous triggering method.

[0047] The logic function of the multi-bit counter 220 is as follows: when the second reset terminal R2 is active at a high level or a low level, the multi-bit counter 220 is in an initial counting state, and its multiple third output terminals generate corresponding output signals (e.g., 0…000, where 0 can represent a high level or a low level) according to a preset base. When the second reset terminal R2 is low (i.e., the first output terminal O1 outputs a high level and the second output terminal O2 outputs a low level), each time the second input terminal CP receives a rising edge or a falling edge of a clock signal, the multi-bit counter 220 begins counting in the current counting state (e.g., the initial counting state) according to a preset counting method (e.g., an incrementing or decrementing method), and the multiple third output terminals generate corresponding output signals (e.g., 0…001). It should be noted that the initial counting state can be 0…000, 1…111, or any other counting state. The preset base depends on the type of the multi-bit counter 220, for example, it can be binary, decimal, etc.

[0048] The second logic circuit 230 can generate a corresponding reset signal based on the logical relationship of the input signals and feed the reset signal back to the first reset terminal of the first logic circuit 210. The second logic circuit 230 can be a combinational logic circuit, and its output state depends only on the input state at the current moment and has nothing to do with its previous state. The second logic circuit 230 can include a third input terminal (e.g., Q'0, Q'1, Q'2, Q'3, ..., Q'4) connected to at least one third output terminal. n-1) and a fourth output terminal O4 connected to the first reset terminal R1 of the first logic circuit 210, wherein only one third output terminal may be connected to a corresponding third input terminal of the multi-bit counter 220, such as Figure 5 As shown, there may also be at least two (for example, n) third output terminals connected to corresponding at least two third input terminals of the multi-bit counter 220. Figure 2 As shown, the number of the third output terminals can be the same as the number of the third input terminals. In addition, the second logic circuit 230 can include a multi-input AND gate circuit (for example, composed of a NAND gate circuit and a NOT gate circuit) or a multi-input NAND gate circuit, for example, an m-input NAND gate circuit, where m represents the number of connections between the third input terminal of the second logic circuit 230 and the third output terminal of the multi-bit counter 220, which can be a positive integer between 1 and n. For example, when m=2, the third input terminals Q'0 and Q'5 of the second logic circuit 230 can be connected to the third output terminals Q0 and Q5 of the multi-bit counter 220, as shown in FIG. Figure 6 The number and manner of connections between the third input terminal of the second logic circuit 230 and the third output terminal of the multi-bit counter 220 can be determined according to the width of the pulse signal to be generated.

[0049] against Figure 3 The pulse generating device shown in the figure works as follows: In the initial state, the first input terminal S of the SR latch is low level, the first reset terminal R1 is low level, the in-phase output terminal Q outputs low level, and the inverting output terminal Output high level, the multi-bit counter is in the initial counting state (for example, 0...000), the second logic circuit outputs low level, and the pulse generating device outputs low level at this time; when the first input terminal S of the SR latch receives the rising edge of the trigger pulse signal, the first input terminal S is high level, the first reset terminal R is low level, and the level state of the SR latch changes immediately, that is, the in-phase output terminal Q outputs high level and the inverting output terminal Output low level, the multi-bit counter is still in the initial counting state, the second logic circuit outputs low level, and the pulse generating device starts to output high level at this time; when the second input terminal CP of the multi-bit counter receives the rising edge or falling edge of the clock signal, the multi-bit counter starts counting based on the initial counting state, and before the count of the multi-bit counter reaches its upper counting limit (for example, 1...111), the second logic circuit keeps outputting low level, and the pulse generating device keeps outputting high level; when the trigger signal has returned to low level and the count of the multi-bit counter reaches its upper counting limit, the second logic circuit outputs high level, the first input terminal S of the SR latch is low level, the non-inverting output terminal Q of the SR latch immediately flips to low level, and the inverting output terminal It immediately flips to a high level, the multi-bit counter is reset to return to the initial counting state, and the second logic circuit outputs a low level; the first input terminal S and the first reset terminal R of the SR latch are both low levels, and the output terminal of the pulse generating device immediately outputs and maintains a low level, thereby returning to the initial state again.

[0050] In actual operation, the pulse generating device outputs a high-level pulse signal under the action of the rising edge of the trigger signal. The rising edge of the high-level pulse signal follows the rising edge of the trigger signal, that is, the time information of the rising edge of the trigger signal is retained, and its falling edge follows the (2nd) n -1) rising edges, thus generating a width of (2 n -1)×Tns pulses, with a control accuracy of T, where n represents the number of bits of the multi-bit counter and T represents the period of the clock signal, for example 10ns.

[0051] In addition, the pulse generating device can provide (2 n -1) valid counting state and the second logic circuit is (2 n -1)×Tns, the short pulse signals output can be used for the control logic of digital circuits.

[0052] against Figure 4 In the pulse generating device shown in FIG, the first input terminal S and the first reset terminal R of the SR latch are both active at low level, and when the first input terminal S receives the falling edge of the trigger signal, the pulse generating device outputs a high level, and the multi-bit counter starts counting. When the count of the multi-bit counter reaches the upper limit (for example, multiple third output terminals all output high levels), the fourth output terminal O4 of the second logic circuit outputs a low level, thereby resetting the SR latch. At this time, the pulse generating device outputs a low level. The pulse generating device can also generate a pulse with a width of (2 n -1)×Tns pulse signal, and its control accuracy is T.

[0053] Figure 7 and Figure 8 Shown respectively Figure 4 and Figure 5 The pulse generator shown in FIG. 1 shows a timing diagram of a pulse signal. The multi-bit counter is 6 bits. The pulse generator can generate a pulse signal with a width of 630ns, a control accuracy of 10ns, and the pulse signal retains the time information of the trigger signal (e.g., the time when the falling edge arrives).

[0054] In another embodiment of the present application, Figure 9As shown, the second logic circuit 230 can also be a numerical comparison circuit composed of gate circuits, which can also include a reference terminal corresponding to the third input terminal (for example, S0, S1, S2, S3...S n-1 ), and only when the first preset base value corresponding to the level of the third input terminal is greater than or equal to the second preset base value corresponding to the level of the reference terminal, the reset signal generated by the second logic circuit 230 is at an effective level. It should be noted that the above statement covers the following three cases: when the first preset base value is greater than the second preset base value, the reset signal generated by the second logic circuit 230 is at an effective level; when the first preset base value is equal to the second preset base value, the reset signal generated by the second logic circuit 230 is at an effective level; or when the first preset base value is greater than or equal to (i.e., not less than) the second preset base value, the reset signal generated by the second logic circuit 230 is at an effective level. In addition, the first preset base value and the second preset base value respectively represent the values ​​obtained by converting the level of the third input terminal and the level of the reference terminal according to the same preset base (e.g., binary), for example, they can be 110001 and 110000, respectively. In addition, the reset signal being at an effective level can mean that the reset signal is high-level effective or low-level effective. For example, in the case where the second logic circuit 230 is composed of a multi-input AND gate, the reset signal is valid when the fourth output terminal of the second logic circuit 230 outputs a high level, that is, the high level is valid; in the case where the second logic circuit 230 is composed of a multi-input NOT gate (such as Figure 4 As shown), the reset signal being valid may mean that the fourth output terminal of the second logic circuit 230 outputs a low level, that is, the low level is valid.

[0055] Taking the first logic circuit 210 as an SR latch as an example, the working principle of the pulse generating device is as follows: in the initial state, the first input terminal S of the SR latch is at a low level, the first reset terminal R1 is at a high level, the in-phase output terminal Q is at a low level, and the inverting output terminal is high, the multi-bit counter is in the initial counting state (for example, 0...000), the second logic circuit outputs a low level, and the pulse generating device outputs a low level at this time; when the first input terminal S of the SR latch receives the rising edge of the trigger pulse signal, the first input terminal S is high, the first reset terminal R1 is low, and the level state of the SR latch changes immediately, that is, the in-phase output terminal Q outputs a high level and the inverting output terminal Output low level, the multi-bit counter is still in the initial counting state, the second logic circuit outputs low level, and at this time the pulse generating device starts to output high level; when the second input terminal CP of the multi-bit counter receives the rising edge or falling edge of the clock signal, the multi-bit counter starts counting based on the initial counting state, and before the level of the third output terminal of the multi-bit counter (i.e., the count of the multi-bit counter) does not reach the preset level (for example, 1...001) of the corresponding reference terminal in the second logic circuit, the second logic circuit keeps outputting low level, and the pulse generating device keeps outputting high level; when the trigger signal has recovered to low level and the level of the third output terminal of the multi-bit counter reaches the preset level of the corresponding reference terminal in the second logic circuit, the second logic circuit outputs high level, the first input terminal S of the SR latch is low level, the non-inverting output terminal Q of the SR latch immediately flips to low level, and the inverting output terminal It immediately flips to a high level, the multi-bit counter is reset to return to the initial counting state, and the second logic circuit outputs a low level; the first input terminal S and the first reset terminal R1 of the SR latch are both low levels, and the output terminal of the pulse generating device immediately outputs and maintains a low level, thereby restoring to the initial state again.

[0056] In actual operation, the pulse generating device outputs a high-level pulse signal under the action of the rising edge of the trigger signal. The rising edge of the high-level pulse signal follows the rising edge of the trigger signal, that is, the time information of the rising edge of the trigger signal is retained; under the control of the reference terminal level of the second logic circuit, its falling edge follows the second (2) n -1) rising edges, thus generating a width of (2 n -1)×Tns pulse signal, its control accuracy is T, where n represents the number of bits of the multi-bit counter and T represents the period of the clock signal, for example 10ns. Figure 3 Based on the pulse generating device in the present invention, this pulse generating device additionally has the function of controlling the width of the output pulse with a control accuracy of 10ns.

[0057] It should be noted that for Figure 9 The pulse generating device shown in FIG, except the second logic circuit, the SR latch and the multi-bit counter are all connected with Figure 3 The SR latch and the multi-bit timer shown in FIG are the same. In addition, although not shown, the second logic circuit can also be Figure 4 The second logic circuit shown in FIG includes a reference terminal corresponding to the third input terminal. Figure 4 and Figure 8 The description of , will not be repeated here. In addition, Figure 9Here, the case where the first logic circuit is an SR latch is taken as an example. The first logic circuit may also be other circuits composed of triggers, which is not limited here.

[0058] From the above description, it can be seen that the embodiment of the present application generates a fixed-width pulse signal by utilizing a first logic circuit, a multi-bit counter, and a second logic circuit. The pulse signal retains the time information of the trigger signal, and the width of the pulse signal is determined by the period of the clock signal and the counting state of the multi-bit counter. This eliminates the influence of the precision error of the capacitors and resistors manufactured using the integrated circuit process on the width control of the pulse signal. In addition, the pulse generating device provided by the embodiment of the present application, which is completely implemented by the logic circuit, only contains the parasitic capacitance and resistance caused by the internal transistors and the interconnections between transistors. Therefore, the pulse generating device is less affected by the deterioration of the width precision of the generated pulse signal caused by the changes in the transistor driving capability and the gate circuit threshold voltage caused by process fluctuations.

[0059] In addition, in the embodiment of the present application, if the width of the generated pulse signal is to be T width , when the period of the clock signal is T, the number of flip-flops required is Therefore, the pulse generator provided by the present invention has a roughly logarithmic relationship between the chip area occupied and the width of the generated pulse signal. In contrast, the chip area occupied by capacitors and resistors in conventional integrated circuits is roughly proportional to the width of the generated pulse signal. Therefore, when generating a pulse signal with a relatively large width is required, the pulse generator provided by the present invention can reduce the chip area occupied.

[0060] In addition, the second logic circuit provided in the embodiment of the present application can also adopt a digital value comparison circuit, which makes it possible to flexibly adjust the width of the generated pulse signal by adjusting the level of the reference end of the second logic circuit or changing the period of the clock signal after the chip is manufactured.

[0061] The present application also provides another pulse generating device, such as Figure 10As shown, the pulse generating device may include a first logic circuit 810 and a multi-bit counter 820 connected to each other. The first logic circuit 810 may be configured to receive a trigger signal and output a pulse signal with a specified width in response to the trigger signal, and may include a first input terminal I1 for receiving the trigger signal, a first reset terminal R1, a first output terminal O1 for outputting a pulse signal, and a second output terminal O2, and when the first logic circuit 810 is in a stable state, the level states of the first output terminal O1 and the second output terminal O2 are opposite; the multi-bit counter 820 may be configured to count the received clock signal when the pulse signal outputted from the first output terminal O1 in the first logic circuit 810 is at a valid level (e.g., a high level), and reset when the pulse signal outputted from the first output terminal O1 in the first logic circuit 810 is at an invalid level (e.g., a low level), and may include a second input terminal CP for receiving the clock signal, a second reset terminal R2 connected to the second output terminal of the first logic circuit 810, and a plurality of third output terminals (Q0, Q1, Q2...Q n-1 ), wherein one of the plurality of third output terminals (eg, Q i , i is an integer between 0 and n-1) is connected to the first reset terminal R1 of the first logic circuit 810, and the level state of the one third output terminal is consistent with the effective level of the first reset terminal R1. Specifically, when the effective level of the first reset terminal R1 is low (i.e., low level is active), the one output terminal should output a low level; correspondingly, when the effective level of the first reset terminal R1 is high (i.e., high level is active), the one output terminal should output a high level.

[0062] For example, when the third output terminal Q of the multi-bit counter 820 is i When connected to the first reset terminal R1 of the first logic circuit 810, the width of the pulse signal generated by the pulse generating device can be 2 i ×T. For example, Figure 11 As shown, when i is 5 and the clock period is 10ns, the width of the generated pulse signal can be 320ns, and the control accuracy is 10ns.

[0063] For the description of the first logic circuit 810 and the multi-bit counter 820 in the pulse generating device, reference may be made to the relevant description of the first logic circuit 210 and the multi-bit counter 220 in the above embodiment, which will not be repeated here.

[0064] The first logic circuit, multi-bit counter, and second logic circuit described in the above embodiments may all include metal-oxide semiconductor (MOS) logic gate circuits, transistor-transistor logic (TTL) gate circuits, emitter-coupled logic (ECL) gate circuits, and / or other circuits that conform to relevant logic functions.

[0065] The embodiment of the present application generates a pulse signal of fixed width by utilizing a first logic circuit and a multi-bit counter and other logic circuits, and the width of the pulse signal is determined by the period of the clock signal and the counting state of the multi-bit counter. This eliminates the influence of the precision error of capacitors and resistors manufactured using integrated circuit technology on the width control of the pulse signal, and can also reduce the occupied chip area.

[0066] In addition, embodiments of the present application further provide a chip that may integrate the pulse generation device described in the above embodiments. The chip may include, but is not limited to, a single-photon avalanche diode array with digital logic functions, a digital silicon photomultiplier, or a time-to-digital converter.

[0067] The devices, circuits, etc. described in the above embodiments can be implemented by chips and / or entities (e.g., discrete components), or by products with certain functions. For the convenience of description, the above devices are described separately according to their functions in various modules. Of course, when implementing the embodiments of the present application, the functions of each module can be integrated into the same or multiple chips.

[0068] Although the present application provides the components described in the above embodiments or drawings, the device may include more or fewer components based on routine or no creative effort. The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments.

[0069] The above embodiments are described to facilitate understanding and use of this application by those skilled in the art. It is apparent that those skilled in the art can easily make various modifications to these embodiments and apply the general principles described herein to other embodiments without requiring creative effort. Therefore, this application is not limited to the above embodiments. Improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope of this application should be within the scope of protection of this application.

Claims

1. A pulse generating device, characterized in that: The pulse generating device comprises: A first logic circuit, comprising a first input terminal for receiving a trigger signal, a first reset terminal, a first output terminal for outputting a pulse signal with a specified width generated in response to the trigger signal, and a second output terminal, wherein when the first logic circuit is in a stable state, the level state of the first output terminal is opposite to that of the second output terminal; a multi-bit counter comprising a second input terminal for receiving a clock signal, a second reset terminal connected to the second output terminal, and a plurality of third output terminals, and configured to count the clock signal when the pulse signal outputted from the first output terminal is at a valid level; and a second logic circuit, comprising a third input terminal connected to at least one of the third output terminals and a fourth output terminal connected to the first reset terminal, and configured to feed back a reset signal to the first logic circuit through the fourth output terminal according to a counting state of the multi-bit counter, wherein the number and mode of connections between the third input terminal of the second logic circuit and the third output terminal of the multi-bit counter are determined according to a width of a pulse signal to be generated; The first logic circuit includes an SR latch or a logic circuit composed of a D latch and having a function equivalent to that of the SR latch; The width of the pulse signal is determined by the period of the clock signal and the counting state of the multi-bit counter.

2. The pulse generating device according to claim 1, characterized in that: The SR latch includes two CMOS NOR gate circuits or two CMOS NAND gate circuits, and the second logic circuit includes a multi-input AND gate circuit or a multi-input NOT gate circuit.

3. The pulse generating device according to claim 1, characterized in that: The multi-bit counter includes a multi-bit binary counter, a multi-bit decimal counter, a multi-bit ring counter or a shift register type counter.

4. The pulse generating device according to claim 1, characterized in that: At least two of the third input terminals are connected to corresponding at least two of the third output terminals of the multi-bit counter.

5. The pulse generating device according to claim 1, characterized in that: The second logic circuit also includes a reference terminal corresponding to the third input terminal, and when a first preset base value corresponding to the level of the third input terminal is greater than or equal to a second preset base value corresponding to the level of the reference terminal, the reset signal generated by the second logic circuit is a valid level.

6. A pulse generating device, characterized in that: The pulse generating device comprises: A first logic circuit, comprising a first input terminal for receiving a trigger signal, a first reset terminal, a first output terminal for outputting a pulse signal with a specified width generated in response to the trigger signal, and a second output terminal, wherein when the first logic circuit is in a stable state, the level state of the first output terminal is opposite to that of the second output terminal; and A multi-bit counter, configured to count a received clock signal when a pulse signal outputted from the first output terminal is at an effective level, and comprising a second input terminal for receiving the clock signal, a second reset terminal connected to the second output terminal, and a plurality of third output terminals, wherein one of the plurality of third output terminals is connected to the first reset terminal, and a level state of one of the third output terminals is consistent with an effective level of the first reset terminal; The first logic circuit includes an SR latch or a logic gate circuit composed of a D latch and having a function equivalent to that of the SR latch; The width of the pulse signal is determined by the period of the clock signal and the counting state of the multi-bit counter.

7. A chip, characterized in that: The chip is integrated with the pulse generating device according to any one of claims 1 to 6.

8. The chip according to claim 7, characterized in that: The chip includes a single photon avalanche diode array, a silicon photomultiplier or a time-to-digital converter.

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