Integrated circuit structure

Abstract

An embodiment of the present disclosure provides an integrated circuit structure, including: a first gate covering a first channel region in an active region; a first transistor including a first channel region, a first source region, a first drain region, and a first gate; a conductive contact directly connected to the first drain region of the first transistor; a second gate separated from the first gate, the second gate covering a second channel region; a second transistor including a second channel region, a second source region, a second drain region, and a second gate; a conductive via directly connected to the second gate; an enlarged conductive via covering the conductive contact and the conductive via so as to electrically connect them to each other, the enlarged conductive via extending in a plane from the conductive contact to the conductive via; and a first electrically insulating layer surrounding the enlarged conductive via.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, and more particularly to an integrated circuit structure. Background Art

[0002] Microprocessors, including their family of microcontrollers, application-specific integrated circuits (ASICs), and various chips with one or more central processing units (CPUs) on a single die, typically include a block of static random access memory (SRAM). When a microprocessor includes a block of SRAM, some of the processes used to manufacture the microprocessor can also be used to manufacture the SRAM. To achieve this goal, the SRAM should be designed to be compatible with the process technology used to manufacture the microprocessor. Different material layers available when constructing a microprocessor should be used in the SRAM. This presents different challenges compared to independently manufactured SRAM chips.

[0003] If the SRAM cells can be constructed using the same masks, materials, deposition steps, insulating layers, and other process technologies when manufacturing a microprocessor, it is possible to eliminate the need for special masks and process steps for the internal structure of the SRAM cells, while also reducing the total number of masks required to manufacture the microprocessor chip. Summary of the Invention

[0004] An embodiment of the present invention provides an integrated circuit structure, comprising: a substrate; a semiconductor active region covering the substrate; a first gate covering a first channel region in the active region; a first transistor comprising a first channel region, a first source region adjacent to a first side of the first channel region in the active region, a first drain region adjacent to a second side of the first channel region, and a first gate; a conductive contact directly connected to the first drain region of the first transistor; a second gate spaced apart from the first gate, the second gate covering the second channel region; a second transistor comprising a second channel region, a second source region adjacent to a first side of the second channel region in the active region, a second drain region adjacent to a second side of the second channel region, and a second gate; a conductive via directly connected to the second gate; an enlarged conductive via covering the conductive contact and the conductive via so as to electrically connect them to each other, the enlarged conductive via extending in a plane from the conductive contact to the conductive via; and a first electrically insulating layer surrounding the enlarged conductive via. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following describes embodiments of the present invention in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of elements may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present invention.

[0006] Figure 1A A circuit diagram of a 6-transistor static random access memory cell is shown.

[0007] Figure 1B A top view of a static random access memory cell layout according to the prior art is shown.

[0008] Figure 1C For the Figure 1B Cross-sectional view taken along the midline segment 1C-1C.

[0009] Figure 2A A top view of a layout of a portion fabricated in a first step of fabricating a static random access memory cell is shown according to some embodiments.

[0010] Figure 2B For the Figure 2A Cross-sectional view taken along line 2B-2B.

[0011] Figure 3A A top view illustrating a layout for subsequent steps in fabricating a static random access memory cell according to some embodiments.

[0012] Figure 3B For the Figure 3A Cross-sectional view taken along line 3B-3B.

[0013] Figure 4A A top view illustrating a layout for subsequent steps in fabricating a static random access memory cell according to some embodiments.

[0014] Figure 4B For the Figure 4A Cross-sectional view taken along line 4B-4B.

[0015] Figure 5A A top view illustrating a layout for subsequent steps in fabricating a static random access memory cell according to some embodiments.

[0016] Figure 5B For the Figure 5A Cross-sectional view taken along line 5B-5B.

[0017] Figure 5C To ensure the smooth operation of the production process at different stages Figure 5A Cross-sectional view taken along line 5B-5B.

[0018] Figure 6A A top view illustrating a layout for subsequent steps in fabricating a static random access memory cell according to some embodiments.

[0019] Figure 6B According to some embodiments, Figure 6A Cross-sectional view taken along line 6B-6B.

[0020] Figure 6C According to some other embodiments, Figure 6A Cross-sectional view taken along line segment 6C-6C.

[0021] Figure 6D According to some further embodiments, a metal layer covers the insulating layer.

[0022] Figure 7 A top view of a static random access memory cell layout is shown, illustrating various nodes in the circuit, according to some embodiments.

[0023] Figure 8A A top view illustrating a layout of steps for manufacturing a static random access memory cell according to some other embodiments.

[0024] Figure 8B For the Figure 8A Cross-sectional view taken along line 8B-8B.

[0025] Figure 9A according to Figure 8A Other embodiments show top views of the layout of steps for manufacturing static random access memory cells.

[0026] Figure 9B For the Figure 9A Cross-sectional view taken along line 9B-9B.

[0027] Figure 10A according to Figure 8A Other embodiments show top views of the layout of steps for manufacturing static random access memory cells.

[0028] Figure 10B For the Figure 10A Cross-sectional view taken along line 10B-10B.

[0029] Description of reference numerals:

[0030] 9~Gate structure

[0031] 10~Static random access memory unit

[0032] 11~Active area

[0033] 12~Active area

[0034] 13~Gate insulator

[0035] 14~Gate

[0036] 15~Electrical insulation layer

[0037] 16~Insulator

[0038] 17~Guide hole

[0039] 18~Contact

[0040] 19~Insulation layer

[0041] 20~guide hole

[0042] 21~Guide hole

[0043] 22~Insulation material

[0044] 23~Guide hole

[0045] 24~Guide hole

[0046] 25~Metal layer

[0047] 25a, 25b, 25c~strip-shaped internal connection

[0048] 26~Opening

[0049] 28~Insulation layer

[0050] 30~Wiring layer

[0051] 42~Enlarge the guide hole

[0052] 44~Hole

[0053] 46~Hole

[0054] 1C-1C, 2B-2B, 3B-3B, 4B-4B, 5B-5B, 6B-6B, 6C-6C, 8B-8B, 9B-9B, 10B-10B ~ line segment

[0055] BL~Bit Line

[0056] ~Inverted bit line

[0057] Q1, Q2~Data Node

[0058] WL~Character Line

[0059] Vdd, Vss~power supply

[0060] Vg1, Vg2~node DETAILED DESCRIPTION

[0061] The following embodiments of the present invention will be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements, and the structures shown therein are not necessarily drawn to scale. It should be understood that this detailed description and the corresponding drawings do not limit the scope of the embodiments of the present invention in any way, and that this detailed description and the drawings merely provide some examples to illustrate some ways in which the concepts of the present invention may be embodied.

[0062] The following discloses many different implementation methods or examples to implement the different features of the embodiments of the present invention. The following describes specific embodiments of components and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration and should not be used to limit the scope of the embodiments of the present invention. For example, when the specification mentions that a first feature is formed on a second feature, it includes an embodiment in which the first feature and the second feature are in direct contact, and also includes an embodiment in which there are other features between the first feature and the second feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the embodiments of the present invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0063] In addition, spatially relative terms may be used, such as "below," "beneath," "lower," "above," "upper," and similar terms. These spatially relative terms are used to facilitate describing the relationship between one element or feature and another element or feature in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or in other orientations, the spatially relative adjectives used therein will also be interpreted based on the rotated orientation.

[0064] Figure 1A According to some embodiments, circuits for constructing a static random access memory cell are shown. The circuit elements and electrical connections of a 6-transistor static random access memory cell are known in the art. Although the circuit itself is known, there are many different layouts that can be used to implement the circuit. Figure 1A The circuit shown in FIG. The embodiments of the present invention are Figure 1A The compact layout of the SRAM cell circuit is compatible with a microprocessor fabricated using the same process in the same semiconductor chip. In some embodiments, the same process steps used to fabricate the microprocessor can be used to fabricate the SRAM cell described herein, which will produce a compact SRAM cell. Figure 1A The circuit shown in FIG. No additional mask is required for manufacturing the microprocessor. Furthermore, the mask used to manufacture the microprocessor has a selected shape in the embedded SRAM portion of the semiconductor chip to achieve the layout and structure described herein. Advantageous circuit connections and operation of the SRAM cell will now be explained.

[0065] Figure 1AAs shown, the static random access memory cell 10 has six transistors. This includes two P-channel transistors P1 and P2, and two N-channel transistors N1 and N2. These four transistors are connected as cross-coupled inverters to store data at data nodes Q1 and Q2. Data node Q1 is connected to the gates of P2 and N2 at node Vg1, and data node Q2 is connected to the gates of P1 and N1 at node Vg2. Access transistor N3 is connected to data node Q1 at one end and to bit line BL at the other end. Access transistor N4 is connected to data node Q2 at one end and to bit line BL at the other end. The word line WL enables transistors N3 and N4 to access data nodes Q1 and Q2 from the bit line. Data nodes Q1 and Q2 can be accessed from the bit line to store data in the data nodes or read data from the data nodes. The sources of transistors P1 and P2 are connected together and connected to Vdd. The sources of transistors N1 and N2 are connected together and connected to Vss. The drains of P1 and N1 are connected, and the drains of P2 and N2 are connected. Figure 1A The specific circuit structure shown acts as a static random access memory cell to control the system to allow data to be written to and read from nodes Q1 and Q2.

[0066] Figure 1B and Figure 1CPortions of a 6-transistor cell using conventional layouts and techniques are shown. Gate structures 9 overlie active regions 11. Electrically insulating layers 15 provide electrical isolation around each gate structure 9. These layers may include interlayer dielectrics, passivation layers, and various layers of insulating materials. Overlying the gate structures is a gate insulator 13, formed from a suitable electrically insulating layer compatible with semiconductor process technology. Electrical contacts 17 are formed to the active regions. Electrical contacts 17 provide contact between the active regions and other circuit elements in the static random access memory cell to nodes Q1 or Q2 within the cell. Electrically insulating layer 19 overlies the gate structures and contacts 17. Using various lithographic (photolithographic) and etching techniques, openings are formed in insulating layer 19, followed by openings in gate insulator 13, to provide vias at selected locations within the gate structures. Vias 21 are formed extending through insulating layer 19 and gate insulator 13 to contact each gate structure 9 at selected locations within the cell. At other locations within the insulating layer 19, openings are formed to the active region contacts 17, and vias 23 are formed therein to electrically connect to the contacts 17. A conductive layer 25, such as a metal layer, is blanket deposited over the insulating layer 19, followed by photolithography and etching to form conductive interconnects 25a, 25b, and 25c that are electrically connected to different nodes of the SRAM cell. In addition to being connected to the active region contacts 17, the same conductive layer 25 is also connected to gate vias 21 at different locations within the cell. Furthermore, the conductive layer 25 is also used to electrically connect to different circuit nodes within the SRAM cell and to connect cells to each other. For example, a strip-shaped interconnect 25b of the same conductive layer 25a extends through the central region of the SRAM cell. Furthermore, other portions 25c are also electrically connected to various nodes of the SRAM cell.

[0067] A particular disadvantage of the existing layout and structure is that electrically connecting metal layer 25 to the active region requires double-stacked contacts and vias 17 and 23. When vias are stacked on top of each other or on top of contacts, mask alignment errors can occur, requiring additional tolerance in mask alignment, leading to an increase in the size of the memory cell layout. Furthermore, the same metal layer 25 is used to form structures 25a, 25b, and 25c. Because each portion of metal layer 25 covers insulating layer 19, this results in very small metal-to-metal spacing in the same plane. As memory cells are made more compact, the individual metal strips 25a, 25b, and 25c become very close to each other, and any discontinuity in the electrical isolation between them can short-circuit each other. Furthermore, when two metal layers are placed in close proximity with a dielectric between them, a capacitor is created. As memory cell dimensions decrease, the different conductive strips of layer 25, shown here as 25a, 25b, and 25c, move closer together, significantly increasing the capacitance of the memory cell, reducing its operating speed and potentially interfering with the long-term storage of data.

[0068] Figure 2A and Figure 2B The layout and first set of steps for fabricating a static random access memory cell are shown according to some embodiments. Active region 12 comprises a semiconductor material. Active region 12 may be silicon, silicon-germanium, or other acceptable semiconductor material combinations. In one embodiment, active region 12 comprises a fin structure to form a fin field-effect transistor (FinFet). Gate 14 overlies active region 12 at selected locations where transistors are to be formed. Gate 14 is made of an acceptable metal, with a gate insulator positioned between active region 12 and gate 14. The gate insulator may comprise hafnium oxide, and in some embodiments, silicon dioxide, silicon nitride, or other insulators. The gate material may comprise molybdenum, titanium, titanium-nitride, tantalum, aluminum, and various other metals and metal alloys selected based on the desired work function of the gate layer of the transistor being formed.

[0069] The electrically insulating structure 16 covers the active region 12, the gate structure 14, and the space between the gate structures. The insulating material 16 may include multiple layers and various spacers, as well as other acceptable electrically insulating layers. The insulating material 16 may be formed of silicon dioxide, silicon nitride, or other suitable electrically insulating materials compatible with semiconductor process technology. In some embodiments, the insulating material 16 includes many different layers and sublayers of different types of insulating materials to facilitate electrical isolation between different structures. Different insulating layers are used to form a microprocessor on a semiconductor chip. These insulating layers are used to form microprocessor circuits, including central processing units, logic, and other transistors that can be deposited in the location of static random access memory cells to form the insulating material 16.

[0070] like Figure 3A and Figure 3B As shown, a contact is formed through the insulating structure 16 to the active region 12. Contact 18 is formed by etching an opening at a selected location in the insulating material 16 and forming the contact using conventional techniques. In one embodiment, the contact 18 is a tungsten plug, with a Ti and / or TiN liner deposited in the opening, followed by blanket deposition of tungsten and etching back to form the contact 18. The structure after forming the contact 18 is shown in FIG. Figure 3A and Figure 3B middle.

[0071] In one embodiment, Figure 3B After the structure is formed, a sealing layer such as Ti or TiN is blanket formed on the entire exposed structure. This provides a sealing layer on the exposed surface of the contact 18 and the insulating structure 16.

[0072] Figure 4A and Figure 4B Subsequent steps are shown according to some embodiments. A blanket insulating layer 22 is formed over the entire structure, covering insulating material 16, as well as contact 18 and gate 14. This layer 22 is formed by blanket deposition. This may be followed by a planarization etchback, typically chemical mechanical polishing (CMP). Insulating layer 22 can be made of any acceptable material, including silicon nitride, silicon oxide, or any other acceptable dielectric.

[0073] An opening is formed in insulating layer 22 to form a via to metal gate 14. The opening in insulating layer 22 is masked with a photoresist deposition and an etch process, and in some embodiments, is formed using an anisotropic etch, such as reactive ion etching. Etching is performed to etch through the upper portion of insulating structure 16, exposing gate 14. In these examples, insulating layer 22 and insulating structure 16 are made of different materials. The etch chemistry can be varied during the etch process to etch different layers, such as silicon oxide, silicon nitride, or other materials that may be present in layers 22 and 16. In embodiments where a sealing layer, such as Ti or TiN, is present over insulating structure 16, layer 22 can be etched until the sealing layer is reached, at which point the etch chemistry is varied to etch the sealing layer at the corresponding location of via 20. Once the sealing layer is removed at that location, the etch chemistry is varied again to etch through insulating structure 16 until gate 14 is reached. Etching can be timed, or an etchant can be used that does not etch gate material 14, thereby acting as an etch stop. Etching is continued until the upper layer of gate structure 14 is exposed. Conductive vias 20, such as metal vias, are formed in the openings of layer 22 and structure 16 to provide electrical contact to metal gate 14. The vias may be formed using any acceptable technology, such as tungsten plugs with Ti and / or TiN liners, and the like.

[0074] Figure 5A 、 Figure 5B and Figure 5C The steps in the sequence of forming a static random access memory cell are shown according to some embodiments. After forming the via 20, subsequent lithography and etching are performed in the same insulating layer 22 with metal deposited therein. This subsequent lithography and etching creates a larger opening 26 in the insulating layer 22 that completely covers the opening formed for the via 20 in the previous step. In addition, the opening is large enough to extend from the via 20 to the contact 18. In some embodiments, as shown in FIG. Figure 5CAs shown, opening 26 in insulating layer 22 is extended to completely encompass the entire area of via 20 and includes the area of contact 18 formed in the previous step. This is large enough to extend between two or more vias and contacts. Next, the opening in insulator 22 is filled with metal material to form an enlarged via 24. Via 24 is considered an enlarged via because it is large enough to connect two adjacent vias, two adjacent contacts, or two adjacent vias and contacts. Enlarged via 24 completely surrounds at least two vias and / or contacts previously formed in the same layer or a previous layer.

[0075] like Figure 5B and Figure 5C As shown, via 24 extends to cover via 20 and contact 18, as well as the material between the two structures. Via 24 thus acts as an interconnect via to electrically connect two vias, or in some cases, to electrically connect a via to a contact.

[0076] The opening of the via 24 is formed in the same insulating layer 22 as the previously formed via, and thus can be considered a double-layer via, which also includes the area where the via was previously formed, and the area of the contact or via below the insulating layer 22.

[0077] like Figure 5C As shown, an opening 26 for via 24 is formed in layer 22 using an appropriate mask and etching chemistry for the particular material. For example, if insulating layer 22 is formed of a combination of silicon dioxide and silicon nitride, the photomask provides a pattern corresponding to the shape of via 24. A subsequent etch is then performed to completely remove the insulating material in layer 22 to form opening 26, exposing contact metal 18. Furthermore, an etching chemistry is used to etch away and remove the metal of via 20.

[0078] like Figure 5C As shown, a variety of different techniques can be used to form opening 26. Various embodiments are described herein, any of which are acceptable for forming opening 26 that exposes contact 18 and via 20 in preparation for depositing the metal for via 24. In some embodiments, the metal of contact 18 and via 20 are the same metal and are both etched with the same etch chemistry. In other embodiments, the metal of contact 18 and the metal of via 20 are different and have different etch rates for a given etchant, thereby allowing selective etching relative to one another. For example, the metal of contact 18 can be etched by an etchant that is not an effective etchant for via 20, or by an etchant that etches the metal of via 20 at a significantly different rate than the metal of contact 18. Alternatively, contact 18 can have an upper layer of a different material serving as an etch stop. Thus, different types of etch chemistries and etching steps can be performed, as described below with reference to different embodiments.

[0079] According to one embodiment, etching is performed using metal 18 as an etch stop indicator layer. This means that the etching process ends when metal 18 is exposed. This particular method is useful when the upper layer of contact 18 is made of a different material than via 20. After exposing the metal above contact 18, etching is then continued briefly to remove any debris, thin strips, or isolating insulators on metal 18. This removes all electrical insulators, allowing good electrical contact to be formed between via 24 and contact 18. After removing the electrically insulating material, the metal forming via 20 is then etched using an etching chemistry selected to remove the metal of via 20 without removing insulating material 22, 16, or the top layer of contact 18. For example, an etching chemistry that selectively removes tungsten but not silicon dioxide, silicon nitride, Ti, or TiN can be used to remove metal 20 until it is flush with the upper layer of electrically insulating layer 22.

[0080] According to one embodiment, Figure 3B After the illustrated structure is formed, a blanket sealing layer is deposited over insulator 16 and contacts 18. The blanket metal layer can be formed of titanium, titanium nitride, tantalum, molybdenum, or other materials that can seal material 18. In some embodiments, the deposited material acts as an etch stop for insulating layer 22. That is, the etching chemistry etches insulating layer 22 without etching the sealing layer. Therefore, in one embodiment, an additional sealing layer is applied over insulating material 16 and contacts 18.

[0081] According to an embodiment of the present invention, a sealing layer covering the insulating material 16 and the contacts 18 is deposited on Figure 3B The opening is etched through the insulating material 22 until it reaches the sealing layer, which acts as an etch stop layer and will not be etched by the same etching chemical that etches the insulating layer 22. Figure 5C As shown, the sealing layer 22 is etched using an etching chemistry, and since the sealing layer extends completely through the top surface of the insulating structure 16 and the contact 18, the etching of the insulating structure 16 and the contact 18 is prevented to achieve a substantially flat top surface. Figure 3B The structure shown provides the advantage that both the contacts 18 and the insulating structure 16 have substantially flat top surfaces when etching of the insulating layer 22 is performed. At this stage, the material of the via 20 is exposed on all sides, such as Figure 5C As shown, since the opening 26 is large enough, the metal of the via 20 remains in the middle of the opening as a pillar.

[0082] Figure 5C Shown between Figure 4B and Figure 5B In particular, Figure 5C As shown, an opening is etched in insulating layer 22 to expose the upper portion of contact 18. In one embodiment, as previously described, etching of opening 26 stops at an etch stop layer that covers conductive contact 18, such as a metal contact, and covers insulating layer 16. That is, etching continues through insulating layer 22, removing all material from opening 26, until the etch stop layer overlying insulating layer 16 is reached. Because the same etch chemistry that etches insulating layer 22 does not etch this layer, etching can continue until material 22 is completely removed from opening 26.

[0083] like Figure 5C As shown, the via 20 is fully exposed, as the opening 26 slightly extends toward the other side of the via metal 20 to ensure full contact with the entire area of the via 20. The extension beyond the via 20 can be small, but considering the tolerance and mask alignment, the small extension provided ensures that the entire structure of the via 20 is exposed for subsequent removal.

[0084] In one embodiment, after the opening 26 is formed, the metal for the via 24 is deposited. This metal is then combined with the remaining metal in the via 20 to form a single large via 24. Due to the combination with the via 24 outside the opening in the insulating layer 16, it is now shown as a single, solid sheet of metal. The metal deposited in the opening 26 will continue to overfill the hole, and then chemical mechanical polishing (CMP) is performed to planarize the hole. Figure 5B and Figure 6B The surface shown.

[0085] In another embodiment, Figure 5C After the structure is formed, the via 20 is etched to be level with the contact 18 and the upper surface of the insulating layer 16. This etching can be performed by several techniques. According to a first embodiment, the material used for the via 20 can be selectively etched relative to the material used for the etch stop layer on the insulating structure 16 and the contact 18. For example, the material of the via 20 can be tungsten, molybdenum, or other metal that is selectively etched relative to Ti or TiN. Therefore, in one embodiment, the contact 18 includes tungsten, the sealing layer includes Ti and / or TiN, and the via 20 includes a metal that is selectively etched relative to the sealing layer. Therefore, in this embodiment, the material 20 is etched until it is coplanar with the upper surface of the sealing layer on the insulator 16.

[0086] The layer 20 may also be slightly over-etched. Figure 5B As shown, the subsequently deposited via metal 24 material will completely fill the entire opening 26. Therefore, if the material 20 is slightly overetched so that its upper surface is slightly lower than the insulating material 16, it is acceptable because the via metal 24 material will completely fill any opening and make full electrical contact.

[0087] According to one embodiment, the material of the contact 18 and the via 20 is the same material, such as tungsten or other suitable materials. In one embodiment, an etch stop layer has been previously deposited to cover the contact 18. As mentioned above, this Figure 3B 18 . In this embodiment, an etch stop layer is used to cover the top surface of contact 18 , which cannot be etched by the same etchant used to etch layers 20 and 18 . The etch stop material can be, for example, Ti, TiN, Ta, or the like. As previously described, with the protective layer covering contact 18 , material 20 is etched in a timed manner until it is flush with the top surface of material 16 . Thereafter, an etch is performed to selectively remove the etch stop layer while leaving the materials of layers 20 and 18 untouched. For example, an etch is performed to selectively remove Ti or TiN while leaving tungsten untouched. This exposes the top surface of contact 18 for subsequent deposition of via 24 .

[0088] In yet another embodiment, the etch stop layer can be left in place and never etched. Ti and TiN are highly conductive materials, so if the via material 24 is composed of Ti or TiN, the via material 24 can be deposited directly on the etch stop layer, providing a good electrical connection to the contact 18 through the etch stop layer. In this embodiment, Ti or TiN is used as a blanket layer covering the entire bottom of the opening 26, providing a highly conductive surface for tungsten deposition. Since the goal is to achieve a low-resistance contact with the contact 18, extending the metal etch stop layer to the entire bottom surface of the opening 26, including the top surface of the insulating structure 16, provides additional electrical contact area and increases conductivity, thereby providing further benefits.

[0089] In some embodiments, when contacts 18 comprise tungsten, no etch stop layer is used on contacts 18, and thus the tungsten will be coplanar with the top surface of insulating structure 16. Even if a Ti or TiN liner is present on the bottom and sidewalls of insulating structure 16, if chemical mechanical polishing or other etching is performed, the exposed material of contacts 18 will be the topmost tungsten.

[0090] In some embodiments, it may be desirable to have the tungsten of vias 24 in direct mechanical and physical contact with the tungsten of contacts 18. In such an example, any capping layer on contacts 18 is removed so that the tungsten of vias 24 is deposited directly on the tungsten of contacts 18, thereby providing continuity of the same metal structure that is highly conductive and less likely to have voids or electrical discontinuities. Figure 5B The illustrated structure may be an embodiment in which via 24 directly overlies contact 18, with no intervening metal layer between the two. In this embodiment, via 24 is made of the same metal as contact 18 and via 20, such as tungsten. Thus, all tungsten materials are in mechanical, physical, and electrical contact with each other, providing a low-conductivity connection for via 24, coupling contact 18 to via 20.

[0091] In the embodiment where the material of the guide hole 20 and the material of the contact 18 are made of the same metal, such as tungsten, the subsequent steps are performed. Figure 5C After the etching shown, in one embodiment, the material of the via 20 is then etched sufficiently to remove Figure 5C The vertical material of via 20 is removed from the insulating material 16 shown in FIG, until the top of via 20 material is flush with insulating material 16. During etching in this embodiment, the top surface of contact 18 may also be etched away to a depth equal to the height of via 20 material. This may be, for example, 15% or 20% of the height of contact 18. In many examples, insulator 22 is approximately 15%, or in some examples, 20%, of the height of insulating material 16. Thus, the pillar of via 20 may be completely etched away, while also etching away approximately 20% of the upper portion of contact 18, leaving a recessed portion above contact 18 equal to the height of via 20 extending above material 16. After etching away the upper region of contact 18 to leave an upper surface flush with the top surface of insulating structure 16, etching is stopped. This may be done using a timed etch or other acceptable technique. Via 24 is then deposited in opening 26. During deposition, any removed portion of contact 18 will be completely filled while filling opening 26. In one embodiment, the material of the vias 24 is tungsten, which when completely filling the openings 26 will also fill any recesses, pockets, or overetches that occur in the contacts 18 and vias 20. After the tungsten completely fills the openings 26 and any recesses in the contacts 18 and vias 20 that may have been created during etching, it will extend above the top surface of layer 22. At this stage, etch back is performed to remove excess material from the outer layer 24 of the vias. This can be a planarization etch performed on the combination of the insulating layer 22 and the vias 24 to planarize their surfaces. Chemical mechanical polishing etching can provide a complete planarization etch of the semiconductor structure at this stage to remove all of the via material 24 outside of the openings 26 to obtain a structure such as Figure 5B The planarized upper surface is shown. Different embodiments of different processes can be performed to Figure 4B The structure of Figure 5B Any of the various embodiments described above may be used, or different process steps may be used to complete the via 24 extending to cover both the contact 18 and the via 20, as shown. Figure 5B As shown, they are electrically connected to each other.

[0092] Figure 6A The insulating layer 28 is shown, covering the insulator 22 and the guide hole 24. Figure 6A 、 Figure 6C and Figure 6DAs shown, a metal layer 30 is disposed within or on insulator 28. Metal 30 serves as an interconnect wiring layer, electrically connecting different portions of the circuit to different signal levels, voltage sources such as ground and power, and providing interconnections between other circuits. Therefore, metal layer 30 serves as a wiring connection layer, distinct from the via structures used in Figures 24 and 20.

[0093] In some embodiments, metal wiring layer 30 is made of a very low-resistivity metal such as aluminum or, in some embodiments, copper. Because Al and Cu have lower resistivities than tungsten and titanium, the use of Al and Cu in wiring layer 30 provides low-resistance connections between circuit components and provides signals and power to different portions of the static random access memory circuit. Wiring layer 30 extends over a considerable length, from portions of a microprocessor formed on the same die to many different portions of the overall circuit. Therefore, the use of low-resistance materials such as Al or Cu is beneficial.

[0094] Figure 6C For the Figure 6A The cross-section is taken along line 6C-6C. It can be seen that this cross-section passes through two active regions 12, two contacts 18, and metal wiring 30. Figure 6C In the first embodiment shown, a metal wiring layer is deposited on the insulating layer 22 and then patterned and etched to obtain a metal wiring layer as shown in FIG. Figure 6C The strip metal 30 is shown. After this, an insulating layer 28 is deposited on top of the metal wiring layer 30. The insulating layer 28 is etched to be planar with the top surface of the wiring layer 30. This can be done by chemical mechanical polishing etching to flatten the entire structure, or by any other acceptable etching method to obtain a planar structure. Figure 6C The structure shown in Figure 6C In another approach to the structure shown, an insulating layer 28 is first deposited, and then a recess is etched in the insulating layer 28. After etching the recess, metal 30 is deposited in the recess to provide embedded wiring 30 in the layer. The wiring layer 30 extends to other circuits and voltage sources in the semiconductor chip as described above.

[0095] As can be seen, the metal 30 and vias 24 are sufficiently spaced apart to ensure that there is no electrical short or contact between the metal 30 and any of the vias 24. Furthermore, because they are on different planes, there is little or no capacitive coupling between the metal 30 and the vias 24. This avoids potential high capacitance issues and the possibility of shorts or stray connections.

[0096] Figure 6DAnother embodiment is shown in which a metal layer 30 is deposited over the insulating layer 28. In particular, in this alternative embodiment, rather than etching a recess into the insulator 28, the metal 30 covers the top of the insulator 28, placing it further away from the via material 24.

[0097] exist Figure 6D In the embodiment, further protection is provided to ensure that the metal 30 cannot short-circuit with any via 24 and also has less capacitive coupling with the via 24. Figure 6D In the embodiment of the present invention, the insulating layer 28 is deposited to cover the Figure 5B The structure shown. After this, metal 30 is deposited over the insulating layer 28. In some parts of the circuit, such as where the microprocessor is formed, openings may be provided in the insulating layer 28 to provide electrical contact between adjacent vertical layers. Thus, the wiring layer 30 is in electrical contact with the underlying conductive layer at some locations in the microprocessor structure. However, in Figure 6D In the embodiment of Figure 6A At certain locations in the cross-sectional view shown, no openings are etched into the insulating layer 28 covering the vias 24. Figure 6A Vd shown, and Figure 7 At these locations of Vdd shown, it is desired that metal 30 contacts the underlying conductor, etch Figure 6C The type of opening shown is formed so that the metal 30 is positioned to contact the metal in the insulating layer 22 located directly below it. Figure 6C or Figure 6D Any embodiment.

[0098] when Figure 6C or Figure 6D After the structure is formed, additional layers are formed to cover the insulating layer 20 and the metal layer 30, including several layers of electrical insulation and wiring layers, and appropriate vias to connect the wiring layers to each other.

[0099] In particular, when other circuits of a microprocessor are constructed on the same semiconductor die, various insulating layers and wiring layers above them are repeatedly formed. Many microprocessors include 7 to 13 metal layers. 6A to 6D The structure shown is then continued with several additional steps to deposit insulating layers and metal layers therebetween.

[0100] This process has significant benefits when forming a microprocessor along with other portions of the same semiconductor chip. In particular, the microprocessor is formed with process steps that result in the formation of a plurality of contacts identical to contacts 18, vias identical to vias 20, and vias corresponding to vias 24. Thus, in the same process steps that form the various insulating materials 16 and 22 in the microprocessor portion of the chip to connect the logic circuits, these layers are formed and etched in the SRAM cells. Similarly, when forming corresponding contacts and vias in the microprocessor portion, the same process steps are performed to form contacts 18 in each SRAM cell. When forming corresponding vias 20 in the microprocessor portion, lithography, etching, and deposition are performed in the SRAM cells to form vias 20. Similarly, forming corresponding vias 24 in the microprocessor portion of the semiconductor chip simultaneously and in the same process steps can be as shown. Figures 5A to 5C As shown, a via 24 is formed in the SRAM cell, extending from the contact 18 to the via 20. Thus, the process steps for forming the SRAM cell are performed simultaneously with the same process steps for forming transistors in the microprocessor portion of the same semiconductor chip, and no additional specific steps are required for the SRAM cell.

[0101] Figure 7 A layout diagram of the various nodes forming the circuitry of a 6-transistor SRAM cell 10 is shown. The top metal line 30 is not shown so that the various nodes can be more easily seen. It will be understood that in the final SRAM cell, the metal line 30, along with other overlying insulating and metal layers, is present to provide electrical connections between the various nodes.

[0102] like Figure 7 As shown, the SRAM cell 10 includes two storage nodes Q1 and Q2. The electrical properties of these two storage nodes are as follows: Figures 3A to 6B The electrical part of the contact 18 shown. In particular, Figure 7 As shown, metal contact 18 electrically connects the drain of transistor P1 to the drain of transistor N1. Since transistors N1 and N3 are both N-channel transistors, they can share a common active region. Contact 18 is connected to this common active region. This is the source of transistor N1, and can be the source or drain of transistor N3, depending on whether data is to be written from the bit line to the data storage node Q1, or read from the data storage node Q1 to the bit line, and the value of the data. It is well known that the definition of a particular terminal of a MOS transistor as a source or drain can change depending on the relative voltages between the two terminals and the operation of the MOS transistor. As shown in FIG. Figure 7 As shown in FIG. 1 , a node Q2 of the transistors N2 and N4 is provided, which also has a contact 18 electrically connecting the common active region of the transistors N2 and N4 to the drain of the transistor P2. Figure 1AAs shown. Each node Vg1 and Vg2 is also Figure 7 As shown in Figure 1A The connections outside the memory cell are labeled, but the wires connecting them are not shown to avoid obscuring the structure of the cell itself. In particular, the electrical connections Vss and Vdd are labeled, as are the connections to the bit line, bit line inversion, and word line.

[0103] 8A to 10B Another embodiment of forming the enlarged guide hole 42 is shown and will be described later.

[0104] Figure 8A FIG. 1 is a top view illustrating the layout of steps for fabricating a static random access memory cell according to another embodiment. Figure 8B For the Figure 8A Cross-sectional view taken along line 8B-8B.

[0105] When the structure is Figure 3B In the state shown, the insulating layer 22 is deposited. After this, holes 44 are etched to form vias later. Holes 44 may also be referred to as recesses, blind holes, openings, or other names indicating a path through layer 22 to gate 14. Figure 8A and Figure 8B As shown, the hole 44 is etched through to reach the gate 14, leaving an open opening, also indicated at Figure 8A In the example of FIG. , two or three different etch chemistries are required due to the different layers, but this can be accomplished in a single patterning and masking step.

[0106] After this, proceed as follows Figure 9A and Figure 9B The second etch is shown. Figure 9B As shown, a second etch is performed using another pattern and mask combination to create an opening over contact 18. Etching is performed to create hole 46. Hole 46 may also be referred to as a recess, blind via, opening, or other terminology indicating a path through layer 22 to gate 14. It can be seen that hole 46 includes the previous hole 44 therein. However, the etching chemistry does not etch insulator 16. In one embodiment, an etch stop layer, such as Ti, TiN, or other suitable etch stop layer, covers insulator 16, and the etch may stop on this layer to create hole 46 as shown.

[0107] In another embodiment, it is also possible to perform a single step of forming hole 46 without patterning, masking, and etching to form hole 44. Since hole 46 includes all of hole 44, it is possible to save a series of patterning, masking, and etching steps and only etch hole 46 without etching hole 44 at all. In another embodiment, the etching chemistry is selected to etch the entire layer covering gate 14. As a result, the insulator 16 between contact 18 and gate 14 is partially etched, and the structure is similar to Figure 9B In some embodiments, it is acceptable to remove the insulator between contact 18 and gate 14 because the purpose of via metal 42 is to provide a low resistance electrical connection between the two structures, and removing the additional insulator will provide a larger contact area between them and via metal 42.

[0108] Figure 10A The top view of the layout after etching hole 46. Metal is deposited to fill holes 44 and 46 simultaneously to form metal via 42. In this embodiment, a single series of metal deposition steps is used instead of a single series of steps. Figures 4A to 5C In this embodiment, only a single metal deposition process is performed, and the same metal is a single integrated continuous metal component from the contact 18 to the gate 14. Figure 10B This will provide a lower resistance between them as shown.

[0109] As can be seen, a compact static random access memory cell is fabricated, where components can be placed very close together, providing a smaller memory cell area than previously possible. Rather than using metal wiring layers to electrically connect contacts to the gates of other transistors, vias are formed to electrically connect the contacts of a transistor's storage node to the common gates of other transistors for other storage nodes. Using enlarged vias that overlap the previous vias and extend to the contacts significantly reduces the space required to form electrical connections in the memory cell. This allows for even more compact memory cells than previously possible.

[0110] exist Figure 7 In the figure, the corresponding Figure 6B In particular, it can be seen that Figure 7 A via 24 extends from contact 18 of Q1 to gate 14, including node Vg1, which is part of the common gate of transistors P2 and N2. Similarly, another via 24 electrically connects node Q2 of contact 18 to Vg2, the common gate connection of another pair of transistors P1 and N1. Thus, the use of enlarged vias 24 avoids the need for metal wiring layers to electrically connect the various internal nodes of the transistors of the 6-transistor SRAM cell, allowing for a more compact cell, resulting in a smaller cell area and a smaller footprint.

[0111] Various embodiments of the present invention provide a compact 6-transistor static random access memory cell with an interconnected structure, providing a small footprint for the static random access memory cell. In the compact static random access memory cell, a common gate of a first pair of transistors is electrically coupled to the drain of a second pair of transistors. The common gate of the second pair of transistors is electrically coupled to the drain of the first pair of transistors, thereby cross-coupling the two pairs of transistors. Metal vias are enlarged to extend from the drains of the transistors to the common gates of the first pair of transistors to provide electrical coupling, thereby achieving a more compact memory cell than previously possible. Using metal vias extending from the drain of one transistor to the common gates of both transistors significantly saves space, mask layers, and process steps. This avoids the need for one or more metal wiring layers for cross-coupling connections, not only making the cell more compact but also reducing stray capacitance that may occur when one or more metal wiring layers simultaneously provide cross-coupling connections for one or more voltage source connections for the memory cell.

[0112] This SRAM cell layout demonstrates that removing two strips of metal wiring from the memory cell allows the cell to be more compact. There are practical limits on how close metal wiring strips can be to adjacent strips; if they are too close, they can short to each other, and capacitance increases as strips get closer together. By using vias in different insulating layers, rather than using metal wiring layers, the elements of the cell can be closer together, avoiding the possibility of shorts or capacitive cross-coupling.

[0113] According to one embodiment, an integrated circuit comprises a substrate and a semiconductor active region covering the substrate. A first gate covers a first channel region in the active region. A first transistor is formed, comprising a first channel region, a first source region adjacent to a first side of the first channel region in the active region, a first drain region adjacent to a second side of the first channel region, and a first gate. A conductive contact is directly connected to the first drain region of the first transistor and a second gate is spaced apart from the first gate. A second gate covers the second channel region. A second transistor is formed in the circuit, comprising a second channel region, a second source region adjacent to a first side of the second channel region in the active region, a second drain region adjacent to a second side of the second channel region, and a second gate. A conductive via is directly connected to the second gate. Furthermore, an enlarged conductive via is formed, covering the conductive contact and the conductive via, electrically connecting them to each other, with the enlarged conductive via extending in a plane from the conductive contact to the conductive via. A first electrically insulating layer surrounds the enlarged conductive via.

[0114] In one embodiment, the insulating structure covers the semiconductor active region and surrounds the first gate and the second gate. The conductive contact is located between the first gate and the second gate. In another embodiment, the conductive contact surrounds the insulating structure.

[0115] In one embodiment, a static random access memory cell is formed having a third transistor and a fourth transistor, wherein the first gate covers the third channel region of the third transistor, the second gate covers the fourth channel region of the fourth transistor, and the drain of the third transistor is electrically coupled to the first gate to form a pair of cross-coupled inverters, thereby forming a static random access memory cell. In other embodiments, the access connection of the pair of transistors is connected to the data storage node, providing a complete 6-transistor static random access memory cell.

[0116] In one embodiment, the second electrically insulating layer covers the enlarged conductive via and the first electrically insulating layer. The conductive wiring layer covers the first electrically insulating layer. The conductive wiring layer is disposed apart from the enlarged conductive via in contact with the first electrically insulating layer and is surrounded by the second electrically insulating layer. The conductive wiring layer is disposed on the second electrically insulating layer.

[0117] In another embodiment, an integrated circuit structure includes a semiconductor active region. A gate overlies a channel region in the active region of a transistor, the transistor including the channel region and a first terminal adjacent to a first side of the channel in the active region. A conductive contact is electrically coupled to the first terminal of a first transistor. A conductive member is spaced apart from the first gate. A conductive via is electrically coupled to the conductive member and overlies the conductive contact, the conductive via electrically coupling the conductive contact to the gate to provide electrical coupling from the first terminal of the transistor to the conductive member. The first conductive via is electrically coupled to the conductive member. A second conductive via is provided overlying the conductive contact and the first conductive via, the second conductive via electrically coupling the conductive contact to the first conductive via to provide electrical coupling from the first terminal of the transistor to the conductive member.

[0118] In one embodiment, the connection is used to provide a compact structure to connect the common gate of a pair of transistors to the drain of another transistor. In this embodiment, the first terminal is the drain of the transistor.

[0119] In one embodiment, the gate has a first height that covers the active region, and the conductive contact has a second height that covers the active region, the second height being greater than the first height. The second conductive member serves as the second gate of the second transistor. This allows a second conductive via to extend from the conductive contact to the first conductive via, thereby covering the conductive contact, the first conductive via, and the second gate. This structure can also be used in fin field-effect transistors and other structures.

[0120] This structure can be formed using the following method steps. A semiconductor active region is formed, followed by forming a gate covering the active region. An insulating structure is formed over the active region and the gate. An opening is etched in a region spaced apart from the insulating structure and the gate, the opening exposing an area of the active region spaced apart from the gate. A first conductive material is deposited in the opening to provide electrical connection to the active region. A first insulating layer is deposited over the insulating structure and the first conductive material, and an opening is then etched in the first insulating layer, the opening spaced apart from the first conductive material, and the opening exposes the conductive structure spaced apart from the first conductive material. A second conductive material is then deposited in the opening, electrically coupled to the conductive structure, and a second insulating material is deposited over the first insulating layer, the first conductive material, and the second conductive material. An opening is then etched in the second insulating layer, the opening extending from the first conductive material to the second conductive material, and a third conductive material is deposited in the opening, the opening extending from the first conductive material to the second conductive material, electrically coupling the active region in the region spaced apart from the gate to the conductive structure.

[0121] In one embodiment, the fabricated structure comprises a first gate electrode of a first transistor, an active region covering a first channel region of the first transistor, and a first conductive structure electrically connected to the drain electrode of the first transistor. The conductive structure comprises a second gate electrode covering a second active region of a second transistor, and a third conductive material electrically connecting the drain electrode of the first transistor to the second gate electrode of the second transistor.

[0122] In one embodiment, each of the first, second, and third conductive materials includes tungsten.

[0123] In one embodiment, the method further includes depositing a sealing layer on the first insulating layer before depositing the second insulating layer, wherein the sealing layer serves as an etch stopper for etching the second insulating layer.

[0124] The above content summarizes the features of many embodiments, so that any person skilled in the art can better understand the various aspects of the embodiments of the present invention. Any person skilled in the art may have no difficulty in designing or modifying other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or obtain the same advantages as the embodiments of the present invention. Any person skilled in the art should also understand that various changes, substitutions and modifications can be made without departing from the concept and scope of the embodiments of the present invention, and the creation of such effects does not exceed the concept and scope of the embodiments of the present invention.

Claims

1. An integrated circuit structure comprising: a substrate; a semiconductor active region covering the substrate; a first gate covering a first channel region in the semiconductor active region; a first transistor comprising the first channel region, a first source region adjacent to a first side of the first channel region in the semiconductor active region, a first drain region adjacent to a second side of the first channel region, and the first gate; a conductive contact directly connected to the first drain region of the first transistor; a second gate, spaced apart from the first gate, the second gate covering a second channel region, and the second gate covering a sidewall of the first drain region of the first transistor; a second transistor comprising the second channel region, a second source region adjacent to a first side of the second channel region in the semiconductor active region, a second drain region adjacent to a second side of the second channel region, and the second gate; a first conductive via directly connected to the second grid; an enlarged conductive via, covering the conductive contact and the first conductive via to electrically connect them to each other, the enlarged conductive via extending from the conductive contact to the first conductive via in a plane; and A first electrical insulating layer surrounds the enlarged conductive via.

2. The integrated circuit structure of claim 1 , further comprising: An insulating structure covers the semiconductor active region and is located around the first gate and the second gate. 3 . The integrated circuit structure of claim 2 , wherein the conductive contact is located between the first gate and the second gate. The integrated circuit structure as claimed in claim 2 , wherein the conductive contact is surrounded by the insulating structure.

5. The integrated circuit structure of claim 1 , further comprising: A third transistor and a fourth transistor, wherein the first gate covers a third channel region of the third transistor, the second gate covers a fourth channel region of the fourth transistor, and a drain of the fourth transistor is electrically coupled to the first gate to form a pair of cross-coupled inverters, providing a static random access memory (SRAM) cell.

6. The integrated circuit structure of claim 1 , further comprising: A second electrical insulating layer covers the enlarged conductive via and the first electrical insulating layer.

7. The integrated circuit structure of claim 6 , further comprising: A conductive wiring layer covers the first electrical insulation layer. 8 . The integrated circuit structure as claimed in claim 7 , wherein the conductive wiring layer is located apart from the enlarged conductive via in contact with the first electrically insulating layer and is surrounded by the second electrically insulating layer. 9 . The integrated circuit structure as claimed in claim 7 , wherein the conductive wiring layer is located and covers the second electrically insulating layer.

10. An integrated circuit structure comprising: a semiconductor active region; a first gate covering a first channel region in the semiconductor active region; a first transistor comprising the first channel region and a first drain region adjacent to a first side of the first channel region in the semiconductor active region; a conductive contact electrically coupled to the first drain region of the first transistor; a second gate, spaced apart from the first gate, the second gate covering a sidewall of the first drain region of the first transistor, and the second gate covering a second channel region; a conductive member, spaced apart from the first gate, covering the second gate, and electrically coupled to the second gate; A conductive via is electrically coupled to the conductive component and is located above the conductive contact. The conductive via is electrically coupled to the conductive contact of the first transistor to provide electrical coupling from the first drain region of the first transistor to the conductive component. 11 . The integrated circuit structure according to claim 10 , wherein the first gate has a first height covering the semiconductor active region, and the conductive contact has a second height covering the semiconductor active region, and the second height is greater than the first height. 12 . The integrated circuit structure of claim 10 , wherein the conductive component is a second gate terminal of a second transistor. 13 . The integrated circuit structure of claim 12 , wherein the conductive via extends from the conductive contact to the conductive member to cover the conductive contact and the second gate.

14. The integrated circuit structure of claim 10, wherein the first transistor is a fin field effect transistor.

15. An integrated circuit structure comprising: a first transistor comprising a first channel region, a first gate covering the first channel region, a first source region, and a first drain region; a conductive contact directly connected to the first drain region of the first transistor, the conductive contact having an upper surface and made of a first material; a second transistor comprising a second channel region, a second gate covering the second channel region, a second source region, and a second drain region, wherein the second gate covers a sidewall of the first drain region; a first conductive via directly connected to the second gate, the first conductive via covering the second gate, the first conductive via having an upper surface made of a second material different from the first material; an enlarged conductive via covering the conductive contact and the first conductive via and electrically connecting the conductive contact to the first conductive via, the enlarged conductive via having a lower surface extending from the conductive contact to the first conductive via, wherein the upper surfaces of the first conductive via and the conductive contact are coplanar with the lower surface of the enlarged conductive via.

16. The integrated circuit structure of claim 15 , further comprising: A substrate includes an active region covering the substrate, wherein the first channel region and the second channel region are in the active region.

17. The integrated circuit structure of claim 15, further comprising: A first electrical insulating layer surrounds the enlarged conductive via. 18 . The integrated circuit structure of claim 15 , wherein the conductive contact is located between the first gate and the second gate.

19. The integrated circuit structure of claim 15, further comprising: A static random access memory cell includes a pair of cross-coupled inverters, including a third transistor and a fourth transistor, wherein the first gate covers a third channel region of the third transistor, the second gate covers a fourth channel region of the fourth transistor, and wherein a drain of the fourth transistor is electrically coupled to the first gate.

20. A method of forming an integrated circuit structure, comprising: forming a first semiconductor active region and a second semiconductor active region; forming a first gate covering a first channel region of the first semiconductor active region; forming a second gate covering a sidewall of a first drain region of the first semiconductor active region, the second gate covering a second channel region of the second semiconductor active region; forming an insulating structure on the first semiconductor active region and the first gate; Etching a first opening in the insulating structure separated from the first gate, the opening exposing a region of the first semiconductor active region separated from the first gate; depositing a first conductive material in the first opening to provide an electrical connection to the first drain region; depositing a first insulating layer on the insulating structure and the first conductive material; Etching a second opening in the first insulating layer, wherein the second opening is separated from the first conductive material and the opening exposes the second gate separated from the first conductive material; Depositing a second conductive material in the second opening so that the second conductive material covers and is electrically coupled to the second gate; Depositing a second insulating layer, the second insulating layer being located on the first insulating layer, the first conductive material, and the second conductive material; Etching a third opening in the second insulating layer, the third opening extending from the first conductive material to the second conductive material; A third conductive material is deposited in the third opening extending from the first conductive material to the second conductive material to electrically couple the first semiconductor active region in a region separated from the first gate to the second gate. 21 . The method for forming an integrated circuit structure according to claim 20 , wherein the first gate is a gate of a first transistor, the first transistor includes the first channel region, and the first conductive material is electrically connected to a drain of the first transistor. 22 . The method for forming an integrated circuit structure according to claim 21 , wherein the second gate is a gate of a second transistor, and the third conductive material electrically connects the drain of the first transistor to the second gate of the second transistor.

23. The method of forming an integrated circuit structure according to claim 20, wherein each of the first conductive material, the second conductive material, and the third conductive material comprises tungsten.

24. The method of forming an integrated circuit structure according to claim 20, further comprising: Before depositing the second insulating layer, a sealing layer is deposited on the first insulating layer. The sealing layer serves as an etching stopper for etching the second insulating layer.

25. An integrated circuit structure comprising: a substrate; a semiconductor active region covering the substrate; a first gate covering a first channel region in the semiconductor active region; a first transistor comprising the first channel region, a first source region adjacent to a first side of the first channel region in the semiconductor active region, a first drain region adjacent to a second side of the first channel region, and the first gate; a conductive contact directly connected to the first drain region of the first transistor, the conductive contact being made of a first conductive material; a second gate, spaced apart from the first gate, the second gate covering a sidewall of the first drain region of the first transistor; a first conductive via, covering and directly connected to the second gate, the first conductive via being made of a second conductive material; an enlarged conductive via covering the conductive contact and the first conductive via to electrically connect them to each other, the enlarged conductive via extending in a plane from the first conductive contact to the conductive via; and A first electrical insulating layer surrounds the enlarged conductive via. 26 . The integrated circuit structure of claim 25 , wherein the conductive contact and the first conductive via each have an upper surface coplanar with the plane.

27. The integrated circuit structure of claim 25, wherein the first conductive material and the second conductive material are different.

28. The integrated circuit structure of claim 25, further comprising: An insulating structure surrounds the conductive contact.

29. The integrated circuit structure of claim 28, wherein the insulating structure is formed of a first dielectric material, and the first electrically insulating layer is formed of a second dielectric material different from the first dielectric material.

30. The integrated circuit structure of claim 25, further comprising: A second electrical insulating layer covers the enlarged conductive via and the first electrical insulating layer.

31. The integrated circuit structure of claim 30, further comprising: A conductive wiring layer covers the first electrical insulation layer.

32. The integrated circuit structure of claim 31, wherein the conductive wiring layer is located apart from the enlarged conductive via in contact with the first electrically insulating layer and is surrounded by the second electrically insulating layer.

33. The integrated circuit structure as claimed in claim 31, wherein the conductive wiring layer is located and covers the second electrically insulating layer.

34. An integrated circuit device comprising: a first semiconductor active region; a first gate covering a first channel region of the first semiconductor active region; a second gate, spaced apart from the first gate, the second gate covering a sidewall of a first drain region of the first semiconductor active region; a conductive contact electrically coupled to the first drain region; a first conductive via, covering and directly connected to the second gate; an enlarged conductive via covering the conductive contact and the first conductive via to electrically connect them to each other, the enlarged conductive via extending in a plane from the conductive contact to the first conductive via; and A first electrical insulating layer surrounds the enlarged conductive via.

35. The integrated circuit device of claim 34, further comprising: An electrical insulating layer surrounds the conductive contact.

36. The integrated circuit device of claim 34, further comprising: a second semiconductor active region; A first transistor includes a first channel region, a first source region adjacent to a first side of the first channel region in the second semiconductor active region, a first drain region adjacent to a second side of the first channel region, and the first gate.

37. The integrated circuit device of claim 36, further comprising: The second gate covers a second channel region of the second semiconductor active region; A second transistor includes the second channel region, a second source region adjacent to a first side of the second channel region in the second semiconductor active region, a second drain region adjacent to a second side of the second channel region, and the second gate.

38. The integrated circuit device of claim 37, further comprising: A third transistor and a fourth transistor, wherein the second gate covers a third channel region of the third transistor, and the first gate covers a fourth channel region of the fourth transistor, and wherein a drain of the third transistor is electrically coupled to the second gate, and a drain of the fourth transistor is electrically connected to a fourth gate, to form a pair of cross-coupled inverters, providing a static random access memory cell.

39. An integrated circuit device comprising: a first semiconductor active region; a first gate covering the first semiconductor active region; a second gate, spaced apart from the first gate, the second gate covering a sidewall of a first drain region of the first semiconductor active region; a conductive contact directly connected to the first drain region, the conductive contact being formed of a first conductive material; an enlarged conductive via, covering the conductive contact and the second gate and directly contacting the second gate, electrically coupling the first drain region to the second gate, the enlarged conductive via being formed of a second conductive material; and A first electrical insulating layer surrounds the enlarged conductive via.

40. The integrated circuit device of claim 39, further comprising: An insulating structure surrounds the conductive contact.

41. The integrated circuit device of claim 39, wherein the first conductive material is different from the second conductive material.

42. The integrated circuit device of claim 39, wherein each of the first conductive material and the second conductive material comprises tungsten.

43. The integrated circuit device of claim 40, further comprising: An etching stop layer is located between the insulating structure and the first electrical insulating layer. The etching stop layer has an opening and is located above the first gate.

44. A method of forming an integrated circuit structure, comprising: forming a first semiconductor active region and a second semiconductor active region; forming a first gate covering the first semiconductor active region; forming a second gate spaced apart from the first gate, the second gate covering a sidewall of a first drain region of the first semiconductor active region, and the second gate covering a second channel region of the second semiconductor active region; forming an insulating structure on the first semiconductor active region and the first gate; Etching a first opening in the insulating structure separated from the first gate, the first opening exposing the first semiconductor active region in a region separated from the first gate; depositing a first conductive material in the first opening to provide an electrical connection to the first drain region; depositing a first insulating layer on the insulating structure and the first conductive material; Etching a second opening in the first insulating layer and the insulating structure, wherein the second opening is separated from the first conductive material and the opening exposes the second gate separated from the first conductive material; Depositing a second conductive material in the second opening so that the second conductive material covers and is electrically coupled to the second gate; Etching a third opening in the first insulating layer, the third opening extending from the first conductive material to the second conductive material; as well as A third conductive material is deposited in the third opening extending from the first conductive material to the second conductive material to electrically couple the first semiconductor active region in a region separated from the first gate to the second gate. 45 . The method for forming an integrated circuit structure according to claim 44 , wherein the first gate is a gate of a first transistor, and the active region covered by the first gate is a first channel region of the first transistor.

46. The method of forming an integrated circuit structure of claim 44, wherein each of the first conductive material, the second conductive material, and the third conductive material comprises tungsten.

47. The method of forming an integrated circuit structure according to claim 44, further comprising: Before depositing the first insulating layer, a sealing layer is deposited on the insulating structure. The sealing layer serves as an etching stopper for etching the first insulating layer.

48. The method of forming an integrated circuit structure according to claim 44, further comprising: An upper surface of the first conductive material and an upper surface of the second conductive material are planarized.

49. The method of forming an integrated circuit structure of claim 44, wherein the second conductive material is different from the first conductive material.

50. A method of forming an integrated circuit structure, comprising: forming a first semiconductor first active region and a second semiconductor active region; forming a first gate covering a first channel region of the first semiconductor active region; forming a second gate covering a sidewall of a first drain region of the first semiconductor active region, the second gate covering a second channel region of the second semiconductor active region; forming an insulating structure on the first drain region and the first gate; Etching a first opening in the insulating structure spaced apart from the first gate, the first opening exposing the first drain region in a region spaced apart from the first gate; depositing a first conductive material in the first opening to provide an electrical connection to the first drain region; depositing a first insulating layer on the insulating structure and the first conductive material; Etching a second opening in the first insulating layer, wherein the second opening is separated from the first conductive material and the second opening exposes the second gate separated from the first conductive material; Depositing a second conductive material in the second opening so that the second conductive material covers and is electrically coupled to the second gate; Etching a third opening in the first insulating layer, the third opening extending from the first conductive material to the second conductive material; as well as A third conductive material is deposited in the third opening extending from the first conductive material to the second conductive material to electrically couple the first drain region in a region spaced apart from the first gate to the second gate.

51. The method for forming an integrated circuit structure according to claim 50, wherein the step of forming the insulating structure comprises: Form multiple layers.

52. The method of forming an integrated circuit structure according to claim 50, further comprising: An upper surface of the first conductive material and an upper surface of the second conductive material are planarized.

53. The method of forming an integrated circuit structure of claim 50, wherein the second conductive material is different from the first conductive material.

54. A method of forming an integrated circuit structure, comprising: forming a first semiconductor active region and a second semiconductor active region; forming a first gate covering a first channel region of the first semiconductor active region; forming a second gate covering a sidewall of a first drain region of the first semiconductor active region, the second gate covering a second channel region of the second semiconductor active region; forming an insulating structure on the first semiconductor active region and the first gate; Etching a first opening in the insulating structure separated from the first gate, the first opening exposing the first semiconductor active region in a region separated from the first gate; depositing a first conductive material in the first opening to provide an electrical connection to the first drain region; depositing an insulating layer on the insulating structure and the first conductive material; Etching a second opening in the insulating structure and the insulating layer, the second opening extending from the first conductive material to the second gate and exposing the first conductive material and the second gate; and A second conductive material is deposited in the second opening. The second conductive material extends from the first conductive material to the second gate, covers the second gate, and electrically couples the first drain region in a region separated from the first gate to the second gate.

55. The method of forming an integrated circuit structure of claim 54, wherein each of the first conductive material and the second conductive material comprises tungsten.

56. The method of forming an integrated circuit structure according to claim 54, further comprising: Before depositing the insulating layer, a sealing layer is deposited to cover the insulating structure. The sealing layer serves as an etching stopper for etching the insulating layer.

57. The method for forming an integrated circuit structure according to claim 56, wherein the step of etching the insulating structure and a second opening in the insulating layer comprises: Etching a gate opening through the insulating structure and the insulating layer to expose the second gate; as well as A recess opening is etched through the insulating layer, extending from the gate opening to the first conductive material, exposing the first conductive material.

58. The method of forming an integrated circuit structure of claim 54, wherein the second conductive material is different from the first conductive material.

59. The method of forming an integrated circuit structure as claimed in claim 54, wherein etching a second opening in the insulating structure and the insulating layer is performed in a single step.

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