Antenna tuning control using general purpose input / output data

Abstract

The present application relates to antenna tuning control using universal input / output data. A digital-to-analog converter (DAC) and a method for operating the DAC are disclosed. The DAC receives a control signal sent according to a binary protocol through a first channel. The DAC also receives data sent according to a multi-level communication protocol different from the binary protocol through a second channel different from the first channel. The DAC determines a plurality of first voltages and a second voltage based on the received data, and identifies a time to switch data transmission or reception between a first antenna and a second antenna based on the control signal. In response to identifying a switching time for data transmission or reception based on the control signal, the DAC outputs the determined plurality of first voltages to a first antenna tuning circuit, or outputs the determined plurality of second voltages to a second antenna tuning circuit.

Description

Technical Field

[0001] The present disclosure relates to a digital-to-analog converter that receives a general purpose input / output (GPIO) signal and uses the received GPIO signal to provide an output voltage for driving an antenna, and in particular to a digital-to-analog converter that receives the GPIO signal in addition to higher-level multi-level modulation protocol data that sets an output voltage level. Background Art

[0002] Digital-to-analog converters are ubiquitous in modern electronic devices. In principle, a digital-to-analog converter receives digital data and outputs an analog voltage based on the received digital data. Modern electronic devices such as handheld devices including smartphones and tablets utilize complex communication protocols to provide interfaces between their components. Examples of such protocols include the Mobile Industry Processor Interface (MIPI) protocol, which is a high-level complex communication protocol for communication between components such as a camera and its corresponding controller or a modem and its corresponding controller.

[0003] However, changes to MIPI protocol signaling in electronic devices are often limited. For example, access to the controller's firmware may be limited, making reconfiguration of MIPI protocol signaling impossible. This adversely affects the interoperability between electronic device components. Therefore, it is desirable to avoid communication protocol limitations and improve the interoperability of device components. Summary of the invention

[0004] A method and a digital-to-analog converter are provided herein that utilize a first protocol, which is a lower-level signaling protocol, such as binary protocol signaling or general purpose input / output (GPIO) protocol signaling, to supplement a second protocol, which is a high-level signaling protocol. In electronic devices such as smartphones and tablets, various components interoperate and communicate with each other, and advanced communication protocols have been developed and used for communication between components. However, due to the existence of proprietary platforms, the reconfiguration of components is sometimes blocked. This results in some component manufacturers being unable to modify the signaling information received by the corresponding components. For example, a controller can be blocked by a manufacturer so that a user or a third party cannot edit or change the operation of the controller. The controller cannot be reconfigured to change the time (by advance or delay) when switching information is signaled to the digital-to-analog converter.

[0005] A method and a digital-to-analog converter are provided herein that receive a first protocol signal and use the first protocol signal to supplement the untimely or insufficient information received by the second protocol signal. The digital-to-analog converter then provides an output voltage based on the timing information collected from the first protocol signal, rather than based on the information received by the second protocol signal, and the second protocol signal is a high-level protocol signal. The first protocol may be a binary protocol, such as a general purpose input / output (GPIO) protocol, and the second protocol may be a high-level communication protocol. The second protocol may employ multi-level signaling beyond binary signaling. Compared to the first protocol, the second protocol may utilize complex signaling, encoding, or modulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram of a multi-antenna system including a digital-to-analog converter (DAC) is shown.

[0007] Figure 2 A diagram showing a multiple antenna system according to an embodiment is shown.

[0008] Figure 3 It shows that according to the embodiment Figure 1 The register array of the DAC.

[0009] Figure 4 A flow chart of a method performed by the control logic of a DAC is shown. DETAILED DESCRIPTION

[0010] In communication devices such as cell phones and tablets, antenna systems are used to send and receive data. Many devices use multiple antennas to implement antenna diversity, where multiple antennas are used to send and receive data. Transmitting or receiving data is alternating or switching between multiple antennas, which increases the communication speed of the device.

[0011] Figure 1 A block diagram of a multi-antenna system 100 including a digital-to-analog converter (DAC) is shown. The system 100 includes a controller 102, a switch 104, a DAC 106, a first tuning circuit 108a, a second tuning circuit 108b, a first antenna 110a, and a second antenna 110b. The system 100 drives the first antenna 110a and the second antenna 110b, and operates the antennas 110a, 110b for transmitting and receiving data.

[0012] The controller 102 may be any type of device configured to control the antennas 110a, 110b to transmit or receive data, turn on or off the first antenna 110a or the second antenna 110b, switch between the first antenna 110a and the second antenna 110b to transmit or receive, or employ transmit or receive diversity using the first antenna 110a and the second antenna 110b. In addition, the controller 102 may control the switch 104 and the DAC 106. The controller 102 may control the DAC 106 to provide an analog voltage level to the first tuning circuit 108a and the second tuning circuit 108b. The controller 102 may also control the switch 104 to switch between using the first antenna 110a and the second antenna 110b.

[0013] For example, the controller 102 may be a modem, a microcontroller, a microprocessor, etc. The controller 102 and the DAC 106 may each include or be coupled to a memory (not shown). Figure 1 ). The memory may store executable instructions that, when executed by the controller 102 or the DAC 106, cause the controller 102 and the DAC 106 to operate as described herein, and the memory may be a static memory or a dynamic memory.

[0014] DAC 106 can be any type of device that is configured to provide one or more output voltages based on input data. DAC 106 can provide analog output voltages based on the input data. DAC 106 can be a high voltage device. For example, DAC 106 can be configured to provide an output voltage greater than 20 volts (V). Switch 104 can be any type of switch such as a double-pole double-throw (DPDT) switch that is configured to select between the first antenna 110a or the second antenna 110b for sending and / or receiving data. In addition, switch 104 can be configured to adopt antenna diversity using both the first antenna 110a and the second antenna 110b. Tuning circuits 108a, 108b can each include one or more capacitors for providing charge to antennas 110a, 110b, respectively.

[0015] The controller 102 has a first output 112 and a second output 114. The switch 104 has an input 116. The first output 112 of the controller 102 is coupled to the input 116 of the switch 104. The DAC 116 has a first input 118 and a second input 120. The second output 114 of the controller 102 is coupled to the second input 120 of the DAC 106.

[0016] The communication between the controller 102 and the switch 104 is conducted via a first communication channel 122 and using a first communication protocol. The communication between the controller 102 and the DAC 106 is conducted via a second communication channel 124 and using a second communication protocol.

[0017] The first communication protocol may be a binary protocol, such as a general purpose input / output (GPIO) protocol. For example, the controller 102 may output a control signal that is a binary signal to the switch 104 via the first output 112. The control signal may have one of two states, whereby the first state may be a logic 0 (or a deactivated or invalid state) and the second state may be a logic 1 (or an activated or valid state). The controller 102 may command the switch 104 to select between the first antenna 110a and the second antenna 110b for transmission or reception of data. For example, a logic 0 may command the switch to use the first antenna 110a for data transmission or reception, while a logic 1 may command the switch to use the second antenna 110b for data transmission or reception.

[0018] In contrast, the second communication protocol (used on the second communication channel 124) may be an advanced communication protocol. The second communication protocol may employ multi-level signaling beyond binary signaling. The second communication protocol may utilize complex signaling, coding, or modulation compared to the binary first communication protocol. For example, the second communication protocol may be a mobile industry processor interface (MIPI) protocol that may communicate at 5 megabits per second (Mbps).

[0019] The controller 102 outputs data indicative of the output voltage of the DAC 106 via the second communication channel 124. Additionally, the controller 102 outputs data indicative of when the switch 104 transitions between states via the second communication channel 124.

[0020] The switch 104 has a first output 126a and a second output 126b. The first antenna 110a has a first input 128a and a second input 136a. The second antenna 110b has a first input 128b and a second input 136. The first output 126a and the second output 126b of the switch 104 are coupled to the first input 128a of the first antenna 110a and the first input 128b of the second antenna 110b, respectively. The switch 104 uses the outputs 126a, 126b to select between the antennas 128a, 128b.

[0021] The DAC 106 has a first output 130a and a second output 130b. The first tuning circuit 108a has an input 132a and the second tuning circuit 108b has an input 132b. The first output 130a of the DAC 106 is coupled to the input 132a of the first tuning circuit 108a. The second output 130b of the DAC 106 is coupled to the input 132b of the second tuning circuit 108b.

[0022] The DAC 106 outputs corresponding output voltages through the first output 130a and the second output 130b according to the data received from the controller 102 through the second communication channel 124. The data may indicate one or more output voltages of the DAC 106. The tuning circuits 132a and 132b receive the output voltages respectively. The corresponding output voltages are used to charge the capacitors of the tuning circuits 132a and 132b.

[0023] The first tuning circuit 108a and the second tuning circuit 108b have respective outputs 134a, 134b. The outputs 134a, 134b are coupled to the second input 136a, 136b of the first antenna 110a and the second input 136b of the second antenna 110b, respectively. The first tuning circuit 108a and the second tuning circuit 108b provide charge to the first antenna 110a and the second antenna 110b at their outputs 134a, 134b, respectively, to tune the first antenna 110a and the second antenna 110b, respectively.

[0024] DAC 106 wants to know simultaneously when switch 104 is operated. Controller 102 outputs two different indications of when the switch is operated. Controller 102 uses first communication channel 122 to command (using GPIO control signal) switch 104 to select between first antenna 110a and second antenna 110b. Thus, through control signal, first communication channel 122 indicates when switch 104 is operated or when it switches between states. The control signal of first communication channel 122 is the most simultaneous indication of when switch 104 is operated. This is because the control signal itself commands switch 104.

[0025] In addition, the controller 102 outputs data indicating when the switch 104 is operated or when a switching operation is performed between the first antenna 110a and the second antenna 110b through the second communication channel 124. The controller 102 may output the data through the second communication channel 124 for use by the DAC 106. However, the controller 102 may not be able to provide the data through the second communication channel 124 in a timely manner. In addition, the controller 102 may be part of a proprietary platform, thereby limiting access to the source code or firmware of the controller 102, so that the controller 102 may not be reconfigured to use the second communication channel 124 to provide data indicating the switching time of the antennas 110a, 110b in a timely manner.

[0026] Thus, while it is contemplated that the DAC 106 relies on data communicated via the second communication channel 124 to identify when the switch 104 is operated, the first communication channel 122 is tapped and provided to the DAC 106. Thus, the DAC 106 receives the control signal of the first communication channel 122 directly. The control signal sent via the first communication channel 122 is a simultaneous indication of when the switch 104 is operated. The DAC 106 may utilize the control signal to determine when the switch is operated. The DAC 106 may be configured as a binary or GPIO that processes the control signal. Because the DAC 106 relies on the switching time indicated by the control signal, the DAC 106 may ignore or discard the indication of timing received via the second communication channel 124. Relying on the control signal to identify when the switch 104 is operated improves the responsiveness of the DAC 106.

[0027] Although the first communication channel 122 may be a GPIO channel, the second communication channel 124 may be a multi-level protocol channel, such as MIPI. The protocol of the second communication channel 124 may be more advanced or more complex than the protocol of the first communication channel 122 in terms of modulation, coding or frequency. For example, the protocol of the second communication channel 124 may be multi-level modulated, while the protocol of the first communication channel 122 may be a binary protocol. In addition, the protocol of the second communication channel 124 may be encoded, for example, using error detection or error correction coding. The protocol of the first communication channel 122 may not utilize error detection or error correction coding. In addition, the transmission frequency of the second communication channel 124 may be higher than the transmission frequency of the first communication channel 122. Due to the complexity of the second communication channel 124 compared to the first communication channel 122, the processing data of the first communication channel 122 may be simpler and may not require as many computing resources as processing the data of the second communication channel 124.

[0028] Therefore, in Figure 1In the system 100, the first communication channel 122 is tapped to the first input 118 of the DAC 106, and the first output 112 of the controller 102 is coupled to the first input 118 of the DAC 106. As described herein, the first communication channel 122 is used by the controller 102 to command the switch 104 to select between the first antenna 110a and the second antenna 110b. The DAC 106 is configured to receive a control signal sent through the first communication channel 122, which can be a GPIO control signal. The control signal of the first communication channel 122 indicates the time when the switch 104 switches between states. The controller 102 can evaluate the received control signal and output a voltage through its first output 130a and the second output 130b based on the control signal. The controller 102 can use the switching timing indicated by the control signal of the first communication channel 122 to determine when to output the voltage to the first tuning circuit 108a and the second tuning circuit 108b.

[0029] Figure 2 FIG. 1 shows a diagram of a multi-antenna system 100a according to an embodiment. Figure 1 Similar elements of the depicted multiple antenna system 100 have the same reference numerals. The first tuning circuit 108a includes a first capacitor 140a, a second capacitor 142a, a third capacitor 144a, and an inductor 146a. Similarly, the second tuning circuit 108b includes a first capacitor 140b, a second capacitor 142b, a third capacitor 144b, and an inductor 146b.

[0030] DAC 106 includes a register array 148 and control logic 150. Register array 148 may be any type of memory configured to store data. Register array 148 may include a plurality of registers. In some embodiments, register array 148 may be a cache, a read-only memory, a random access memory, or the like. Control logic 150 may be a controller, a processor, a hardware circuit device, or the like. Register array 148 and control logic 150 are communicatively coupled. Control logic 150 is also coupled to first input 118 and second input 120 of DAC 106, and is configured to receive data from controller 102 through first input 118 and second input 120. Control logic 150 may receive data through first input 118 and second input 120, operate DAC 106, and configure register array 148 according to the data.

[0031] The first output 130a of the DAC 106 is shown to include three output voltage lines to the first tuning circuit 108a, including a first output voltage line 152a, a second output voltage line 154a, and a third output voltage line 156a. Similarly, the second output 130b is shown to include three output voltage lines to the second tuning circuit 108b, including a first output voltage line 152b, a second output voltage line 154b, and a third output voltage line 156b. Each output voltage line 152a, 154a, 156a, 152b, 154b, 156b is used to charge the capacitors 140a, 142a, 144a, 140b, 142b, 144b of the first tuning circuit 108a and the second tuning circuit 108b, respectively.

[0032] The control logic 150 receives data indicating the output voltage level for each output voltage line 152a, 154a, 156a, 152b, 154b, 156b via the second communication channel 124. As described herein, the control logic 150 processes the data and stores the data in the register array 148. The control logic 150 then uses the data stored in the register array 148 to cause the DAC 106 to generate the output voltage level of the corresponding output voltage line 152a, 154a, 156a, 152b, 154b, 156b. The switch 104 can be coupled to the antenna 110a, the antenna 110b and drives the antenna 110a and the antenna 110b.

[0033] Figure 3 A register array 148 of a DAC according to an embodiment is shown. The register array 148 includes a plurality of registers 160. Each register in the plurality of registers 160 is associated with a register number 162 and has a unique address 164. Each register in the plurality of registers 160 includes a plurality of bits 166 (shown as including eight bits from the least significant bit (LSB) represented as "D0" to the most significant bit (MSB) represented as "D7") and is associated with a read / write access type 168, which indicates whether read or write access rights to the register are available.

[0034] The plurality of registers 160 include a first group of registers and a second group of registers, the first group of registers including a first register 170a, a second register 170b, and a third register 170c, and the second group of registers including a first register 172a, a second register 172b, and a third register 172c. The registers 170a, 170b, 170c, 172a, 172b, 172c store the output voltage levels of the output voltage lines 152a, 154a, 156a, 152b, 154b, 156b, respectively. In particular, seven bits are used to store the output voltage level of each line, thereby allowing 2 7= 128 different voltage levels. For example, if the DAC 106 has a maximum output voltage level of 24V, then the DAC can output voltages from 0V to 24V in increments of 0.19V.

[0035] If the control signal provided through the first communication channel 122 has a first state (e.g., logic 0 or 1), the control logic 150 can use the voltage levels stored in the registers 170a, 170b, 170c to indicate the output voltage levels of the output voltage lines 152a, 154a, 156a. The voltage levels stored in another set of registers (registers 172a, 172b, 172c) indicate the output voltage levels of the output voltage lines 152b, 154b, 156b.

[0036] Conversely, if the control signal provided via the first communication channel 122 has a second state (e.g., a logical 0 or 1's complement of the first state), the control logic 150 may use the voltage levels stored in the registers 172a, 172b, 172c to indicate the output voltage levels of the output voltage lines 152a, 154a, 156a. The voltage levels stored in another set of registers (registers 170a, 170b, 170c) indicate the output voltage levels of the output voltage lines 152b, 154b, 156b.

[0037] The state of the control signal provided via the first communication channel 122 is used by the control logic 150 to identify a register location from which to obtain an indication of the output voltage level. The output voltage is provided to the capacitance of the first tuning circuit 108a or the second tuning circuit 108b via output voltage lines 152a, 154a, 156a, 152b, 154b, 156b.

[0038] Figure 4 A flow chart of a method 400 performed by control logic of the digital-to-analog converter 106 is shown. Examples of control logic include reference Figure 2 The control logic 150 described above. The control logic may be a hardware circuit device or a controller, a processor or a microcontroller, etc. In the method 400, at 402, the control logic receives a control signal through a first communication channel, the control signal is sent according to a binary protocol and indicates switching between a first antenna and a second antenna for data transmission or reception. For example, the first communication channel may be a GPIO channel. At 404, the control logic receives data through a second communication channel different from the first communication channel, the data being sent according to a multi-level communication protocol different from the binary protocol. The second communication channel may be a MIPI channel.

[0039] At 406, the control logic determines a plurality of first voltages and a second voltage based on the received data. The plurality of first voltages and the second voltages may be signaled in the data. At 408, the control logic causes the determined plurality of first voltages and the second voltages to be stored in a register array. For example, each voltage level may be stored in a corresponding register of the register array. At 410, the control logic identifies a time to switch data transmission or reception between the first antenna and the second antenna based on the control signal. At 412, in response to identifying a time to switch data transmission or reception between the antennas, the control logic causes the determined plurality of first voltages to be output to the first antenna tuning circuit, or causes the determined plurality of second voltages to be output to the second antenna tuning circuit.

[0040] Note that in various embodiments, instead of using data sent using a higher complexity protocol such as MIPI data, data sent using a lower complexity protocol such as GPIO data can be used to identify relevant information. For example, determining whether a universal serial bus (USB) device is plugged into a USB port can be performed by examining a data line of the bus. If the data line is powered or data is exchanged through the data line, it can be determined that the USB device has been plugged into the USB port. Conversely, if the line is not powered or if no data is exchanged through the data line, it can be determined that the USB device is not plugged into the USB port.

[0041] In one embodiment, the detection of whether the USB cable is plugged in triggers the switching of the transmit or receive frequency of the first 110a or second antenna 110b. For example, the multi-antenna system 100 can be part of a smartphone. When the USB cable is connected to or plugged into the smartphone, the operating frequency of the antenna at the bottom of the smartphone is reduced by 100 megahertz (MHz).

[0042] refer to Figure 1 , the first communication channel 122 can carry a USB detection signal, which is a binary signal (e.g., according to the GPIO protocol). The USB detection signal can be asserted or activated when the USB cable is connected to the smartphone, and can be deasserted or deactivated when the USB cable is connected to the smartphone. In alternative embodiments, the signal convention can also be reversed.

[0043] DAC 106 receives the USB detection signal and identifies whether the USB cable is connected to the smart phone based on the USB detection signal. Figure 3As described, the DAC 106 has a register array 148, and the register array 148 includes a first group of registers 170a, 170b, 170c and a second group of registers 172a, 172b, 172c. The first group of registers 170a, 170b, 170c can store the output voltage level of the DAC 106 when the USB cable is connected, and the second group of registers 172a, 172b, 172c can store the output voltage level of the DAC 106 when the USB cable is not connected. The DAC 106 receives a USB detection signal and switches between outputting the voltage level stored in the first group or the second group of registers based on the USB detection signal. When the USB detection signal indicates that the USB cable is connected, the DAC 106 outputs the voltage level stored in the first group of registers 170a, 170b, 170c. When the USB detection signal indicates that the USB cable is not connected, the DAC 106 outputs the voltage level stored in the second group of registers 172a, 172b, 172c. Therefore, the antenna configuration and operation are automatically adjusted according to whether the USB cable is connected.

[0044] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to these embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents given by such claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A multi-antenna system, the system include: a first antenna configured to transmit or receive data; a second antenna configured to transmit or receive data; a first antenna tuning circuit configured to receive a plurality of first voltages for charging the first antenna; a second antenna tuning circuit configured to receive a plurality of second voltages for charging the second antenna; and A digital-to-analog converter, the digital-to-analog converter being configured to: receiving a control signal through a first communication channel, the control signal being sent according to a binary protocol and the control signal instructing switching between the first antenna and the second antenna for data transmission or reception; and receiving data via a second communication channel different from the first communication channel, the received data being sent according to a multi-level communication protocol different from the binary protocol; determining the plurality of first voltages and the plurality of second voltages based on the received data; identifying a change in state based on the control signal, the change in state indicating switching data transmission or reception between the first antenna and the second antenna; as well as In response to the switching of the data transmission or reception, the determined plurality of first voltages are output to the first antenna tuning circuit or the determined plurality of second voltages are output to the second antenna tuning circuit.

2. The system according to claim 1, in, The binary protocol is a General Purpose Input / Output (GPIO) protocol, and the multi-level communication protocol is a Mobile Industry Processor Interface (MIPI) protocol.

3. The system according to claim 1, in, The received data includes an indication of when to switch data transmission or reception between the first antenna and the second antenna, and wherein the digital-to-analog converter is configured to discard the indication and utilize the control signal to identify switching data transmission or reception between the first antenna and the second antenna.

4. The system according to claim 1, in, When the control signal is in a first state, data transmission or reception is performed by the first antenna, and when the control signal is in a second state, data transmission or reception is performed by the second antenna.

5. The system according to claim 1, in, The multi-level communication protocol has multiple modulation levels and includes error detection or error correction coding, and the binary protocol has two states and does not include the error detection or the error correction coding.

6. The system according to claim 1, include: a switch configured to receive the control signal and select one of the first antenna and the second antenna for data transmission or reception based on the control signal; A controller, the controller being configured to: outputting the control signal to the switch through the first communication channel; and The data is output to the digital-to-analog converter through the second communication channel.

7. The system according to claim 6, in, The first communication channel between the controller and the switch is tapped to provide the first communication channel to the digital-to-analog converter.

8. The system according to claim 7, in, The firmware of the controller is access-protected to prevent the controller from reconfiguring a time to switch between the first antenna and the second antenna for data transmission or reception indicated by the second communication channel.

9. An antenna tuning control method, include: receiving a control signal via a first communication channel, the control signal being sent according to a first protocol, the first protocol being a binary protocol, and the control signal instructing switching between a first antenna and a second antenna for data transmission or reception; and receiving data via a second communication channel different from the first communication channel, the received data being sent according to a second communication protocol different from the first protocol; determining a plurality of first voltages and a plurality of second voltages based on the received data; identifying when to switch data transmission or reception between the first antenna and the second antenna based on the control signal; and In response to identifying when to switch data transmission or reception between the first antenna and the second antenna based on the control signal, the determined plurality of first voltages are output to the first antenna tuning circuit or the determined plurality of second voltages are output to the second antenna tuning circuit.

10. The method according to claim 9, in, The first protocol is a General Purpose Input / Output (GPIO) protocol, and the second communication protocol is a Mobile Industry Processor Interface (MIPI) protocol.

11. The method according to claim 9, It is characterized in that The received data includes an indication of when to switch data transmission or reception between the first antenna and the second antenna.

12. The method according to claim 11, include: discarding the indication of when to switch the data transmission or reception between the first antenna and the second antenna; and The control signal is used to identify a time to switch the data transmission or reception between the first antenna and the second antenna.

13. The method according to claim 9, in, When the control signal is in a first state, data transmission or reception is performed by the first antenna, and when the control signal is in a second state, data transmission or reception is performed by the second antenna.

14. The method according to claim 9, in, The second communication protocol has multiple modulation levels and includes error detection or error correction coding, and the first protocol has two states and does not include the error detection or the error correction coding.

15. The method according to claim 9, include: The first communication channel between the tap controller and the switch is provided to a digital-to-analog converter.

16. The method according to claim 15, in, The firmware of the controller is access-protected to prevent the controller from reconfiguring the timing of switching between the first antenna and the second antenna for data transmission or reception indicated by the second communication channel.

17. A digital-to-analog converter, include: register array; and A control logic configured to: receiving a control signal through a first communication channel, the control signal being sent according to a binary protocol and the control signal instructing switching between a first antenna and a second antenna for data transmission or reception; as well as receiving data via a second communication channel different from the first communication channel, the received data being sent according to a multi-level communication protocol different from the binary protocol; determining a plurality of first voltages and a plurality of second voltages based on the received data; causing the determined plurality of first voltages and the determined plurality of second voltages to be stored in the register array; identifying, based on the control signal, when to switch data transmission or reception between the first antenna and the second antenna; as well as In response to identifying when to switch data transmission or reception between the first antenna and the second antenna based on the control signal, the determined plurality of first voltages are output to the first antenna tuning circuit or the determined plurality of second voltages are output to the second antenna tuning circuit.

18. The digital-to-analog converter according to claim 17, in, The binary protocol is a General Purpose Input / Output (GPIO) protocol, and the multi-level communication protocol is a Mobile Industry Processor Interface (MIPI) protocol.

19. The digital-to-analog converter according to claim 17, in, The received data includes an indication of when to switch data transmission or reception between the first antenna and the second antenna, and wherein the digital-to-analog converter is configured to discard the indication and utilize the control signal to identify when to switch data transmission or reception between the first antenna and the second antenna.

20. The digital-to-analog converter according to claim 17, in, The multi-level communication protocol has multiple modulation levels and includes error detection or error correction coding, and the binary protocol has two states and does not include the error detection or the error correction coding.

21. The digital-to-analog converter of claim 17, wherein the control logic is configured to: Identify whether a universal serial bus (USB) cable is connected or not connected based on the control signal; in response to identifying that the USB cable is connected based on the control signal, causing the determined plurality of first voltages to be output to the first antenna tuning circuit; as well as In response to identifying that the USB cable is not connected based on the control signal, the determined plurality of second voltages are output to the first antenna tuning circuit.

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