A pixel display structure and panel

Abstract

A pixel display structure and panel, including a first thin film transistor, a second thin film transistor, wherein the source of the first thin film transistor is connected to a column drive signal, the gate is connected to a current level scanning signal, the drain is connected to the source of the second thin film transistor, and the gate of the second thin film transistor is connected to a previous level scanning signal. By designing the second thin film transistor to perform pre-discharge, the charging time is short and the required voltage is low when the first thin film transistor is refreshed, which can ultimately reduce power consumption and be more energy-saving and environmentally friendly.

Description

Technical Field

[0001] The present invention relates to a new pixel display structure design in a panel, and in particular to a structure capable of reducing the energy consumption of the panel, thereby achieving the effect of power saving and environmental protection. Background Art

[0002] The array substrate of existing LCD display screens generally uses materials such as a-Si, Poly-Si or IGZO as the active layer; with the popularization of consumer electronic products, the power consumption of the liquid crystal display module (LCM), which is an important component, will affect the product's endurance. Therefore, reducing LCD power consumption has always been one of the key parameters for panel R&D performance evaluation. The existing display panel is composed of an array substrate and a color filter CF substrate, in which the electrical signal for liquid crystal driving is provided by the array substrate. In order to improve the liquid crystal residue caused by the same polarity voltage drive, the existing liquid crystal display panel generally adopts a column inversion method, that is, the TFT on the same data line data has opposite polarity of pixel capacitance in two frames (on the pixel electrode: if the previous frame is positively charged, the next frame is negatively charged). When the electrical signal switches between frames, it is necessary to supply a reverse voltage to the capacitor with reversed polarity, and the charging and discharging time is longer and the supply voltage is higher. Therefore, the energy consumption is relatively large. Summary of the invention

[0003] Therefore, it is necessary to provide a new pixel display structure on a panel to achieve the effect of reducing energy consumption when the panel is refreshed between frames.

[0004] To achieve the above-mentioned purpose, the inventor provides a pixel display structure, including a first thin film transistor and a second thin film transistor, wherein the source of the first thin film transistor is connected to a column drive signal, the gate is connected to a current level scan signal, the drain is connected to the source of the second thin film transistor, and the gate of the second thin film transistor is connected to a previous level scan signal.

[0005] Specifically, the drain of the first thin film transistor is also connected to the first capacitor.

[0006] Specifically, the drain of the second thin film transistor is grounded or connected to the comparison voltage COM.

[0007] Specifically, the drain of the first thin film transistor is also connected to the ground or to the comparison voltage COM through the first capacitor.

[0008] Furthermore, the first thin film transistor and the second thin film transistor are double-etched channel structures on the same wafer.

[0009] A panel comprises the above-mentioned pixel display structure arranged in an array.

[0010] Different from the prior art, the second thin film transistor is designed to be pre-discharged, so that the charging time is short and the required voltage is low when the first thin film transistor is refreshed, which can ultimately reduce power consumption and be more energy-saving and environmentally friendly. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of a pixel TFT circuit in a display area according to a specific implementation method;

[0012] Figure 2 It is a schematic diagram of a column inversion mode TFT array circuit according to a specific implementation method;

[0013] Figure 3 is a schematic cross-sectional view of a pixel structure described in a specific implementation manner;

[0014] Figure 4 It is an auxiliary diagram of the steps in the patterning of the array process described in the specific implementation method;

[0015] Figure 5 It is a schematic diagram of a low-power pixel display structure described in a specific implementation manner;

[0016] Figure 6 It is a cross-sectional schematic diagram of a low-power array substrate pixel structure described in a specific implementation manner;

[0017] Figure 7 It is a schematic diagram of a low-power pixel display structure described in a specific implementation manner;

[0018] Figure 8 It is a schematic cross-sectional view of a low-power array substrate pixel structure according to a specific implementation method. DETAILED DESCRIPTION

[0019] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0020] Please see here Figure 1 , Figure 1 The embodiment shown shows the circuit principle diagram of pixel TFT in the display area of ​​the array substrate of the display panel: the display panel is composed of the array substrate and the color filter CF substrate, wherein the electric signal for driving the liquid crystal is provided by the array substrate, as shown in the figure, which shows the TFT device diagram in the display area of ​​the array substrate. In order to improve the liquid crystal residue caused by the same polarity voltage driving, the existing liquid crystal display panel generally adopts the column inversion method, that is, the TFT on the same data line data has opposite polarity of the pixel capacitor in two frames (on the pixel electrode: if the previous frame is positively charged, the next frame is negatively charged).

[0021] Figure 2The illustrated embodiment shows a schematic diagram of the TFT array circuit of the above-mentioned panel in the column inversion mode. When the electrical signal switches between frames, the charge polarity of the pixel electrodes of each row of TFTs changes: for example, the polarity of data_Rn in the previous frame is positive, and the drive circuit refreshes the display TFTs step by step from top to bottom. If it is refreshed to the nth row, the TFT of the data_Rn column of the nth row will be charged from the original positive voltage to the expected negative voltage, thereby achieving polarity reversal; the charge polarity of the pixel electrode of the TFT of the data_Rn column n-1 row is the same as that of the nth row, while the charge polarity of the TFT of the n+1th row is opposite to that of the n-1th row because it has not been refreshed yet.

[0022] The structure of this pixel structure is as follows Figure 3 As shown, Figure 3 Taking the semiconductor oxide array substrate process as an example, a cross-sectional schematic diagram of the pixel structure is shown. From the figure, we can see that this type of wafer includes glass-gate GE-gate insulating layer GI-barrier layer ES-source SD-passivation layer PV-planarization layer OC-common memory BC-insulating layer CH-pixel electrode PE. From the figure, we can see that the wafer is a single TFT design. When the pixel electrode signal is written, the gate is given a turn-on voltage, and the source data line signal is transmitted to the drain area through the TFT channel area. The drain SD is electrically connected to the pixel electrode PE, so the pixel electrode PE will be charged to the target potential; at this time, there is an electric field distribution between the pixel electrode and the common electrode, thereby driving the liquid crystal to rotate to achieve the purpose of changing light and dark. And Figure 4 The illustrated embodiment shows auxiliary diagrams of individual steps in the array process patterning of the above-mentioned scheme.

[0023] In other embodiments, Figure 5 As shown, Figure 5It shows that a TFT is added on the basis of the TFT design in the above example, that is, it includes a first thin film transistor TFT1 and a second thin film transistor TFT2; the source of TFT2 is connected to the drain of TFT1, and the drain of TFT2 is connected to the common electrode (connected to the drain of other pixel TFT2); when scanning to the nth row, the data line charges the nth row TFT1, and at the same time the n+1th row TFT2 is turned on, the charge of the pixel electrode of the n+1th row TFT1 is transferred to the common electrode for neutralization, and the potential is pulled to the Com potential (close to 0V), so as to realize the pre-discharge of the n+1th row pixel. In other words, the gate of TFT2 of the n+1th row is connected to the previous level scan signal. In this embodiment, the gate of TFT2 of the first row can be connected to the last row scan signal line, so that the first row can be pre-discharged in advance when refreshing and scanning to the last row, but it may also cause the signal line to be too long, which is not conducive to simplifying the GIP line setting. In order to simplify the circuit, some other embodiments provide a puppet GIP unit in the first row and the last row respectively to overcome the problem of not being able to pre-charge the first row when scanning; another method: pre-charging the Data line between frames to achieve charge inversion of the Data line; the first row does not perform charge neutralization, and this structure does not need to provide a puppet GIP unit, which can simplify the circuit. In the step-by-step scanning process, the pixel charge of the next row is conducted to the common electrode for neutralization in advance (the opposite is true for adjacent pixel electrodes), and the pixel TFT1 charging does not need to switch between -5V and +5V (the maximum voltage difference is 10V), but switches from 0V to + / -5V (the maximum voltage difference is 5V); therefore, this technical proposal can reduce the data writing power consumption of the panel when displaying. For example Figure 5 In the specific embodiment shown, the drain of the first thin film transistor is also connected to the first capacitor. It can also be connected to the ground or to the comparison voltage COM through the first capacitor. The capacitor here can be an inherent capacitor on the wafer, such as the native capacitor between the liquid crystal and the plate. The display effect of the TFT is maintained by connecting the capacitor.

[0024] exist Figure 6 The embodiment shown shows a schematic cross-sectional view of the pixel structure of the array substrate of the present invention. From the figure, we can see that the first thin film transistor and the second thin film transistor are double-etched channel structures on the same wafer. On this basis, those skilled in the art can make various changes to the realization of double TFT based on this concept.

[0025] exist Figure 7 and Figure 8In the embodiment shown, another implementation method of the drain connection of TFT2 is proposed. The drain of TFT2 in the same row is short-circuited to the reference potential wiring (assigning Com potential or 0V), and the reference potential wiring can be set in the existing conductive film layer or a new conductive film layer, and its potential can be connected to the common electrode or ground wiring, or a separate lead can be given a reference potential by IC or FPC. Figure 8 This is a cross-sectional schematic diagram of the corresponding array substrate pixel structure.

[0026] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A pixel display structure, characterized in that: It includes a first thin film transistor and a second thin film transistor, wherein the source of the first thin film transistor is connected to a column drive signal, the gate is connected to a current level scan signal, the drain is connected to the source of the second thin film transistor, the gate of the second thin film transistor is connected to a previous level scan signal, wherein the gate of the second thin film transistor in the first row is connected to the last row scan signal wiring; The drain of the second thin film transistor is grounded or connected to a comparison voltage COM; The first thin film transistor and the second thin film transistor are double-etched channel structures on the same wafer; When scanning to the nth row, the data line charges the first thin film transistor in the nth row, and at the same time the second thin film transistor in the n+1th row is turned on, the charge of the pixel electrode of the first thin film transistor in the n+1th row is transferred to the common electrode for neutralization, and the potential is pulled to the Com potential, thereby realizing the pre-discharge of the pixel in the n+1th row.

2. The pixel display structure according to claim 1, characterized in that: The drain of the first thin film transistor is also connected to the first capacitor.

3. The pixel display structure according to claim 1, characterized in that: The drain of the first thin film transistor is also connected to the ground or to the comparison voltage COM through the first capacitor.

4. A panel, characterized in that: A pixel display structure comprising the pixel display structure as claimed in any one of claims 1 to 3 arranged in an array.

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