Large-board fan-out double-sided antenna packaging structure and preparation method thereof

Abstract

The present invention discloses a large-board fan-out double-sided antenna packaging structure and a preparation method thereof. The large-board fan-out double-sided antenna packaging structure includes: a carrier; a plurality of semiconductor chips, the back of which is attached to the two sides of the carrier; a packaging layer, which is respectively located on the two sides of the carrier and covers the semiconductor chips, and the front of the semiconductor chips is exposed to the packaging layer; the transmission layer, the wiring layer and the antenna layer are all located on the packaging layer, one side of the transmission layer is electrically connected to the front of the packaging layer and the semiconductor chip, and the other side is electrically connected to the wiring layer and the antenna layer, and the wiring layer has a pad area and a non-pad area; a solder mask layer, which is located on the packaging layer and covers the antenna layer and the non-pad area; a metal bump, which is welded to the pad area of ​​the wiring layer. The antenna layer of the present invention occupies a small volume, and the packaging structure is reasonably arranged, which can improve the integration performance of the antenna packaging structure and the efficiency of the antenna, and will not cause surface warping due to differences in material properties, and can ensure the accuracy, yield and welding stability during production.

Description

Technical Field

[0001] The present invention relates to the technical field of fan-out packaging, and in particular to a large-plate fan-out double-sided antenna packaging structure and a preparation method thereof. Background Art

[0002] Fan-out packaging is one of the most flexible advanced packaging methods, and has unique advantages over conventional wafer-level packaging. In the fan-out antenna packaging structure, the antenna needs to be combined with multiple functional chip modules to transmit and receive signals.

[0003] The traditional approach to fan-out antenna packaging is to attach a semiconductor chip to one side of a substrate, and then lead out the antenna through an electrical connection structure so that the antenna is located on the surface of the circuit board. This approach has the following defects in the actual production and application of the product:

[0004] (1) For a large-board fan-out packaging structure, due to its large size, the warpage of the large-board fan-out packaging structure is relatively large;

[0005] (ii) The antenna occupies additional circuit board area, increasing the volume of the fan-out antenna packaging structure, resulting in poor product integration and high cost. For various high-tech electronic products, if the antenna is directly made on the surface of the circuit board and then the antenna and chip are connected through an electrical connection structure, it means that a larger circuit board is required, which makes the high-tech electronic product also occupy a larger volume, and will make the transmission line longer, the performance is poor, and the power consumption is high, which is contrary to people's demand for miniaturization, convenience, high performance, and low power consumption of high-tech electronic products;

[0006] (3) Only one fan-out antenna packaging structure is made on one carrier board, which has low production efficiency and thus increases the production cost of the product.

[0007] Therefore, how to reduce the volume of the large-board fan-out antenna packaging structure, reduce power consumption, improve the integration performance of the fan-out antenna packaging structure and reduce production costs are problems that need to be urgently solved in these electronic devices. Summary of the invention

[0008] One object of the present invention is to provide a large-board fan-out antenna packaging structure that will not cause surface warping due to differences in material properties, can reduce the packaging volume, and improve the transmission efficiency of the antenna and the integration performance of the packaging structure.

[0009] Another object of the present invention is to provide a method for preparing a large-board fan-out antenna packaging structure, which will not cause product surface warping due to differences in material properties and can improve production efficiency.

[0010] To achieve this object, the present invention adopts the following technical solutions:

[0011] On the one hand, a large-board fan-out double-sided antenna packaging structure is provided, comprising:

[0012] A carrier plate having a first surface and a second surface opposite to each other along a thickness direction thereof;

[0013] A plurality of semiconductor chips, wherein the back surfaces of the plurality of semiconductor chips are respectively attached to the first surface and the second surface of the carrier through peeling layers;

[0014] A packaging layer, located on the first surface and the second surface of the carrier and covering the semiconductor chip, wherein the front surface of the semiconductor chip is exposed to the packaging layer;

[0015] The transmission layer, the wiring layer and the antenna layer are located on a side of the packaging layer away from the carrier, one side of the transmission layer is electrically connected to the packaging layer and the front surface of the semiconductor chip, and the other side is electrically connected to the wiring layer and the antenna layer, and the wiring layer has a pad area and a non-pad area;

[0016] A solder resist layer, located on a side of the packaging layer away from the carrier and covering the outside of the non-pad area of ​​the antenna layer and the wiring layer;

[0017] The metal bump is welded to the pad area of ​​the wiring layer.

[0018] As a preferred solution for a large-board fan-out double-sided antenna packaging structure, the semiconductor chip includes a bare chip, an I / O terminal located inside the bare chip, and a connecting column protruding outside the bare chip and electrically connected to the I / O terminal, and one end of the connecting column away from the bare chip is parallel to the surface of the packaging layer and connected to the transmission layer.

[0019] As a preferred solution for a large-board fan-out double-sided antenna packaging structure, the transmission layer includes a dielectric layer attached to the packaging layer and a seed layer attached to the dielectric layer, the dielectric layer has vias along its thickness direction to expose the connecting posts of the semiconductor chip, and the seed layer extends into the vias to be electrically connected to the connecting posts.

[0020] As a preferred solution for the large-board fan-out double-sided antenna packaging structure, the seed layer includes a titanium metal layer located on a side of the packaging layer away from the carrier board and a copper metal layer located on the titanium metal layer.

[0021] As a preferred solution of the large-board fan-out double-sided antenna packaging structure, the thickness of the antenna layer is less than the thickness of the wiring layer.

[0022] On the other hand, a method for preparing a large-plate fan-out double-sided antenna packaging structure is provided, comprising the following steps:

[0023] S10, providing a carrier and a plurality of semiconductor chips, and using packaging layers to package some of the semiconductor chips on a first side of the carrier and the remaining semiconductor chips on a second side of the carrier, and making the front sides of the semiconductor chips face away from the carrier;

[0024] S20, manufacturing a transmission layer on the packaging layer, so that the front surface of the semiconductor chip is electrically connected to the transmission layer;

[0025] S30, manufacturing a wiring layer and an antenna layer on the transmission layer;

[0026] S40, coating a photosensitive ink on a side of the packaging layer away from the carrier to form a solder resist layer, and making the solder resist layer cover the non-pad area of ​​the wiring layer and the antenna layer, and making the pad area of ​​the wiring layer exposed to the solder resist layer;

[0027] S50, providing a metal bump, and implanting the metal bump into the pad area.

[0028] As a preferred solution of the method for preparing a large-board fan-out double-sided antenna packaging structure, the step S10 specifically includes the following steps:

[0029] S10a, providing a carrier board and a first peeling layer, and attaching the first peeling layer to a first surface of the carrier board;

[0030] S10b, providing a plurality of first semiconductor chips, attaching the first semiconductor chips to the first peeling layer, and making the front surfaces of the first semiconductor chips face the side away from the carrier;

[0031] S10c, manufacturing a first packaging layer on the first surface of the carrier, so that the first packaging layer covers the first surface and the first semiconductor chip;

[0032] S10d, providing a second peeling layer, turning over the carrier, and attaching the second peeling layer to the second surface of the carrier;

[0033] S10e, providing a plurality of second semiconductor chips, attaching the second semiconductor chips to the second peeling layer, and making the front sides of the second semiconductor chips face the side away from the carrier;

[0034] S10f, manufacturing a second packaging layer on the second surface of the carrier board, so that the second packaging layer covers the second surface and the second semiconductor chip.

[0035] As a preferred solution of the method for preparing a large-board fan-out double-sided antenna packaging structure, the step S20 specifically includes the following steps:

[0036] S20a, grinding the first packaging layer and the second packaging layer simultaneously, so that the connection pillars of the first semiconductor chip are exposed in the first packaging layer, and the connection pillars of the second semiconductor chip are exposed in the second packaging layer;

[0037] S20b, providing a dielectric layer, and attaching the dielectric layer to the first packaging layer and the second packaging layer after grinding respectively;

[0038] S20c, performing laser drilling on the dielectric layer to form via holes along the thickness direction of the dielectric layer, so as to expose the connection pillars of the first semiconductor chip and the connection pillars of the second semiconductor chip;

[0039] S20d, forming a seed layer in the dielectric layer and the via hole by vacuum sputtering, wherein the dielectric layer and the seed layer constitute the transmission layer.

[0040] As a preferred solution of the method for preparing a large-board fan-out double-sided antenna packaging structure, the step S30 specifically includes the following steps:

[0041] S30a, providing a first photosensitive dry film, and attaching the first photosensitive dry film to the transmission layer;

[0042] S30b, forming a first patterned hole having a blind hole and a through hole for exposing the transmission layer to the first photosensitive dry film through a first exposure and development process;

[0043] S30c, performing electroplating on the first patterned hole to form a filling layer in the first patterned hole;

[0044] S30d, providing a second photosensitive dry film, and attaching the second photosensitive dry film to the first photosensitive dry film and the filling layer;

[0045] S30e, through a second exposure and development process, forming a second patterned hole on the second photosensitive dry film so that part of the filling layer is exposed from the second photosensitive dry film, and the part of the filling layer covered by the second photosensitive dry film forms the wiring layer;

[0046] S30f, performing super-roughening treatment on the filling layer in the second patterned hole to reduce the thickness of the filling layer to form the antenna layer.

[0047] As a preferred solution of the method for preparing a large-board fan-out double-sided antenna packaging structure, step S31 is further included between step S30 and step S40, and step S31 specifically includes the following steps:

[0048] S31a, removing the remaining first photosensitive dry film and the second photosensitive dry film;

[0049] S31b, providing an etching solution, and using the etching solution to etch the seed layer exposed after the first photosensitive dry film and the second photosensitive dry film are removed, so as to remove the seed layer.

[0050] Beneficial effects of the present invention: The present invention sequentially packages semiconductor chips on both sides of the carrier, and the two-sided packaging layers are tightly combined with the carrier, which will not cause surface warping due to material performance differences, and can well guarantee the accuracy, yield rate and welding stability during production; after the semiconductor chip is packaged, the double-sided transmission layer, wiring layer, antenna layer and solder mask layer can be made at the same time, which can effectively improve production efficiency. The wiring layer and the antenna layer are located on the same horizontal plane, the antenna layer occupies a small volume, and the packaging structure is reasonably arranged, which can improve the integration performance of the antenna packaging structure and the signal transmission efficiency of the antenna, and reduce the power consumption of the antenna packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 It is a cross-sectional view of the intermediate product obtained in step S10a described in the embodiment of the present invention.

[0053] Figure 2 It is a cross-sectional view of the intermediate product obtained in step S10b described in the embodiment of the present invention.

[0054] Figure 3 It is a cross-sectional view of the intermediate product obtained in step S10c described in the embodiment of the present invention.

[0055] Figure 4 It is a cross-sectional view of the intermediate product obtained in step S10d described in the embodiment of the present invention.

[0056] Figure 5 It is a cross-sectional view of the intermediate product obtained in step S10e described in the embodiment of the present invention.

[0057] Figure 6 It is a cross-sectional view of the intermediate product obtained in step S10f described in the embodiment of the present invention.

[0058] Figure 7 It is a cross-sectional view of the intermediate product obtained in step S20a described in the embodiment of the present invention.

[0059] Figure 8It is a cross-sectional view of the intermediate product obtained in step S20d described in the embodiment of the present invention.

[0060] Fig. 9 It is a cross-sectional view of the intermediate product obtained in step S30a described in the embodiment of the present invention.

[0061] Fig.10 It is a cross-sectional view of the intermediate product obtained in step S30b described in the embodiment of the present invention.

[0062] Fig.11 It is a cross-sectional view of the intermediate product obtained in step S30c described in the embodiment of the present invention.

[0063] Fig.12 It is a cross-sectional view of the intermediate product obtained in step S30d described in the embodiment of the present invention.

[0064] Fig.13 It is a cross-sectional view of the intermediate product obtained in step S30e described in the embodiment of the present invention.

[0065] Fig.14 It is a cross-sectional view of the intermediate product obtained in step S30f described in the embodiment of the present invention.

[0066] Fig.15 It is a cross-sectional view of the intermediate product obtained in step S31a described in the embodiment of the present invention.

[0067] Fig.16 It is a cross-sectional view of the intermediate product obtained in step S31b described in the embodiment of the present invention.

[0068] Fig.17 It is a cross-sectional view of the intermediate product obtained in step S40 described in the embodiment of the present invention.

[0069] Fig.18 It is a cross-sectional view of the intermediate product obtained in step S50a described in the embodiment of the present invention.

[0070] Fig.19 It is a cross-sectional view of the intermediate product obtained in step S50b described in the embodiment of the present invention.

[0071] Fig. 20 It is a flow chart of a method for preparing a large-board fan-out double-sided antenna packaging structure according to an embodiment of the present invention.

[0072] Fig.21 It is a specific flow chart of step S10 described in the embodiment of the present invention.

[0073] Fig. 22 It is a specific flow chart of step S20 described in the embodiment of the present invention.

[0074] Fig.23It is a specific flow chart of step S30 described in the embodiment of the present invention.

[0075] Figures 1 to 19 middle:

[0076] 1. Carrier board;

[0077] 2. semiconductor chip; 21. first semiconductor chip; 22. second semiconductor chip; 201. bare chip; 202. I / O terminal; 203. connection column;

[0078] 3. peeling layer; 31. first peeling layer; 32. second peeling layer;

[0079] 4. Encapsulation layer; 41. First encapsulation layer; 42. Second encapsulation layer;

[0080] 5. Seed layer;

[0081] 6. Wiring layer; 61. Pad area; 62. Non-pad area;

[0082] 7. Antenna layer;

[0083] 8. Solder mask;

[0084] 9. Metal bumps;

[0085] 101, first photosensitive dry film; 102, first patterned hole; 103, second photosensitive dry film; 104, second patterned hole;

[0086] 11. Filling layer. DETAILED DESCRIPTION

[0087] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0088] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on this patent; in order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0089] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as a limitation on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0090] In the description of the present invention, unless otherwise clearly specified and limited, if the term "connection" or the like appears to indicate the connection relationship between components, the term should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0091] Unless otherwise specified, various raw materials used in the preparation method of the large-board fan-out double-sided antenna packaging structure of the present invention can be purchased commercially or prepared according to conventional methods in the technical field.

[0092] like Fig.19 As shown, an embodiment of the present invention provides a large-board fan-out double-sided antenna packaging structure, including:

[0093] A carrier plate 1 having a first surface and a second surface opposite to each other along a thickness direction thereof;

[0094] A plurality of semiconductor chips 2, wherein the back surfaces of the plurality of semiconductor chips 2 are respectively attached to the first surface and the second surface of the carrier 1 through a peeling layer 3;

[0095] A packaging layer 4 is located on the first surface and the second surface of the carrier 1 and covers the semiconductor chip 2, and the front surface of the semiconductor chip 2 is exposed to the packaging layer 4;

[0096] The transmission layer, the wiring layer 6 and the antenna layer 7 are located on the side of the packaging layer 4 away from the carrier 1, one side of the transmission layer is electrically connected to the packaging layer 4 and the front surface of the semiconductor chip 2, and the other side is electrically connected to the wiring layer 6 and the antenna layer 7, and the wiring layer 6 has a pad area 61 and a non-pad area 62;

[0097] A solder resist layer 8, located at a side of the packaging layer 4 away from the carrier 1 and covering the outside of the antenna layer 7 and the non-pad area 62 of the wiring layer 6;

[0098] The metal bump 9 is welded to the pad area 61 of the wiring layer 6 .

[0099] In this embodiment, unless otherwise specified, the term "covering" refers to wrapping the outer surface of a component that is not in contact with other components. For example, the solder resist layer 8 covers the antenna layer 7, which means that the solder resist layer 8 wraps the outer surface of the antenna layer 7 that is not in contact with the seed layer 5.

[0100] In this embodiment, antenna packaging structures are arranged on both sides of the carrier board 1. The packaging layers 4 on both sides are tightly combined with the carrier board 1, and the surface warping will not be caused by the performance difference of the materials, which can well ensure the accuracy, yield rate and welding stability during production; and the wiring layer 6 and the antenna layer 7 are both arranged on the transmission layer, that is, the wiring layer 6 and the antenna layer 7 are located on the same horizontal plane, which can reduce the volume occupied by the antenna layer 7. Compared with the prior art, the antenna layer 7 of the large-board fan-out double-sided antenna packaging structure of this embodiment occupies a small volume, and the packaging structure is reasonably arranged, which can improve the integration performance of the antenna packaging structure and the efficiency of the antenna, and reduce the power consumption of the antenna packaging structure.

[0101] The size of the large plate in this embodiment is 600 mm*600 mm, but is not limited to this size. In other embodiments, a suitable size can be designed according to specific application products.

[0102] Optionally, the carrier board 1 is made of stainless steel, glass or FR5, so as to facilitate the peeling layer 3 to be attached to the carrier board 1 .

[0103] The peeling layer 3 is a temporary bonding material to facilitate bonding and subsequent separation.

[0104] Optionally, the metal bump 9 is tin solder, silver solder or gold-tin alloy solder. In this embodiment, the metal bump 9 is preferably a tin ball made of tin solder. The tin ball is implanted in the pad area 61 by welding to achieve electrical lead-out of the wiring layer 6 .

[0105] In this embodiment, the semiconductor chip 2 includes a bare chip 201, an I / O terminal 202 located inside the bare chip 201, and a connecting column 203 protruding from the bare chip 201 and electrically connected to the I / O terminal 202, and one end of the connecting column 203 away from the bare chip 201 is parallel to the surface of the packaging layer 4 and connected to the transmission layer. Among them, the connecting column 203 is a metal conductive material, preferably a copper column. The semiconductor chip 2 of this embodiment has its own connecting column 203, which can simplify the subsequent packaging process; and the front side of the semiconductor chip 2 (connecting column 203) faces the side away from the carrier 1. Compared with the front side of the semiconductor chip being set on the side facing away from the carrier, the connection between the semiconductor chip 2 and the carrier 1 is tighter, which can avoid the occurrence of surface warping caused by poor connection tightness.

[0106] Furthermore, the transmission layer includes a dielectric layer attached to the packaging layer 4 and a seed layer 5 attached to the dielectric layer, the dielectric layer has a via hole along its thickness direction to expose the connection column 203 of the semiconductor chip 2, and the seed layer 5 extends into the via hole and is electrically connected to the connection column 203. The dielectric layer is made of ABF (Ajinomoto Build-up Film) or PP (Polypropylene) material, attached to the packaging layer 4, and plays an insulating role. The dielectric layer is not shown in the figure.

[0107] Furthermore, the seed layer 5 includes a titanium metal layer located on the side of the packaging layer 4 away from the carrier 1 and a copper metal layer located on the titanium metal layer. The titanium metal layer has high adhesion, excellent electrical conductivity and uniform thickness, and the copper metal layer can be stably attached to the packaging layer 4 through the titanium metal layer. Optionally, the thickness of the titanium metal layer is 85 to 125 nm, and the thickness of the copper metal layer is 275 to 325 nm.

[0108] Furthermore, the thickness of the antenna layer 7 is less than that of the wiring layer 6 and does not occupy any additional volume. The surface of the antenna layer 7 is a rough surface.

[0109] In this embodiment, the thickness of the antenna layer 7 is not limited and is determined according to the design requirements of the electronic product.

[0110] There is a gap between the pad area 61 of the wiring layer 6 and the solder resist layer 8 to facilitate welding of the metal bumps 9 .

[0111] In this embodiment, the solder resist layer 8 is a photosensitive ink layer. Using photosensitive ink as the solder resist layer 8 can not only protect the wiring layer 6 and the antenna layer 7, but also remove part of the seed layer 5 by exposure and development, thereby simplifying the process.

[0112] Optionally, the material of the encapsulation layer 4 includes polyimide, silicone and EMC (Epoxy Molding Compound). In this embodiment, EMC is preferred, that is, the encapsulation layer 4 is an epoxy resin encapsulation layer, which can make the semiconductor chip 2 stably adhere to the carrier 1 and protect the semiconductor chip 2.

[0113] like Fig. 20 As shown, an embodiment of the present invention also provides a method for preparing a large-board fan-out double-sided antenna packaging structure, comprising the following steps:

[0114] S10, providing a carrier board 1 and a plurality of semiconductor chips 2, and respectively using a packaging layer 4 to package some of the semiconductor chips 2 on a first side of the carrier board 1 and the remaining semiconductor chips 2 on a second side of the carrier board 1, and making the front sides of the semiconductor chips 2 face away from the carrier board 1;

[0115] S20, manufacturing a transmission layer on the packaging layer 4, so that the front surface of the semiconductor chip 2 is electrically connected to the transmission layer;

[0116] S30, manufacturing a wiring layer 6 and an antenna layer 7 on the transmission layer;

[0117] S40, coating a photosensitive ink on a side of the packaging layer 4 away from the carrier 1 to form a solder resist layer 8, and making the solder resist layer 8 cover the non-pad area 62 of the wiring layer 6 and the antenna layer 7, and making the pad area 61 of the wiring layer 6 exposed from the solder resist layer 8;

[0118] S50 , providing a metal bump 9 , and implanting the metal bump 9 into the pad area 61 .

[0119] In step S40 of this embodiment, the photosensitive ink is evenly coated on the packaging layer 4, the non-pad area 62 of the wiring layer 6 and the antenna layer 7 by printing, and then pre-baked.

[0120] In this embodiment, semiconductor chips 2 are packaged on both sides of the carrier 1 in sequence, and the double-sided packaging layer 4 is tightly combined with the carrier 1, so that surface warping will not occur due to material performance differences, and the accuracy, yield rate and welding stability during production can be well guaranteed; after the semiconductor chip 2 is packaged, the double-sided transmission layer, wiring layer 6, antenna layer 7 and solder mask layer 8 can be made at the same time, which can effectively improve production efficiency. The wiring layer 6 and the antenna layer 7 are located on the same horizontal plane, the antenna layer 7 occupies a small volume, and the packaging structure is arranged reasonably, which can improve the integration performance of the antenna packaging structure and the signal transmission efficiency of the antenna, and reduce the power consumption of the antenna packaging structure.

[0121] In this embodiment, the semiconductor chip 2 includes a first semiconductor chip 21 for attaching to the first surface of the carrier 1 and a second semiconductor chip 22 for attaching to the second surface of the carrier 1. The structures of the first semiconductor chip 21 and the second semiconductor chip 22 are exactly the same, and only the positions of the settings are different. Correspondingly, the peeling layer 3 includes a first peeling layer 31 attached to the first semiconductor chip 21 and the first surface of the carrier 1 and a second peeling layer 32 attached to the second semiconductor chip 22 and the second surface of the carrier 1. The structures and materials of the first peeling layer 31 and the second peeling layer 32 are exactly the same, and only the positions of the settings are different; correspondingly, the packaging layer 4 includes a first packaging layer 41 for packaging the first semiconductor chip 21 on the first surface of the carrier 1 and a second packaging layer 42 for packaging the second semiconductor chip 22 on the second surface of the carrier 1. The structures and materials of the first packaging layer 41 and the second packaging layer 42 are exactly the same, and only the positions of the settings are different.

[0122] like Fig.21 As shown, step S10 specifically includes the following steps:

[0123] S10a, providing a carrier board 1 and a first peeling layer 31, and attaching the first peeling layer 31 to the first surface of the carrier board 1 (the obtained intermediate product can refer to Figure 1 ), so as to facilitate the bonding of the first semiconductor chip 21 in step S10b, wherein the first peeling layer 31 is a temporary bonding material;

[0124] S10b, providing a plurality of first semiconductor chips 21, and attaching the first semiconductor chips 21 to the first peeling layer 31 by a chip mounter, with the front side of the first semiconductor chips 21 facing away from the carrier 1 (the intermediate product obtained can refer to Figure 2 );

[0125] S10c, manufacturing a first packaging layer 41 on the first surface of the carrier 1, so that the first packaging layer 41 covers the first surface and the first semiconductor chip 21 (the intermediate product obtained can refer to Figure 3 ), that is, firstly, the EMC plastic packaging material is tightly wrapped around the first semiconductor chip 21 by vacuum pressing, and then the EMC plastic packaging material is cured by high temperature, so as to form a first packaging layer 41 to protect the first semiconductor chip 21;

[0126] S10d, providing a second peeling layer 32, turning over the carrier 1, and attaching the second peeling layer 32 to the second surface of the carrier 1 (the obtained intermediate product can refer to Figure 4 ), so as to facilitate the bonding of the second semiconductor chip 22 in step S10e, wherein the first peeling layer 31 is a temporary bonding material;

[0127] S10e, providing a plurality of second semiconductor chips 22, and attaching the second semiconductor chips 22 to the second peeling layer 32 by a chip mounter, and making the front side of the second semiconductor chips 22 face away from the carrier 1 (the intermediate product obtained can refer to Figure 5 );

[0128] S10f, manufacturing a second packaging layer 42 on the second surface of the carrier 1, so that the second packaging layer 42 covers the second surface and the second semiconductor chip 22 (the obtained intermediate product can refer to Figure 6 ), that is, firstly, the EMC molding compound is tightly wrapped around the second semiconductor chip 22 by vacuum pressing, and then the EMC molding compound is cured by high temperature, thereby forming a second packaging layer 42 to protect the second semiconductor chip 22.

[0129] like Fig. 22 As shown, the step S20 specifically includes the following steps:

[0130] S20a, grinding the first packaging layer 41 and the second packaging layer 42 at the same time, so that the connection pillars 203 of the first semiconductor chip 21 are exposed on the first packaging layer 41, and the connection pillars 203 of the second semiconductor chip 22 are exposed on the second packaging layer 42 (the intermediate product obtained can refer to Figure 7 ); Specifically, the surface of the connection pillar 203 of the first semiconductor chip 21 is flush with the surface of the first packaging layer 41, and the surface of the connection pillar 203 of the second semiconductor chip 22 is flush with the surface of the second packaging layer 42;

[0131] S20b, providing a dielectric layer, and attaching the dielectric layer to the first packaging layer 41 and the second packaging layer 42 after grinding, respectively, to achieve insulation treatment of the first packaging layer 41 and the second packaging layer 42;

[0132] S20c, performing laser drilling (UV laser) on the dielectric layer to form via holes along the thickness direction of the dielectric layer, so that the connection pillars 203 of the first semiconductor chip 21 and the connection pillars 203 of the second semiconductor chip 22 are exposed, which is convenient for subsequent circuit connection;

[0133] S20d, forming a seed layer 5 in the dielectric layer and the via hole by vacuum sputtering, wherein the dielectric layer and the seed layer 5 constitute the transmission layer (the intermediate product obtained can refer to Figure 8 );

[0134] Preferably, the intermediate product obtained in step S20c is first heated in a high vacuum state, and after the moisture and contaminants on the intermediate product are removed, a titanium metal layer with high adhesion, excellent electrical conductivity and uniform thickness is prepared by magnetron sputtering, and the thickness is about 85 to 125 nm. Finally, a copper metal layer is prepared by magnetron sputtering, and the thickness is about 275 to 325 nm. The titanium metal layer and the copper metal layer constitute the seed layer.

[0135] like Fig.23 As shown, the step S30 specifically includes the following steps:

[0136] S30a, providing a first photosensitive dry film 101, and attaching the first photosensitive dry film 101 to the transmission layer (the intermediate product obtained can refer to Fig. 9 );

[0137] S30b, through the first exposure and development process, a first patterned hole 102 having a blind hole and a through hole that exposes the transmission layer from the first photosensitive dry film 101 is formed on the first photosensitive dry film 101 (the intermediate product obtained can refer to Fig.10 );

[0138] S30c, electroplating the first patterned hole 102 to form a filling layer 11 in the first patterned hole 102 (the intermediate product obtained can refer to Fig.11 );

[0139] S30d, providing a second photosensitive dry film 103, attaching the second photosensitive dry film 103 to the first photosensitive dry film 101 and the filling layer 11 (the intermediate product obtained can refer to Fig.12 );

[0140] S30e, through a second exposure and development process, a second patterned hole 104 is formed on the second photosensitive dry film 103 so that part of the filling layer 11 is exposed from the second photosensitive dry film 103, and the part of the filling layer 11 covered by the second photosensitive dry film 103 forms the wiring layer 6 (the intermediate product obtained can refer to Fig.13 );

[0141] S30f, super-roughening the filling layer 11 in the second patterned hole 104, so that the thickness of the filling layer 11 is reduced to form the antenna layer 7, and the roughness reaches the antenna requirement (the intermediate product can refer to Fig.14 ).

[0142] In this embodiment, the first photosensitive dry film 101 and the second photosensitive dry film 103 are both high-resolution photosensitive dry films, which can be evenly attached to the seed layer 5 by a film attaching machine.

[0143] Step S30b specifically includes: using an LDI (Laser Direct Imaging) exposure machine to transfer the required image data to the first photosensitive dry film 101 through UV or laser light, wherein the pattern width of the exposed area in the data is 10-35um, and the pattern width of the non-exposed area is 10-35um, and then removing the first photosensitive dry film 101 in the non-exposed area through development to form a first patterned hole 102, leaving the pattern irradiated by UV or laser light, and the first patterned hole 102 has a blind hole and a through hole that exposes the seed layer 5 of the transmission layer to the first photosensitive dry film 101. The pattern widths of the exposed area and the non-exposed area are not limited to the above ranges, and are determined specifically according to the design requirements of the electronic product.

[0144] Step S30c specifically includes: performing pattern electroplating on the first patterned hole 102 (the exposed portion of the copper metal layer and the blind hole) to form a pure copper filling layer 11, wherein the total thickness of the copper metal layer in the seed layer 5 and the filling layer 11 is 15 to 20 um but not limited to this range, depending on the design requirements of the electronic product, and the blind hole filling fullness is above 95%.

[0145] Step S30e specifically includes: using an LDI exposure machine to transfer the required image data to the second photosensitive dry film 103 through UV or laser light, and then removing the unexposed portion of the second photosensitive dry film 103 through development to form a second patterned hole 104, leaving a pattern irradiated by UV or laser light, and the filling layer 11 covered by the pattern is the wiring layer 6.

[0146] Furthermore, the method for preparing the large-board fan-out double-sided antenna packaging structure of this embodiment further includes step S31 between step S30 and step S40, and step S31 specifically includes the following steps:

[0147] S31a, removing the remaining first photosensitive dry film 101 and the second photosensitive dry film 103 (the obtained intermediate product can refer to Fig.15 );

[0148] S31b, providing an etching solution, using the etching solution to etch the seed layer 5 exposed after the first photosensitive dry film 101 and the second photosensitive dry film 103 are removed, so as to remove the seed layer 5 (the obtained intermediate product can refer to Fig.16 ).

[0149] Further, step S31b includes: firstly, using an etching solution composed of sulfuric acid and hydrogen peroxide to remove the copper metal layer, and then using an etching solution composed of ammonium bifluoride and hydrogen peroxide to remove the titanium metal layer.

[0150] The intermediate product obtained in step S40 is referred to as Fig.17The solder resist layer 8 (photosensitive ink) covers the non-pad area 62 of the wiring layer 6 and the outside of the antenna layer 7 .

[0151] Furthermore, the step S50 specifically includes the following steps:

[0152] S50a, through the third exposure and development process, a through hole is formed on the solder resist layer 8 to expose the pad area 61 of the wiring layer 6 to the solder resist layer 8 (the intermediate product obtained can refer to Fig.18 );

[0153] S50b, providing the metal bump 9, and implanting the metal bump 9 into the pad area 61 (the intermediate product obtained can refer to Fig.19 ).

[0154] After the photosensitive ink is pre-baked in step S40, a solder mask layer 8 is formed; then, an LDI exposure machine is used to transfer the required image data to the solder mask layer 8 through UV or laser light, and then the photosensitive ink of the unexposed part is removed by development treatment to form a through hole that exposes the pad area 61 of the wiring layer 6 to the solder mask layer 8, leaving a pattern irradiated by UV or laser light, and then the solder mask layer 8 is baked and cured; finally, the metal bump 9 is implanted into the pad area 61, and the obtained Fig.19 The large board fan-out double-sided antenna packaging structure shown.

[0155] The carrier board 1 can be separated from the products on both sides thereof by releasing the bonding, thus obtaining the final product.

[0156] In summary, the preparation method of the large-board fan-out double-sided antenna packaging structure of the present invention respectively packages the semiconductor chip and the antenna on the two sides of the carrier board, and the two-sided packaging layers are tightly combined with the carrier board, and will not cause surface warping due to material performance differences. The accuracy, yield and welding stability during production can be well guaranteed, and the packaging efficiency can be effectively improved; the wiring layer and the antenna layer are located on the same horizontal plane, the antenna layer occupies a small volume, and the packaging structure is reasonably arranged, which improves the integration performance of the antenna packaging structure, effectively shortens the signal transmission line of the components in the packaged antenna structure, and reduces the power consumption of the antenna packaging structure.

[0157] It should be noted that the above specific implementations are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art should understand that various modifications, equivalent substitutions, changes, etc. can be made to the present invention. However, these changes, as well as the equivalent substitution of the raw materials of the product of the present invention, the addition of auxiliary components, the selection of specific methods, etc., should all be within the scope of protection of the present invention. In addition, some terms used in the specification and claims of this application are not restrictive, but are only for the convenience of description.

Claims

1. A method for preparing a large-plate fan-out double-sided antenna packaging structure, characterized in that: The following steps are involved: S10, providing a carrier and a plurality of semiconductor chips, and using packaging layers to package some of the semiconductor chips on a first side of the carrier and the remaining semiconductor chips on a second side of the carrier, and making the front sides of the semiconductor chips face away from the carrier; S20, manufacturing a transmission layer on the packaging layer, so that the front surface of the semiconductor chip is electrically connected to the transmission layer; S30, manufacturing a wiring layer and an antenna layer on the transmission layer: S30a, providing a first photosensitive dry film, and attaching the first photosensitive dry film to the transmission layer; S30b, forming a first patterned hole having a blind hole and a through hole for exposing the transmission layer to the first photosensitive dry film through a first exposure and development process; S30c, performing electroplating on the first patterned hole to form a filling layer in the first patterned hole; S30d, providing a second photosensitive dry film, and attaching the second photosensitive dry film to the first photosensitive dry film and the filling layer; S30e, through a second exposure and development process, forming a second patterned hole on the second photosensitive dry film so that part of the filling layer is exposed from the second photosensitive dry film, and the part of the filling layer covered by the second photosensitive dry film forms the wiring layer; S30f, performing super-roughening treatment on the filling layer in the second patterned hole to reduce the thickness of the filling layer to form the antenna layer; S40, coating a photosensitive ink on a side of the packaging layer away from the carrier to form a solder resist layer, and making the solder resist layer cover the non-pad area of ​​the wiring layer and the antenna layer, and making the pad area of ​​the wiring layer exposed to the solder resist layer; S50, providing a metal bump, and implanting the metal bump into the pad area.

2. The method for preparing the large-board fan-out double-sided antenna packaging structure according to claim 1, characterized in that: The step S10 specifically includes the following steps: S10a, providing a carrier board and a first peeling layer, and attaching the first peeling layer to a first surface of the carrier board; S10b, providing a plurality of first semiconductor chips, attaching the first semiconductor chips to the first peeling layer, and making the front surfaces of the first semiconductor chips face the side away from the carrier; S10c, manufacturing a first packaging layer on the first surface of the carrier, so that the first packaging layer covers the first surface and the first semiconductor chip; S10d, providing a second peeling layer, turning over the carrier, and attaching the second peeling layer to the second surface of the carrier; S10e, providing a plurality of second semiconductor chips, attaching the second semiconductor chips to the second peeling layer, and making the front sides of the second semiconductor chips face the side away from the carrier; S10f, manufacturing a second packaging layer on the second surface of the carrier board, so that the second packaging layer covers the second surface and the second semiconductor chip.

3. The method for preparing the large-board fan-out double-sided antenna packaging structure according to claim 2, characterized in that: The step S20 specifically includes the following steps: S20a, grinding the first packaging layer and the second packaging layer simultaneously, so that the connection pillars of the first semiconductor chip are exposed in the first packaging layer, and the connection pillars of the second semiconductor chip are exposed in the second packaging layer; S20b, providing a dielectric layer, and attaching the dielectric layer to the first packaging layer and the second packaging layer after grinding respectively; S20c, performing laser drilling on the dielectric layer to form via holes along the thickness direction of the dielectric layer, so as to expose the connection pillars of the first semiconductor chip and the connection pillars of the second semiconductor chip; S20d, forming a seed layer in the dielectric layer and the via hole by vacuum sputtering, wherein the dielectric layer and the seed layer constitute the transmission layer.

4. The method for preparing the large-board fan-out double-sided antenna packaging structure according to claim 1, characterized in that: Step S31 is further included between step S30 and step S40, and step S31 specifically includes the following steps: S31a, removing the remaining first photosensitive dry film and the second photosensitive dry film; S31b, providing an etching solution, and using the etching solution to etch the seed layer exposed after the first photosensitive dry film and the second photosensitive dry film are removed, so as to remove the seed layer.

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