Integrated circuit device and method of operating the integrated circuit device

Abstract

An integrated circuit device and an operating method of the integrated circuit device are disclosed. The integrated circuit device includes a shuffler, a logic unit, and registers each including two or more bit storage devices. The shuffler receives an address indicating one of the multiple registers and multiple data bits, selects multiple target bit storage devices to store the multiple data bits from the multiple bit storage devices of the multiple registers according to a shuffle configuration and the address, stores the multiple data bits in the multiple target bit storage devices, and transmits the multiple data bits from the multiple target bit storage devices according to the shuffle configuration. The logic unit receives the multiple data bits transmitted from the shuffler and performs an operation using the received multiple data bits. The shuffle configuration is adjusted when a reset operation is performed.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2018-0053296 filed on May 9, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept herein relates to a semiconductor device, and more particularly, to an integrated circuit device for improving security of received data and an operating method of the integrated circuit device. Background Art

[0003] Semiconductor devices are used in various fields, some of which require security. For example, smart cards can perform encryption and decryption using keys. The encryption or decryption may be based on the Advanced Encryption Standard (AES).

[0004] For the purpose of performing encryption and decryption, a key may be provided to the AES engine. However, when the key is transmitted to the AES engine, the key may be leaked in a variety of ways, such as side channel attacks (SCA). In the event that the key is leaked, the smart card may be hacked.

[0005] Thus, security is required to prevent data from being leaked in the process of transferring data. The inventive concept is directed to an integrated circuit device and an operating method of the integrated circuit device having improved security to prevent data leakage. Summary of the invention

[0006] Embodiments of the inventive concept provide an integrated circuit device that transmits or receives a plurality of data bits with improved security and an operating method of the integrated circuit device.

[0007] An embodiment of the inventive concept provides an integrated circuit device, comprising: a plurality of registers, each including two or more bit storages; a shuffler, receiving an address indicating one of the plurality of registers and a plurality of data bits, selecting a plurality of target bit storage devices to store the plurality of data bits from the plurality of bit storage devices of the plurality of registers according to a shuffle configuration and the address, storing the plurality of data bits in the plurality of target bit storage devices, and transmitting the plurality of data bits from the plurality of target bit storage devices according to the shuffle configuration; a logic unit, receiving the plurality of data bits transmitted from the shuffler, and operating using the received plurality of data bits. The shuffle configuration is adjusted when a reset operation is performed.

[0008] An embodiment of the inventive concept also provides an integrated circuit device, comprising: a processor core, outputting an address and a key including two or more data bits; a power manager, activating a reset signal when a reset operation is performed; a random number generator, generating a random number in response to the reset signal; a peripheral circuit, storing the key in response to the address and the random number, and performing encryption or decryption in response to the key. The peripheral circuit comprises: a plurality of registers, each comprising two or more bit storage devices; a shuffler, adjusting a plurality of target bit storage devices to store the key from among the plurality of bit storage devices of the plurality of registers according to the address and the random number.

[0009] An embodiment of the inventive concept also provides an operating method of an integrated circuit device, wherein the integrated circuit device includes a register, a shuffler, and a logic unit. The operating method includes: in response to a detected reset, receiving a random number by the shuffler; receiving the address and the plurality of data bits by the shuffler; selecting, by the shuffler, a plurality of bit storage devices of the plurality of registers as a plurality of target bit storage devices according to the random number and the address; and storing, by the shuffler, the plurality of data bits in the plurality of target bit storage devices.

[0010] An embodiment of the inventive concept also provides an integrated circuit, comprising: a plurality of registers; a random number generator, generating a random number in response to a power reset operation; a shuffler, receiving the random number, an address, and a plurality of data bits having a first order. The shuffler generates the plurality of converted data bits having a second order by rearranging the plurality of data bits based on the random number, selects a plurality of bit storage devices of a register as a plurality of target bit storage devices from among the plurality of registers based on the address, and stores the plurality of converted data bits in the plurality of target bit storage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present inventive concept will become apparent in consideration of the following detailed description of embodiments of the present inventive concept with reference to the accompanying drawings.

[0012] Figure 1 A block diagram of an integrated circuit device according to an embodiment of the inventive concept is shown.

[0013] Figure 2 A flowchart illustrating an operating method of an integrated circuit device according to an embodiment of the inventive concept.

[0014] Figure 3 A block diagram illustrating peripheral blocks according to an embodiment of the inventive concept.

[0015] Figure 4A diagram showing an example in which a plurality of data bits are stored in a special function register when a shuffle configuration is not applied.

[0016] Figure 5 A diagram showing a method of storing a plurality of data bits to which a shuffling configuration according to a first example is applied.

[0017] Figure 6 A diagram illustrating an example of converting an address according to selected bits of a random number.

[0018] Figure 7 The restorer is shown according to Figure 6 A diagram of an example of an internal transmission path adjusted by a corresponding shuffle configuration.

[0019] Figure 8 A diagram showing a method of storing a plurality of data bits to which a shuffling configuration according to a second example is applied.

[0020] Fig. 9 A diagram illustrating an example of converting an address according to selected bits of a random number.

[0021] Fig.10 The restorer is shown according to Fig. 9 A diagram of an example of an internal transmission path adjusted by a corresponding shuffle configuration.

[0022] Fig.11 A block diagram illustrating peripheral blocks according to an embodiment of the inventive concept.

[0023] Fig.12 A diagram showing a method of storing a plurality of data bits to which a shuffling configuration according to a third example is applied.

[0024] Fig.13 A diagram illustrating an example of converting an address according to a converted address and a plurality of first bits and a plurality of second bits selected from random numbers.

[0025] Fig.14 A block diagram illustrating peripheral blocks according to an embodiment of the inventive concept.

[0026] Fig.15 A diagram showing a method of storing a plurality of data bits to which a shuffling configuration according to a fourth example is applied.

[0027] Fig.16 A block diagram illustrating peripheral blocks according to an embodiment of the inventive concept.

[0028] Fig.17 A diagram showing a method of storing a plurality of data bits to which a shuffling configuration according to a fifth example is applied.

[0029] Fig.18A diagram showing a method of storing a plurality of data bits to which a shuffling configuration according to a sixth example is applied.

[0030] Fig.19 A block diagram illustrating peripheral blocks according to an embodiment of the inventive concept.

[0031] Fig. 20 A block diagram illustrating peripheral blocks according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the inventive concept are described in detail and clearly to such an extent that a person having ordinary skill in the art can easily implement the inventive concept.

[0033] As in the tradition of the field of the present invention, the embodiment can be described and illustrated according to the block of the function or multiple functions of the execution description.These blocks, which may be referred to as units or modules, etc., are physically implemented by analog and / or digital circuits (such as, logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc.), and can be selectively driven by firmware and / or software.For example, the circuit may be implemented in one or more semiconductor chips, or implemented on substrate supports (such as, printed circuit boards, etc.).The circuit constituting the block may be implemented by dedicated hardware, or by a processor (for example, one or more programmed microprocessors and associated circuits) or by a combination of dedicated hardware for executing some functions of the block and a processor for executing other functions of the block.Without departing from the scope of the present invention, each block of the embodiment may be physically divided into two or more interacting and discrete blocks.Similarly, without departing from the scope of the present invention, the block of the embodiment may be physically combined into more complex blocks.

[0034] Figure 1 FIG. 1 is a block diagram of an integrated circuit device 10 according to an embodiment of the inventive concept. Figure 1 The integrated circuit device 10 includes a processor core 11, a random number generator 12, a power manager 13, and a peripheral block 100. The processor core 11 may control the integrated circuit device 10.

[0035] The processor core 11 transmits a plurality of data bits DB and an address AD indicating a location where the plurality of data bits DB are to be stored to the peripheral block 100. For example, the peripheral block 100 may be an encryption and decryption block such as an Advanced Encryption Standard (AES) engine. When encryption and decryption are required, the processor core 11 may transmit a key as the plurality of data bits DB to the peripheral block 100.

[0036] The random number generator 12 generates a random number RN in response to the reset signal RST. Whenever the random number RN is generated, the random number generator 12 may adjust the value of the random number RN. For example, the random number generator 12 may generate the random number RN by using the time of a clock (not shown) provided to the integrated circuit device 10 as a seed.

[0037] The power manager 13 detects a reset or power of the integrated circuit device 10. When the reset or power is detected, the power manager 13 may activate a reset signal RST to be provided to the random number generator 12.

[0038] The peripheral block 100 includes a shuffler 110, a special function register (SFR) 120, and a logic unit 130. The shuffler 110 receives an address AD and a plurality of data bits DB from the processor core 11. The address AD may indicate the location of a plurality of storage devices (e.g., a plurality of bit storage devices) of the special function register 120 where the plurality of data bits DB are to be stored. In an embodiment, the peripheral block 100 may be characterized as a peripheral circuit.

[0039] The shuffler 110 may adjust a shuffle configuration according to the random number RN. The shuffler 110 selects a plurality of target bit storage devices that will store a plurality of data bits DB from among a plurality of bit storage devices of the special function register 120 according to the shuffle configuration and the address AD.

[0040] The shuffler 110 stores the plurality of data bits DB to the plurality of target bit storage devices of the special function register 120. The shuffler 110 may receive the plurality of data bits DB from the plurality of target bit storage devices of the special function register 120 according to the shuffle configuration and may transfer the received plurality of data bits DB to the logic unit 130.

[0041] The logic unit 130 performs a specific operation by using the plurality of data bits DB transferred from the shuffler 110. For example, the logic unit 130 may perform encryption or decryption using the plurality of data bits DB as a key.

[0042] According to an embodiment of the inventive concept, even if the same address AD may be received at different times, the position of the special function register 120 where the plurality of data bits DB are to be stored varies with the shuffle configuration. When the reset signal RST is activated, the shuffle configuration may be adjusted. For example, when a reset operation is performed, or in other words, in response to a reset operation, the shuffler 110 may adjust the shuffle configuration. Therefore, the integrated circuit device 10 is provided with high security, which makes it possible to prevent a side channel attack (SCA) for probing a special function register (SFR) in an attempt to obtain a plurality of data bits DB.

[0043] Figure 2 FIG. 1 is a flowchart showing an operation method of the integrated circuit device 10 according to an embodiment of the inventive concept. Figure 1 and Figure 2 In operation S110, the integrated circuit device 10 is reset. The power manager 13 may activate the reset signal RST. The random number generator 12 may generate a random number RN in response to the activation of the reset signal RST.

[0044] In operation S120, the shuffler 110 adjusts a shuffle configuration according to the random number RN. The shuffle configuration may include some of the multiple bits in the random number RN. In operation S130, the shuffler 110 receives an address AD and multiple data bits DB. In operation S140, the shuffler 110 selects multiple target bit storage devices that will store multiple data bits DB from among the multiple bit storage devices of the special function register 120 according to the shuffle configuration and the address AD.

[0045] In operation S150, the shuffler 110 stores the plurality of data bits DB in the plurality of target bit storage devices. In operation S160, the shuffler 110 provides the plurality of data bits DB transferred from the plurality of target bit storage devices to the logic unit 130 according to the shuffling configuration.

[0046] Figure 3 FIG. 1 is a block diagram of a peripheral block 100 a according to an embodiment of the inventive concept. Figure 3 , the peripheral block 100a includes a shuffler 110a, a special function register 120, and a logic unit 130. The special function register 120 may include a first register 121 to a fourth register 124 (e.g., SFR1 to SFR4). Each of the first register 121 to the fourth register 124 may include two or more bit storage devices. Each of the two or more bit storage devices may include a flip-flop.

[0047] The shuffler 110a includes an address converter 111, an address decoder 112, and a restorer 113. The address converter 111 receives an address AD and a random number RN. The address AD may indicate one of the first to fourth registers 121 to 124. The address converter 111 may convert the address AD by using the random number RN.

[0048] The converted address AD_C may indicate one of the first to fourth registers 121 to 124. The converted address AD_C may be the same as or different from the address AD. The address converter 111 may adjust a plurality of target bit storage devices according to a shuffle configuration by converting the address AD using the random number RN.

[0049] The address converter 111 provides the converted address AD_C to the address decoder 112. The address decoder 112 receives the converted address AD_C and a plurality of data bits DB. The address decoder 112 provides (or stores) the plurality of data bits DB to one of the first to fourth registers 121 to 124 according to the converted address AD_C. For example, the address decoder 112 may provide the plurality of data bits DB to one of the first to fourth registers 121 to 124 as one of the first to fourth information I1 to I4.

[0050] The restorer 113 receives the random number RN. The restorer 113 outputs the first information I1 to the fourth information I4 as the first restoration information RI1 to the fourth restoration information RI4 according to the random number RN. The restorer 113 may adjust the path through which the first information I1 to the fourth information I4 are output as the first restoration information RI1 to the fourth restoration information RI4 according to the random number RN.

[0051] The logic unit 130 may have inputs corresponding to the first to fourth registers 121 to 124, respectively. The inputs are configured to receive the first to fourth restoration information RI1 to RI4, respectively. The restorer 113 may adjust an internal transmission path so that a plurality of data bits DB are transmitted to the input corresponding to the address AD.

[0052] For example, according to the shuffle configuration, the plurality of data bits DB received together with the address AD indicating the first register 121 may be stored in the third register 123 as the third information I3. The restorer 113 may output the third information I3 transmitted from the third register 123 as the first restored information RI1 according to the shuffle configuration. The restorer 113 may transmit the plurality of data bits DB from the plurality of target bit storage devices to the appropriate input of the logic unit 130 according to the shuffle configuration by adjusting the internal transmission path according to the random number RN.

[0053] Figure 4 A diagram showing an example in which a plurality of data bits DB are stored in the special function register 120 when no shuffle configuration is applied. Figure 4 , a plurality of data bits DB are received together with the address AD “01”. The plurality of data bits DB may include a first bit D1 to an eighth bit D8.

[0054] The first to eighth bits D1 to D8 may have an offset bit OFF marked by "000" to "111" according to their positions. The offset bit OFF may not be a value included in the address AD or included in the plurality of data bits DB. The offset bit OFF may be a temporary value specified according to the positions of the first to eighth bits D1 to D8.

[0055] like Figure 4As shown in the embodiment of FIG. 1 , the first register 121 is designated to correspond to the address AD “00”. The second register 122 is designated to correspond to the address AD “01”. The third register 123 is designated to correspond to the address AD “10”. The fourth register 124 is designated to correspond to the address AD “11”. Each of the first to fourth registers 121 to 124 may include a first bit storage device B1 to an eighth bit storage device B8.

[0056] In the case where the shuffle configuration is not applied, according to the address AD "01", the plurality of data bits DB are stored in the second register 122. In the case where the shuffle configuration is not applied, the first bit D1 to the eighth bit D8 are stored in the first bit storage device B1 to the eighth bit storage device B8, respectively. In the case where the shuffle configuration is not applied, the plurality of data bits DB associated with the address AD "01" are usually stored in the second register 122. Therefore, the plurality of data bits DB may be vulnerable to a sideband channel attack.

[0057] Figure 5 A diagram showing a method of storing a plurality of data bits DB to which a shuffle configuration according to a first example is applied. Figure 5 , a plurality of data bits DB are received together with an address AD “01”. The random number RN includes a plurality of bits “1011011100”. The shuffled configuration includes the third and fourth bits from the left among the plurality of bits of the random number RN, ie, “11”.

[0058] The shuffler 110 performs an exclusive OR (XOR) operation using the address AD "01" and a plurality of bits "11" selected from a plurality of bits of the random number RN. The result of the XOR operation is the converted address AD_C. For example, the converted address AD_C in this example is "10". According to the converted address AD_C, the first bit D1 to the eighth bit D8 are stored in the first bit storage device B1 to the eighth bit storage device B8 of the third register 123, respectively.

[0059] Figure 6 A diagram showing an example of converting an address AD according to selected bits of a random number RN. Figure 3 and Figure 6 , when the selected bits of the random number RN are "00", the shuffle configuration may correspond to the first state S1. In the first state S1, the address converter 111 outputs the address AD as the converted address AD_C.

[0060] When the selected bit of the random number RN is "01", the shuffle configuration corresponds to the second state S2. In the second state S2, the address converter 111 converts the addresses AD "00", "01", "10" and "11" into converted addresses AD_C "01", "00", "11" and "10", respectively. When the selected bit of the random number RN is "10", the shuffle configuration corresponds to the third state S3. In the third state S3, the address converter 111 converts the addresses AD "00", "01", "10" and "11" into converted addresses AD_C "10", "11", "00" and "01", respectively.

[0061] When the selected bit of the random number RN is "11", the shuffle configuration corresponds to the fourth state S4. In the fourth state S4, the address converter 111 converts the addresses AD "00", "01", "10" and "11" into converted addresses AD_C "11", "10", "01" and "00", respectively.

[0062] When the integrated circuit device 10 (refer to Figure 1 ) is reset or when power is supplied to the integrated circuit device 10, the random number RN is updated. That is, when the integrated circuit device 10 (refer to Figure 1 ) is reset or when power is supplied to the integrated circuit device 10, the state of the shuffling configuration may be changed.

[0063] When the integrated circuit device 10 is reset or when power is supplied to the integrated circuit device 10, even if the same address AD may be received at different times, the locations of the plurality of target bit storage devices storing the plurality of data bits DB are changed. Therefore, the plurality of data bits DB can be prevented from being leaked through a sideband channel attack.

[0064] Figure 7 The restorer 113 is shown according to Figure 6 A diagram showing an example of an internal transmission path adjusted by a corresponding shuffle configuration. Figure 3 and Figure 7 , when the shuffle configuration corresponds to the first state S1, the restorer 113 outputs the first to fourth information I1 to I4 as first to fourth restored information RI1 to RI4, respectively.

[0065] When the shuffle configuration corresponds to the second state S2, the restorer 113 outputs the first information I1 as the second restored information RI2 and outputs the second information I2 as the first restored information RI1. In addition, the restorer 113 outputs the third information I3 as the fourth restored information RI4 and outputs the fourth information I4 as the third restored information RI3.

[0066] When the shuffle configuration corresponds to the third state S3, the restorer 113 outputs the first information I1 as the third restoration information RI3 and the second information I2 as the fourth restoration information RI4. In addition, the restorer 113 outputs the third information I3 as the first restoration information RI1 and the fourth information I4 as the second restoration information RI2.

[0067] When the shuffle configuration corresponds to the fourth state S4, the restorer 113 outputs the first information I1 as the fourth restoration information RI4 and the second information I2 as the third restoration information RI3. In addition, the restorer 113 outputs the third information I3 as the second restoration information RI2 and the fourth information I4 as the first restoration information RI1.

[0068] Figure 8 A diagram showing a method of storing a plurality of data bits DB to which a shuffle configuration according to a second example is applied. Figure 5 In contrast, the shuffler 110 selects one bit, for example, the third bit from the left (for example, "1"), from the random number RN. In addition, the shuffler 110 selects a portion of the bits of the address AD, for example, the first bit from the left (for example, "0").

[0069] The shuffler 110 performs an XOR operation (e.g., which can be characterized as consisting of Figure 3 The result of the XOR operation is used to replace the selected bit of the address AD. The result of the replacement operation is the converted address AD_C. For example, the converted address AD_C in this example is "11". According to the converted address AD_C, a plurality of data bits DB are stored in the fourth register 124.

[0070] Fig. 9 A diagram showing an example of converting an address AD according to selected bits of a random number RN. Figure 3 and Fig. 9 , when the selected bit of the random number RN is "0", the shuffle configuration corresponds to the first state S1. In the first state S1, the address converter 111 outputs the address AD as the converted address AD_C. When the selected bit of the random number RN is "1", the shuffle configuration corresponds to the second state S2. The second state S2 can be compared with the reference Figure 6 The third state S3 described is the same.

[0071] Fig.10 The restorer 113 is shown according to Fig. 9 A diagram showing an example of an internal transmission path adjusted by a corresponding shuffle configuration. Figure 3 and Fig.10, when the shuffle configuration corresponds to the first state S1, the restorer 113 outputs the first to fourth information I1 to I4 as first to fourth restored information RI1 to RI4, respectively.

[0072] When the shuffle configuration corresponds to the second state S2, the restorer 113 outputs the first information I1 as the third restored information RI3 and the second information I2 as the fourth restored information RI4. In addition, the restorer 113 outputs the third information I3 as the first restored information RI1 and the fourth information I4 as the second restored information RI2.

[0073] With reference Figures 5 to 7 The shuffle configuration described is compared to the reference Figures 8 to 10 The described shuffle configuration performs a limited number of transformation operations. Figure 7 Compared with the restorer 113, Fig.10 The restorer 113 has a reduced number of states. Therefore, the complexity, size and manufacturing cost of the restorer 113 are reduced.

[0074] Fig.11 FIG. 1 is a block diagram of a peripheral block 100 b according to an embodiment of the inventive concept. Fig.11 , the peripheral block 100b includes a shuffler 110b, a special function register 120a and a logic unit 130. The logic unit 130 can be connected to Figure 3 The logic unit 130 is the same.

[0075] The special function register 120a includes a first register 121 to a fifth register 125. The address AD may not be specified for at least one register (e.g., the fifth register 125) among the first register 121 to the fifth register 125 (e.g., SFR1 to SFR5). In other words, in one embodiment, the fifth register 125 is not assigned to the range of the address AD. The fifth register 125 may be characterized as a dummy register including a plurality of dummy bit storage devices. The fifth register 125 may be used to improve the security of a plurality of data bits DB.

[0076] The shuffler 110b includes an address converter 111, an address decoder 112a, and a restorer 113a. The operation and configuration of the address converter 111 may be similar to Figure 3 The address converter 111 is basically the same as Figure 3 Compared with the address decoder 112 of FIG. 1 , the address decoder 112a also receives the random number RN. The address decoder 112a also adjusts the location where the plurality of data bits DB are to be stored according to the shuffling configuration.

[0077] The address decoder 112a provides a plurality of data bits DB to one of the first to fifth registers 121 to 125 as one of the first to fifth information I1 to I5 according to the converted address AD_C and the random number RN. The restorer 113a outputs the first to fifth information I1 to I5 transmitted from the first to fifth registers 121 to 125 to the logic unit 130 as the first to fourth restored information RI1 to RI4.

[0078] Fig.12 A diagram showing a method of storing a plurality of data bits DB to which a shuffle configuration according to a third example is applied. Fig.11 and Fig.12 , the address AD in this example is "01". Figure 5 As described above, the address converter 111 performs an XOR operation on a plurality of bits (eg, a plurality of first bits) selected from the random number RN and the address AD.

[0079] The converted address AD_C in this example is "10". The address decoder 112a refers to the plurality of second bits selected from the random number RN. Therefore, the plurality of second bits selected in this example are the second and third bits from the right among the plurality of bits of the random number RN (e.g., "10"). The address decoder 112a compares (COMP) the plurality of second bits selected from the random number RN with the converted address AD_C.

[0080] When the value of the converted address AD_C is different from the value of the plurality of second bits, the address decoder 112a selects one of the first to fourth registers 121 to 124 according to the converted address AD_C. When the value of the converted address AD_C is the same as the value of the plurality of second bits, the converted address AD_C is determined to satisfy the dummy condition of the shuffle configuration. When the converted address AD_C satisfies the dummy condition, the address decoder 112a selects the first to fourth registers 121 to 124 according to the converted address AD_C. Fig.12 When the converted address AD_C is determined not to satisfy the dummy condition of the shuffle configuration, the address decoder 112a selects one of the first to fourth registers 121 to 124 as indicated by the converted address AD_C.

[0081] According to an embodiment of the inventive concept, the plurality of data bits DB are stored in one of the five registers according to the address AD indicating one of the four registers. Therefore, the security of the plurality of data bits DB can be further improved.

[0082] exist Fig.12, a description is given in which the address decoder 112a selects the fifth register 125 according to the converted address AD_C and a plurality of second bits selected from the random number RN. However, the reference used by the address decoder 112a to select the fifth register 125 is not limited to the converted address AD_C and a plurality of second bits selected from the random number RN.

[0083] Fig.13 A diagram showing an example of converting an address according to a converted address AD_C and a plurality of first bits and a plurality of second bits selected from a random number RN. Fig.11 and Fig.13 , according to a plurality of first bits RN_XOR selected from the random number RN, the shuffle configuration may have a first state S1 to a fourth state S4. The first state S1 to the fourth state S4 may correspond to the reference Figure 6 The first state S1 to the fourth state S4 are described.

[0084] In each of the first state S1 to the fourth state S4, the abnormal condition EXC may be satisfied according to the plurality of second bits RN_COMP selected from the random number RN. When the abnormal condition EXC is satisfied, as shown in FIG. Fig.12 As described above, the address decoder 112a selects the fifth register 125 regardless of the converted address AD_C.

[0085] The plurality of second bits RN_COMP may have values ​​of "00" to "11". In the first state S1 to the fourth state S4, when the value of the converted address AD_C is the same as the value of the plurality of second bits RN_COMP, the abnormal condition EXC may be satisfied. Fig.13 As understood, the value of the address AD satisfying the exception condition EXC varies with the plurality of first bits RN_XOR and the plurality of second bits RN_COMP selected from the random number RN. Therefore, the security of the plurality of data bits DB can be improved.

[0086] In addition to reference Figure 7 In addition to the above configuration, the restorer 113a may be further configured to output the fifth information I5 from the fifth register 125 as one of the first to fourth restoration information RI1 to RI4 when the abnormal condition EXC is satisfied.

[0087] Fig.14 FIG. 1 is a block diagram of a peripheral block 100 c according to an embodiment of the inventive concept. Fig.14 , the peripheral block 100c includes a shuffler 110c, a special function register 120, and a logic unit 130. The configuration and operation of the special function register 120 and the logic unit 130 are similar to those of the reference Figure 3 The configuration and operation described are the same.

[0088] The shuffler 110c includes an address decoder 112, a restorer 113b, and an offset converter 114. The offset converter 114 receives a plurality of data bits DB and a random number RN. The offset converter 114 may convert the offset bit OFF of the plurality of data bits DB according to the random number RN, and may convert the order of the plurality of data bits DB according to the converted offset bit OFF_C. The offset converter 114 outputs the converted plurality of data bits DB_C as a result of the conversion.

[0089] The address decoder 112 receives the address AD and the converted multiple data bits DB_C. The address decoder 112 stores the converted multiple data bits DB_C in one of the first register 121 to the fourth register 124 according to the address AD. The converted multiple data bits DB_C may be stored in one of the first register 121 to the fourth register 124 as one of the first information I1 to the fourth information I4.

[0090] The restorer 113b receives the random number RN. The restorer 113b transmits the first information I1 to the fourth information I4 as the first restored information RI1 to the fourth restored information RI4 to the logic unit 130 according to the random number RN. The restorer 113b can restore the offset bits of the converted plurality of data bits DB_C according to the random number RN, and can restore the plurality of data bits DB by using the restored offset bits.

[0091] Fig.15 A diagram showing a method of storing a plurality of data bits using a shuffle configuration according to a fourth example. Fig.14 and Fig.15 The offset converter 114 identifies the offset bit OFF according to the position (or order) of the first to eighth bits D1 to D8. The offset bit OFF (ie, the first offset bit) indicates the order (ie, the first order) of the plurality of data bits DB.

[0092] The offset converter 114 in this example selects the third to fifth bits from the left among the plurality of bits of the random number RN. The offset converter 114 generates the converted offset bits OFF_C by performing an XOR operation on all the offset bits OFF and the bits selected from the random number RN. For example, the offset converter 114 performs an XOR operation on the offset bits "000" (e.g., D1) of the offset bits OFF and the bits selected from the random number (e.g., "110") to provide the converted offset bits "110" (e.g., D1) of the converted plurality of data bits DB_C. The converted offset bits OFF_C (i.e., the second offset bits) indicate the order of the converted plurality of data bits DB_C (i.e., the second order).

[0093] The offset converter 114 may generate the converted plurality of data bits DB_C by rearranging the first to eighth bits D1 to D8 according to the converted offset bits OFF_C. Fig.15 As shown in , the converted multiple data bits DB_C are rearranged in the order of multiple offset data bits "111" to "000" corresponding to the converted multiple data bits D2, D1, D4, D3, D6, D5, D8 and D7, respectively. Since the address AD is "01", the address decoder 112 stores the converted multiple data bits DB_C in the second register 122.

[0094] The restorer 113b receives the random number RN. The restorer 113b restores the offset bits OFF of the converted plurality of data bits DB_C of the first information I1 to the fourth information I4 by using bits selected from the random number RN, and restores the plurality of data bits DB according to the restored offset bits OFF.

[0095] Reference Figures 3 to 13 The described embodiment adjusts a plurality of target bit storage devices that will store a plurality of data bits DB by adjusting a register that will store a plurality of data bits DB according to a shuffle configuration. Fig.14 and Fig.15 The described embodiment adjusts a plurality of target bit storage devices where a plurality of data bits DB are to be stored by adjusting positions of the plurality of data bits DB to be stored in a register according to a shuffle configuration.

[0096] Fig.16 FIG. 1 is a block diagram of a peripheral block 100 d according to an embodiment of the inventive concept. Fig.16 , the peripheral block 100d includes a shuffler 110d, a special function register 120, and a logic unit 130. The configuration and operation of the special function register 120 and the logic unit 130 are similar to those of the reference Figure 3 The configuration and operation described are the same.

[0097] The shuffler 110d includes an address decoder 112, an offset converter 114a, and first to fourth restorers 113_1 to 113_4. The configuration and operation of the address decoder 112 are similar to those of the reference Fig.14 The configuration and operation described are the same.

[0098] The offset converter 114a receives an address AD, a random number RN, and a plurality of data bits DB. The offset converter 114a selects different bits among a plurality of bits in the random number RN according to the address AD. The offset converter 114a converts the plurality of data bits DB into converted plurality of data bits DB_C according to the bits selected from the random number RN.

[0099] The first restorer 113_1 to the fourth restorer 113_4 receive different bits selected from the random number RN. When the address AD is "00", the first restorer 113_1 receives the selected bit; when the address AD is "01", the second restorer 113_2 receives the selected bit. When the address AD is "10", the third restorer 113_3 receives the selected bit; when the address AD is "11", the fourth restorer 113_4 receives the selected bit. Each of the first restorer 113_1 to the fourth restorer 113_4 can restore the offset of the converted multiple data bits DB_C from the corresponding register according to the bit selected from the random number RN.

[0100] Fig.17 A diagram showing a method of storing a plurality of data bits DB to which a shuffle configuration according to a fifth example is applied. Fig.16 and Fig.17 When the address AD is "00", the offset converter 114a converts the offset bit OFF using a plurality of first bits RN_00 selected from the random number RN. When the address AD is "01", the offset converter 114a converts the offset bit OFF using a plurality of second bits RN_01 selected from the random number RN.

[0101] When the address AD is "10", the offset converter 114a converts the offset bit OFF using the plurality of third bits RN_10 selected from the random number RN. When the address AD is "11", the offset converter 114a converts the offset bit OFF using the plurality of fourth bits RN_11 selected from the random number RN. The selected plurality of first bits RN_00 to the plurality of fourth bits RN_11 may be different from each other.

[0102] With targeting Fig.15 Similarly as described, the offset converter 114a generates the converted multiple data bits DB_C by performing an XOR operation on all the offset bits OFF of the multiple data bits DB and the bits selected from the random number RN. For example, when the address AD is "00", the offset converter 114a performs an XOR operation on the offset bits "000" (e.g., D1) of the offset bits OFF and the bits selected from the random number RN (e.g., "101") to provide the converted multiple offset data bits "101" (e.g., D1) of the converted multiple data bits DB_C. As shown, the converted multiple data bits DB_C are rearranged in the order of the multiple offset data bits "111" to "000" corresponding to the converted multiple data bits D3, D4, D1, D2, D7, D8, D5 and D6, respectively.

[0103] Since the bits of the random number RN are selected differently according to the address AD, the plurality of data bits DB may be converted differently according to the address AD. Fig.17The example is shown as an arrangement order of the first to eighth bits D1 to D8 of the plurality of data bits DB_C to be converted changes as the address AD changes.

[0104] When power is supplied to the integrated circuit device 10 (refer to Figure 1 ) or when the integrated circuit device 10 is reset, the random number RN is updated. Therefore, when power is supplied to the integrated circuit device 10 (refer to Figure 1 ) or when the integrated circuit device 10 is reset, the order in which the first to eighth bits D1 to D8 are rearranged changes with the address AD, and thus, the security of the plurality of data bits DB can be further improved.

[0105] Fig.18 A diagram showing a method of storing a plurality of data bits DB to which a shuffle configuration according to a sixth example is applied. Fig.17 In contrast, the offset converter 114a performs an XOR operation on a portion (e.g., the most significant bit) of the offset bit OFF. The offset converter 114a may select different bits of the random number RN as a plurality of first selection bits RN_00 to a plurality of fourth selection bits RN_11, respectively. For example, when the address AD is "00", the offset converter 114a performs an XOR operation on the most significant bit of the offset bit OFF and the bit "0" (the second bit from the left) of the random number RN to provide a plurality of data bits DB_C that are rearranged as previously described.

[0106] With reference Fig.17 The shuffle configuration described is compared to the reference Fig.18 The described shuffle configuration performs limited transitions with the offset bits OFF. Fig.17 The conversion and recovery of the offset converter 114a and the first recovery 113_1 to the fourth recovery 113_4 are compared to perform Fig.18 The complexity, size, and manufacturing cost of the conversion and recovery offset converter 114 a and the first to fourth restorers 113_1 to 113_4 are reduced.

[0107] In reference Fig.14 and Fig.15 In the described embodiments of the inventive concept, limited conversion can also be applied to examples where a plurality of data bits DB are converted regardless of the address AD. That is, Fig.14 The offset converter 114 in may perform an XOR operation on at least one bit of the address AD and a bit of the random number RN.

[0108] Fig.19 FIG. 1 is a block diagram of a peripheral block 100 e according to an embodiment of the inventive concept. Fig.19, the peripheral block 100e includes a shuffler 110e, a special function register 120, and a logic unit 130. The configuration and operation of the special function register 120 and the logic unit 130 are similar to those of the reference Figure 3 The configuration and operation described are the same.

[0109] The shuffler 110e includes an address converter 111, an address decoder 112, a first restorer 113, an offset converter 114, and a second restorer 115. The configuration and operation of the address converter 111 are similar to those of the reference Figure 3 The configuration and operation of the offset converter 114 are the same as those of the reference Fig.14 The configuration and operation described are the same.

[0110] The configuration and operation of the address decoder 112 are similar to those of the reference numeral 114, except that the converted plurality of data bits DB_C are stored instead of the plurality of data bits DB. Figure 3 The configuration and operation of the first restorer 113 are the same as those described in the reference except that the output of the first restorer 113 is transmitted to the second restorer 115. Figure 3 or Fig.14 The configuration and operation of the second restorer 115 are the same as those described in the reference except that the input of the second restorer 115 is transmitted from the first restorer 113. Figure 3 or Fig.14 The first restorer 113 described is the same.

[0111] The shuffler 110 e may adjust a plurality of target bit storage devices that will store the plurality of data bits DB by converting the address AD and rearranging the plurality of data bits DB according to the shuffling configuration.

[0112] The address converter 111 and the offset converter 114 may select different bits of the random number RN. The first recovery 113 may select a bit of the random number RN at the same position as the address converter 111 or the offset converter 114. The second recovery 115 may select a bit of the random number RN at the same position as the offset converter 114 or the address converter 111.

[0113] Fig. 20 FIG. 1 is a block diagram of a peripheral block 100 f according to an embodiment of the inventive concept. Fig. 20 , the peripheral block 100f includes a shuffler 110f, a special function register 120a, and a logic unit 130. The configuration and operation of the special function register 120a and the logic unit 130 are similar to those of FIG. Fig.11 The configuration and operation described are the same.

[0114] The shuffler 110f includes an address converter 111, an address decoder 112a, a first restorer 113a, an offset converter 114a, and second restorers 115_1 to 115_4. The configuration and operation of the address converter 111 are similar to those of FIG. Figure 3 The configuration and operation of the offset converter 114a are the same as those of the reference Fig.16 The configuration and operation described are the same.

[0115] The configuration and operation of the address decoder 112a are similar to those of the reference numeral 114, except that the converted plurality of data bits DB_C are stored instead of the plurality of data bits DB. Fig.11 The configuration and operation of the first restorer 113a are the same as those described in the reference except that the output of the first restorer 113 is transmitted to the second restorers 115_1 to 115_4. Figure 3 The first restorer 113 described is the same.

[0116] The configuration and operation of the second restorers 115_1 to 115_4 are similar to those of the first restorer 113a, except that the inputs of the second restorers 115_1 to 115_4 are transmitted from the first restorer 113a. Fig.16 The configurations and operations of the described first to fourth restorers 113_1 to 113_4 are the same.

[0117] The shuffler 110f may adjust a plurality of target bit storage devices that will store a plurality of data bits DB by converting the address AD and rearranging the plurality of data bits DB according to the shuffle configuration. The plurality of target bit storage devices may be selected from a plurality of bit storage devices whose number is greater than the number of bit storage devices identified by the address AD.

[0118] In the above-mentioned embodiments, the components of the embodiments according to the inventive concept are represented by using the term "block". The "block" can be implemented by various hardware devices (such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), software (such as firmware and applications driven by hardware devices), or a combination of hardware devices and software. In addition, the "block" may include a circuit or intellectual property (IP) implemented by a semiconductor device of an IC.

[0119] According to the inventive concept, the location where multiple data bits are to be stored is specified by a shuffle configuration, and the shuffle configuration is adjusted when a reset operation is performed. Therefore, an integrated circuit device for transmitting or receiving multiple data bits with improved security and an operating method of the integrated circuit device are provided.

[0120] While the inventive concepts have been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concepts as set forth in the following claims.

Claims

1. An integrated circuit device comprising: a plurality of registers each comprising two or more bit storage devices; a shuffler configured to: receive an address indicating one of the plurality of registers and a plurality of data bits, select a plurality of target bit storage devices to store the plurality of data bits from among the plurality of bit storage devices of the plurality of registers according to a shuffle configuration and the address, store the plurality of data bits in the plurality of target bit storage devices, and transfer the plurality of data bits from the plurality of target bit storage devices according to the shuffle configuration; as well as a logic unit configured to: receive the plurality of data bits transmitted from the shuffler and perform an operation using the received plurality of data bits, wherein the shuffler is configured to: adjust the shuffle configuration when a reset operation is performed, Wherein, the shuffler comprises: An address converter configured to: receive the address and generate a converted address from the address according to the shuffle configuration; an address decoder configured to: when the converted address satisfies the dummy condition of the shuffle configuration, select a plurality of first bit storage devices of a first register that is not assigned to the range of the address from among the plurality of registers as the plurality of target bit storage devices, and when the converted address does not satisfy the dummy condition, select a plurality of second bit storage devices of a second register indicated by the converted address from among the plurality of registers as the plurality of target bit storage devices, and transfer the plurality of data bits to the plurality of target bit storage devices; and A restorer is configured to transfer the plurality of data bits from one of the first register and the second register to the logic unit according to the shuffle configuration.

2. The integrated circuit device according to claim 1, wherein: The shuffle configuration includes a random number comprising two or more bits, The address converter is configured to generate the converted address from the address by performing an XOR operation on multiple first bits of the random number and the address, and determine that the fictitious condition is satisfied when the value of the converted address matches the values ​​of multiple second bits of the random number.

3. The integrated circuit device according to claim 2, wherein: The logic unit includes a plurality of inputs corresponding to the address ranges respectively. The restorer is configured to select, based on the dummy condition, an input to which one of the first register and the second register is to be connected from among the plurality of inputs.

4. The integrated circuit device according to claim 1, wherein: The shuffle configuration includes a random number comprising two or more bits, Wherein, the address converter is configured to: generate the converted address by performing an exclusive OR operation on at least one first bit of the random number and at least one second bit of multiple bits of the address, and when the value of the converted address matches the value of at least one second bit of the random number, determine that the fictitious condition is satisfied.

5. The integrated circuit device according to claim 1, wherein: The shuffler also includes: an offset converter configured to generate a plurality of converted data bits by rearranging the plurality of data bits arranged in the first order in a second order according to the shuffle configuration, The restorer is further configured to restore the converted multiple data bits to the multiple data bits from the multiple target bit storage devices according to the shuffle configuration, and transmit the restored multiple data bits to the logic unit.

6. The integrated circuit device according to claim 5, wherein: The shuffle configuration includes a random number comprising two or more bits, Wherein, the offset converter is configured as: generating a plurality of second offset bits indicating the second order by performing an exclusive OR operation on a plurality of first offset bits indicating the first order of the plurality of data bits and a plurality of first bits of the random number, The converted plurality of data bits are generated from the plurality of data bits by rearranging the plurality of data bits according to the plurality of second offset bits.

7. The integrated circuit device according to claim 5, wherein: The shuffle configuration includes a random number comprising two or more bits, Wherein, the offset converter is configured as: selecting a plurality of first bits of a plurality of bits of the random number according to the address, generating a plurality of second offset bits indicating the second order by performing an exclusive OR operation on a plurality of first offset bits indicating the first order of the plurality of data bits and the plurality of first bits of the random number, and The converted plurality of data bits are generated from the plurality of data bits by rearranging the plurality of data bits according to the plurality of second offset bits.

8. The integrated circuit device according to claim 5, wherein: The shuffle configuration includes a random number comprising two or more bits, Wherein, the offset converter is configured as: generating a plurality of second offset bits indicating the second order by performing an exclusive OR operation on at least one of the plurality of first offset bits indicating the first order of the plurality of data bits and at least one second bit of the random number, and The converted plurality of data bits are generated from the plurality of data bits by rearranging the plurality of data bits according to the plurality of second offset bits.

9. The integrated circuit device according to claim 1, wherein: The shuffle configuration includes a random number, When the reset operation is performed, the random number is newly generated.

10. An integrated circuit device comprising: A processor core is configured to: output an address and a key including two or more data bits; The power manager is configured to: activate a reset signal when a reset operation is performed; a random number generator configured to: generate a random number in response to the reset signal; as well as a peripheral circuit configured to: store the key in response to the address and the random number, and perform encryption or decryption in response to the key, Wherein, the peripheral circuit includes: a plurality of registers each comprising two or more bit storage devices; and a shuffler configured to adjust a plurality of target bit storage devices that will store the key from among the plurality of bit storage devices of the plurality of registers according to the address and the random number, Wherein, the shuffler comprises: An address converter configured to: receive the address and generate a converted address from the address according to the random number; and The address decoder is configured to: when the converted address satisfies the dummy condition of the random number, select a plurality of first bit storage devices of the first register that is not allocated to the address range from among the plurality of registers as the plurality of target bit storage devices; when the converted address does not satisfy the dummy condition, select a plurality of second bit storage devices of the second register indicated by the converted address from among the plurality of registers as the plurality of target bit storage devices, and transmit the key to the plurality of target bit storage devices.

11. The integrated circuit device according to claim 10, wherein: The shuffler is configured to adjust the plurality of target bit stores by converting an order of the two or more data bits of the address and the key.

12. The integrated circuit device according to claim 10, wherein: The peripheral circuit also includes: a logic unit configured to perform encryption or decryption using the key, The shuffler is configured to: transmit the key from the plurality of target bit storage devices to the logic unit according to the random number.

13. A method for operating an integrated circuit device, the integrated circuit device comprising a plurality of registers, a shuffler and a logic unit, the method comprising: receiving, by the shuffler, a random number in response to the detected reset; receiving, by the shuffler, an address and a plurality of data bits; The shuffler selects, according to the random number and the address, a plurality of bit storage devices of the plurality of registers as a plurality of target bit storage devices; as well as The shuffler stores the plurality of data bits in the plurality of target bit storage devices, The step of selecting the plurality of bit storage devices of the plurality of registers as the plurality of target bit storage devices comprises: generating a converted address from the address according to the random number, When the converted address satisfies the dummy condition of the random number, a plurality of first bit storage devices of a first register not allocated to the address range are selected from the plurality of registers as the plurality of target bit storage devices, and When the converted address does not satisfy the dummy condition, a plurality of second bit storage devices of a second register indicated by the converted address are selected from among the plurality of registers as the plurality of target bit storage devices.

14. The operating method according to claim 13, further comprising: The plurality of data bits are transferred from the plurality of target bit storage devices to the logic unit by the shuffler according to the random number.

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