Device measurements using two source measure units

Abstract

A test environment includes: a first measurement unit connected to the gate of a MOSFET device; and a second measurement unit connected to the drain of the MOSFET device. The test environment is particularly useful for testing the gate charge of a MOSFET device. In a first stage, the gate of the device is driven with a current while the drain is driven with a constant voltage. As the MOSFET device is turned on, the second measurement unit switches from providing the constant voltage to providing a constant current to the drain of the MOSFET while measuring the drain voltage. The switching of modes is automatic and occurs without user intervention. After the MOSFET device has been driven to VgsMax by the gate current, all relevant data is stored, which can be analyzed and presented to the user in a user interface, or presented in other ways.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a non-provisional application of U.S. Provisional Patent Application No. 62 / 669,252, filed on May 9, 2018, entitled GATE CHARGE MEASUREMENTS USING TWOSOURCE MEASUREMENT UNITS, and claims the benefit of the U.S. Provisional Patent Application, the contents of which are hereby incorporated herein by reference. Technical Field

[0003] The present disclosure relates to systems and methods related to test and measurement systems, and in particular, to test and measurement instrumentation systems for measuring properties of transistors, such as gate charge. Background Art

[0004] A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a special type of MOSFET that is capable of operating at higher or much higher power levels than a standard MOSFET. Power MOSFETs are used in a variety of applications, including high-speed switching devices. The switching speed of the device is largely affected by the internal capacitance, which is often specified in the data sheet for a specific device as input capacitance (Ciss), output capacitance (Coss), and reverse transfer capacitance (Crss). The input and output capacitances are generally derived from the gate-source capacitance (Cgs) and gate-drain capacitance (Cgd). In addition to the various capacitances, the gate charge between the gate and the source (Qgs) and the gate charge between the gate and the drain (Qgd) can also be used to assess the switching performance of the MOSFET.

[0005] The main component of power loss when operating a power MOSFET is largely due to switching. This loss is directly related to the gate charge (Qg) and parasitic capacitance. Therefore, it is important for circuit designers to be able to accurately measure the gate charge (Qg) and other parameters of the power MOSFET.

[0006] Although important, accurately measuring power MOSFET parameters is difficult to accomplish. For example, the JESD24-2 ("Gate Charge Test Method") standard of the JEDEC (Joint Electron Device Engineering Council) specifies that testing the gate charge (Qg) of a power transistor includes the use of a pulsed current generator, a voltage monitor, and a resistive load to make gate charge measurements. Testing equipment parameters according to this standard is complex in terms of setup and can lead to errors.

[0007] Embodiments of the present invention address these and other limitations of the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects, features, and advantages of embodiments of the present disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 is a graph illustrating a typical gate voltage versus gate charge waveform of a power MOSFET and the variation of the operation phase.

[0010] Figure 2 is a graph illustrating typical gate-source voltage, drain voltage, and drain current changes with respect to time waveforms of a power MOSFET according to an embodiment of the present disclosure.

[0011] Figure 3 is a schematic block diagram of an example test and measurement device for implementing embodiments of the present disclosure.

[0012] Figure 4 is a schematic block diagram of an example test and measurement system for measuring parameters of a power MOSFET according to an embodiment of the present disclosure.

[0013] Figure 5 is a state diagram illustrating various states of devices within a test and measurement system for measuring the gate charge of a power MOSFET according to an embodiment of the present disclosure.

[0014] Figure 6 is an example flow chart illustrating operations used by embodiments of the present disclosure for measuring various parameters of a device in accordance with embodiments of the present disclosure.

[0015] Figure 7 is an example of a user interface on a display according to an embodiment of the present disclosure.

[0016] Figure 8 is a graph illustrating an example gate voltage waveform that may be generated by a test and measurement system according to an embodiment of the present disclosure.

[0017] Fig. 9 is a graph illustrating example gate-source voltage, drain voltage, and drain current versus time waveforms displayed by a user interface of a test and measurement system according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] A test and measurement system is disclosed herein that allows a user to make common power device tests using a pair of source measurement units (SMUs). The test may include, for example, measuring the gate charge of a transistor. The embodiments herein follow the JEDEC standard for measuring gate charge, but are implemented using new technology. The JEDEC standard JESD24-x for measuring gate charge is incorporated herein by reference.

[0019] In the embodiments disclosed herein, a fixed test current (I g ) is forced into the gate of a MOS transistor and the measured gate-source voltage (V gs ). A fixed voltage bias is applied to the drain terminal of the MOS transistor. Then, after the transistor is turned on, a fixed current flows to the drain terminal of the MOS transistor and the falling drain voltage is measured. All measurements are made with reference to an accurate clock so that the measured values ​​can be accurately plotted. Figure 1 The variation of a typical gate voltage with respect to the gate charge of a power MOSFET during three phases of operation (Phase I, Phase II, and Phase III) is shown, as described in detail below.

[0020] The gate charge (Q) is the sum of the forced gate current and the time the current is applied (I g dt). Gate-source charge (Q gs ) is the voltage reached (V gs ) The charge required for the start of the almost constant flat region is Figure 1 According to the JEDEC standard, the flat or Miller voltage (V pl ) is defined as when dV gs The voltage plateau region (i.e., phase II) is the region when the MOS transistor is switching from the off state to the on state. The gate charge required to complete this switching (that is, the charge required to switch the device from the beginning of phase II to the end of phase II) is defined as the gate-to-drain charge (Q gd ) and is called the Miller charge. Phase III is the operating phase in which the MOS transistor is turned on and the gate voltage rises from the Miller voltage to the maximum gate voltage (V gsMax ). Total gate charge (Q g ) is the distance from the origin to where the gate-source voltage (V gs ) is equal to the specified maximum value (V gsMax ), i.e., the total charge forced to the gate through all three phases (Phase I, Phase II, and Phase III).

[0021] S1 describes the V gs The slope of the line segment. S2 is the slope of V during phase III. gs The slope of the line segment. Slopes S1 and S2 are used to calculate Q gs and Q gd , as specified in the JESD24-2 standard.

[0022] Figure 2The graph shows typical gate and drain waveforms applied to and / or measured from a connected device as a function of time. As current is forced to the gate of the connected MOS device in Phase I, V gs increases until it reaches the threshold voltage. At this point, at the end of phase I, the drain current (I d ) starts to flow. When C gs When charging, I d Keep constant and drain voltage (V d ) decreases during Phase II. V gs remains constant until it reaches the end of the plateau at the end of phase II. Once C gd To charge, the gate-source voltage (V gs ) starts to increase again in phase III until it reaches the specified maximum gate voltage (V gsMax ).

[0023] According to an embodiment of the present invention, two SMUs (Source Measure Units) are used to source the gate current and provide power to the drain of the device.

[0024] Figure 3 is a block diagram of an example test and measurement instrument 300 (such as an SMU) for implementing embodiments of the present disclosure as disclosed herein. The test and measurement instrument 300 includes one or more input ports 302 and one or more output ports 304 that can be any electrical signaling medium. The ports 302, 304 may include receivers, transmitters, and / or transceivers. The input port 302 is used to receive signals from an attached device (such as a DUT (device under test), a MOSFET, a power MOSFET, or other object under test). The output port 304 is used to carry the generated signal outward from the instrument 300 to be applied to the device or DUT. Examples of output signals include waveforms and constant currents and voltages, and can be applied to one or more devices under test. Each input port 302 is a channel of the test and measurement instrument 300. The input port 302 is coupled to one or more processors 316 to process the signals and / or waveforms received from one or more devices under test at the port 302. The output port 304 can be coupled to the processor 316 or other components within the instrument 300 that generate appropriate output signals. Although in Figure 3 Only one processor 316 is shown in FIG. 3 for ease of illustration, but as will be appreciated by those skilled in the art, multiple processors 316 of different types may be used in combination rather than a single processor 316 .

[0025] The input port 302 may also be connected to a measurement unit within the test instrument 300, which is not depicted for ease of illustration. Such a measurement unit may include any component capable of measuring aspects of a signal received via the input port 302 (e.g., voltage, amperage, amplitude, etc.). The output port 304 may also be connected to various components of the instrument 300, such as a voltage source, a current source, or a waveform generator, which are not depicted for ease of illustration. The test and measurement instrument 300 may include additional hardware and / or processors, such as conditioning circuits, analog-to-digital converters, and / or other circuits for converting the received signal into a waveform for further analysis. The resulting waveform may then be stored in the memory 310 and displayed on the display 312.

[0026] The one or more processors 316 may be configured to execute instructions from the memory 310, and may perform any method and / or associated steps indicated by such instructions, such as displaying the measured values ​​to the coupled device according to the disclosed embodiments. The memory 310 may be implemented as a processor cache, a random access memory (RAM), a read-only memory (ROM), a solid-state memory, (one or more) hard disk drives, or any other memory type. The memory 310 acts as a medium for storing data, computer program products, and other instructions.

[0027] A user input 314 is coupled to the processor 316. The user input 314 may include a keyboard, a mouse, a trackball, a touch screen, and / or any other control device that a user may employ with respect to a user interface on the display 312. The display 312 may be a digital screen, a cathode ray tube-based display, or any other monitor for displaying waveforms, measurements, and other data to a user. Although the components of the test instrument 300 are depicted as being integrated within the test and measurement instrument 300, it will be appreciated by those of ordinary skill in the art that any of these components may be external to the test instrument 300 and may be coupled to the test instrument 300 in any conventional manner (e.g., wired and / or wireless communication media and / or mechanisms). For example, in some embodiments, the display 312 may be remote from the test and measurement instrument 300.

[0028] Figure 4 An example test and measurement system for measuring gate charge using two SMUs is shown. The test and measurement system includes two SMUs 410, 420, which may be Figure 3. For example, the SMUs 410, 420 may be embedded in another device such as the S530 / S540 Parametric Tester or 4200A-SCS System from Keithley Instruments. In some embodiments, the two SMUs 410, 420 may be connected to a processor or any other type of computing device.

[0029] Figure 4 The basic circuit diagram and connections for performing a gate charge test are shown. The forced HI terminal 412 of the SMU 410 is connected to the gate terminal of the MOSFET 430, and the forced gate current (I g ) and the gate-source voltage (V gs The second SMU 420 is connected to the drain of the MOSFET 430 by forcing the HI terminal 422 and providing a specified current compliance (I ds ) will be fixed voltage (V ds ) is applied to the drain.

[0030] During the gate charge test, approximately Figure 2 At the end of Phase 1 described in , the gate voltage is increased and turns on the MOSFET transistor 430. During the transition in the flat region (Phase II), the drain SMU 420 switches from the voltage control mode to the current control mode because the measured drain current exceeds the specified compliance level. The SMU 420 is programmed to d ) rises quickly as MOSFET 430 turns on to make this switch automatically (i.e., without operator intervention). Figure 2 As seen in FIG. 4 , after switching from voltage control mode to current control mode, SMU 420 drives a steady current into the drain of MOSFET 430. In addition to driving the drain current when in current control mode, SMU 420 also measures the voltage at the drain (V d ). The software controls the SMU 420 to return the measured drain current transient and the measured drain voltage during the transition from the off state to the on state.

[0031] Figure 5 5 is a state diagram illustrating various states of devices within a test and measurement system 400 for measuring gate charge of a power MOSFET according to an embodiment of the present disclosure. The state diagram 500 is broken down into three phases: Phase I, Phase II, and Phase III, which correspond to the previous reference Figure 1 and 2In phase I, the MOSFET device 430 is in the off state while SMU1 410 is driving the gate current and measuring the gate voltage and time of the MOSFET 430. Also during phase I, SMU2 420 is driving the drain voltage of the MOSFET 430 while measuring the drain current. During phase II, the MOSFET device 430 is turning on, as determined by SMU2 420 detecting a sudden rise in the drain current, as shown in FIG. Figure 2 When SMU2 420 determines that MOSFET device 430 is turned on, SMU2 420, operating compliantly, automatically switches from driving the drain of MOSFET 430 with a constant voltage to driving the drain of MOSFET 430 with a constant current while monitoring the voltage of the drain. During Phase II, as shown in FIG. Figure 2 As shown in FIG. 4 , the drain voltage decreases as MOSFET 430 turns on. Finally, during Phase III, SMU1 410 and SMU2 420 remain in the same state as during Phase II, with MOSFET 430 fully turned on and the gate voltage increased to its maximum voltage (V gsMax ).

[0032] Figure 6 6 is an example flow chart 600 illustrating operations used by embodiments of the present disclosure for measuring gate charge. In a first operation 610, SMU1 410 is connected to the gate of a MOSFET device to be tested, and input parameters for SMU1 are entered by a user. In a second operation 620, SMU2 420 is connected to the drain of the same MOSFET device, and input parameters for SMU2 are entered by a user. In an operation 630, the LO terminals of both SMUs are connected to the MOSFET source.

[0033] In operation 640, SMU1 410 drives current into the MOSFET gate and measures the gate current, voltage, and time. In operation 650, SMU2 420 forces voltage to the MOSFET drain and measures the drain current and voltage. As described above, the specific voltages and currents sourced or measured by the SMUs 410, 420 are tied to accurate timing maintained internally by the SMUs.

[0034] In operation 660 , SMU2 420 detects that the MOSFET has turned on and switches to current compliance mode when a falling voltage at the drain is measured.

[0035] Operation 670 stores and displays the measured values. After the test is completed, the gate charge is calculated in operation 680, and the results of the test can be output to the user in operation 690. The output can be in graphical form, although the output can also be stored as a data file.

[0036] Before the test is executed, input test parameters are entered in the user interface, an example of which is shown in Figure 7 The input parameters will vary depending on the device and which model of SMU is used. A description of example input parameters that may be used is listed in Table 1.

[0037] Table 1: Example input parameters

[0038]

[0039] First, the SMU numbers (1-8) connected to the gate (gateSMU) and drain (drainSMU) of the MOSFET must be specified. The source terminal is connected to the GNDU or force LO. The magnitude of the current forced to the gate by the gateSMU is the gateCurrent (Ig) parameter. The drain voltage (Vds) is the bias voltage applied to the drain, and drainLimitI is the compliance current of the drain SMU.

[0040] The Coffset parameter (offset capacitance) is used by the test system to correct for offset capacitance, which may negatively affect the measurement results. Depending on the cabling and connections of the measurement system, offset capacitance may be present in the test system. Offset capacitance is typically in the range of single picofarad to hundreds of picofarads. In some embodiments, these offset capacitances can be corrected by the test system.

[0041] Embodiments of the present invention can accurately measure the offset capacitance by first performing a gate charge test with an open circuit (which measures the offset capacitance). The measured offset capacitance can then be entered into the test system during setup, as described below.

[0042] To measure the offset capacitance, the user sets the SMU test parameters as described above with an open circuit, setting the parameters as if the device were connected to the SMU. However, VgsMax is typically set higher for offset measurements than for actual testing. For example, during actual charge gate testing, VgsMax may be set to 5V, while for testing to measure offset capacitance, VgsMax may be set to 50V. Once the parameters are set, a gate charge test is performed with the open circuit.

[0043] After the test is performed with the open circuit, the measured offset capacitance of the system is calculated by software running on both SMUs and output to the user interface as Ceff. The software derives Ceff from the maximum gate voltage, gate current, and time. Because the open circuit is measured during this step, a test status value of -9 or -12 may appear in the test status field after the test is performed, as discussed in further detail below. This is because no device is actually measured during the offset capacitance test, and therefore, there is no flat zone. However, the Ceff value is correct and can be entered in the setup as Coffset, as shown in Figure 7 As shown in the figure.

[0044] Next, the gate charge test can be run on the device using the Coffset parameter calculated during the offset capacitance test, as described above. Note that it is not strictly necessary to know the offset capacitance before running the gate charge test, although more accurate results will be generated when the offset capacitance is used. After the charge test is completed, several parameters are returned from the software. Table 2 lists the description of the various parameters returned.

[0045] Table 2: Example output parameters

[0046]

[0047] The resulting gate-source voltage measured by the test can be plotted as a function of gate charge.The measured parameters can be plotted as a function of time. Figure 8 A typical gate voltage waveform that can be generated from the values ​​measured during a gate charge test is illustrated.

[0048] In addition to plotting Vgs, Vds and Id measurements can also be plotted as a function of gate charge or time. Fig. 9 An example output on a user interface showing all three parameters plotted as a function of gate charge is illustrated. In this example plot, voltage is shown on the Y1 axis and current is plotted on the Y2 axis.

[0049] Each time a test is executed, a test status value is returned to the user interface. Table 3 shows the possible test status values ​​for the test results and their corresponding descriptions and comments.

[0050] Table 3: Example test status values

[0051]

[0052] As will be appreciated by those skilled in the art, various input, output and test state parameters may vary depending on the test and measurement system used and required by a particular test setup. Tables 1, 2 and 3 list parameters and states that may be received and / or output from a test and measurement system.

[0053] Aspects of the present disclosure may operate on specially created hardware, firmware, digital signal processors, or on specially programmed computers including processors that operate according to programmed instructions. As used herein, the terms "controller" or "processor" are intended to include microprocessors, microcomputers, application specific integrated circuits (ASICs), and dedicated hardware controllers. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions executed by one or more computers (including monitoring modules) or other devices, such as, embodied in one or more program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types when executed by processors in computers or other devices. Computer executable instructions may be stored on computer-readable storage media (such as hard disks, optical disks, removable storage media, solid-state memory, random access memory (RAM), etc.). As those skilled in the art will appreciate, the functions of program modules may be combined or distributed as desired in various aspects. Additionally, the functions may be embodied in firmware or hardware equivalents (such as integrated circuits, FPGAs, etc.) in whole or in part. Certain data structures may be used to more efficiently implement one or more aspects of the present disclosure, and such data structures are contemplated within the scope of the computer-executable instructions and computer-usable data described herein.

[0054] The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable storage media, which may be read and executed by one or more processors. Such instructions may be referred to as computer program products. As discussed herein, computer-readable media means any medium accessible by a computing device. As an example and not limitation, computer-readable media may include computer storage media and communication media. Computer storage media means any medium that may be used to store computer-readable information. As an example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disk (DVD), or other optical disk storage, cassette, tape, disk storage or other magnetic storage device, and any other volatile or non-volatile, removable or non-removable medium implemented in any technology. Computer storage media excludes signal transmission of the signal itself and transient forms.

[0055] Aspects of the present disclosure operate in various modified and alternative forms. Specific aspects have been shown in the drawings as examples and are described in detail below. However, it should be noted that the examples disclosed herein are presented for the purpose of clarity of discussion and are not intended to limit the scope of the disclosed general concept to the specific examples described herein, unless expressly limited. Thus, the present disclosure is intended to cover all modifications, equivalents, and alternatives of the described aspects according to the drawings and claims.

[0056] References to embodiments, aspects, examples, etc. in the specification indicate that the described items may include a particular feature, structure, or characteristic. However, each disclosed aspect may or may not necessarily include the particular feature, structure, or characteristic. In addition, such phrases do not necessarily refer to the same aspect unless specifically noted. Further, when a particular feature, structure, or characteristic is described with respect to a particular aspect, such feature, structure, or characteristic may be employed in conjunction with another disclosed aspect, regardless of whether such feature is explicitly described in conjunction with such another disclosed aspect.

[0057] Example

[0058] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more and any combination of the examples described below.

[0059] Example 1: A test system for testing one or more values ​​of a MOSFET device, comprising: a first source measurement unit connected to the gate of the MOSFET device and programmed to drive a predetermined current to the gate of the MOSFET device; and a second source measurement unit connected to the drain of the MOSFET device, the second source measurement unit being configured to drive a predetermined voltage to the drain of the MOSFET device, measure the current of the drain of the MOSFET device, detect whether the drain current exceeds a compliance current, and measure the drain voltage of the MOSFET device over time.

[0060] Example 2 is the test system of Example 1, wherein one of the source measurement units derives and stores data including a MOSFET gate charge over a time period and a MOSFET gate voltage over the same time period.

[0061] Example 3 is a test system according to any one of Examples 1 and 2, wherein one of the source measurement units measures and outputs a gate voltage during the time period and derives a gate charge of the MOSFET during the time period.

[0062] Example 4 is a test system according to any one of Examples 1-3, wherein one of the source measurement units outputs the gate charge in the time period and the MOSFET gate voltage in the time period to a user.

[0063] Example 5 is a test system according to any one of Examples 1-4, wherein one of the source measurement units outputs the gate charge in the time period and the MOSFET gate voltage in the time period in a user interface.

[0064] Example 6 is a test system according to any of Examples 1-5, wherein one of the source measurement units outputs a gate charge during the time period and a MOSFET gate voltage during the time period in a data file.

[0065] Example 7 is the test system of any of Examples 1-6, wherein one of the source measurement units is structured to automatically switch an operation mode without user intervention when a leakage current exceeds a compliance current.

[0066] Example 8 is a method in a test environment, in which a first source / measurement unit is connected to a gate of a MOSFET device, and in which a second source / measurement unit is connected to a drain of the MOSFET device, the method comprising: driving a predetermined current to the gate of the MOSFET device; driving a predetermined voltage to the drain of the MOSFET device; measuring the current of the drain of the MOSFET device; determining whether the measured leakage current is within a compliance limit based on the measured leakage current; and measuring the voltage of the drain of the MOSFET device over time.

[0067] Example 9 is the method of Example 8, further comprising storing data including a MOSFET gate charge over a time period and a MOSFET gate voltage over the same time period.

[0068] Example 10 is a method according to one of Examples 8 or 9, further comprising: deriving a gate charge of the MOSFET from a gate charge during the time period and a gate voltage during the time period.

[0069] Example 11 is a method according to Example 10, further comprising: outputting the gate charge in the time period and the MOSFET gate voltage in the time period to a user.

[0070] Example 12 is a method according to Example 11, wherein outputting the gate charge within the time period includes: displaying gate charge data and gate voltage data on a user interface; or providing gate charge data and gate voltage data in a data file.

[0071] Example 13 is a method according to any of Examples 8-12, further comprising: in response to the current level reaching the compliance limit, automatically switching the operating mode without user intervention.

[0072] Example 14 is one or more computer-readable storage media comprising instructions, which, when executed by one or more processors of a test environment in which a first measurement unit is connected to a gate of a MOSFET device and in which a second measurement unit is connected to a drain of the MOSFET device, causes at least one of the first measurement unit and the second measurement unit to perform the following operations: driving a predetermined current to the gate of the MOSFET device; driving a predetermined voltage to the drain of the MOSFET device; measuring the current of the drain of the MOSFET device; determining whether the drain current has reached a compliance current based on the measured drain current; and measuring the voltage of the drain of the MOSFET device over time.

[0073] Example 15 is one or more computer-readable storage media according to Example 14, further comprising instructions configured to cause at least one of the first measurement unit and the second measurement unit to perform the following operations: storing data including MOSFET gate charge within a time period and MOSFET gate voltage within the same time period.

[0074] Example 16 is one or more computer-readable storage media according to one of Examples 14 and 15, further comprising instructions configured to cause at least one of the first measurement unit and the second measurement unit to perform the following operations: deriving the gate charge of the MOSFET from the gate charge within the time period and the gate voltage within the time period.

[0075] Example 17 is one or more computer-readable storage media according to one of Examples 14-16, further comprising instructions configured to cause at least one of the first measurement unit and the second measurement unit to perform the following operations: outputting the gate charge within the time period and the MOSFET gate voltage within the time period to a user.

[0076] Example 18 is one or more computer-readable storage media according to any one of Examples 14-17, wherein outputting the gate charge within the time period comprises: displaying the gate charge data and the gate voltage data on a user interface.

[0077] Example 19 is one or more computer-readable storage media according to one of Examples 14-18, further comprising instructions configured to cause at least one of the first measurement unit and the second measurement unit to perform the following operations: in response to the leakage current level reaching a compliance limit, automatically switching the operating mode without user intervention.

[0078] The previously described versions of the disclosed subject matter have many advantages that are described or will be apparent to those of ordinary skill in the art. Even so, these advantages or features are not necessarily required in all versions of the disclosed apparatus, system or method.

[0079] Additionally, the written description makes reference to specific features. It should be understood that the disclosure in this specification includes all possible combinations of those specific features. Where a specific feature is disclosed in the context of a particular aspect or example, the feature may also be used in the context of other aspects and examples to the extent possible.

[0080] Furthermore, when reference is made in the present application to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes those possibilities.

[0081] Although specific examples of the present invention have been illustrated and described for purposes of illustration, it should be understood that various modifications may be made without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be limited except as by the appended claims.

Claims

1. A test system for testing one or more values ​​of a MOSFET device, the test system comprising: a first source measurement unit connected to the gate of the MOSFET device and programmed to drive a predetermined current into the gate of the MOSFET device; as well as a second source measurement unit connected to the drain of the MOSFET device, the second source measurement unit being configured to: drive a predetermined voltage to the drain of the MOSFET device, Measuring the current at the drain of the MOSFET device, Detects if the leakage current exceeds the compliance current, and The drain voltage of the MOSFET device is measured over time.

2. The test system of claim 1, wherein one of the source measurement units derives and stores data including a MOSFET gate charge over a time period and a MOSFET gate voltage over the same time period.

3. The test system of claim 2, wherein one of the source measurement units measures and outputs the gate voltage during the time period and derives the gate charge of the MOSFET during the time period. 4 . The test system of claim 2 , wherein one of the source measurement units outputs the gate charge in the time period and the MOSFET gate voltage in the time period to a user. 5 . The test system of claim 4 , wherein one of the source measurement units outputs the gate charge in the time period and the MOSFET gate voltage in the time period in a user interface. 6 . The test system of claim 4 , wherein one of the source measurement units outputs the gate charge during the time period and the MOSFET gate voltage during the time period in a data file.

7. The test system of claim 4, wherein one of the source measurement units is structured to automatically switch an operation mode without user intervention when the leakage current exceeds the compliance current.

8. A method for testing one or more values ​​of a MOSFET device in a test environment, wherein a first source measurement unit is connected to a gate of the MOSFET device, and wherein a second source measurement unit is connected to a drain of the MOSFET device, the method comprising: driving a predetermined current into a gate of the MOSFET device; driving a predetermined voltage to a drain of the MOSFET device; measuring a current at a drain of the MOSFET device; determining, based on the measured leakage current, whether the measured leakage current is within a compliance limit; as well as The voltage at the drain of the MOSFET device is measured over time.

9. The method according to claim 8, further comprising: Data including the MOSFET gate charge over a period of time and the MOSFET gate voltage over the same period of time is stored.

10. The method according to claim 9, further comprising: The gate charge of the MOSFET is derived from the gate charge during the time period and the gate voltage during the time period.

11. The method according to claim 9, further comprising: The gate charge in the time period and the MOSFET gate voltage in the time period are output to the user.

12. The method according to claim 11, wherein outputting the gate charge within the time period comprises: The gate charge data and the gate voltage data are displayed on a user interface; or the gate charge data and the gate voltage data are provided in a data file.

13. The method according to claim 8, further comprising: In response to the current level reaching the compliance limit, the operating mode is automatically switched without user intervention.

14. One or more computer-readable storage media comprising instructions that, when executed by one or more processors of a test environment in which a first source measurement unit is connected to a gate of a MOSFET device and in which a second source measurement unit is connected to a drain of the MOSFET device, cause the first source measurement unit to drive a predetermined current to the gate of the MOSFET device and cause the second source measurement unit to perform the following operations: driving a predetermined voltage to a drain of the MOSFET device; measuring a current at a drain of the MOSFET device; determining, based on the measured leakage current, whether the leakage current has reached a compliance current; as well as The voltage at the drain of the MOSFET device is measured over time.

15. The one or more computer-readable storage media of claim 14, further comprising instructions configured to cause at least one of the first source measurement unit and the second source measurement unit to perform the following operation: store data including MOSFET gate charge over a time period and MOSFET gate voltage over the same time period.

16. The one or more computer-readable storage media of claim 15, further comprising instructions configured to cause at least one of the first source measurement unit and the second source measurement unit to perform the following operation: deriving a gate charge of the MOSFET from a gate charge during the time period and a gate voltage during the time period.

17. The one or more computer-readable storage media of claim 15, further comprising instructions configured to cause at least one of the first source measurement unit and the second source measurement unit to perform the following operation: outputting the gate charge in the time period and the MOSFET gate voltage in the time period to a user.

18. The one or more computer-readable storage media of claim 17, wherein outputting the gate charge during the time period comprises: Display gate charge data and gate voltage data on the user interface.

19. The one or more computer-readable storage media of claim 14, further comprising instructions configured to cause at least one of the first source measurement unit and the second source measurement unit to automatically switch an operating mode without user intervention in response to a leakage current level reaching a compliance limit.

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