An on-off keying demodulator for ultra-wideband radio frequency receiver

Abstract

The invention discloses an on-off keying demodulator applied to an ultra-wideband radio frequency receiver, comprising an envelope detector, a voltage amplifier, a voltage comparator and a pulse width adjustment circuit; the input end of the envelope detector forms the input end of the on-off keying demodulator, the output end of the envelope detector is connected to the input end of the voltage amplifier, the output end of the voltage amplifier is connected to the input end of the voltage comparator, the output end of the voltage comparator is connected to the input end of the pulse width adjustment circuit, and the output end of the pulse width adjustment circuit forms the output end of the on-off keying demodulator. The invention has the characteristics of wide dynamic range and high sensitivity.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an on-off keying (OOK) demodulator applied to an ultra-wideband radio frequency receiver. Background Art

[0002] With the rapid development of integrated circuits and communication technology, high-speed wireless communication technology has become an urgent need for people. Ultra Wide Band (UWB) technology has become one of the most promising communication technologies with its high speed, low power consumption, low cost, easy implementation, large capacity, strong penetration and anti-multipath capabilities, and is regarded as a key technology for the next generation of wireless communications. The ultimate goal of any communication system is to receive the transmitted signal and restore the original information, and ultra-wideband communication systems are no exception. As the core module of an ultra-wideband RF receiver, the demodulator (DM) has a vital impact on the performance of the entire receiver system in terms of sensitivity, dynamic range, power consumption and other indicators. At present, the existing demodulation circuits are either limited by the circuit structure and cannot meet the requirements of a larger dynamic range; or they can only demodulate signals with large input amplitudes and cannot obtain higher sensitivity. Summary of the invention

[0003] Aiming at the problem that the existing demodulation circuit cannot take into account both wide dynamic range and high sensitivity, the present invention provides an on-off keying demodulator applied to an ultra-wideband radio frequency receiver.

[0004] To solve the above problems, the present invention is achieved through the following technical solutions:

[0005] An on-off keying demodulator applied to an ultra-wideband radio frequency receiver comprises an envelope detector, a voltage amplifier, a voltage comparator and a pulse width adjustment circuit; the input end of the envelope detector forms the input end of the on-off keying demodulator, the output end of the envelope detector is connected to the input end of the voltage amplifier, the output end of the voltage amplifier is connected to the input end of the voltage comparator, the output end of the voltage comparator is connected to the input end of the pulse width adjustment circuit, and the output end of the pulse width adjustment circuit forms the output end of the on-off keying demodulator.

[0006] In the above scheme, the pulse width adjustment circuit includes MOS tubes M34-M48, a resistor R18 and a capacitor C9; the sources of the MOS tubes M34, M36, M38, M40, M41, M43 and M47 are all connected to the digital ground DGND; the sources of the MOS tubes M35, M37, M39, M42, M45, M46 and M48 are all connected to the digital power supply DVDD; the gate of the MOS tube M34 is connected to the gate of the MOS tube M35 to form the input terminal CMP of the pulse width adjustment circuit; the drain of the MOS tube M34, the drain of the MOS tube M35, the gate of the MOS tube M36 are connected to the gate of the MOS tube M37; the drain of the MOS tube M36, the drain of the MOS tube M37, the gate of the MOS tube M40, the gate of the MOS tube M38 are connected to the gate of the MOS tube M39; the drain of the MOS tube M38 is connected to the gate of the MOS tube M39; The electrode, the drain of the MOS tube M39, the gate of the MOS tube M44 and the gate of the MOS tube M45 are all connected to one end of the resistor R18; the other end of the resistor R18 is connected to one end of the capacitor C9, the drain of the MOS tube M40, the gate of the MOS tube M41 and the gate of the MOS tube M42; the other end of the capacitor C9 is connected to the digital ground DGND; the drain of the MOS tube M41, the drain of the MOS tube M42, the gate of the MOS tube M43 and the gate of the MOS tube M46 are connected; the drain of the MOS tube M43 is connected to the source of the MOS tube M44; the drain of the MOS tube M44 and the drain of the MOS tube M45 are connected, the drain of the MOS tube M46, the gate of the MOS tube M47 and the gate of the MOS tube M48 are connected; the drain of the MOS tube M47 is connected to the drain of the MOS tube M48, and the output end OUT of the pulse width adjustment circuit is formed.

[0007] In the above scheme, the envelope detector includes MOS tubes M1-M10, resistors R1-R6 and capacitors C1-C4; the sources of MOS tubes M1 and M2 are connected to the ground GND; the sources of MOS tubes M7, M8, M9 and M10 are connected to the power supply VDD; the gate of MOS tube M1 is connected to the bias signal VBIAS through resistor R3; the gate of MOS tube M2 is connected to the bias signal VBIAS through resistor R4; the drain of MOS tube M1, the source of MOS tube M3 and the source of MOS tube M4 are connected; the drain of MOS tube M2, the source of MOS tube M5 and the source of MOS tube M6 are connected; after the gate of MOS tube M3 is connected to the gate of MOS tube M5, the input terminal INP of the envelope detector is formed through capacitor C1; after the gate of MOS tube M4 is connected to the gate of MOS tube M6, the input terminal INP of the envelope detector is formed through capacitor C2 The input terminal INN of the envelope detector is formed; the gate of the MOS tube M3 is connected to the input bias signal IN_VBIAS through the bias resistor R1; the gate of the MOS tube M4 is connected to the input bias signal IN_VBIAS through the resistor R2; the drain of the MOS tube M3, the drain and gate of the MOS tube M7, the gate of the MOS tube M8 and the drain of the MOS tube M6 are connected; the drain of the MOS tube M4 and the drain of the MOS tube M5 are connected to the drain and gate of the MOS tube M9 and the gate of the MOS tube M10; the drain of the MOS tube M8 forms the output terminal DMP of the envelope detector; the drain of the MOS tube M10 forms the output terminal DMN of the envelope detector; the drain of the MOS tube M8 is connected to the ground GND through the parallel resistor R5 and the capacitor C3 respectively; the drain of the MOS tube M10 is connected to the ground GND through the parallel resistor R6 and the capacitor C4 respectively.

[0008] In the above scheme, the voltage amplifier includes MOS tubes M11-M16, resistors R7-R16 and capacitors C5-C8; the sources of MOS tubes M11 and MOS tubes M14 are connected to the ground GND; the gate of MOS tube M11 is connected to the bias signal VBIAS through resistor R11; the drain of MOS tube M11, the source of MOS tube M12 and the source of MOS tube M13 are connected; the gate of MOS tube M12 forms the input terminal DMP of the voltage amplifier through capacitor C5; the gate of MOS tube M13 forms the input terminal DMN of the voltage amplifier through capacitor C6; the gate of MOS tube M12 is connected to the input bias signal IN_VBIAS through bias resistor R7; the gate of MOS tube M13 is connected to the input bias signal IN_VBIAS through bias resistor R8; the drain of MOS tube M12 is divided into two paths, one is connected to the power supply VDD through resistor R9, and the other is connected to the power supply VDD through capacitor C 7 is connected to the gate of the MOS tube M15; the drain of the MOS tube M13 is divided into two paths, one of which is connected to the power supply VDD through the resistor R10, and the other is connected to the gate of the MOS tube M16 through the capacitor C8; the gate of the MOS tube M14 is connected to the bias signal VBIAS through the resistor R16; the drain of the MOS tube M14, the source of the MOS tube M15 and the source of the MOS tube M16 are connected; the gate of the MOS tube M15 is connected to the input bias signal IN_VBIAS through the bias resistor R12; the drain of the MOS tube M15 is connected to the power supply VDD through the resistor R14; the drain of the MOS tube M15 forms the output terminal AMP of the voltage amplifier; the gate of the MOS tube M16 is connected to the input bias signal IN_VBIAS through the bias resistor R13; the drain of the MOS tube M16 is connected to the power supply VDD through the resistor R15; the drain of the MOS tube M15 forms the output terminal AMN of the voltage amplifier.

[0009] In the above scheme, the voltage comparator includes MOS tubes M17-M33 and a resistor R17; the sources of the MOS tubes M17, M24 and M29 are all connected to the ground GND, and the sources of the MOS tubes M20, M21, M22, M23, M32 and M33 are all connected to the power supply VDD; the gate of the MOS tube M17 is connected to the bias signal VBIAS through the resistor R17; the drain of the MOS tube M17, the source of the MOS tube M18 and the source of the MOS tube M19 are connected; the gate of the MOS tube M18 forms the input terminal AMP of the voltage comparator; the gate of the MOS tube M19 forms the input terminal AMN of the voltage comparator; the drain of the MOS tube M18, the gate and drain of the MOS tube M20, and the gate of the MOS tube M21 are connected; the drain of the MOS tube M19, the gate and drain of the MOS tube M22, and the gate of the MOS tube M23 are connected; The drain of the MOS tube M25, the gate and drain of the MOS tube M26, the gate of the MOS tube M27 and the gate of the MOS tube M31 are connected; the drain of the MOS tube M23, the gate of the MOS tube M26, the drain of the MOS tube M27, the gate and drain of the MOS tube M28 and the gate of the MOS tube M30 are connected; the gate and drain of the MOS tube M24 are connected together, and then connected to the source of the MOS tube M25, the source of the MOS tube M26, the source of the MOS tube M27 and the source of the MOS tube M28; the drain of the MOS tube M29, the source of the MOS tube M30 and the source of the MOS tube M31 are connected; the gate of the MOS tube M29, the drain of the MOS tube M30, the gate and drain of the MOS tube M32 and the gate of the MOS tube M33 are connected; the drain of the MOS tube M31 and the drain of the MOS tube M33 are connected to form the output terminal CMP of the voltage comparator.

[0010] Compared with the prior art, the present invention has the following characteristics:

[0011] 1. Considering that the pulse width of the demodulated pulse signal may be inconsistent, a pulse width adjustment circuit is used to achieve uniform pulse width.

[0012] 2. Add a MOS switch controlled by the input signal to the pulse width adjustment circuit, with the gate connected to the input signal, the drain connected to the output of the delay circuit, and the source connected to the ground. When the input signal is high, the MOS tube is turned on, the switch is turned on, and the output level of the delay circuit is immediately pulled down to the ground; when the input signal is low, the MOS tube is turned off, the switch is closed, and the delay circuit composed of the delay resistor and capacitor works, and the output signal is delayed. Using this MOS tube, the pulse output is stabilized, so that the overall circuit can achieve pulse width adjustment.

[0013] 3. Use the envelope detection method for demodulation. First, square the signal to get the square current, and then use RC as the load to convert the current into voltage. At the same time, the RC circuit can be used as a low-pass filter circuit to filter out the high-frequency components of the circuit and obtain the envelope signal.

[0014] 4. The present invention has the characteristics of wide dynamic range and high sensitivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The figure is an overall structural block diagram of an on-off keying demodulator applied to an ultra-wideband radio frequency receiver.

[0016] Figure 2 for Figure 1 Circuit diagram of the envelope detector.

[0017] Figure 3 for Figure 1 Circuit schematic of a medium voltage amplifier.

[0018] Figure 4 for Figure 1 Circuit diagram of the medium voltage comparator.

[0019] Figure 5 for Figure 1 Circuit schematic diagram of the pulse width adjustment circuit in .

[0020] Figure 6 This is a simulation diagram of an on-off keying demodulator used in an ultra-wideband RF receiver, where (a) is the overall circuit simulation result when the input signal is 3mV, and (b) is the simulation result after a partial enlargement of Figure (a). DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific examples.

[0022] See also Figure 1 , an on-off keying demodulator applied to an ultra-wideband radio frequency receiver, mainly composed of an envelope detector, a voltage amplifier, a voltage comparator and a pulse width adjustment circuit. The input end of the envelope detector forms the input end of the on-off keying demodulator, the output end of the envelope detector is connected to the input end of the voltage amplifier, the output end of the voltage amplifier is connected to the input end of the voltage comparator, the output end of the voltage comparator is connected to the input end of the pulse width adjustment circuit, and the output end of the pulse width adjustment circuit forms the output end of the on-off keying demodulator.

[0023] The envelope detector is used to perform envelope detection on the input signal. It is composed of a square circuit and a filter circuit. The square circuit receives the input signal, and then performs a square operation on the input signal to obtain an output current. The current output by the square circuit is converted into a voltage through an RC load and the high-frequency component is filtered out as the final output of the envelope detector. In a preferred embodiment of the present invention, the envelope detector is as follows: Figure 2 As shown, it is composed of MOS tubes M1-M10, resistors R1-R6 and capacitors C1-C4. Among them, MOS tubes M1-M6 are NMOS tubes, and MOS tubes M7-M10 are PMOS tubes. The sources of NMOS tubes M1 and M2 are connected to the ground terminal GND, and the sources of PMOS tubes M7, M8, M9 and M10 are connected to the power supply VDD. The gate of NMOS tube M1 is connected to resistor R3 and then connected to bias VBIAS. The drain of NMOS tube M1 is connected to the source of NMOS tube M3 and the source of NMOS tube M4 respectively. The gate of NMOS tube M2 is connected to resistor R4 and then connected to bias VBIAS. The drain of NMOS tube M2 is connected to the source of NMOS tube M5 and the source of NMOS tube M6 respectively. The gate of the NMOS tube M3 is connected to the input INP through the capacitor C1, and is also connected to the input bias IN_VBIAS through the bias resistor R1. The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M7. The gate of the NMOS tube M4 is connected to the input INN after being connected to the capacitor C2. The gate of the NMOS tube M4 is also connected to the input bias IN_VBIAS after being connected to the resistor R2. The drain of the NMOS tube M4 is connected to the drain of the PMOS tube M9. The gate of the NMOS tube M5 is connected to the gate of the NMOS tube M3, and the drain of the NMOS tube M5 is connected to the drain of the NMOS tube M4. The gate of the NMOS tube M6 is connected to the gate of the NMOS tube M4, and the drain of the NMOS tube M6 is connected to the drain of the NMOS tube M3. The gate and drain of the PMOS tube M7 are connected together and connected to the gate of the PMOS tube M8. The drain of the PMOS tube M8 is connected to the port DMP as an output of the envelope detector, and is connected to the ground terminal GND through a resistor R5 and a capacitor C3. The gate and drain of the PMOS tube M9 are connected together and then connected to the gate of the PMOS tube M10. The drain of the PMOS tube M10 is connected to the port DMN as another output of the envelope detector, and is connected to the ground terminal GND through a resistor R6 and a capacitor C4.

[0024] The voltage amplifier is used to amplify the input signal, and is composed of a two-stage differential amplifier circuit. Figure 3As shown, it is composed of NMOS tubes M11-M16, resistors R7-R16 and capacitors C5-C8. The source of NMOS tube M11 and the source of NMOS tube M14 are both connected to the ground terminal GND. The gate of NMOS tube M11 is connected to the bias VBIAS through resistor R11. The drain of NMOS tube M11 is connected to the source of NMOS tube M12 and the source of NMOS tube M13 respectively. The gate of NMOS tube M12 is connected to the input terminal DMP of the voltage amplifier through capacitor C5 and to the input bias IN_VBIAS through bias resistor R7. The drain of NMOS tube M12 is connected to the power supply VDD through resistor R9 and to the gate of NMOS tube M15 through capacitor C7. The gate of NMOS tube M13 is connected to the input terminal DMN of the voltage amplifier through capacitor C6 and to the input bias IN_VBIAS through bias resistor R8. The drain of the NMOS tube M13 is connected to the power supply VDD through the resistor R10, and is connected to the gate of the NMOS tube M16 through the capacitor C8. The gate of the NMOS tube M14 is connected to the bias VBIAS through the resistor R16. The drain of the NMOS tube M14 is connected to the source of the NMOS tube M15 and the source of the NMOS tube M16 respectively. The gate of the NMOS tube M15 is connected to the input bias IN_VBIAS through the bias resistor R12. The drain of the NMOS tube M15 is connected to the power supply VDD through the resistor R14, and is connected to the output terminal AMP of the voltage amplifier as an output. The gate of the NMOS tube M16 is connected to the input bias IN_VBIAS through the bias resistor R13. The drain of the NMOS tube M16 is connected to the power supply VDD through the resistor R15, and is connected to the output terminal AMN of the voltage amplifier as an output.

[0025] The voltage comparator is used to compare the voltages of two input signals, and is composed of a pre-amplification module, a decision circuit module, and an output buffer module. In a preferred embodiment of the present invention, the voltage comparator is as follows: Figure 4As shown, it is composed of MOS tubes M17-M33 and resistor R17. Among them, MOS tubes M17, M18, M19, M24, M25, M26, M27, M28, M29, M30 and M31 are NMOS tubes, and MOS tubes M20, M21, M22, M23, M32 and M33 are PMOS tubes. The sources of NMOS tubes M17, M24 and M29 are all connected to the ground terminal GND, and the sources of PMOS tubes M20, M21, M22, M23, M32 and M33 are all connected to the power supply VDD. The pre-amplification module is composed of MOS tubes M17-M23, which is a differential amplifier circuit using active load to pre-amplify the input signal. The NMOS tube M17 serves as a tail current tube, and its gate is connected to the bias VBIAS through the bias resistor R17, and its drain is connected to the source of the NMOS tube M18 and the source of the NMOS tube M19 respectively. The gate of the NMOS tube M18 is connected to the input AMP of the voltage comparator, and the drain of the NMOS tube M18 is connected to the drain of the PMOS tube M20. The gate of the NMOS tube M19 is connected to another input AMN of the voltage comparator, and the drain of the NMOS tube M19 is connected to the drain of the PMOS tube M22. The gate and drain of the PMOS tube M20 are connected together and then connected to the gate of the PMOS tube M21. The drain of the PMOS tube M21 is connected to the drain of the NMOS tube M25. The gate and drain of the PMOS tube M22 are connected together and then connected to the gate of the PMOS tube M23. The drain of the PMOS tube M23 is connected to the drain of the NMOS tube M28. The decision circuit module is composed of MOS tubes M24-M28. The circuit uses the positive feedback of the interconnected cross gates of NMOS tubes M26 and M27 to improve the gain of the decision circuit. The gate and drain of NMOS tube M24 are connected together and are respectively connected to the source of NMOS tube M25, the source of NMOS tube M26, the source of NMOS tube M27, and the source of NMOS tube M28. The gate and drain of NMOS tube M25 are connected together and are connected to the gate of NMOS tube M31. The gate of NMOS tube M26 is connected to the drain of NMOS tube M27. The drain of NMOS tube M26 is connected to both the drain of NMOS tube M25 and the gate of NMOS tube M27. The drain of NMOS tube M27 is connected to both the drain of NMOS tube M28 and the gate of NMOS tube M30. The gate and drain of NMOS tube M28 are connected together and are connected to the gate of NMOS tube M30. The output buffer module is composed of MOS tubes M29-M33, which are mainly used to convert the output signal of the judgment circuit into a logic signal. The gate of the NMOS tube M29 is connected to the drain of the PMOS tube M32, and the drain of the NMOS tube M29 is connected to the source of the NMOS tube M30 and the source of the NMOS tube M31 respectively. The drain of the NMOS tube M30 is connected to the drain of the PMOS tube M32. The drain of the NMOS tube M31 is connected to the drain of the PMOS tube M33.The gate and drain of the PMOS tube M32 are connected together and then connected to the gate of the PMOS tube M33. The drain of the PMOS tube M33 is connected to the output CMP of the voltage comparator.

[0026] The pulse width adjustment circuit is used to adjust the pulse width of the input signal to achieve uniform pulse width. In a preferred embodiment of the present invention, the pulse width adjustment circuit is as follows Figure 5As shown, it is composed of MOS tubes M34-M48, resistor R18 and capacitor C9. Among them, MOS tubes M34, M36, M38, M40, M41, M43, M44, and M47 are NMOS tubes, and MOS tubes M35, M37, M39, M42, M45, M46, and M48 are PMOS tubes. The sources of NMOS tubes M34, M36, M38, M40, M41, M43, and M47 are all connected to the digital ground DGND. The sources of PMOS tubes M35, M37, M39, M42, M45, M46, and M48 are all connected to the digital power supply DVDD. The gate of NMOS tube M34 is connected to the gate of PMOS tube M35 and then connected to the input terminal CMP. The drain of NMOS tube M34 is connected to the drain of PMOS tube M35 and then connected to the gate of NMOS tube M36. The gate of the NMOS tube M36 is connected to the gate of the PMOS tube M37, and the drain of the NMOS tube M36 is connected to the drain of the PMOS tube M37 and then connected to the gate of the NMOS tube M40. The gate of the NMOS tube M38 is connected to the gate of the PMOS tube M39 and connected to the drain of the NMOS tube M36. The drain of the NMOS tube M38 is connected to the drain of the PMOS tube M39. The MOS tubes M34-M39 form three buffers for amplifying and shaping the input signal. One end of the resistor R18 is connected to the drain of the NMOS tube M38. The other end of the resistor R18 is connected to the digital ground DGND through the capacitor C9 and is also connected to the drain of the NMOS tube M40. The gate of the NMOS tube M41 is connected to the gate of the PMOS tube M42 and connected to the drain of the NMOS tube M40. After the drain of the NMOS tube M41 is connected to the drain of the PMOS tube M42, it is connected to the gate of the NMOS tube M43 and the gate of the PMOS tube M46. The resistor R18, the capacitor C9 and the MOS tubes M40-M42 form a delay circuit. The pulse width can be controlled by adjusting the value of the capacitor C9. When the input signal is at a high level, the level of the right end of the resistor R18 is immediately pulled down to the ground by controlling the NMOS tube M40; and when the input signal is at a low level, the NMOS tube M40 is cut off, and the voltage signal directly charges the capacitor C9 through the resistor R18. The drain of the NMOS tube M43 is connected to the source of the NMOS tube M44. The gate of the NMOS tube M44 is connected to the gate of the PMOS tube M45 and to the drain of the PMOS tube M39. The drain of the NMOS tube M44 is connected to the drain of the PMOS tube M45 and to the drain of the PMOS tube M46. The gate of the NMOS tube M47 is connected to the gate of the PMOS tube M48 and to the drain of the PMOS tube M46. The drain of the NMOS tube M47 is connected to the drain of the PMOS tube M48 and to the output terminal OUT of the pulse adjustment circuit. The delay circuit and the MOS tubes M43-M48 together realize the function of pulse width adjustment.

[0027] The present invention is designed and simulated using TSMC 0.18um CMOS technology, using dual power supplies of analog power and digital power, both of which have a power supply voltage of 1.8V and a carrier frequency of 4GHz. Figure 6 This is a simulation diagram of the present invention. "PPMin" indicates that a rectangular pulse is used as the baseband signal of PPM. As can be seen from the figure, the baseband signal has an amplitude of 800mV, a pulse width of 4ns, and a period of 20ns. "PPMout" indicates the signal demodulated from TH-UWB with a peak value of 3mV. The simulation results show that the demodulator designed by the present invention can correctly demodulate the input signal, the amplitude of the demodulated signal is 1.8V, and the pulse width is unified.

[0028] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. An on-off keying demodulator for ultra-wideband radio frequency receiver, characterized in that: It includes an envelope detector, a voltage amplifier, a voltage comparator and a pulse width adjustment circuit; The input end of the envelope detector forms the input end of the on-off keying demodulator, the output end of the envelope detector is connected to the input end of the voltage amplifier, the output end of the voltage amplifier is connected to the input end of the voltage comparator, the output end of the voltage comparator is connected to the input end of the pulse width adjustment circuit, and the output end of the pulse width adjustment circuit forms the output end of the on-off keying demodulator; The pulse width adjustment circuit includes MOS tubes M34-M48, a resistor R18 and a capacitor C9; the sources of MOS tubes M34, M36, M38, M40, M41, M43 and M47 are all connected to the digital ground DGND; the sources of MOS tubes M35, M37, M39, M42, M45, M46 and M48 are all connected to the digital power supply DVDD; the gate of MOS tube M34 is connected to the gate of MOS tube M35 to form the input terminal CMP of the pulse width adjustment circuit; the drain of MOS tube M34, the drain of MOS tube M35, the gate of MOS tube M36 and the gate of MOS tube M37 are connected; the drain of MOS tube M36, the drain of MOS tube M37, the gate of MOS tube M40, the gate of MOS tube M38 and the gate of MOS tube M39 are connected; the drain of MOS tube M38, The drain of the MOS tube M39, the gate of the MOS tube M44 and the gate of the MOS tube M45 are all connected to one end of the resistor R18; the other end of the resistor R18 is connected to one end of the capacitor C9, the drain of the MOS tube M40, the gate of the MOS tube M41 and the gate of the MOS tube M42; the other end of the capacitor C9 is connected to the digital ground DGND; the drain of the MOS tube M41, the drain of the MOS tube M42, the gate of the MOS tube M43 and the gate of the MOS tube M46 are connected; the drain of the MOS tube M43 is connected to the source of the MOS tube M44; the drain of the MOS tube M44, the drain of the MOS tube M45 are connected, the drain of the MOS tube M46, the gate of the MOS tube M47 and the gate of the MOS tube M48 are connected; after the drain of the MOS tube M47 is connected to the drain of the MOS tube M48, the output end OUT of the pulse width adjustment circuit is formed; The above-mentioned envelope detector includes MOS tubes M1-M10, resistors R1-R6 and capacitors C1-C4; the sources of MOS tubes M1 and M2 are connected to the ground GND; the sources of MOS tubes M7, M8, M9 and M10 are connected to the power supply VDD; the gate of MOS tube M1 is connected to the bias signal VBIAS through resistor R3; the gate of MOS tube M2 is connected to the bias signal VBIAS through resistor R4; the drain of MOS tube M1, the source of MOS tube M3 and the source of MOS tube M4 are connected; the drain of MOS tube M2, the source of MOS tube M5 and the source of MOS tube M6 are connected; after the gate of MOS tube M3 and the gate of MOS tube M5 are connected, the input terminal INP of the envelope detector is formed through capacitor C1; After the gate of the MOS transistor M4 is connected to the gate of the MOS transistor M6, the input terminal INN of the envelope detector is formed through the capacitor C2; the gate of the MOS transistor M3 is connected to the input bias signal IN_VBIAS through the bias resistor R1; the gate of the MOS transistor M4 is connected to the input bias signal IN_VBIAS through the resistor R2; the drain of the MOS transistor M3, the drain and gate of the MOS transistor M7, the gate of the MOS transistor M8 and the drain of the MOS transistor M6 are connected; the drain of the MOS transistor M4 and the drain of the MOS transistor M5 are connected to the drain and gate of the MOS transistor M9 and the gate of the MOS transistor M10; the drain of the MOS transistor M8 forms the output terminal DMP of the envelope detector; the drain of the MOS transistor M10 forms the output terminal DMN of the envelope detector; the drain of the MOS transistor M8 is connected to the ground GND through the parallel resistor R5 and the capacitor C3 respectively; the drain of the MOS transistor M10 is connected to the ground GND through the parallel resistor R6 and the capacitor C4 respectively.

2. The on-off keying demodulator for ultra-wideband radio frequency receiver according to claim 1, characterized in that: The voltage amplifier includes MOS tubes M11-M16, resistors R7-R16 and capacitors C5-C8; The sources of the MOS tube M11 and the MOS tube M14 are both connected to the ground GND; the gate of the MOS tube M11 is connected to the bias signal VBIAS through the resistor R11; the drain of the MOS tube M11, the source of the MOS tube M12 and the source of the MOS tube M13 are connected; the gate of the MOS tube M12 forms the input terminal DMP of the voltage amplifier through the capacitor C5; the gate of the MOS tube M13 forms the input terminal DMN of the voltage amplifier through the capacitor C6; the gate of the MOS tube M12 is connected to the input bias signal IN_VBIAS through the bias resistor R7; the gate of the MOS tube M13 is connected to the input bias signal IN_VBIAS through the bias resistor R8; the drain of the MOS tube M12 is divided into two paths, one is connected to the power supply VDD through the resistor R9, and the other is connected to the gate of the MOS tube M15 through the capacitor C7; the MOS tube M1 The drain of MOS tube M3 is divided into two paths, one path is connected to the power supply VDD through the resistor R10, and the other path is connected to the gate of MOS tube M16 through the capacitor C8; the gate of MOS tube M14 is connected to the bias signal VBIAS through the resistor R16; the drain of MOS tube M14, the source of MOS tube M15 and the source of MOS tube M16 are connected; the gate of MOS tube M15 is connected to the input bias signal IN_VBIAS through the bias resistor R12; the drain of MOS tube M15 is connected to the power supply VDD through the resistor R14; the drain of MOS tube M15 forms the output terminal AMP of the voltage amplifier; the gate of MOS tube M16 is connected to the input bias signal IN_VBIAS through the bias resistor R13; the drain of MOS tube M16 is connected to the power supply VDD through the resistor R15; the drain of MOS tube M15 forms the output terminal AMN of the voltage amplifier.

3. The on-off keying demodulator for ultra-wideband radio frequency receiver according to claim 1, characterized in that: The voltage comparator includes MOS tubes M17-M33 and a resistor R17; The sources of the MOS tubes M17, M24 and M29 are all connected to the ground GND, and the sources of the MOS tubes M20, M21, M22, M23, M32 and M33 are all connected to the power supply VDD; the gate of the MOS tube M17 is connected to the bias signal VBIAS through the resistor R17; the drain of the MOS tube M17, the source of the MOS tube M18 and the source of the MOS tube M19 are connected; the gate of the MOS tube M18 forms the input terminal AMP of the voltage comparator; the gate of the MOS tube M19 forms the input terminal AMN of the voltage comparator; the drain of the MOS tube M18, the gate and drain of the MOS tube M20, and the gate of the MOS tube M21 are connected; the drain of the MOS tube M19, the gate and drain of the MOS tube M22, and the gate of the MOS tube M23 are connected; the drain of the MOS tube M21, the gate and drain of the MOS tube M25 are connected The gate of the MOS tube M29, the drain of the MOS tube M30, the gate and drain of the MOS tube M32 are connected to the gate of the MOS tube M33; the drain of the MOS tube M23, the gate of the MOS tube M26, the drain of the MOS tube M27, the gate and drain of the MOS tube M28 are connected to the gate of the MOS tube M30; the gate and drain of the MOS tube M24 are connected together, and then connected to the source of the MOS tube M25, the source of the MOS tube M26, the source of the MOS tube M27 and the source of the MOS tube M28; the drain of the MOS tube M29, the source of the MOS tube M30 and the source of the MOS tube M31 are connected; the gate of the MOS tube M29, the drain of the MOS tube M30, the gate and drain of the MOS tube M32 are connected to the gate of the MOS tube M33; the drain of the MOS tube M31 is connected to the drain of the MOS tube M33, and then form the output terminal CMP of the voltage comparator.

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