Integrated circuit including multiple height standard cells and design method thereof

Abstract

An integrated circuit including a multiple height standard cell and a design method thereof are provided. According to an embodiment, the integrated circuit includes a semiconductor substrate, first to third power rails, first to third selection gate lines, and row connection wiring. The first to third power rails on the semiconductor substrate extend in a first direction and are arranged sequentially in a second direction perpendicular to the first direction. The first to third selection gate lines on the semiconductor substrate extend in a second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0072863, filed on June 25, 2018 in the Korean Intellectual Property Office, entitled “Integrated circuit including multiple-height standard cells and design method thereof” is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate generally to semiconductor integrated circuits, and more particularly, to an integrated circuit including a multiple-height standard cell and a method of designing the integrated circuit. Background Art

[0004] Standard cells with fixed functions can be used in the design of integrated circuits. Standard cells have a predetermined architecture and are stored in a cell library. When designing an integrated circuit, standard cells are taken out of the cell library and placed in the desired location on the integrated circuit layout. Then wiring is performed to connect the standard cells to each other and to other cells. Standard cells have a predetermined (or set) architecture, for example, cell width, cell height, cell length, etc. The design efficiency of the integrated circuit can be determined based on the configuration and layout of the standard cells. Summary of the invention

[0005] According to example embodiments, an integrated circuit includes a semiconductor substrate, a first power rail, a second power rail, a third power rail, a first selection gate line, a second selection gate line, a third selection gate line, and a row connection wiring.

[0006] The first power rail, the second power rail, and the third power rail are above the semiconductor substrate, extend in a first direction, and are sequentially arranged in a second direction perpendicular to the first direction. The first selection gate line, the second selection gate line, and the third selection gate line are above the semiconductor substrate, extend in the second direction to pass through a first region between the first power rail and the second power rail, and a second region between the second power rail and the third power rail, and are sequentially arranged in the first direction. The row connection wiring is above the semiconductor substrate and extends in the first direction to connect the first selection gate line and the third selection gate line.

[0007] According to an example embodiment, an integrated circuit includes: a first selection transistor gated by an inverted voltage level of a second selection signal to pull up a first output node; a second selection transistor configured to be gated by a voltage level of the first selection signal to pull down the first output node; a third selection transistor gated by an inverted voltage level of the first selection signal to pull up the first output node; a fourth selection transistor gated by a voltage level of the second selection signal to pull down the first output node; a fifth selection transistor gated by an inverted voltage level of the second selection signal to pull up the second output node; a sixth selection transistor gated by a voltage level of the first selection signal a seventh selection transistor, gated by the inverted voltage level of the first selection signal to pull up the second output node; an eighth selection transistor, gated by the voltage level of the second selection signal to pull down the second output node; a first selection gate line, serving as a gate electrode of the second selection transistor and the sixth selection transistor; a second selection gate line, serving as a gate electrode of the first selection transistor, the fourth selection transistor, the fifth selection transistor and the eighth selection transistor; a third selection gate line, serving as a gate electrode of the third selection transistor and the seventh selection transistor; and a row connection wiring connecting the first selection gate line and the third selection gate line.

[0008] According to an example embodiment, a method for designing an integrated circuit includes receiving input data defining the integrated circuit, providing at least one multiple height standard cell in a standard cell library, performing placement and routing based on the input data and the standard cell library, and generating output data defining the integrated circuit based on the results of the placement and routing. The multiple height standard cell includes a semiconductor substrate, a first power rail, a second power rail, a third power rail, a first selection gate line, a second selection gate line, a third selection gate line, and a row connection wiring as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A plan view of an integrated circuit according to an example embodiment is shown.

[0011] Figure 2 Shows the application Figure 1 An example embodiment of a layout of an integrated circuit.

[0012] Figure 3 A plan view of an example standard cell is shown.

[0013] Figure 4A , 4B and 4C shows Figure 3 Cross-sectional view of a standard cell.

[0014] Figure 5 A circuit diagram of an integrated circuit according to an example embodiment is shown.

[0015] Figure 6 Shown with Figure 5 A plan view of an example embodiment of a layout of a standard cell corresponding to an integrated circuit.

[0016] Fig. 7A , 7B , 7C, 7D and 7E show examples of Figure 6 Cross-sectional view of a standard cell.

[0017] Figure 8 Shown with Figure 5 A plan view of an example embodiment of a layout of a standard cell corresponding to an integrated circuit.

[0018] Fig.9A and 9B According to an example embodiment, Figure 8 Cross-sectional view of a standard cell.

[0019] Fig.10 and 11 Shown with Figure 5 A plan view of an example embodiment of a layout of a standard cell corresponding to an integrated circuit.

[0020] Fig.12 A circuit diagram of an integrated circuit according to an example embodiment is shown.

[0021] Fig.13 and 14 Shown with Fig.12 A plan view of an example embodiment of a layout of a standard cell corresponding to an integrated circuit.

[0022] Fig.15 A circuit diagram of an integrated circuit according to an example embodiment is shown.

[0023] Fig.16 A flowchart of a method of designing an integrated circuit according to an example embodiment is shown.

[0024] Fig.17 A block diagram of a design system for an integrated circuit according to an example embodiment is shown.

[0025] Fig.18 Shows Fig.17 A flowchart of an example operation of the design system.

[0026] Fig.19 A plan view showing a layout of an integrated circuit according to example embodiments is shown.

[0027] Fig. 20A block diagram of a mobile device according to an example embodiment is shown. DETAILED DESCRIPTION

[0028] Various example embodiments will be described more fully below with reference to the accompanying drawings, in which some example embodiments are shown. In the accompanying drawings, the same reference numerals always represent the same elements. Repeated descriptions may be omitted.

[0029] Hereinafter, the structure of the integrated circuit according to the example embodiment is described in a three-dimensional space using a first direction X, a second direction Y, and a third direction Z. The first direction X may be a row direction, the second direction Y may be a column direction, and the third direction Z may be a vertical direction. The first direction X, the second direction Y, and the third direction Z may intersect, for example, may be orthogonal or perpendicular to each other.

[0030] Figure 1 is a diagram showing a layout of an integrated circuit according to an example embodiment. Figure 1 , the integrated circuit 200 may include a first power rail PR1, a second power rail PR2, a third power rail PR3, a first selection gate line GL1, a second selection gate line GL2, a third selection gate line GL3, and a row connection wiring RCW.

[0031] The first, second and third power rails PR1, PR2 and PR3 are formed over the semiconductor substrate and extend in the first direction X. The first, second and third power rails PR1, PR2 and PR3 are spaced apart from each other and are sequentially arranged in the second direction Y.

[0032] The first selection gate line GL1, the second selection gate line GL2, and the third selection gate line GL3 are formed over the semiconductor substrate and extend in the second direction Y to pass through (e.g., extend over) a first region RG1 between the first power rail PR1 and the second power rail PR2 and a second region RG2 between the second power rail PR2 and the third power rail PR3. The first selection gate line GL1, the second selection gate line GL2, and the third selection gate line GL3 are spaced apart from each other and are sequentially arranged in the first direction X.

[0033] The row connection wiring RCW is formed over the semiconductor substrate and extends over the first selection gate line GL1, the second selection gate line GL2, and the third selection gate line GL3 in the first direction X. The row connection wiring RCW may be located in a metal layer over the gate lines GL1, GL2, and GL3. The row connection wiring RCW may be connected to the first selection gate line GL1 and the third selection gate line GL3 via vertical direct contacts VC1 and VC2.

[0034] Through such wiring of the gate lines GL1, GL2, and GL3 and the row connection wiring RCW, the selection node can receive a selection signal. For example, the first selection gate line GL1, the third selection gate line GL3, and the row connection wiring RCW can form a first selection node that receives a first selection signal A, and the second selection gate line GL2 can form a second selection node that receives a second selection signal B.

[0035] Figure 1 A double height standard cell having a first selection gate line GL1, a second selection gate line GL2, and a third selection gate line GL3 in two adjacent regions RG1 and RG2 defined by three power rails PR1, PR2, and PR3 is shown. However, example embodiments may be applied to a layout of a multiple height standard cell in which the first selection gate line GL1, the second selection gate line GL2, and the third selection gate line GL3 are in two or more adjacent regions defined by three or more power rails.

[0036] In this way, through efficient routing of gate lines and connection wirings, using multiple height standard cells including selection nodes, the integrated circuit can occupy a smaller area, and the performance of the integrated circuit can be enhanced.

[0037] Figure 2 It is shown that it can be applied to Figure 1 FIG. 1 is a diagram of an example embodiment of a layout of an integrated circuit. Figure 2 , the integrated circuit 201 may include a first multiplexer MX1 ​​and a second multiplexer MX2. The first multiplexer MX1 ​​may select one of the first input signal C1 and the second input signal D1 based on the first selection signal A and the second selection signal B to output the first output signal Y1. The second multiplexer MX2 may select one of the third input signal C2 and the fourth input signal D2 based on the first selection signal A and the second selection signal B to output the second output signal Y2.

[0038] refer to Figure 1 and Figure 2, the first multiplexer MX1 ​​may be formed in a first region RG1 between the first power rail PR1 and the second power rail PR2, and the second multiplexer MX2 may be formed in a second region RG2 between the second power rail PR2 and the third power rail PR3. The first multiplexer MX1 ​​and the second multiplexer MX2 may receive a first selection signal A and a second selection signal B in common. The first selection signal A may be applied in common to the first multiplexer MX1 ​​and the second multiplexer MX2 through a first selection node formed by connecting the first selection gate line GL1, the third selection gate line GL3, and the row connection wiring RCW. The second selection signal B may be applied in common to the first multiplexer MX1 ​​and the second multiplexer MX2 through a second selection node formed by the second selection gate line GL2.

[0039] In the following, reference Figure 3 , 4A , 4B and 4C describe example structures of standard cells.

[0040] Figure 3 is a diagram showing a layout of an example standard cell, and Figure 4A , 4B and 4C is Figure 3 Cross-sectional view of a standard cell.

[0041] Figure 4A , 4B and 4C show a portion of a standard cell SCL including a fin field effect transistor (FinFET). Figure 4A It is along the AA′ line Figure 3 A cross-sectional view of a standard cell SCL. Figure 4B It is along the BB′ line Figure 3 A cross-sectional view of a standard cell SCL. Figure 4C It is along the CC' line Figure 3 A cross-sectional view of a standard cell SCL.

[0042] refer to Figure 3 , 4A , 4B, and 4C, the standard cell SCL may be formed on the substrate 110 whose upper surface 110A extends in a horizontal direction (eg, a first direction X and a second direction Y).

[0043] In some example embodiments, the substrate 110 may include a semiconductor such as silicon (Si), germanium (Ge), etc., or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InP, etc. In other embodiments, the substrate 110 may have a silicon-on-insulator (SOI) structure. The substrate 110 may include a conductive region such as an impurity-doped well or an impurity-doped structure.

[0044] The standard cell SCL may include a first device region RX1, a second device region RX2, and an active cutting region ACR separating the first device region RX1 and the second device region RX2 along a second direction Y. Each of the first device region RX1 and the second device region RX2 may include a plurality of fin-type active regions AC protruding from the substrate 110 along a third direction Z (see FIG. Figure 4C ).

[0045] The plurality of active regions AC may extend parallel to each other in the first direction X. The device isolation layer 112 may be located between the plurality of active regions AC on the substrate 110 in the second direction Y. The plurality of active regions AC protrude from the device isolation layer 112 in the third direction Z in the form of fins.

[0046] A plurality of gate insulating layers 118 and a plurality of gate lines PC 11, 12, 13, 14, 15, and 16 may be formed on the substrate 110. The gate lines PC 11, 12, 13, 14, 15, and 16 may extend in a direction Y, crossing the plurality of active regions AC. The plurality of gate insulating layers 118 and the plurality of gate lines PC 11, 12, 13, 14, 15, and 16 may cover the upper surface and sidewall of each active region AC and the upper surface of the device isolation layer 112. Specifically, the plurality of gate insulating layers 118 may be located, for example, directly on the upper surface of the device isolation layer 112, and may be located, for example, directly on the upper surface and sidewall of each active region AC extending from the upper surface of the device isolation layer 112 along the third direction Z.

[0047] A plurality of metal oxide semiconductor (MOS) transistors may be formed along the plurality of gate lines PC 11, 12, 13, 14, 15, and 16. The MOS transistor may have a three-dimensional structure in which a channel is formed in an upper surface and both sidewalls of an active region AC.

[0048] The gate insulating layer 118 may be formed of a silicon oxide layer, a high-k dielectric layer, or a combination thereof. A plurality of gate lines PC 11, 12, 13, 14, 15, and 16 may extend on the gate insulating layer 118 across a plurality of active regions AC while covering an upper surface and both sidewalls of each active region AC.

[0049] The mask 122 may be formed on each of the gate lines PC 11, 12, 13, 14, 15, and 16. The sidewalls of the gate insulating layer 118, the gate lines PC, and the mask 122 may be covered by the partition wall 124. Specifically, the partition wall 124 may extend along the gate insulating layer 118, the gate lines PC, and the mask 122 in the third direction Z. Figure 4C In the illustrated cross section, the gate insulating layer 118 may extend along the third direction Z between the gate line PC and the partition wall 124 .

[0050] The gate lines PC 11, 12, 13, 14, 15 and 16 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer and a gap filling metal layer are sequentially stacked. The metal nitride layer and the metal layer may include titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), etc. The metal layer and the metal nitride layer may be formed, for example, by using an atomic layer deposition (ALD) method, a metal organic ALD method and / or a metal organic chemical vapor deposition (MOCVD) method. The conductive capping layer may be used as a protective layer to prevent oxidation of the metal layer surface. In addition, the conductive capping layer may be used as an adhesive layer (for example, a wetting layer) that helps to deposit another conductive layer on the metal layer. The conductive capping layer may be formed of metal nitrides such as TiN, TaN, combinations thereof, etc. The gap filling metal layer may fill the space between the active regions AC and extend on the conductive capping layer. The gap filling metal layer may be formed, for example, of a tungsten (W) layer. The gap-fill metal layer may be formed, for example, by using an ALD method, a CVD method, or a physical vapor deposition (PVD) method.

[0051] A plurality of conductive contacts CA and CB may be located on the first layer LY1 above the active region AC. The plurality of conductive contacts CA and CB include a plurality of first contacts CA 21, 22, 23, 24, 25, 31, 32, 33, 34, and 35 connected to the source / drain regions 116 of the active region AC (see FIG. Figure 4B ) and a plurality of second contacts CB 41, 42 and 43 connected to the gate lines 11, 12, 13, 14, 15 and 16 (see Figure 4A and 4C ).

[0052] The plurality of conductive contacts CA and CB may be insulated from each other by the first interlayer insulating layer 132 covering the active region AC and the gate line GL. Upper surfaces of the plurality of conductive contacts CA and CB may be at substantially the same height as an upper surface of the first interlayer insulating layer 132. The first interlayer insulating layer 132 may be a silicon oxide layer.

[0053] A second interlayer insulating layer 134 and a plurality of lower via contacts V0 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, and 62 passing through the second interlayer insulating layer 134 are positioned on the first interlayer insulating layer 132. The second interlayer insulating layer 134 may be a silicon oxide layer.

[0054] A plurality of wirings M171, 72, 73, 74, 75, 76, 77, and 78 on a second layer LY2 (higher than the first layer LY1, for example, farther from the substrate 110 along the third direction Z) may be located above the second interlayer insulating layer 134. Each wiring M1 may be connected to one of the plurality of conductive contacts CA and CB through one of the plurality of lower via contacts V0 formed between the first layer LY1 and the second layer LY2. Each of the plurality of lower via contacts V0 may be connected to one of the plurality of conductive contacts CA and CB, for example, by passing through the second interlayer insulating layer 134. The plurality of lower via contacts V0 may be insulated from each other by the second interlayer insulating layer 134.

[0055] The wirings 71 to 78 may include internal connection wirings that electrically connect multiple regions in the standard cell SCL. For example, the internal connection wiring 78 may electrically connect the active region AC in the first device region RX1 and the active region AC in the second device region RX2 through the lower via contacts 55 and 58 and the first contacts 24 and 33.

[0056] The wirings 71 and 72 may correspond to the first power rail PR1 and the second power rail PR2, respectively. The first power rail 71 may be connected to the active area AC in the first device region RX1. The second power rail 72 may be connected to the active area AC in the second device region RX2. One of the first power rail 71 and the second power rail 72 may be a wiring for providing a power supply voltage (e.g., a first power supply voltage VDD), and the other of the first power rail 71 and the second power rail 72 may be a wiring for providing a ground voltage (e.g., a second power supply voltage VSS).

[0057] The first power rail 71 and the second power rail 72 may extend parallel to each other on the second layer LY2 along the first direction X. In some example embodiments, the power rails 71 and 72 may be formed substantially simultaneously with other wirings 73 to 78. The wiring M1 may pass through the third interlayer insulating layer 136. The third interlayer insulating layer 136 may insulate the wirings M1 from each other.

[0058] A cell height CH of the standard cell SCL may be defined by a distance between the first power rail 71 and the second power rail 72 along the second direction Y. A cell width CW of the standard cell SCL may be defined along a first direction X parallel to the power rails 71 and 72 .

[0059] Due to the minimum spacing rule, the spacing of the wiring M1 may have to meet some restrictions. For example, the wiring M1 may have to meet restrictions based on the "tip-to-side" constraint and the "corner rounding" constraint. The size, arrangement and spacing of the wiring M1 may be limited by these constraints.

[0060] The lower via contact V0 and the wiring M1 may have a stacked structure of a barrier layer and a wiring conductive layer. The barrier layer may be formed of, for example, TiN, TaN, a combination thereof, etc. The wiring conductive layer may be formed of, for example, W, Cu, an alloy thereof, a combination thereof, etc. The wiring M1 and the lower via contact V0 may be formed using a CVD method, an ALD method, and / or an electroplating method.

[0061] The integrated circuit according to some example embodiments may correspond to a combination of various standard cells. Hereinafter, the same reference numerals or numbers may be used to indicate a signal and a node of the signal. For example, "A" may be used to indicate a first selection signal or a first selection node to which the first selection signal is applied.

[0062] Figure 5 is a circuit diagram illustrating an integrated circuit according to an example embodiment. Figure 5 , the integrated circuit 202 may include a first multiplexer MX1 ​​and a second multiplexer MX2. The first multiplexer MX1 ​​may select one of the first input signal C1 and the second input signal D1 based on the first selection signal A and the second selection signal B to output the first output signal Y1. The second multiplexer MX2 may select one of the third input signal C2 and the fourth input signal D2 based on the first selection signal A and the second selection signal B to output the second output signal Y2.

[0063] The first multiplexer MX1 ​​may include first, second, third and fourth input transistors MP1, MN1, MP3 and MN3, first, second, third and fourth selection transistors MP2, MN2, MP4 and MN4.

[0064] The first selection transistor MP2 is gated by the inverted voltage level of the second selection signal B at its gate electrode, for example, to pull up the first output node Y1 that generates the first output signal Y1. The second selection transistor MN2 is gated by the voltage level of the first selection signal A to pull down the first output node Y1. The third selection transistor MP4 is gated by the inverted voltage level of the first selection signal A to pull up the first output node Y1. The fourth selection transistor MN4 is gated by the voltage level of the second selection signal B to pull down the first output node Y1.

[0065] The first input transistor MP1 is gated by the inverted voltage level of the first input signal C1 to connect the first selection transistor MP2 to the power supply voltage VDD. The second input transistor MN1 is gated by the voltage level of the first input signal C1 to connect the second selection transistor MN2 to the ground voltage VSS. The third input transistor MP3 is gated by the inverted voltage level of the second input signal D1 to connect the third selection transistor MP4 to the power supply voltage VDD. The fourth input transistor MN3 is gated by the voltage level of the second input signal D1 to connect the fourth selection transistor MN4 to the ground voltage VSS.

[0066] The second multiplexer MX2 may include a fifth input transistor MP5 , a sixth input transistor MN5 , a seventh input transistor MP7 , an eighth input transistor MN7 , a fifth selection transistor MP6 , a sixth selection transistor MN6 , a seventh selection transistor MP8 , and an eighth selection transistor MN8 .

[0067] The fifth selection transistor MP6 is gated by the inverted voltage level of the second selection signal B to pull up the second output node Y2 that generates the second output signal Y2. The sixth selection transistor MN6 is gated by the voltage level of the first selection signal A to pull down the second output node Y2. The seventh selection transistor MP8 is gated by the inverted voltage level of the first selection signal A to pull up the second output node Y2. The eighth selection transistor MN8 is gated by the voltage level of the second selection signal B to pull down the second output node Y2.

[0068] The fifth input transistor MP5 is gated by the inverted voltage level of the third input signal C2 to connect the fifth selection transistor MP6 to the power supply voltage VDD. The sixth input transistor MN5 is gated by the voltage level of the third input signal C2 to connect the sixth selection transistor MN6 to the ground voltage VSS. The seventh input transistor MP7 is gated by the inverted voltage level of the fourth input signal D2 to connect the seventh selection transistor MP8 to the power supply voltage VDD. The eighth input transistor MN7 is gated by the voltage level of the fourth input signal D2 to connect the eighth selection transistor MN8 to the ground voltage VSS.

[0069] Figure 6 is shown with Figure 5 FIG. 1 is a diagram of an example embodiment of a layout of a standard cell corresponding to an integrated circuit, Fig. 7A , 7B , 7C, 7D and 7E are according to example embodiments Figure 6 Cross-sectional view of a standard cell. Fig. 7A It is along the DD' line Figure 6 A cross-sectional view of a standard cell SCL. Figure 7B It is along the EE' line Figure 6 A cross-sectional view of a standard cell SCL. Figure 7C It is along the FF′ line Figure 6 A cross-sectional view of a standard cell SCL. Fig.7D It is along the GG′ line Figure 6 A cross-sectional view of a standard cell SCL. Fig. 7E It is along the HH′ line Figure 6 The cross-sectional view of the standard cell SCL can be omitted. Figure 3 , 4A , 4B and 4C are repeated in those descriptions.

[0070] refer to Figure 6 , 7A , 7B, 7C, 7D and 7E, the standard cell in the semiconductor substrate may include a first power rail 271, a second power rail 272, a third power rail 273, a first selection gate line 213, a second selection gate line 214, a third selection gate line 215, a first input gate line 212, a second input gate line 216, dummy gate lines 211 and 217, wiring 274~279 in the first metal layer M1, and a row connection wiring 291 and a column connection wiring 292 in the second metal layer M2.

[0071] The conductive contacts CA and CB and the wiring in the first metal layer M1 may be connected through the lower via contact V0, and the wiring in the first metal layer M1 and the wiring in the second metal layer M2 may be connected through the upper via contact V1. The first metal layer M1 may be the lowest metal layer, or there may be at least one metal layer below the first metal layer M1. The first metal layer M1 and the second metal layer M2 may be adjacent in the third direction Z, or at least one metal layer may be between the first metal layer M1 and the second metal layer M2. The power rails 271, 272, and 273 may be located in the first metal layer M1, as shown in FIG. Figure 6 , 7A , 7B, 7C, 7D and 7E.

[0072] At least one of the gate lines 211 to 217 may be cut or separated by the gate cutting region CT so that the gate line may include a plurality of gate segments. For example, the first selection gate line 213 may include a first gate segment 213a and a second gate segment 213b, and the third selection gate line 215 may include a first gate segment 215a and a second gate segment 215b.

[0073] A first multiplexer MX1 ​​including first to fourth input transistors MP1, MN1, MP3, and MN3 and first to fourth selection transistors MP2, MN2, MP4, and MN4 may be located in a first region RG1 between a first power rail 271 and a second power rail 272. A second multiplexer MX2 including fifth to eighth input transistors MP5, MN5, MP7, and MN7 and fifth to eighth selection transistors MP6, MN6, MP8, and MN8 may be located in a second region RG2 between a second power rail 272 and a third power rail 273. In this way, Figure 6 The standard cell may have a normal standard cell (e.g. Figure 3 The unit height 2CH is twice the unit height CH shown in FIG. Figure 6 A standard cell having a cell height N*CH that is N times (N is an integer greater than 1) the normal cell height CH may be referred to as a double-height standard cell. In general, a standard cell having a cell height N*CH that is N times (N is an integer greater than 1) the normal cell height CH may be referred to as a multiple-height standard cell.

[0074] The first region RG1 may include a first device region RX11, a second device region RX12, and a first active cutting region ACR1. The second region RG2 may include a third device region RX21, a fourth device region RX22, and a second active cutting region ACR2. A region between the first region RG1 and the second region RG2 may be referred to as a boundary region BND.

[0075] The first multiplexer MX1 ​​may include a first output wiring 278 in the first metal layer M1 to provide a first output signal Y1. Figure 6 As shown in , the column extension portion of the first output wiring 278 may be disposed along and above the first selection gate line 213 .

[0076] The second multiplexer MX2 may include a second output wiring 276 in the first metal layer M1 to provide a second output signal Y2. Figure 6 As shown in , the column extension portion of the second output wiring 276 can extend along the second selection gate line 214 and above the second selection gate line 214 in the second direction Y. The row connection wiring 291 can be in the second metal layer M2. Therefore, the row connection wiring 291 extending in the first direction X can cross the column extension portion of the second output wiring 276 extending in the second direction Y, for example, at a right angle.

[0077] like Figure 6As shown in , the power supply voltage VDD may be applied to the first power rail 271 and the third power rail 273, and the ground voltage VSS may be applied to the second power rail 272. In this case, the P-type transistors MP1 to MP8 may be formed in the first device region RX11 and the fourth device region RX22, and the N-type transistors MN1 to MN8 may be formed in the second device region RX12 and the third device region RX21.

[0078] The row connection wiring 291 may connect the first selection gate line 213 and the third selection gate line 215. Figure 6 and 7A As shown in , the row connection wiring 291 may be connected to the second gate segment 213 b of the first selection gate line 213 and the second gate segment 215 b of the third selection gate line 215 . Figure 6 and 7A The row connection wiring 291 is shown connected to the first gate selection line 213 and the third gate selection line 215 through the upper via contact V1, the wirings 274 and 275 in the first metal layer M1, and the lower via contact V0.

[0079] like Figure 6 As shown in FIG. 1 , the first selection gate line 213 may form the gate electrodes of the second selection transistor MN2 and the sixth selection transistor MN6, the second selection gate line 214 may form the gate electrodes of the first selection transistor MP2, the fourth selection transistor MN4, the fifth selection transistor MP6, and the eighth selection transistor MN8, and the third selection gate line 215 may form the gate electrodes of the third selection transistor MP4 and the seventh selection transistor MP8. The row connection wiring 291 may connect the gate electrode of the sixth selection transistor MN6 and the gate electrode of the seventh selection transistor MP8.

[0080] The first selection gate line 213 may connect the gate electrode of the selection transistor in the first region RG1 (corresponding to a portion of the first selection gate line 213) and the gate electrode of the selection transistor in the second region RG2 (corresponding to another portion of the first selection gate line 213). Figure 6 and Figure 7B As shown, the gate electrode of the second selection transistor MN2 in the first region RG1 and the gate electrode of the sixth selection transistor MN6 in the second region RG2 may be connected through the first selection gate line 213. Even if the first selection gate line 213 is cut and separated into gate segments 213a, 213b, and 213c by the gate cutting region CT, the gate electrodes of the second selection transistor MN2 and the sixth selection transistor MN6 may be formed by the same gate segment 213b of the first selection gate line 213.

[0081] like Figure 6 and Figure 7CAs shown in , the third selection gate line 215 may be cut into a first gate segment 215a and a second gate segment 215b by the gate cutting region CT, so that the first gate segment 215a may be used as a gate electrode of the third selection transistor MP4 in the first region RG1, and the second gate segment 215b separated from the first gate segment 215a along the second direction Y may be used as a gate electrode of the seventh selection transistor MP8 in the second region RG2. The column connection wiring 292 may be formed over the semiconductor substrate and extend in the second direction Y to connect the first gate segment 215a of the third selection gate line 215 and the second gate segment 215b of the third selection gate line 215.

[0082] The second selection gate line 214 may connect the gate electrode of the selection transistor in the first region RG1 (corresponding to a portion of the second selection gate line 214) and the gate electrode of the selection transistor in the second region RG2 (corresponding to another portion of the second selection gate line 214). Figure 6 and 7D As shown, the second selection gate line 214 may not be cut, for example, separated, by the gate cutting region CT in the first region RG1 and the second region RG2. As a result, all gate electrodes of the first selection transistor MP2 and the fourth selection transistor MN4 in the first region RG1 and the fifth selection transistor MP6 and the eighth selection transistor MN8 in the second region RG2 may be connected by the second selection gate line 214.

[0083] The active regions on both sides of the dummy gate segment can be connected by a jumper structure. Fig. 7E As shown in FIG. 1 , the jumper structure JMP1 may include first contacts 234 and 235 and a second contact 245. The jumper structure JMP1 may be formed by combining the first contacts 234 and 235 on the active regions 114 and 115 on both sides and the second contact 245 on the gate segment 213a. By using such a jumper structure JMP1, the gate segment 213a may be connected to the active regions 114 and 115.

[0084] Figure 8 is shown with Figure 5 FIG. 1 is a diagram of an example embodiment of a layout of a standard cell corresponding to an integrated circuit. Fig.9A and 9B According to an example embodiment Figure 8 Cross-sectional view of a standard cell.

[0085] Figure 8 The standard unit and Figure 6 The standard cell is substantially the same except for the third selection gate line 215, that is, except for Figure 7C Therefore, the Figure 6 , 7A, 7B, 7D and 7E are repeated descriptions.

[0086] The third selection gate line 215 may connect the gate electrode of the selection transistor in the first region RG1 (corresponding to a portion of the third selection gate line 215) and the gate electrode of the selection transistor in the second region RG2 (corresponding to another portion of the third selection gate line 215). Figure 8 and 9A As shown, the third selection gate line 215 may not be cut, for example, separated, by the gate cutting region CT in the first and second regions RG1 and RG2 . As a result, gate electrodes of the third and seventh selection transistors MP4 and MP8 may be formed and connected by the third selection gate line 215 .

[0087] The active regions on both sides of the third selection gate line 215 may be connected by a jumper structure. Fig. 9B As shown in FIG. 1 , the jumper structure JMP2 may include first contacts 234 and 235 and a second contact 245. The jumper structure JMP2 may be formed by combining the first contacts 234 and 235 on the active regions 114 and 115 on both sides and the second contact 245 on the gate mask 122. Using such a jumper structure JMP2 electrically disconnected from the third selection gate line 215 by the gate mask 122, the active regions 114 and 115 on both sides of the third selection gate line 215 may be connected to each other.

[0088] In some example embodiments, as shown in FIG. Figure 6 and Figure 7C As mentioned above, due to the use of Fig. 7E The jumper structure JMP1 can connect the gate segments 215a and 215b of the third selection gate line 215 using the column connection wiring 292. In other example embodiments, by using Fig. 9B By using the jumper structure JPM2, the column connection wiring 292 can be omitted, and the entire third selection gate line 215 can be used as the first selection node A.

[0089] The gate electrode of the second selection transistor MN2 in the first region RG1 and the gate electrode of the sixth selection transistor MN6 in the second region RG2 may be connected by the first selection gate line 213. Even if the first selection gate line 213 is cut and separated into gate segments 213a, 213b, and 213c by the gate cutting region CT, the gate electrodes of the second selection transistor MN2 and the sixth selection transistor MN6 may be formed by the same gate segment 213b of the first selection gate line 213.

[0090] Fig.10 and 11 is shown with Figure 5 FIG. 1 is a diagram of an example embodiment of a layout of a standard cell corresponding to an integrated circuit. Fig.10The standard unit and Figure 8 The standard cells are substantially the same except for the first output wiring 278', and therefore, a repeated description may be omitted.

[0091] The first output wiring 278′ is connected to Figure 8 The first output wiring 278 has bilateral symmetry. In other words, Fig.10 The portion of the first output wiring 278′ extending in the second direction Y is above the third selection gate line 215 along the third selection gate line 215, and Figure 6 and 8 A portion of the first output wiring 278 extending in the second direction Y is along and above the first selection gate line 213 .

[0092] Thus, a portion of the first output wiring 278 or 278' extending in the second direction Y may be respectively above the first selection gate line 213 or the third selection gate line 215. Therefore, a dummy gate line for a column extension portion extending in the second direction Y may be omitted to reduce the cell width CW.

[0093] Fig.11 The standard unit and Figure 6 The standard cells are basically the same except for the type of transistors, so repeated descriptions can be omitted. Fig.11 As shown in , the ground voltage VSS may be applied to the first power rail 271 and the third power rail 273, and the power supply voltage VDD may be applied to the second power rail 272. In this case, N-type transistors MN1-MN8 may be formed in the first device region RX11 and the fourth device region RX22, and P-type transistors MP1-MP8 may be formed in the second device region RX12 and the third device region RX21.

[0094] Fig.12 is a circuit diagram illustrating an integrated circuit according to an example embodiment. Fig.12 , the integrated circuit 203 may include a first multiplexer MX1 ​​and a second multiplexer MX2. The first multiplexer MX1 ​​may select one of the first input signal C1 and the second input signal D1 based on the first selection signal A and the second selection signal B to output the first output signal Y1. The second multiplexer MX2 may select one of the third input signal C2 and the fourth input signal D2 based on the first selection signal A and the second selection signal B to output the second output signal Y2.

[0095] The first multiplexer MX1 ​​may include a first input transistor MP1 , a second input transistor MN1 , a third input transistor MP3 , a fourth input transistor MN3 , a first selection transistor MP2 , a second selection transistor MN2 , a third selection transistor MP4 , and a fourth selection transistor MN4 .

[0096] The second multiplexer MX2 may include a fifth input transistor MP5 , a sixth input transistor MN5 , a seventh input transistor MP7 , an eighth input transistor MN7 , a fifth selection transistor MP6 , a sixth selection transistor MN6 , a seventh selection transistor MP8 , and an eighth selection transistor MN8 .

[0097] Fig.12 The integrated circuit 203 and Figure 5 The integrated circuit 202 is substantially the same except that the first selection signal A and the second selection signal B are swapped, and repeated description may be omitted.

[0098] The first selection transistor MP2 is gated by the inverted voltage level of the first selection signal A to pull up the first output node Y1 that generates the first output signal Y1. The second selection transistor MN2 is gated by the voltage level of the second selection signal B to pull down the first output node Y1. The third selection transistor MP4 is gated by the inverted voltage level of the second selection signal B to pull up the first output node Y1. The fourth selection transistor MN4 is gated by the voltage level of the first selection signal A to pull down the first output node Y1.

[0099] The fifth selection transistor MP6 is gated by the inverted voltage level of the first selection signal A to pull up the second output node Y2 that generates the second output signal Y2. The sixth selection transistor MN6 is gated by the voltage level of the second selection signal B to pull down the second output node Y2. The seventh selection transistor MP8 is gated by the inverted voltage level of the second selection signal B to pull up the second output node Y2. The eighth selection transistor MN8 is gated by the voltage level of the first selection signal A to pull down the second output node Y2.

[0100] Fig.13 and 14 is shown with Fig.12 FIG. 1 is a diagram of an example embodiment of a layout of a standard cell corresponding to an integrated circuit. Fig.13 The standard unit and Figure 6 The standard units are basically the same. Fig.14 The standard unit and Fig.11 The standard units are basically the same. Therefore, repeated descriptions can be omitted.

[0101] Fig.13 The standard unit and Figure 6The standard unit has bilateral symmetry. The cross-sectional structure corresponding to line II′ is similar to Fig. 7A The cross-sectional structure of the line JJ′ is basically the same as Figure 7B The cross-sectional structure of the line KK′ is basically the same as Figure 7C The cross-sectional structure of the line LL′ is basically the same as Fig.7D The cross-sectional structures are basically the same. Fig.14 The standard unit and Fig.13 The standard cell is basically the same, except that the P-type and N-type transistors are swapped.

[0102] Fig.15 is a circuit diagram illustrating an integrated circuit according to an example embodiment. Fig.15 , the integrated circuit 204 may include a first multiplexer MX1, a second multiplexer MX2, and a third multiplexer MX3, which include a plurality of transistors MP1-MP12 and MN1-MN12. The first multiplexer MX1 ​​may select one of the first input signal C1 and the second input signal D1 based on the first selection signal A and the second selection signal B to output the first output signal Y1. The second multiplexer MX2 may select one of the third input signal C2 and the fourth input signal D2 based on the first selection signal A and the second selection signal B to output the second output signal Y2. The third multiplexer MX3 may select one of the fifth input signal C3 and the sixth input signal D3 based on the first selection signal A and the second selection signal B to output the third output signal Y3.

[0103] The integrated circuit 204 including three multiplexers MX1, MX2 and MX3 can be implemented as a standard cell so that the first gate selection line GL1, the second gate selection line GL2 and the third gate selection line GL3 are in three areas defined by four power rails and adjacent in the second direction Y. In this way, Fig.15 The standard cell may have a cell height 3CH which is three times the cell height CH of a normal standard cell. Fig.15 A standard cell having a cell height N*CH that is N times (N is an integer greater than 1) of a normal cell height CH may be referred to as a triple-height standard cell. In general, a standard cell having a cell height N*CH that is N times (N is an integer greater than 1) of a normal cell height CH may be referred to as a multiple-height standard cell.

[0104] Fig.16 is a flowchart illustrating a method of designing an integrated circuit according to example embodiments. Fig.16The method may include a method of designing an integrated circuit layout performed by a design tool. In some example embodiments, the design tool may include programming software including a plurality of instructions executable by a processor, i.e., software implemented in some form of hardware (e.g., a processor, ASIC, etc.).

[0105] refer to Fig.16 , input data defining an integrated circuit may be received (S100). For example, the integrated circuit may be defined by a plurality of cells, and a cell library including information of the plurality of cells may be used to design the integrated circuit. Hereinafter, the cell may be a standard cell, and the cell library may be a standard cell library.

[0106] In some example embodiments, the input data may be data generated from an abstract form of the behavior of the integrated circuit. For example, the input data may be defined in a register translation level (RTL) by synthesis using a standard cell library. For example, the input data may be a bitstream and / or netlist generated by synthesizing an integrated circuit defined by a hardware description language (HDL) such as VHSIC Hardware Description Language (VHDL) or Verilog.

[0107] In some example embodiments, the input data may be data for defining a layout of an integrated circuit. For example, the input data may include geometric information for defining structures implemented as semiconductor materials, metals, and insulators. For example, the layout of the integrated circuit indicated by the input data may have a layout of cells and wires for connecting the cells to each other.

[0108] At least one multiple height standard cell is provided in the standard cell library (S200). The term "standard cell" may refer to a cell of an integrated circuit, wherein the size of the layout satisfies a preset or specified rule. The standard cell may include an input pin and an output pin, and may process a signal received through the input pin to output a signal through the output pin. For example, the standard cell may be a basic cell such as an AND logic gate, an OR logic gate, a NOR logic gate or an inverter, a composite cell such as an OR / AND / Inverter (OAI) or an AND / OR / Inverter (AOI), or a storage element such as a master-slave flip-flop or a latch.

[0109] Multiple height standard cells may include reference Figures 1 to 15 The selection node is achieved through efficient routing of gate lines and connecting wiring.

[0110] The standard cell library may include information about a plurality of standard cells. For example, the standard cell library may include the name and function of the standard cell, as well as timing information, power information, and layout information of the standard cell. The standard cell library may be stored in a storage device, and the standard cell library may be provided by accessing the storage device.

[0111] Placement and routing are performed based on input data and a standard cell library (S300), and output data defining an integrated circuit is provided based on a result of the placement and routing (S400).

[0112] In some example embodiments, when the received input data is data such as a bitstream or a netlist generated by synthesizing an integrated circuit, the output data may be a bitstream or a netlist. In other example embodiments, when the received input data is data defining a layout of an integrated circuit, such as data in a Graphic Data System II (GDSII) format, the format of the output data may also be data defining a layout of an integrated circuit.

[0113] As such, the method of designing an integrated circuit according to example embodiments and the integrated circuit obtained by the method can reduce the area occupied by the integrated circuit through efficient routing of gate lines and connection wirings and enhance the performance of the integrated circuit using multiple height standard cells including selection nodes.

[0114] Fig.17 is a block diagram illustrating a design system for an integrated circuit according to an example embodiment. Fig.17 , the design system 1000 may include a storage medium 1100 , a design module 1400 , and a processor 1500 .

[0115] The storage medium 1100 (e.g., a storage device) may store a standard cell library SCLB 1110. The standard cell library 1110 may be provided to the design module 1400 from the storage medium 1100. The standard cell library 1110 may include a plurality of standard cells. According to example embodiments, the plurality of standard cells may include at least one multiple height standard cell. The standard cell may be a small (e.g., minimum) cell for designing a module, a device, and / or a chip.

[0116] The storage medium 1100 may include any computer-readable storage medium that is used to provide commands and / or data to a computer as a computer-readable storage medium. For example, the computer-readable storage medium 1100 may include volatile memory such as random access memory (RAM), read-only memory (ROM), etc., and non-volatile memory such as flash memory, magnetoresistive RAM (MRAM), phase change RAM (PRAM), resistive RAM (RRAM), etc. The computer-readable storage medium 1100 may be inserted into a computer, may be integrated into a computer, or may be coupled to a computer via a communication medium such as a network and / or a wireless link.

[0117] The design module 1400 may include a placement module PLMD 1200 and a routing module RTMD 1300. Here, the term "module" may refer to, but is not limited to, a software and / or hardware component that performs a specific task, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). A module may reside in a tangible addressable storage medium and may be executed on one or more processors. For example, a module may include a software component, a class component, a task component, a process, a function, a property, a procedure, a subroutine, a program code segment, a driver, firmware, microcode, circuit, data, a database, a data structure, a table, an array, a parameter, etc. A module may be divided into multiple modules that perform specific functions.

[0118] The placement module 1200 may use the processor 1500 to arrange the standard cells based on the input data DI defining the integrated circuit and the standard cell library 1110. The routing module 1300 may perform signal routing for the cell placement provided from the placement module 1200. If the routing is unsuccessful, the placement module 1200 may modify the previous cell placement, and the routing module 1300 may perform signal routing using the modified cell placement. When the routing is successfully completed, the routing module 1300 may provide output data DO defining the integrated circuit.

[0119] The placement module 1200 and the routing module 1300 may be implemented by a single integrated design module 1400, or may be implemented by separate different modules. The integrated design module 1400 including the placement module 1200 and the routing module 1300 may perform placement and routing so that delay matching and / or duty cycle adjustment may be implemented in an integrated circuit using a plurality of load standard cells.

[0120] The placement module 1200 and / or the routing module 1300 may be implemented in software, but example embodiments are not limited thereto. If the placement module 1200 and the routing module 1300 are implemented in software, they may be stored as program codes in the storage medium 1100 or in other storage media.

[0121] When the design module 1400 performs calculations, the processor 1500 may be used. Fig.17 In the embodiment, only one processor 1500 is shown. Alternatively, multiple processors may be included in the design system 1000. In addition, the processor 1500 may include a cache to increase computing capacity.

[0122] As such, the integrated circuit and the method of designing the integrated circuit according to example embodiments may reduce the area occupied by the integrated circuit and enhance the performance of the integrated circuit using multiple height standard cells including selection nodes through efficient routing of gate lines and connection wirings.

[0123] Fig.18 It shows Fig.17 A flowchart of an example operation of the design system. Fig.17 and 18 , the design module 1400 may receive input data DI defining an integrated circuit (S11). The placement module 1200 may reference the standard cell library 1110 including at least one multiple-height standard cell as described above to extract a standard cell corresponding to the input data DI, and may perform cell placement using the extracted standard cell (S12). The routing module 1300 may perform signal routing for the placed cell (S13).

[0124] When the signal routing is unsuccessful (S14: No), the placement module 1200 may replace at least one standard cell, for example, by replacing at least one standard cell with another standard cell to modify the placement of the cell (S15). The routing module 1300 may perform signal routing again for the modified placement (S13).

[0125] In this way, replacement and routing may be repeatedly performed until signal routing is successfully completed. When signal routing is successfully completed (S14: Yes), the design module 1400 may generate output data DO defining the integrated circuit (S16).

[0126] Fig.19 is a diagram illustrating a layout of an integrated circuit according to example embodiments. Fig.19 The integrated circuit 300 may be an application specific integrated circuit (ASIC). The layout of the integrated circuit 300 may be determined by performing the above-mentioned placement and routing of the standard cells SC1 to SC12. Power may be provided to the standard cells SC1 to SC12 through power rails 311 to 316. The power rails 311 to 316 may include high power rails 311, 313, and 315 for providing a first power supply voltage VDD and low power rails 312, 314, and 316 for providing a second power supply voltage VSS lower than the first power supply voltage VDD. For example, the first power supply voltage VDD may have a positive voltage level, and the second power supply voltage VSS may have a ground level (e.g., 0V) or a negative voltage level.

[0127] The high power rails 311, 313 and 315 and the low power rails 312, 314 and 316 extend in the first direction X and are alternately arranged one by one in the second direction Y, thereby forming boundaries of a plurality of circuit rows CR1-CR5 corresponding to areas defined by the power rails 311-316 arranged in the second direction Y.

[0128] According to some example embodiments, power may be distributed to the power rails 311-316 through power grid lines 321-324 extending in the second direction Y. Some power grid lines 322 and 324 may provide a first power supply voltage VDD, while other power grid lines 321 and 323 may provide a second power supply voltage VSS. The power grid lines 321-324 may be connected to the power rails 311-316 through vertical contacts VC, such as through-hole contacts.

[0129] Typically, each circuit row CR1-CR5 can be connected to two adjacent power rails located at its boundary to be powered. For example, standard cells SC1, SC2, SC3, and SC4 in the first circuit row CR1 can be connected to corresponding adjacent power rail pairs including high power rail 311 and low power rail 312.

[0130] For example, Fig.19 As shown, the standard cell SC6 may be a double-height standard cell formed in two circuit rows CR2 and CR3, and the standard cell SC7 may be a triple-height standard cell formed in three circuit rows CR2, CR3, and CR4. In this way, through the efficient wiring of the single-height standard cells SC1-SC5 and SC8-SC12 and the multiple-height standard cells SC6 and SC7, the area occupied by the integrated circuit 300 may be reduced, and the performance of the integrated circuit 300 may be enhanced.

[0131] Fig. 20 is a block diagram illustrating a mobile device according to an example embodiment. Fig. 20 , the mobile device 4000 may include at least one application processor 4100 , a communication module 4200 , a display / touch module 4300 , a storage device 4400 , and a buffer RAM 4500 .

[0132] The application processor 4100 may control the operation of the mobile device 4000. The communication module 4200 is implemented to perform wireless or wired communication with an external device. The display / touch module 4300 is implemented to display data processed by the application processor 4100 and / or receive data through a touch panel. The storage device 4400 is implemented to store user data. The storage device 4400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash storage device (UFS), etc. The storage device 4400 may perform a cache of mapping data and user data as described above.

[0133] The buffer RAM 4500 may temporarily store data for processing operations of the mobile device 4000. For example, the buffer RAM 4500 may be a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0134] At least one component in the mobile device 4000 may include at least one multiple height standard cell according to an example embodiment. As described above, the design of the multiple height standard cell may be included in a standard cell library, and an integrated circuit included in the mobile device 4000 may be designed by automatic placement and routing by a design tool.

[0135] As described above, integrated circuits and methods of designing integrated circuits according to example embodiments may reduce an area occupied by integrated circuits and enhance performance of integrated circuits using multiple height standard cells including selection nodes through efficient routing of gate lines and connection wirings.

[0136] The embodiments can be applied to any electronic device and system. For example, the embodiments can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0137] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general descriptive sense and not for purposes of limitation. In some cases, it should be clear to those of ordinary skill in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. An integrated circuit, include: Semiconductor substrate; a first power rail, a second power rail, and a third power rail extending in a first direction and arranged sequentially on the semiconductor substrate in a second direction perpendicular to the first direction; a first selection gate line, a second selection gate line, and a third selection gate line extending along the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and arranged sequentially in the first direction; as well as A row connection wiring extending in the first direction to connect the first selection gate line and the third selection gate line, wherein The second selection gate line connects a first gate electrode of a selection transistor in the first region and a second gate electrode of a selection transistor in the second region, the first gate electrode corresponds to a portion of the second selection gate line, and the second gate electrode corresponds to another portion of the second selection gate line.

2. The integrated circuit according to claim 1, in, The first selection gate line, the third selection gate line, and the row connection wiring form a first selection node that receives a first selection signal, and The second selection gate line serves as a second selection node receiving a second selection signal.

3. The integrated circuit according to claim 1, in, The second selection gate line is not cut by the gate cutting region in the first region and the second region.

4. The integrated circuit according to claim 1, in, The first selection gate line connects a first gate electrode of a selection transistor in the first region and a second gate electrode of a selection transistor in the second region, the first gate electrode corresponds to a portion of the first selection gate line, and the second gate electrode corresponds to another portion of the first selection gate line.

5. The integrated circuit according to claim 1, in, The third selection gate line is cut by the gate cutting region into a first gate segment corresponding to the first gate electrode of the selection transistor in the first region and a second gate segment corresponding to the second gate electrode of the selection transistor in the second region.

6. The integrated circuit according to claim 5, further comprising: include: A column connection wiring extends in the second direction to connect the first gate segment of the third selection gate line and the second gate segment of the third selection gate line.

7. The integrated circuit according to claim 1, in, The third selection gate line connects a first gate electrode of a selection transistor in the first region and a second gate electrode of a selection transistor in the second region, the first gate electrode corresponds to a portion of the third selection gate line, and the second gate electrode corresponds to another portion of the third selection gate line.

8. The integrated circuit according to claim 1, further comprising: include: a first multiplexer in the first region, the first multiplexer selecting one of the first input signal and the second input signal based on the first selection signal and the second selection signal to output a first output signal; as well as A second multiplexer in the second region, the second multiplexer selects one of a third input signal and a fourth input signal based on the first selection signal and the second selection signal to output a second output signal.

9. The integrated circuit according to claim 8, in, The first multiplexer includes a first output wire located in a metal layer and configured to provide the first output signal, and The column extension portion of the first output wiring is along and above the first selection gate line or the third selection gate line.

10. The integrated circuit according to claim 8, in, The second multiplexer includes a second output wiring located in the first metal layer and configured to provide the second output signal, and The column extension portion of the second output wiring is above the second selection gate line along the second selection gate line.

11. The integrated circuit according to claim 10, in, The row connection wiring is located in a second metal layer above the first metal layer.

12. The integrated circuit according to claim 10, in, The row connection wiring crosses the column extension portion of the second output wiring at a right angle.

13. The integrated circuit according to claim 8, in, The first multiplexer comprises: a first selection transistor gated by an inverted voltage level of the second selection signal to pull up a first output node generating the first output signal; a second selection transistor gated by the voltage level of the first selection signal to pull down the first output node; a third selection transistor gated by an inverted voltage level of the first selection signal to pull up the first output node; and a fourth selection transistor gated by the voltage level of the second selection signal to pull down the first output node, and Wherein, the second multiplexer comprises: a fifth selection transistor gated by an inverted voltage level of the second selection signal to pull up a second output node generating the second output signal; a sixth selection transistor gated by the voltage level of the first selection signal to pull down the second output node; a seventh selection transistor gated by an inverted voltage level of the first selection signal to pull up the second output node; and An eighth selection transistor is gated by the voltage level of the second selection signal to pull down the second output node.

14. The integrated circuit according to claim 13, in, The first selection gate line is used as a gate electrode of the second selection transistor and the sixth selection transistor, The second selection gate line serves as a gate electrode of the first selection transistor, the fourth selection transistor, the fifth selection transistor, and the eighth selection transistor, and The third selection gate line serves as gate electrodes of the third selection transistor and the seventh selection transistor.

15. The integrated circuit according to claim 14, in, The row connection wiring connects a gate electrode of the sixth selection transistor and a gate electrode of the seventh selection transistor.

16. The integrated circuit according to claim 14, in, The first selection transistor, the third selection transistor, the fifth selection transistor, and the seventh selection transistor are first type transistors, and The second selection transistor, the fourth selection transistor, the sixth selection transistor, and the eighth selection transistor are second type transistors.

17. An integrated circuit, include: a first selection transistor gated by an inverted voltage level of a second selection signal to pull up the first output node; a second selection transistor gated by a voltage level of a first selection signal to pull down the first output node; a third selection transistor gated by an inverted voltage level of the first selection signal to pull up the first output node; a fourth selection transistor gated by the voltage level of the second selection signal to pull down the first output node, a fifth selection transistor gated by an inverted voltage level of the second selection signal to pull up the second output node; a sixth selection transistor gated by the voltage level of the first selection signal to pull down the second output node; a seventh selection transistor gated by an inverted voltage level of the first selection signal to pull up the second output node; an eighth selection transistor gated by a voltage level of the second selection signal to pull down the second output node; a first selection gate line used as a gate electrode of the second selection transistor and the sixth selection transistor; a second selection gate line used as gate electrodes of the first selection transistor, the fourth selection transistor, the fifth selection transistor, and the eighth selection transistor; a third selection gate line used as a gate electrode of the third selection transistor and the seventh selection transistor; as well as A row connection line connects the first selection gate line and the third selection gate line.

18. The integrated circuit according to claim 17, in, The first output node and the second output node include wiring in a first metal layer, and The row connection wiring is located in a second metal layer different from the first metal layer.

19. A method for designing an integrated circuit, include: receiving input data defining the integrated circuit; providing at least one multiple height standard cell in a standard cell library; performing placement and routing based on the input data and the standard cell library; as well as generating output data defining the integrated circuit based on the results of the placing and the routing, Wherein, the multiple height standard unit comprises: Semiconductor substrate; A first power rail, a second power rail, and a third power rail on the semiconductor substrate extending in a first direction and arranged sequentially in a second direction perpendicular to the first direction; A first selection gate line, a second selection gate line, and a third selection gate line on the semiconductor substrate extend along the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are sequentially arranged in the first direction; and The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

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