Biasing method for the output of a folded cascode stage in a comparator and corresponding comparator

Abstract

The present disclosure relates to a biasing method for the outputs of a folded cascode stage in a comparator and to a corresponding comparator. For example, a comparator includes a folded cascode stage having positive and negative outputs. The folded cascode stage includes: a common-mode voltage regulation circuit including resistive elements respectively located between each output and a common-mode node. A compensation circuit is configured to regulate the difference between the voltages on the outputs and is configured to generate a constant and continuous compensation current in the two resistive elements. A hysteresis circuit is configured to offset the voltages on the outputs and to generate a hysteresis current in the two resistive elements.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority of French Patent Application No. 1856189, filed on July 5, 2018, the content of which is incorporated herein by reference. Technical Field

[0003] The present invention generally relates to electronic systems and methods, and in particular embodiments, to a biasing method for the output of a folded cascode stage in a comparator and a corresponding comparator. Background Art

[0004] In a comparator circuit, two input voltages are compared and an output voltage representing the difference between the input voltages is generated. The comparison is typically performed by a differential transistor pair.

[0005] Figure 1 Examples of differential transistor pairs are shown, which are configured to be incorporated into a comparator but have drawbacks in terms of efficiency.

[0006] The differential transistor pair preferably has very close characteristics, especially voltage thresholds, to ensure accurate comparison. Due to the manufacturing uncertainties of transistors, it is difficult to manufacture paired transistors with strictly identical characteristics at a reasonable cost. Generally, in order to pair the differential transistor pair, a resistor compensator 20 (including resistor elements 21, 23 connected to the sources of the differential transistor pair) makes it possible to apply a correction potential to the corresponding sources. The correction potential pre-biases the gate-source voltage of the transistor pair so that they exhibit similar behavior in response to the input voltages IN-, IN+ on their gates. This improves the input accuracy of the comparator.

[0007] Furthermore, hysteresis between the input voltages IN-, IN+ is typically introduced after the comparison is triggered. The hysteresis effect ensures the avoidance of spurious comparisons due to unforeseen changes (e.g., due to electrical noise). The hysteresis effect is typically achieved by modifying the conductivity of one transistor in the differential pair and biasing the input value required to trigger the transistor. For example, in order to modify the conductivity of the transistor, a conventional solution includes making the stack of transistors 11, 12, 13, 14, 15, 16, 17 parallel to one transistor in the differential pair or disconnecting the stack of transistors 11, 12, 13, 14, 15, 16, 17 from one transistor in the differential pair according to a request.

[0008] This type of hysteresis structure 10 requires a non - negligible surface area for implementation, and the parallel - connected transistors 11 - 17 introduce stray capacitance at the inputs IN - and IN +, which increases the propagation delay of the signal in the comparator. For example, the stray capacitance (such as the gate capacitance of the parallel - connected transistors 11 - 17) can have a value more than five times that of the input capacitance without the hysteresis structure 10.

[0009] In addition, the resistor elements 21, 23 belonging to the resistor compensator 20 typically introduce stray polysilicon / substrate capacitance to the sources of the differential transistor pair.

[0010] In comparators where high efficiency is desired, especially in terms of input - output propagation speed, these stray capacitances are extremely harmful and difficult to reduce in the art.

[0011] Therefore, there is a need to design a high - speed comparator whose input capacitance is minimized while maintaining input accuracy and the generation of hysteresis effects. SUMMARY OF THE INVENTION

[0012] One or more embodiments relate to a high - speed comparator.

[0013] According to one aspect, an embodiment relates to a method for biasing the positive output and the negative output of a folded cascode stage of a comparator. The method includes adjusting the voltages on the positive output and the negative output, including causing an adjustment current to flow through two resistor elements, which are respectively located between the two outputs and a common - mode node having a constant common - mode voltage. A constant and continuous compensation current is generated in the two resistor elements to compensate for the difference between the effective thresholds of at least one differential transistor pair of the comparator, which pair is coupled upstream of the folded cascode stage. A hysteresis current is generated in the two resistor elements in a manner controlled by a hysteresis control signal to introduce a hysteresis offset into the input value of the comparator, which is necessary for triggering an output signal representing the comparison of the input values.

[0014] According to multiple aspects, improvements are proposed to the input accuracy of the comparator and the generation of hysteresis on the folded cascode stage of the comparator without introducing stray capacitances that would slow down the operating speed. In this way, the input - output speed of the comparator is increased while perfectly controlling the input accuracy and the generation of hysteresis.

[0015] According to one embodiment, the compensation current is injected into one of the positive output or the negative output through a corresponding cascode transistor and extracted from the other output through another corresponding cascode transistor.

[0016] The cascode transistors are advantageously controlled to increase the output impedance of the positive and negative outputs.

[0017] Since the compensation current can thus flow in one direction or the other in the resistive element, it is possible to compensate for a positive or negative difference between the effective thresholds of the differential transistor pair.

[0018] Furthermore, by means of cascode transistors, it is possible in particular not to increase the stray capacitance at the nodes where the comparator supports rapid signal changes, thus not increasing the propagation time of the comparator.

[0019] According to one embodiment in which the comparator includes two differential pairs having two corresponding types of conductivity, the generated compensation current is dedicated to each type of conductivity according to the conductivity of the effective differential pair.

[0020] Specifically, the method according to this aspect makes it possible to compensate for any measurement of the difference, and according to this implementation mode, the compensation is carried out dynamically, in particular in a manner applied to the differential pairs used in the comparator.

[0021] According to one embodiment, the hysteresis control signal is the output signal of the comparator.

[0022] According to one embodiment, the hysteresis current is injected onto the positive output through a cascode transistor and extracted from the negative output through another cascode transistor.

[0023] The cascode transistors are advantageously controlled to increase the output impedance of the positive and negative outputs.

[0024] The intensity of the hysteresis current thus generated makes it possible to configure the amplitude of the hysteresis offset. Thus, for the same identical product, the amplitude of the hysteresis offset is not fixed, whereby various requirements can be adapted.

[0025] Furthermore, by means of cascode transistors, it is possible in particular not to increase the stray capacitance at the nodes where the comparator supports rapid signal changes, thus not increasing the propagation time of the comparator.

[0026] According to another aspect, an integrated circuit includes: a comparator configured to generate an output signal representing a comparison between input values, the comparator including a folded cascode stage having a positive output and a negative output. An adjustment circuit is configured to adjust the voltages on the positive and negative outputs, including resistive elements respectively located between each output and a common-mode node configured to have a constant common-mode voltage. A compensation circuit includes at least one first current generator configured to generate a constant and continuous compensation current in the two resistive elements to compensate for the difference between the effective thresholds of at least one pair of differential transistor pairs of the comparator, this pair of transistors being coupled upstream of the folded cascode stage. A hysteresis circuit includes a second current generator configured to generate a hysteresis current in the two resistive elements in a manner controlled by a hysteresis control signal to introduce a hysteresis offset to the input values required to generate the output signal of the comparator.

[0027] According to one embodiment, each first current generator includes a pair of first current generation circuits, which are respectively configured to inject a compensation current into one of the positive output or the negative output through a respective cascode transistor, and extract the compensation current from the other output through another respective cascode transistor.

[0028] The cascode transistors are advantageously controlled to increase the output impedance of the positive and negative outputs.

[0029] According to one embodiment where the comparator includes two differential pairs having two respective types of conductivity, the compensation circuit is configured to generate compensation currents dedicated to each type of conductivity, controlled by a control signal representing the conductivity of the effective differential pair.

[0030] For example, the hysteresis control signal is the output signal of the comparator.

[0031] According to one embodiment, the hysteresis circuit includes a pair of second current generators, which are respectively configured to inject a hysteresis current onto the positive output through a cascode transistor, and extract the hysteresis current from the negative output through another cascode transistor.

[0032] Advantageously, the cascode transistors are controlled to increase the output impedance of the positive and negative outputs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other advantages and features of the present invention will become apparent upon reading the following detailed description of non - limiting embodiments and implementations, as well as the drawings, in which:

[0034] Figure 1 A differential transistor pair that may belong to a conventional comparator is shown; and

[0035] Figures 2 to 7 Exemplary embodiments and implementations of the present invention are shown. DETAILED DESCRIPTION

[0036] Figure 2 An exemplary integrated circuit CI is shown, which includes a comparator CMP configured to: generate a signal VCOMP at a first voltage level (logic '1') when the level of the positive input voltage IN+ exceeds the level of the negative input voltage IN-.

[0037] The comparator CMP includes a differential pre - amplification stage PAD that receives the positive and negative input voltages at respective inputs IN +, IN - (referred to as the positive input and the negative input, respectively).

[0038] Figure 3 An example of the differential pre - amplification stage PAD and a power supply device configured to supply a bias current Ib to the stage PAD is shown.

[0039] The differential preamplifier stage PAD includes two pairs of differential transistors. One differential pair, called the p-type conductive differential pair, includes two PMOS transistors MP+ and MP-, whose sources are coupled to the p-type conductive bias node IBP. The other differential pair, called the n-type conductive differential pair, includes two NMOS transistors MN+ and MN-, whose sources are coupled to the n-type conductive bias node IBN.

[0040] The gates of transistors MP+ and MN+ are coupled to the positive input IN+, while the gates of transistors MP- and MN- are coupled to the negative input IN-. The drain of each transistor forms a corresponding intermediate output, called the p-type conductive output and the n-type conductive output, denoted as OUTP+, OUTP-, OUTN+, and OUTN- respectively.

[0041] The preamplifier stage PAD is provided with a bias current Ib generated by a bias current generator IbGEN. The bias current Ib is applied to either the p-type conductive bias node IBP or the n-type conductive bias node IBN. The bias current Ibb flowing to the node IBN originates from a current mirror assembly Cp, which is configured to copy the bias current Ib leaving the bias current generator IbGEN to the n-type conductive bias node IBN. The current mirror assembly Cp includes a diode-connected MOS transistor Md and a copy MOS transistor Mc controlled by the gate voltage of the diode-connected MOS transistor Md.

[0042] The current mirror assembly Cp is coupled to the bias current generator IbGEN through a MOS transistor MSW controlled by a signal CASCN, giving it a switching function. The transistor MSW and the signal CASCN are configured to automatically switch the transistor MSW when the voltage VGSMSW between the gate and source terminals of the transistor MSW is in the p-type or n-type conduction in the corresponding differential pairs MP+ / MP- and MN+ / MN-.

[0043] In the differential preamplifier stage PAD, no additional components introduce stray capacitance at the nodes for routing the differential signals of the comparator CMP.

[0044] Refer again to Figure 2 , as is commonly said, the differential preamplifier stage PAD is coupled upstream of the folded cascode stage CASCR.

[0045] The folded cascode stage CASCR receives signals at the four intermediate outputs OUTN+, OUTN-, OUTP+, and OUTP- of the differential pairs MP+ / MP- and MN+ / MN- of the differential preamplifier stage PAD.

[0046] The folded cascode stage CASCR includes a first branch BR1 and a second branch BR2, which are symmetric and configured to generate two differential output signals VOUT- and VOUT+ at respective differential output nodes OUT- and OUT+ based on four intermediate outputs of a differential preamplifier stage PAD. Figure 7 )

[0047] According to the convention of this example, odd reference numbers (e.g., MP1 or MN3) are used to denote elements belonging to the first branch BR1 on which a negative differential output signal OUT- is generated. Even reference numbers (e.g., MP2 or MN4) are used to denote elements belonging to the second branch BR2 on which a positive differential output signal OUT+ is generated.

[0048] Each branch includes current-generating PMOS transistors MP1 and MP2, which are controlled by a signal BIASP to draw current from a power supply terminal VDD into each branch.

[0049] Cascode PMOS transistors MP3 and MP4 are coupled between the current-generating transistors MP1 and MP2 and the respective output nodes OUT- and OUT+. The cascode transistors MP3 and MP4 are controlled by a cascode signal CASCP to increase the output impedance and thereby reduce the variation of the current with respect to the drain voltage. Thus, for any variation, particularly in the power supply VDD, the current-generating transistors MP1 and MP2 have the same drain potential to generate a stable current.

[0050] Each branch includes current mirror NMOS transistors MN1 and MN2, which, in a manner similar to the cascode PMOS transistors MP3 and MP4, are coupled between a reference voltage terminal GND and the respective differential output nodes OUT- and OUT+ through cascode NMOS transistors MN3 and MN4 controlled by the cascode signal CASCP.

[0051] Each current mirror NMOS transistor MN1 and MN2 is configured to replicate the current flowing into the branch of the other current mirror transistor. Specifically, the gates of the current mirror transistors MN1 and MN2 are coupled to a common mode node MCBias, which is resistively coupled to each output node OUT- and OUT+.

[0052] Corresponding output elements R1 and R2 are located between each of the outputs OUT- and OUT+ and the common mode node MCBias.

[0053] It is clarified here that the nature of the current mirror assembly MN1 and MN2 imposes a constant voltage on the common mode node MCBias, referred to as the MCBias common mode voltage.

[0054] Reference Figure 2 and Figure 3 The positive n-type conductive intermediate output OUTN+ from the drain of the n-type conductive transistor MN+ controlled by the positive input IN+ is coupled to the output (drain) of the current generating transistor MP2 of the second branch BR2 of the folded cascode assembly CASCR.

[0055] The negative n-type conductive intermediate output OUTN- from the drain of the n-type conductive transistor MN- controlled by the negative input IN- is coupled to the output (drain) of the current generating transistor MP1 of the first branch BR1 of the folded cascode assembly CASCR.

[0056] The positive p-type conductive intermediate output OUTP+ from the drain of the p-type conductive transistor MP+ controlled by the positive input IN+ is coupled to the output (drain) of the current mirror transistor MN1 of the first branch BR1 of the folded cascode assembly CASCR.

[0057] The negative p-type conductive intermediate output OUTP- from the drain of the p-type conductive transistor MP- controlled by the negative input IN- is coupled to the output (drain) of the current mirror transistor MN2 of the second branch BR2 of the folded cascode assembly CASCR.

[0058] Therefore, in the n-type conductivity, a given distribution of the bias current Ibb is extracted from the drains of the current generating transistors MP1 and MP2. The given distribution of the extracted current is directly generated by the corresponding conductivities of the transistors MN+ / MN- of the n-type conductive differential pair.

[0059] In the p-type conductivity, a given distribution of the bias current Ib is injected into the drains of the current mirror transistors MN1 and MN2. The given distribution of the injected current is directly generated by the corresponding conductivities of the transistors MP+ / MP- of the p-type conductive differential pair.

[0060] Due to the effect of the current mirror assembly of the transistors MN1 and MN2, the difference between the currents generated at the differential outputs OUT- and OUT+ in the first branch BR1 and the second branch BR2 is forced to be balanced. Therefore, the regulating current flows through the resistive elements R1 and R2 to the common-mode node MCBias and between the two outputs OUT- and OUT+.

[0061] The resistive elements R1 and R2 are biased by regulating the flow of current and generate voltages at their terminals. The common-mode node MCBias naturally has the constant potential of the current mirror assembly MN1 and MN2. This potential is called the MCBias common-mode voltage.

[0062] Thus, when an adjustment current flows through the resistance elements R1, R2 due to the resistance effect, the voltages on the positive output OUT+ and the negative output OUT- increase or decrease in opposite directions to each other.

[0063] The adjustment current is caused by the extraction or injection of current branches BR1, BR2 directly due to the difference in conductivity of the transistors of the differential preamplifier stage PAD, where the transistors are controlled by the positive input signal IN+ and the negative input signal IN-.

[0064] In other words, as Figure 7 shown, the differential output voltages VOUT+, VOUT- (drawn here with dashed lines) approach and move away from the MCBias common-mode voltage in proportion to the difference between the positive input voltage VIN+ and the negative input voltage VIN-. In this description, the MCBias common-mode voltage will be located at the intersection of the output signals VOUT+, VOUT-.

[0065] Referring again to Figure 2 , it can be seen that the resistance elements R1, R2 together with the current mirror transistors MN1, MN2 enable the generation of output voltages VOUT+, VOUT- that are self-adjusted to the MCBias common-mode voltage.

[0066] Therefore, in this example, the resistance elements R1, R2 and the common-mode node MCBias (which is configured to have a constant common-mode voltage by means of the current mirror transistors MN1, MN2) together form an adjustment circuit 300 configured to adjust the voltages on the positive output OUT+ and the negative output OUT-.

[0067] In addition, the output stage OUT (such as an all-or-nothing comparator) receives the outputs OUT-, OUT+ of the folded cascode component CASCR, and enables the generation of an output signal VCOMP (e.g., a step signal) when the positive output voltage OUT+ exceeds the negative output voltage OUT, as specifically Figure 7 shown in the example.

[0068] In addition, the integrated circuit CI includes first and second compensation circuits 210, 220 and a hysteresis circuit 100, enabling the compensation of input inaccuracies and the generation of hysteresis respectively without affecting the operating speed of the comparator CMP.

[0069] Specifically, as Figure 3 shown, the inputs IN+, IN- are not affected by the stray capacitance elements in the differential preamplifier PAD.

[0070] Now refer to Figure 4 .

[0071] The hysteresis circuit 100 is configured to cancel the voltages on the positive output OUT+ and the negative output OUT- by an offset Vhyst.

[0072] In this regard, the hysteresis circuit 100 includes a current generator 101 configured to inject a hysteresis current Ihyst into a second branch BR2 of a folded cascode assembly CASCR. The hysteresis circuit 100 further includes a current generator 102 configured to extract a current equal to the hysteresis current Ihyst from a first branch BR1 of the folded cascode assembly CASCR.

[0073] For example, the hysteresis current Ihyst is injected at the drain of a current generating transistor MP2 and extracted at the drain of a current mirror transistor MN1. In other words, the hysteresis current Ihyst is injected into the positive output OUT+ through a cascode transistor MP4 and extracted from the negative output OUT- through a cascode transistor MN3.

[0074] Thereby, the hysteresis current Ihyst is forced through two resistor elements R1, R2 respectively located between each differential output OUT+, OUT- and a common mode node MCBias.

[0075] The hysteresis current Ihyst flows in the same direction (from the negative differential output OUT- to the positive differential output OUT+ in this example) through the two resistor elements R1, R2.

[0076] Thus, the hysteresis current biases the resistor elements R1, R2, and the resistor elements generate a voltage Vhyst at their terminals. Since the MCBias common mode voltage is constant, an offset Vhyst is introduced in the voltages on the positive output OUT+ and the negative output OUT- through the hysteresis circuit.

[0077] Therefore, a hysteresis offset is introduced to reduce the voltage on the negative output OUT- and increase the voltage on the positive output OUT+.

[0078] The hysteresis current generators 101, 102 can be controlled (e.g., controlled by an output signal VCOMP) through a hysteresis control signal ComHyst.

[0079] Figure 7 The positive and negative output voltages VOUT+ and VOUT- respectively having the influence of an offset DecHyst introduced by the hysteresis circuit 100 are shown (continuous lines).

[0080] The hysteresis offset DecHyst on the output voltages VOUT+, VOUT- introduces an offset to the values of the input voltages VIN+, VIN-, which is necessary to trigger the generation of the output signal VCOMP.

[0081] Specifically, as Figure 7As shown, the positive input voltage VIN+ must be at least lower than the negative input voltage VIN- by an offset ΔVhyst to equalize the differential output voltages VOUT+ and VOUT-. Once the differential output voltages VOUT+ and VOUT- are equalized, the output voltage ramp VCOMP drops to a low level, and the control stops generating the hysteresis offset DecHyst.

[0082] Now refer to Figure 5 .

[0083] The compensation circuits 210, 220 are configured to regulate the difference between the voltages on the positive output OUT+ and the negative output OUT-, including at least one current generator configured to generate a constant and continuous compensation current in two resistor elements R1, R2.

[0084] For example, the compensation circuits 210, 220 are used to compensate for the difference between the effective thresholds of the differential transistor pairs MN+ / MN- and MP+ / MP- upstream of the differential preamplifier of the folded cascode stage CASCR of the comparator CMP.

[0085] In other words, if the effective thresholds of the transistor pairs are not the same, the comparator may trigger the output signal VCOMP while the signals at the input are not equal. Therefore, there is what is commonly referred to as an offset between the inputs IN+ and IN-.

[0086] In this case, compensating the effective thresholds of the transistor pairs is equivalent to refining the offset between the positive input IN+ and the negative input IN-. This allows for a more precise comparison.

[0087] The compensation of the effective thresholds can be dedicated to each of the two differential pairs, that is, separately for the p-type conducting pair and the n-type conducting pair.

[0088] Furthermore, depending on the effective value of a given embodiment, the compensation of the effective thresholds dedicated to each pair can be performed by making the differential output voltages OUT+ and OUT- have a positive or negative distance relative to each other.

[0089] Therefore, the compensation circuit includes a positive offset compensation circuit 210 configured to increase the positive output voltage OUT+ relative to the negative output voltage OUT- and a negative offset compensation circuit 220 configured to decrease the positive output voltage OUT+ relative to the negative output voltage OUT-.

[0090] The positive offset compensation circuit 210 includes: two current generators 212, 214 that operate together to compensate for the effective threshold voltages of the transistors of the n-type conducting differential pair; and two similar current generators 211, 213 that operate together to compensate for the effective threshold voltages of the transistors of the p-type conducting differential pair.

[0091] Similarly, the negative offset compensation circuit 220 includes: two current generators 222, 224, which are used to operate together to compensate the effective threshold voltage of the transistors of the n-type conductive differential pair; and two similar current generators 221, 223, which are used to operate together to compensate the effective threshold voltage of the transistors of the p-type conductive differential pair.

[0092] For example, the positive compensation circuit 210 includes a current generator 211, which is configured to inject a positive offset compensation current Ioff+P into the first branch BR1 of the folded cascode assembly CASCR. The positive compensation circuit 210 further includes a current generator 213, which is configured to extract an equal positive offset compensation current Ioff+P from the second branch BR2 of the folded cascode assembly CASCR.

[0093] For example, the compensation current Ioff+P is injected at the drain of the current generating transistor MP1 and extracted at the drain of the current mirror transistor MN2. In other words, the compensation current Ioff+P is injected into the negative output OUT- through the cascode transistor MP3 and extracted from the positive output OUT+ through the cascode transistor MN4.

[0094] In this example, the current Ioff+P makes it possible to compensate the threshold of the transistors of the p-type conductive differential pair.

[0095] Two current generators 212, 214 connected in the same manner as the current generators 211, 213 mentioned above make it possible to compensate the threshold of the transistors of the n-type conductive differential pair.

[0096] The compensation currents Ioff+P, Ioff+N are forced through two resistive elements R1, R2 respectively located between each differential output OUT+, OUT- and the common mode node MCBias.

[0097] The compensation currents Ioff+P, Ioff+N flow in the same direction (in this example, from the positive differential output OUT+ to the negative differential output OUT-) through the two resistive elements R1, R2.

[0098] Thereby, the compensation currents Ioff+P, Ioff+N bias the resistive elements R1, R2, and the resistive elements generate a voltage Voff+ at their terminals. Since the MCBias common mode voltage is constant, a negative offset Voff- in the voltage on the positive output OUT+ and a positive offset Voff+ on the negative output OUT- are introduced through the compensation circuit.

[0099] According to the conduction type of the active differential pair, each pair of current generators 211 / 213 and 212 / 214 of the positive offset compensation circuit 210 is controlled by the signal SCOND.

[0100] When the input voltages IN+ and IN- cause the p-type conductive differential pair to conduct, the signal SCOND controls generators 211 / 213, and when the n-type conductive differential pair conducts, the signal SCOND controls generators 212 / 214.

[0101] For example, the signal SCOND can be generated digitally, or by a comparator receiving voltages at inputs IN+ and IN-, or derived from the switching transistor MSW described above with reference to Figure 3 the description.

[0102] Figure 6 A negative offset compensation circuit 220 is shown, including: two current generators 221, 223, which are used to operate together to compensate the effective threshold voltage of the transistors of the p-type conductive differential pair; and two similar current generators 222, 224, which are used to operate together to compensate the effective threshold voltage of the transistors of the n-type conductive differential pair.

[0103] The function of the negative offset compensation circuit 220 is opposite to that of the positive offset compensation circuit 210, introducing a positive offset Voff+ in the voltage on the positive output OUT+ and a negative offset Voff- on the negative output OUT-, and being located at the same position as the hysteresis circuit in the folded cascode assembly CASCR.

[0104] All current generators 211, 212, 213, 214, 221, 222, 223, 224 belonging to the compensation circuits 210, 220 are configured to generate currents with intensities dedicated to the effective values of the threshold voltages of each hardware manufacturing implementation of the differential pair and its threshold voltage. For example, during the calibration phase of manufacturing the integrated circuit CI, measurements and adjustments of the current generators are performed in this regard.

[0105] In addition, the hysteresis current generators 101, 102 can also be configured to be able to apply various hysteresis offset values to one and the same integrated circuit CI.

[0106] Due to the production limitations of the compensation circuit and the hysteresis circuit, the intensities of the compensation and hysteresis currents can be adjusted according to the hierarchical values set in the integrated circuit manufacturing according to their spacing.

[0107] In addition, it is advantageous that the current generators 101, 102, 211, 212, 213, 214, 221, 222, 223, 224 belonging to the hysteresis circuit 100 and the compensation circuits 210, 220 are coupled to the positive output OUT+ and the negative output OUT- through the corresponding cascode transistors MP3, MP4, MN3, MN4, especially without adding capacitive elements, directly from the current generation circuit to the outputs OUT+, OUT-.

[0108] Specifically, the rapid changes in the output voltages VOUT+ and VOUT- stem from the regulating current flowing in the two resistor elements R1 and R2, but this regulating current does not flow beyond the conductive terminals of the cascode transistors MP3, MP4, MN3, and MN4. Effectively, due to the action of the current flowing in the symmetric branches BR1 and BR2 of the folded cascode stage CASCR, the drains of the current mirror transistors MN1, MN2 and the current generating transistors MP1, MP2 hardly support the variations.

[0109] Therefore, this enables functionally not adding stray capacitance at the nodes of the comparator that support rapid signal changes, thereby not increasing the propagation time of the comparator.

Claims

1. A method for biasing the positive and negative outputs of a folded cascode stage of a comparator, the method comprising: Adjusting the voltages on the positive and negative outputs by causing an adjustment current to flow through a first resistive element and a second resistive element, wherein the first resistive element and the second resistive element are coupled between the positive and negative outputs, and wherein a common-mode node having a constant common-mode voltage is coupled between the first resistive element and the second resistive element; Generating a constant and continuous compensation current in the first resistive element and the second resistive element to compensate for a difference between effective thresholds of a differential transistor pair of the comparator, the differential transistor pair being coupled upstream of the folded cascode stage; And Generating a hysteresis current in the first resistive element and the second resistive element in a manner controlled by a hysteresis control signal to introduce a hysteresis offset into an input value of the comparator, thereby triggering an output signal indicative of a comparison of the input value.

2. The method according to claim 1, wherein the compensation current is injected into one of the positive or negative outputs through a respective cascode transistor and extracted from the other of the positive or negative outputs through another respective cascode transistor.

3. The method according to claim 1, wherein the comparator includes two differential pairs having two respective types of conductivity, and wherein the generated compensation current is dedicated to each type of conductivity according to the conductivity of an effective differential pair of the two differential pairs.

4. The method according to claim 1, wherein the hysteresis control signal is the output signal.

5. The method according to claim 1, wherein the hysteresis current is injected into the positive output through a cascode transistor and extracted from the negative output through another cascode transistor.

6. An integrated circuit, comprising a comparator configured to generate an output signal indicative of a comparison between input values, the comparator including a folded cascode stage having a positive output and a negative output, the folded cascode stage including: An adjustment circuit configured to adjust the voltages on the positive and negative outputs, the adjustment circuit including resistive elements coupled between the positive and negative outputs, wherein a common-mode node configured to have a constant common-mode voltage is coupled between the resistive elements; A compensation circuit including a first current generator configured to generate a compensation current in the resistive elements to compensate for a difference between effective thresholds of a pair of transistors of the comparator, wherein the pair of transistors is coupled upstream of the folded cascode stage; And A hysteresis circuit including a second current generator configured to generate a hysteresis current in the resistive elements in a manner controlled by a hysteresis control signal to introduce a hysteresis offset into the input value, thereby generating the output signal of the comparator.

7. The integrated circuit according to claim 6, wherein the first current generator includes a pair of first current generation circuits, which are respectively configured to inject the compensation current into one of the positive output or the negative output through a corresponding cascode transistor, and extract the compensation current from the other output of the positive output or the negative output through another corresponding cascode transistor.

8. The integrated circuit according to claim 6, wherein the comparator further includes two differential pairs having two corresponding types of conductivity, wherein the compensation circuit is controlled by a control signal representing the conductivity of the effective differential pair of the two differential pairs, and wherein the compensation circuit is configured to generate compensation currents dedicated to each type of conductivity.

9. The integrated circuit according to claim 6, wherein the hysteresis control signal is the output signal of the comparator.

10. The integrated circuit according to claim 6, wherein the hysteresis circuit further includes a pair of second current generators, which are respectively configured to inject the hysteresis current into the positive output through a cascode transistor and extract the hysteresis current from the negative output through another cascode transistor.

11. A circuit, comprising: a first input and a second input, configured to receive a first input signal and a second input signal respectively; a comparator output, configured to generate an output signal based on the difference between the first input signal and the second input signal and a hysteresis offset; a folded cascode stage, coupled between the first input and the second input and the comparator output, the folded cascode stage including: a first output and a second output, configured to generate a first output signal and a second output signal respectively; a first differential pair of a first type, coupled between the first output and the second output and a first power supply terminal; a second differential pair of a second type, coupled between the first output and the second output and a second power supply terminal; a first resistor and a second resistor, coupled between the first output and the second output; a first current generator, configured to generate a compensation current flowing through the first resistor and the second resistor; and a second current generator, configured to generate a hysteresis current flowing through the first resistor and the second resistor to introduce the hysteresis offset.

12. The circuit according to claim 11, wherein: the first current generator includes: a first generator current circuit, coupled between the first differential pair and the first power supply terminal, the first generator current circuit being configured to inject the compensation current via the first differential pair, and a second generator current circuit, coupled between the second differential pair and the second power supply terminal, the second generator current circuit being configured to extract the compensation current via the second differential pair; and the second current generator includes: a third generator current circuit, coupled between the first differential pair and the first power supply terminal, the third generator current circuit being configured to inject the hysteresis current via the first differential pair, and A fourth generator current circuit, coupled between the second differential pair and the second power supply terminal, the fourth generator current circuit being configured to extract the hysteresis current via the second differential pair.

13. The circuit according to claim 12, wherein the first generator current circuit and the second generator current circuit are controlled by a first control signal.

14. The circuit according to claim 13, further comprising a second comparator having a first input and a second input configured to receive the first input signal and the second input signal, respectively, and configured to generate the first control signal.

15. The circuit according to claim 11, further comprising a differential preamplifier stage coupled between the first input and the second input and the folded cascode stage.

16. The circuit according to claim 15, wherein: The first transistor and the second transistor of the first differential pair are respectively coupled between a first node and a second node and the first resistor and the second resistor; The third transistor and the fourth transistor of the second differential pair are respectively coupled between a third node and a fourth node and the first resistor and the second resistor; And The differential preamplifier stage includes: A fifth transistor of the first type, coupled between the first power supply terminal and the third node, and having a control terminal coupled to the first input, A sixth transistor of the first type, coupled between the first power supply terminal and the fourth node, and having a control terminal coupled to the second input, A seventh transistor of the second type, coupled between the second power supply terminal and the second node, and having a control terminal coupled to the first input, and An eighth transistor of the second type, coupled between the second power supply terminal and the first node, and having a control terminal coupled to the second input.

17. The circuit according to claim 16, wherein the folded cascode stage further includes: A ninth transistor of the second type, coupled between the third transistor and the second power supply terminal; And A tenth transistor of the second type, coupled between the fourth transistor and the second power supply terminal, wherein a common-mode node coupled between the first resistor and the second resistor is coupled to the control terminals of the ninth transistor and the tenth transistor.

18. The circuit according to claim 11, wherein the second current generator is controlled by the output signal.

19. The circuit according to claim 11, wherein the first type is p-type and the second type is n-type.

20. The circuit according to claim 11, wherein the second power supply terminal is coupled to ground, and wherein the first power supply terminal is configured to receive a voltage higher than ground.

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