Integrated circuit to prevent reverse polarity and buffer power-up

Abstract

The present invention relates to an integrated circuit for preventing reverse polarity and buffering power-on. A buffer resistor R1 and an anti-reverse polarity diode D1 are connected in series, and then connected in parallel with a forward thyristor T2 and a reverse thyristor T1 connected in parallel to form a main circuit. The main circuit is connected in series to the front end of the positive pole on the DC input side of a power conversion device to form a protection circuit. The drive circuits for the gates of the forward thyristor T2 and the reverse thyristor T1 are connected in front of the main circuit. A DC power supply is connected to the power conversion device, and the drive circuit automatically determines whether the main circuit is turned on by identifying the polarity of the DC power supply. Not only does it have a buffering power-on function, reducing the impact on the power conversion device at the moment of power-on, it can also determine the positive and negative polarity of the input voltage to prevent damage to the power conversion device due to reverse polarity. It protects the power supply and the power conversion device to a great extent. At the same time, compared with other devices with the above functions, this design circuit also greatly reduces the volume and saves space.

Description

Technical Field

[0001] The present invention relates to a protection circuit, in particular to an integrated circuit for preventing positive and negative pole reverse connection and buffering power-on. Background Art

[0002] For devices such as frequency converters and inverters with DC input, the positive and negative polarity of the input power supply is very important. If it is reversed, it will cause immeasurable consequences. The anti-reverse polarity circuit can identify the polarity of the input power supply and play a protective role. At the moment of power-on, the bus capacitor has a large impact, and the buffer circuit can play a role in reducing the impact of the bus capacitor. The circuit for preventing power reverse connection described in Chinese Patent No. 201710885164.0, although it can achieve the function, takes a long time, is complex to control, and requires a separate buffer power-on circuit design; the buffer power-on circuit described in Chinese Patent No. 201711067384.9 has a complex circuit topology and cannot effectively determine the polarity of the input power supply. Both of the above circuit structures fail to fully achieve fast and efficient performance and space saving. Summary of the Invention

[0003] The present invention addresses the issues of impact on bus capacitors at the moment of power-on and damage to power conversion devices caused by reverse connection of positive and negative poles. It proposes an integrated circuit for preventing reverse connection of positive and negative poles and buffering power-on. The circuit structure effectively determines the positive and negative polarity of the DC source and buffers the bus capacitors during power-on, thus protecting the device to a great extent.

[0004] The technical solution of the present invention is: an integrated circuit for preventing positive and negative pole reverse connection and buffering power-on. A buffer resistor R1 and an anti-reverse connection diode D1 are connected in series, and then connected in parallel with a forward thyristor T2 and a reverse thyristor T1 connected in parallel to form a main circuit. The main circuit is connected in series to the front end of the positive pole on the DC input side of the power conversion device to form a protection circuit. The drive circuit of the gate of the forward thyristor T2 and the reverse thyristor T1 is connected in front of the main circuit. The DC power supply is connected to the power conversion device. The drive circuit automatically determines whether to conduct the main circuit by identifying the polarity of the DC power supply.

[0005] The driving circuit includes an identification circuit, a delay circuit and a trigger circuit in sequence.

[0006] Identification circuit: Three unidirectional anti-reverse polarity diodes D2, D3, and D4 and a current-limiting resistor R4 are connected in series between the positive terminal A and the negative terminal B of the DC power input of the power conversion device. An inverse voltage-limiting diode D5 is connected in parallel with the middle anti-reverse polarity diode D3 of the three unidirectional series-connected diodes. The negative and positive electrodes of the inverse voltage-limiting diode D5 are respectively connected to the positive and negative electrodes of the input terminal of the signal processing optocoupler chip P1. The output terminal of the signal processing optocoupler chip P1 is connected in series with a pull-down resistor R5, which is connected between the circuit power supply VCC and VCC_GND ground. The output terminal of the signal processing optocoupler chip P1 and the pull-down resistor R5 are connected in series to the delay circuit.

[0007] Delay circuit: The output terminal of the signal processing optocoupler chip P1 and the series connection point of the pull-down resistor R5 are connected to the No. 2 input pins of the two logic AND gates AND1 and AND2 respectively. The No. 1 input pins of the two logic AND gates AND1 and AND2 are connected to the delay control signal T_Drive. When T_Drive reaches the high level V of the two logic AND gates AND1 and AND2, the delay control signal T_Drive is generated. high When the output level is determined by judging the level of the logic gate 2 pin, the output of the two logic gates AND1 and AND2 contact the circuit;

[0008] Trigger circuit:

[0009] The output of the logic AND gate AND1 is connected to the positive input of the thyristor driver optocoupler chip P2, and a current limiting resistor R2 is connected in series between the two. The output of the thyristor driver optocoupler chip P2 and the current limiting resistor R6 are connected in series to the power supply V DD1 Between the gate g1 of the reverse thyristor T1,

[0010] The output of the logic AND gate AND2 is connected to the positive input of the thyristor driver optocoupler chip P3, and a current limiting resistor R3 is connected in series between the two. The output of the thyristor driver optocoupler chip P3 and the current limiting resistor R7 are connected in series between the power supply VDD1 and the gate g2 of the forward thyristor T2.

[0011] The cathode S1 of the reverse thyristor T1 is grounded to VDD1_GND, and the cathode S2 of the forward thyristor T2 is grounded to VDD2_GND. VDD1_GND and VDD2_GND must be isolated from each other.

[0012] The beneficial effects of the present invention are as follows: The integrated circuit for preventing reverse polarity and buffering power-up not only buffers power-up, reducing the impact on the power conversion device at the moment of power-up, but also determines the positive and negative polarity of the input voltage, preventing damage to the power conversion device caused by reverse polarity. This significantly protects the power supply and power conversion device. Furthermore, compared to other devices with these functions, this circuit design is significantly smaller, saving space. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the main circuit diagram of the integrated circuit for preventing positive and negative pole reverse connection and buffering power-on of the present invention;

[0014] Figure 2 This is the forward and reverse thyristor driving circuit diagram of the present invention. DETAILED DESCRIPTION

[0015] like Figure 1 The main circuit of the integrated circuit shown in the figure, after the buffer resistor 4 (R1) and the anti-reverse polarity diode 3 (D1) are connected in series, and then connected in parallel with the forward thyristor 1 (T2) and the reverse thyristor 2 (T1) connected in parallel, constitutes the main circuit of the integrated circuit to prevent positive and negative polarity reverse polarity and buffer power-on shock. The main circuit is connected in series with the front end of the positive terminal on the DC input side of the power conversion device to form a protection circuit. Among them, the buffer resistor R1 is a power resistor, and the resistance value of R1 is selected to be consistent with the maximum allowable DC input voltage value U of the power conversion device. max It is related to the impact current Ic of the bus capacitor C. The resistance range of R1 is 10U max / Ic~30U max / Ic. The positive electrode of the anti-reverse diode 3 is connected to one end of the DC power supply through the buffer resistor R1, and the negative electrode is connected to the DC bus capacitor of the power conversion device. The reverse peak voltage of the anti-reverse diode D1 is V RWM1 The maximum allowable value of DC input voltage of power conversion device U max The current carrying capacity I1 is related to the maximum allowable value of the DC input voltage U max It is related to the resistance of the buffer resistor R1, that is, 3U max >V RWM1 >2U max , 3U max / R1>I1>2U max / R1. The positive electrode of the forward thyristor 1 is connected to one end of the DC power supply, and the negative electrode is connected to the DC bus capacitor of the power conversion device. The negative electrode of the reverse thyristor 2 is connected to one end of the DC power supply, and the positive electrode is connected to the DC bus capacitor of the power conversion device. The two thyristors can be modular thyristors (i.e., one package contains two thyristor elements). Thyristor reverse peak voltage V RWM2 The maximum allowable value of DC input voltage of power conversion device U max The current carrying capacity I2 is related to the minimum allowable DC input voltage U of the power conversion device. min It is related to the power P of the power conversion device. The selection range of the thyristor reverse peak voltage is 3U max >V RWM2 >2U max The selection range of the thyristor reverse peak voltage withstand current value is 3P / U min >I2>2P / U min .

[0016] In this embodiment, the DC input voltage range is 350V~640V, that is, U max =640V, U min =350V, the busbar capacitor's surge current I c =800A, power conversion device power P = 35kVA. After optimization calculation, the buffer resistor (4) resistance R1 = 0.8 ~ 24Ω, preferably 20Ω; the reverse peak voltage V RWM1 =1280V~1920V, preferably 1500V, current resistance value I1=64~96A, preferably 60A; current resistance value I2 of forward thyristor (1) and reverse thyristor (2)=200~300A, preferably 250A, reverse peak voltage V RWM2 =1280V~1920V, preferably 1500V.

[0017] like Figure 2 The driving circuit of the forward thyristor 1 and the reverse thyristor 2 is designed as shown. Three unidirectional anti-reverse diodes 6, 7, 8 (D2, D3, D4) and a current limiting resistor 5 (R4) are connected in series between the positive terminal A and the negative terminal B of the DC power supply input of the power conversion device. A reverse voltage limiting diode 9 (D5) is connected in parallel to the middle anti-reverse diode 7 (D3) of the three unidirectional series anti-reverse diodes. The negative and positive poles of the reverse voltage limiting diode 9 (D5) are respectively connected to the positive and negative poles of the input terminal of the signal processing optocoupler chip 10 (P1). The three anti-reverse diodes and the reverse voltage limiting diode 9 can be selected from the same type of diode, and the reverse withstand voltage value of the selected diode is V DRM3 The maximum allowable value of DC input voltage of power conversion device U max The average forward current I3 is related to the forward conduction current If1 of the signal processing optocoupler chip 10 (P1), that is, 3U max >V DRM3 >2U max , 40If1>I3>20If1. The current limiting resistor 5 (R4) is selected as a power resistor, and the resistance of R4 is proportional to the minimum allowable value of the DC input voltage of the power conversion device U min , the forward conduction current If1 of the signal processing optocoupler chip 10 (P1) is related to 3U min / 10If1>R4>3U min / 15If1; Rated power P of R4 R4 Its resistance and the maximum allowable value of DC input voltage U max Related, namely 3(U max )2 / R4>P R4 >2(U max )2 / R4. In this embodiment, the DC input voltage range is 350V~640V, that is, U max =640V, U min=350V, the forward conduction current I of the signal processing optocoupler chip (10) f1 is 5mA. After optimization calculation, V DRM3 =1280V~1920V, preferably 1500V, I3=100mA~200mA, preferably 100mA, R4=14~21kΩ, preferably 17kΩ, P R4 =48~72W, preferably 60W.

[0018] The output end of the signal processing optocoupler chip 10 (P1) is connected in series with a pull-down resistor 19 (R5) between the circuit power supply VCC (23) and the VCC_GND (22) ground. The point where the output end of the signal processing optocoupler chip 10 (P1) and the pull-down resistor 19 (R5) are connected in series with the No. 2 input pin of the logic AND gates 11 and 12 (AND1 and AND2). The resistance of the pull-down resistor R5 is proportional to the voltage value U of the power supply VCC (22). VCC It is related to the load capacity of the signal processing optocoupler chip 10 (P1). The load current of the signal processing optocoupler chip 10 (P1) is Icb, then 15U VCC / Icb <R5<20U VCC / Icb. VCC(22) voltage value U VCC The magnitude is equal to the high level V of the logic AND gates 11 and 12 (AND1 and AND2). high Related, that is, V high VCC <1.2V high Among them, the logic AND gates 11 and 12 (AND1 and AND2) can be integrated into the same chip. The input pin 1 of the logic AND gates 11 and 12 (AND1 and AND2) is connected to the delay control signal T_Drive to control the operation of the circuit. When T_Drive reaches the high level V of the logic AND gates 11 and 12 (AND1 and AND2), the delay control signal T_Drive is connected to the input pin 1 of the logic AND gates 11 and 12 (AND1 and AND2). high Only when the level of the logic AND gate pin 2 is judged can the output level be determined. Otherwise, the outputs of the logic AND gates 11 and 12 (AND1 and AND2) are always low and the circuit cannot work.

[0019] In this embodiment, the high level V of the logic AND gate (11) (12) integrated chip high =3.3V, the load current of the signal processing optocoupler chip (10) is I cb =5mA. Then U VCC ​=3.3~4V, preferably 3.3V; R5 = 8.6~13.2kΩ, preferably 10kΩ. The input pin 1 of the logic AND gate (11) (12) is connected to the control signal T_Drive to control whether the circuit works or not. When T_Drive reaches the high level (3.3V) of the logic AND gate 11, 12, the output level can be determined by judging the level of pin 2. Otherwise, the output of the logic AND gate 11, 12 is always low and the circuit cannot work.

[0020] The output end of the logic AND gate 11 (AND1) is connected to the positive input of the thyristor driver optocoupler chip 13 (P2), and a current limiting resistor 20 (R2) is connected in series between the two. The resistance of the current limiting resistor 20 (R2) is proportional to the high level voltage V of the logic AND gate (11) (AND1) integrated chip. high It is related to the forward conduction current If2 of the signal processing optocoupler chip 13 (P2), and 1.1V high / If2 <R2<1.5V high / If2. The negative input terminal of the thyristor driver optocoupler chip (13) (P2) is grounded to VCC_GND (22). The output terminal of the logic AND gate 12 (AND2) is connected to the positive input terminal of the thyristor driver optocoupler chip 14 (P3), and a current limiting resistor 21 (R3) is connected in series between the two. The resistance of the current limiting resistor 21 (R3) is proportional to the high level voltage V of the logic AND gate 12 (AND2) integrated chip. high It is related to the forward conduction current If3 of the signal processing optocoupler chip 14 (P3), and 1.1V high / If3 <R3<1.5V high / If3. The negative input terminal of the thyristor driver optocoupler chip 14 (P3) is grounded to VCC_GND (22).

[0021] In this embodiment, the forward conduction current I f2 =5mA, the forward conduction current I of the signal processing optocoupler chip 14 f3 =5mA, the high level voltage V of the logic AND gate 11 and 12 integrated chip high =3.3V, then the resistance value R2 of the current limiting resistor (20) is 726-990Ω, preferably 750Ω, and the resistance value R3 of the current limiting resistor 21 is 726-990Ω, preferably 750Ω.

[0022] The output end of the thyristor driver optocoupler chip 13 (P2) and the current limiting resistor 23 (R6) are connected in series to the power supply V DD1 (15) and the gate g1 of the reverse thyristor 2 (T1). Where VDD1 (15) is the power supply voltage U VDD1 It is related to the trigger voltage VT2 of the reverse thyristor 2 (T1), that is, VT2 VDD1 ​<1.2VT2. The resistance of current limiting resistor 23 (R6) is related to the holding current Id2 of reverse thyristor 2 (T1), and 0.8U VDD1 / Id2 <R6<U VDD1 / Id2. In this embodiment, the reverse thyristor (2) trigger voltage V T2 =5V, maintaining current I d2 =250mA. Then R6 = 20~16Ω, preferably 18Ω, U VDD1 =5V; U VDD1 =5~6V, preferably 5V.

[0023] The output end of the thyristor driver optocoupler chip 14 (P3) and the current limiting resistor 24 (R7) are connected in series between the power supply VDD1 (16) and the gate g2 of the forward thyristor 1 (T2). VDD1 (15) and VDD2 (16) must be isolated from each other. DD2 (16) Power supply voltage U VDD2 It is related to the trigger voltage VT1 of the forward thyristor 1 (T2), that is, VT1 VDD2 <1.2VT1. The resistance of current limiting resistor 24 (R7) is related to the holding current Id1 of forward thyristor 1 (T2) and 0.8U VDD2 / Id1 <R7<U VDD2 / Id1. In this embodiment, the reverse thyristor (2) trigger voltage V T1 =5V, maintaining current I d1 =250mA. Then R7 = 20~16Ω, preferably 18Ω, U VDD2 =5V; U VDD2 =5~6V, preferably 5V.

[0024] The cathode S1 of the reverse thyristor (2) is connected to the ground VDD1_GND (17) of VDD1 (15), and the cathode S2 of the forward thyristor 1 (T2) is connected to the ground VDD2_GND (18) of VDD2 (16). VDD1_GND (17) and VDD2_GND (18) must be isolated from each other.

[0025] ​When the DC input voltage polarity of the power converter is correct, signal processing optocoupler chip 10 (P1) turns on, and pin 1 of logic AND gates 11 and 12 is set to a high level (3.3V), ensuring that the thyristors are ready for turn-on. When the T_Drive delay reaches the high level (3.3V) of logic AND gates 11 and 12, logic AND gates 11 and 12 output a high level, which in turn drives signal processing optocoupler chips 13 (P2) and 14 (P3) to turn on. Power supply VDD1 is applied to terminal g1, and VDD2 is applied to terminal g2, driving forward thyristor 1 and reverse thyristor 2 to turn on, completing the buffered power-up process. When the DC input power supply of the power conversion device is reversed, the signal processing optocoupler chip 10 (P1) cannot be turned on, and the 1 pins of the logic AND gates 11 and 12 are always low. Regardless of whether T_Drive reaches the high level (3.3V) of the logic AND gates 11 and 12, the outputs of the logic AND gates 11 and 12 are both low, thereby driving the signal processing optocoupler chips 13 (P2) and 14 (P3) to not conduct, so that the forward thyristor 1 and the reverse thyristor 2 cannot receive the driving signal and remain in the closed state, thereby protecting the equipment from damage.

Claims

1. An integrated circuit for preventing reverse polarity and buffering power-up, characterized in that: The buffer resistor R1 and the anti-reverse polarity diode D1 are connected in series, and then connected in parallel with the forward thyristor T2 and the reverse thyristor T1 to form a main circuit. The main circuit is connected in series to the front end of the positive electrode of the DC input side of the power conversion device to form a protection circuit. The drive circuit of the gate of the forward thyristor T2 and the reverse thyristor T1 is connected before the main circuit. The DC power supply is connected to the power conversion device. The drive circuit automatically determines whether to conduct the main circuit by identifying the polarity of the DC power supply. The drive circuit includes an identification circuit, a delay circuit and a trigger circuit in sequence. Identification circuit: Three unidirectional anti-reverse polarity diodes D2, D3, and D4 and a current-limiting resistor R4 are connected in series between the positive terminal A and the negative terminal B of the DC power input of the power conversion device. An inverse voltage-limiting diode D5 is connected in parallel with the middle anti-reverse polarity diode D3 of the three unidirectional series-connected diodes. The negative and positive electrodes of the inverse voltage-limiting diode D5 are respectively connected to the positive and negative electrodes of the input terminal of the signal processing optocoupler chip P1. The output terminal of the signal processing optocoupler chip P1 is connected in series with a pull-down resistor R5, which is connected between the circuit power supply VCC and VCC_GND ground. The output terminal of the signal processing optocoupler chip P1 and the pull-down resistor R5 are connected in series to the delay circuit. Delay circuit: The output terminal of the signal processing optocoupler chip P1 and the series connection point of the pull-down resistor R5 are connected to the No. 2 input pins of the two logic AND gates AND1 and AND2 respectively. The No. 1 input pins of the two logic AND gates AND1 and AND2 are connected to the delay control signal T_Drive. When T_Drive reaches the high level V of the two logic AND gates AND1 and AND2, the delay control signal T_Drive is generated. high When the output level is determined by judging the level of the logic gate 2 pin, the output of the two logic gates AND1 and AND2 contact the circuit; Trigger circuit: The output of the logic AND gate AND1 is connected to the positive input of the thyristor driver optocoupler chip P2, and a current limiting resistor R2 is connected in series between the two. The output of the thyristor driver optocoupler chip P2 and the current limiting resistor R6 are connected in series to the power supply V DD1 Between the gate g1 of the reverse thyristor T1, The output of the logic AND gate AND2 is connected to the positive input of the thyristor driver optocoupler chip P3, and a current limiting resistor R3 is connected in series between the two. The output of the thyristor driver optocoupler chip P3 and the current limiting resistor R7 are connected in series between the power supply VDD1 and the gate g2 of the forward thyristor T2. A cathode S1 of the reverse thyristor T1 is grounded to VDD1_GND, a cathode S2 of the forward thyristor T2 is grounded to VDD2_GND, and VDD1_GND and VDD2_GND are isolated from each other.

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