Semiconductor device and manufacturing method

Abstract

The present invention provides a semiconductor device having a barrier metal and a small deviation in threshold voltage and a manufacturing method thereof. The semiconductor device comprises: a semiconductor substrate; an interlayer insulating film arranged on the upper surface of the semiconductor substrate; a titanium layer arranged on the interlayer insulating film; and a titanium nitride layer arranged on the titanium layer, wherein an opening is provided in the interlayer insulating film to expose a portion of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also arranged in the opening, and the titanium layer in contact with the semiconductor substrate and arranged at the bottom of the opening is entirely titanium silicided.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Conventionally, it is known that a semiconductor device provided with a transistor such as an insulated gate bipolar transistor (IGBT) includes a barrier metal structure in which a titanium layer and a titanium nitride layer are stacked (for example, see Patent Documents 1 to 4).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2016-225512

[0004] Patent Document 2: Japanese Patent Application Publication No. 2000-195819

[0005] Patent Document 3: Japanese Patent No. 5672719

[0006] Patent Document 4: Japanese Patent Application Laid-Open No. 6-97111 Summary of the invention

[0007] Technical issues

[0008] Defects formed in the semiconductor substrate can be restored by injecting hydrogen ions into the semiconductor substrate. However, since the titanium layer blocks the passage of hydrogen, if a barrier metal is provided, the defects in the semiconductor substrate may not be fully restored.

[0009] Technical Solution

[0010] In order to solve the above-mentioned problems, in a first embodiment of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor device may have an interlayer insulating film arranged on the upper surface of the semiconductor substrate. The semiconductor device may have a titanium layer arranged on the interlayer insulating film. The semiconductor device may have a titanium nitride layer arranged on the titanium layer. The interlayer insulating film may be provided with an opening that exposes a portion of the upper surface of the semiconductor substrate. The titanium layer and the titanium nitride layer may also be provided in the opening. The titanium layer that is in contact with the semiconductor substrate and arranged at the bottom of the opening may be entirely titanium silicided.

[0011] The semiconductor device may include a tungsten plug provided on the titanium nitride layer in the opening.

[0012] The titanium layer provided on the interlayer insulating film in the region other than the opening may be a titanium layer not including a portion subjected to titanium silicide.

[0013] The thickness of the titanium layer provided on the interlayer insulating film in the region other than the opening may be greater than or equal to 30 nm and less than or equal to 45 nm.

[0014] At least a portion of a side wall of the interlayer insulating film in the opening may have an upwardly convex curved surface shape.

[0015] The semiconductor substrate may have a plurality of groove portions arranged from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate and arranged side by side on the upper surface of the semiconductor substrate along a predetermined arrangement direction. The semiconductor substrate may have a mesa portion sandwiched by two groove portions in the arrangement direction. The interlayer insulating film may be arranged in a manner covering the upper ends of at least a portion of the groove portions. The opening may be arranged in a manner exposing at least a portion of the upper surface of the mesa portion. At least above the two ends of the mesa portion in the arrangement direction, the sidewall of the interlayer insulating film may have a curved surface shape.

[0016] The semiconductor device may include a second titanium layer which is provided on the titanium nitride layer and the tungsten plug and is not silicided.

[0017] In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method may include an insulating film forming step of forming an interlayer insulating film on the upper surface of a semiconductor substrate. The manufacturing method may include an opening forming step of forming an opening in the interlayer insulating film to expose a portion of the upper surface of the semiconductor substrate. The manufacturing method may include a titanium layer forming step of forming a titanium layer on the interlayer insulating film and in the opening. The manufacturing method may include a titanium nitride layer forming step of forming a titanium nitride layer on the titanium layer. The manufacturing method may include a titanium silicide step of subjecting the entire titanium layer that is in contact with the semiconductor substrate and arranged at the bottom of the opening to titanium silicide.

[0018] In the titanium silicidation step, the semiconductor substrate may be annealed at a temperature above 700° C.

[0019] In the titanium layer forming step, a titanium layer having a thickness of 30 nm or more and 45 nm or less can be formed.

[0020] The manufacturing method may include a tungsten plug forming step of forming a tungsten plug on the titanium nitride layer in the opening. The temperature at which the semiconductor substrate is annealed in the titanium silicide step may be higher than the temperature at which tungsten is formed into a film in the tungsten plug forming step.

[0021] The manufacturing method may include a hydrogen annealing step of annealing the semiconductor substrate in an atmosphere containing hydrogen before the titanium layer forming step. The temperature at which the semiconductor substrate is annealed in the titanium silicidation step may be higher than the annealing temperature in the hydrogen annealing step.

[0022] It should be noted that the above-mentioned summary of the invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute other inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. 1 is a diagram showing a structure of a top surface of a semiconductor device 100 according to an embodiment of the present invention.

[0024] Figure 2It is magnified Figure 1 A diagram of the vicinity of region 130 in FIG.

[0025] Figure 3 Yes means Figure 2 FIG. 1 is a diagram of an example of the aa section in FIG.

[0026] Figure 4 is a cross-sectional view showing an example of the structure of the barrier metal 110 .

[0027] Figure 5 FIG. 5 is a diagram showing another example of the shape of the contact hole 54 .

[0028] Figure 6 1 is a diagram showing another structural example of the barrier metal 110 .

[0029] Figure 7 The diagram shows a part of the steps in the method for manufacturing the semiconductor device 100 .

[0030] Figure 8 3 is a graph showing the relationship between the annealing temperature in the titanium silicidation step S610 and the variation (3σ) in the threshold voltage Vth of the semiconductor device 100 .

[0031] Fig. 9 3 is a graph showing the relationship between the thickness T1 of the titanium layer 114 and the variation in the threshold voltage Vth.

[0032] Explanation of symbols

[0033] 10···semiconductor substrate, 11···well region, 12···emitter region, 14···base region, 15···contact region, 16···accumulation region, 18···drift region, 20···buffer region, 21···upper surface, 22···collector region, 23···lower surface, 24···collector, 25···connecting portion, 30···dummy groove portion, 32···dummy insulating film, 34···dummy conductive portion, 38···interlayer insulating film, 39···upper position, 40···gate groove portion, 42···gate insulating film, 44···gate conductive portion, 48···gate runner, 49···contact hole, 50···gate metal layer, 52 ···Emitter, 53···Sidewall, 54···Contact hole, 55···Bottom, 56···Contact hole, 60···Mesa portion, 61···Two ends, 70···Transistor portion, 80···Diode portion, 82···Cathode region, 90···Edge terminal structure portion, 92···Guard ring, 100···Semiconductor device, 102···Active region, 104···Gate pad, 106···Emitter pad, 110···Barrier metal, 112···Titanium nitride layer, 114···Titanium layer, 115···Second titanium layer, 116···Titanium silicide layer, 120···Tungsten plug, 130···Region, 140···Peripheral end. DETAILED DESCRIPTION

[0034] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention of the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the solution of the invention.

[0035] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the mounting direction to a substrate when mounting a semiconductor device.

[0036] In this specification, technical matters are sometimes described using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the upper surface of a semiconductor substrate is referred to as an XY plane, and a depth direction perpendicular to the upper surface of the semiconductor substrate is referred to as a Z axis.

[0037] In each embodiment, an example is shown in which the conductivity type of each region in the semiconductor substrate is set to N type or P type, but the conductivity type of each region can be the opposite conductivity type. In addition, in this specification, when it is recorded as P+ type (or N+ type), it means that the doping concentration is higher than that of P type (or N type), and when it is recorded as P-type (or N-type), it means that the doping concentration is lower than that of P type (or N type).

[0038] In this specification, doping concentration refers to the concentration of donor- or acceptor-type impurities. In this specification, the difference in concentration between donors and acceptors is sometimes referred to as doping concentration. In addition, the peak value of the doping concentration distribution in a doping region is sometimes referred to as the doping concentration in the doping region.

[0039] Figure 1 1 is a diagram showing the structure of the upper surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 in this example is a silicon substrate, but it may be a substrate of other materials as long as it is a substrate damaged by hydrogen ions. There are damages such as crystal defects caused by the implantation of donor ions or acceptor ions inside the semiconductor substrate 10.

[0040] In this specification, the end of the periphery of the semiconductor substrate 10 when viewed from above is referred to as the peripheral end 140. Viewed from above refers to the situation of observing from the upper surface side of the semiconductor substrate 10 in parallel with the Z axis. The semiconductor device 100 of this example includes an active region 102 and an edge terminal structure portion 90. The active region 102 is a region where the main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in the on state. In other words, it is a region where the current flows inside the semiconductor substrate 10 along the depth direction from the upper surface of the semiconductor substrate 10 toward the lower surface, or from the lower surface toward the upper surface.

[0041] The transistor portion 70 is provided in the active region 102. Figure 1 As shown, a diode unit 80 may be further provided in the active region 102. The transistor unit 70 includes a transistor such as an IGBT. The diode unit 80 includes a diode such as a freewheeling diode (FWD). The transistor unit 70 and the diode unit 80 are alternately arranged on the upper surface of the semiconductor substrate 10 in a predetermined arrangement direction. The arrangement direction is Figure 1 The X-axis direction.

[0042] In each diode portion 80 , an N+ type cathode region is provided in a region in contact with the lower surface of the semiconductor substrate 10 . Figure 1The diode portion 80 indicated by the solid line in FIG. 1 is a region where a cathode region is provided on the lower surface of the semiconductor substrate 10. In the semiconductor device 100 of this example, the region other than the cathode region in the region in contact with the lower surface of the semiconductor substrate is a P+ type collector region.

[0043] The edge termination structure portion 90 is provided on the upper surface of the semiconductor substrate 10 between the active region 102 and the outer peripheral end 140 of the semiconductor substrate 10. The edge termination structure portion 90 may be arranged in a ring shape on the upper surface of the semiconductor substrate 10 so as to surround the active region 102. The edge termination structure portion 90 of this example is arranged along the outer peripheral end 140 of the semiconductor substrate 10. The edge termination structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 includes, for example, a guard ring, a field plate, a surface field reduction structure, and a structure formed by combining them.

[0044] On the upper surface of the semiconductor substrate 10, a gate metal layer 50 is provided between the edge termination structure 90 and the active region 102. An interlayer insulating film is provided between the gate metal layer 50 and the semiconductor substrate 10. Figure 1 Omitted in.

[0045] When looking down at the semiconductor substrate 10, the gate metal layer 50 may be provided in a manner of surrounding the active region 102. The gate metal layer 50 is electrically connected to a gate pad 104 provided outside the active region 102. The gate pad 104 may be disposed between the gate metal layer 50 and the active region 102. One or more pads such as an emitter pad 106 electrically connected to the emitter may be provided between the gate metal layer 50 and the active region 102.

[0046] The gate metal layer 50 may be formed of aluminum or an aluminum-silicon alloy. The gate metal layer 50 is electrically connected to the transistor portion 70 and supplies a gate voltage to the transistor portion 70.

[0047] The semiconductor device 100 may include a gate runner 48. The gate runner 48 is electrically connected to the gate metal layer 50 and extends above the active region 102. At least one gate runner 48 may be provided in a manner that crosses the active region 102 in the X-axis direction. The gate runner 48 supplies a gate voltage to the transistor portion 70. The gate runner 48 may be formed of a semiconductor material such as polysilicon doped with impurities, or may be formed of a metal. The gate runner 48 is provided above or inside the semiconductor substrate 10, and the semiconductor substrate 10 and the gate runner 48 are insulated by an insulating film.

[0048] Figure 2 It is magnified Figure 1130 in the vicinity of the region 130 in the semiconductor substrate 10. The semiconductor device 100 of this example includes a guard ring 92, a gate groove portion 40, a dummy groove portion 30, a P+ type well region 11, an N+ type emitter region 12, a P- type base region 14, and a P+ type contact region 15, which are arranged inside the semiconductor substrate 10 and exposed on the upper surface of the semiconductor substrate 10. In this specification, the gate groove portion 40 or the dummy groove portion 30 is sometimes simply referred to as a groove portion. In addition, the semiconductor device 100 of this example includes an emitter 52 and a gate metal layer 50 arranged above the upper surface of the semiconductor substrate 10. The emitter 52 and the gate metal layer 50 are arranged in a manner separated from each other.

[0049] An edge termination structure 90 is disposed outside the gate metal layer 50 (on the positive side in the Y-axis direction). As described above, the edge termination structure 90 may have one or more guard rings 92. The guard ring 92 is a P-type region disposed inside the semiconductor substrate 10. The guard ring 92 is disposed in a ring shape outside the gate metal layer 50 so as to surround the active region 102.

[0050] An interlayer insulating film is provided between the emitter 52 and the gate metal layer 50 and the upper surface of the semiconductor substrate 10. Figure 2 In the interlayer insulating film of this example, the contact hole 56, the contact hole 49, and the contact hole 54 are provided so as to penetrate the interlayer insulating film.

[0051] The emitter 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. In addition, the emitter 52 is connected to the dummy conductive portion in the dummy groove portion 30 through the contact hole 56. A connecting portion 25 formed of a conductive material such as polysilicon doped with impurities may be provided between the emitter 52 and the dummy conductive portion. An insulating film such as an oxide film is formed between the connecting portion 25 and the upper surface of the semiconductor substrate 10.

[0052] The gate metal layer 50 contacts the gate runner 48 through the contact hole 49. Figure 1 In the embodiment of the present invention, the gate runner 48 in the region 130 is omitted. At the end of the active region 102, the gate metal layer 50 can be connected to the gate trench portion 40 without the gate runner 48 being interposed.

[0053] The gate runner 48 is formed of polysilicon doped with impurities, etc. The gate runner 48 is connected to the gate conductive portion in the gate groove portion 40 on the upper surface of the semiconductor substrate 10. The gate runner 48 is not connected to the dummy conductive portion in the dummy groove portion 30. The gate runner 48 of this example is provided from the bottom of the contact hole 49 to the front end of the gate groove portion 40.

[0054] An insulating film such as an oxide film is provided between the gate runner 48 and the upper surface of the semiconductor substrate 10. At the front end of the gate trench 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate 10. A contact hole for connecting the gate conductive portion and the gate runner 48 is provided in the insulating film above the gate conductive portion.

[0055] The emitter 52 is formed of a material containing metal. It should be noted that a barrier metal including a titanium layer and a titanium nitride layer is provided between the emitter 52 and the semiconductor substrate 10, but Figure 2 The barrier metal may be provided in the transistor portion 70 or in the transistor portion 70 and the diode portion 80. The barrier metal in this example is provided in the entire region where the emitter electrode 52 is arranged.

[0056] One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. In the transistor portion 70 of this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately arranged along the arrangement direction. The dummy trench portions 30 are arranged between the gate trench portions 40. In the diode portion 80, a plurality of dummy trench portions 30 are arranged on the upper surface of the semiconductor substrate 10 along the X-axis direction.

[0057] Emitter 52 is disposed above gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. Well region 11 may have a diffusion depth deeper than gate trench 40 and dummy trench 30.

[0058] One or more mesa portions 60 sandwiched between the trench portions are provided in each of the transistor portion 70 and the diode portion 80. The mesa portion 60 is a region of the semiconductor substrate 10 sandwiched between the trench portions and located closer to the upper surface than the deepest bottom of the trench portion.

[0059] The base region 14 is provided in the mesa portion 60 sandwiched between the trench portions. The base region 14 is of the second conductivity type (P-type) having a lower doping concentration than the well region 11 .

[0060] A contact region 15 of the second conductivity type having a higher doping concentration than the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60. The base region 14 is exposed between the well region 11 and the contact region 15 on the upper surface of the semiconductor substrate 10.

[0061] In the transistor portion 70 , the emitter region 12 of the first conductivity type having a higher doping concentration than the drift region provided in the semiconductor substrate 10 is selectively provided on the upper surface of the mesa portion 60 .

[0062] In the mesa portion 60 of the transistor portion 70 of this example, the contact region 15 and the emitter region 12 are alternately arranged along the Y-axis direction. The contact region 15 and the emitter region 12 are respectively arranged from one adjacent groove portion to the other groove portion. In another example, the contact region 15 and the emitter region 12 can be respectively arranged in a stripe shape along the Y-axis direction. In this case, in the mesa portion 60, the emitter region 12 can be arranged at both ends in the X-axis direction in contact with the groove portion, and the contact region 15 can be arranged in the center of the mesa portion 60 in the X-axis direction sandwiched by the two emitter regions 12.

[0063] In one or more mesa portions 60 provided at the boundary with the diode portion 80 among the mesa portions 60 of the transistor portion 70 , a contact region 15 having a larger area than that of the contact regions 15 of the other mesa portions 60 is provided.

[0064] The base region 14 is arranged on the upper surface of the mesa portion 60 of the diode portion 80. However, the contact region 15 may be selectively provided on the mesa portion 60.

[0065] In each mesa portion 60 of this example, the contact hole 54 is provided above each region of the contact region 15, the emitter region 12, and the base region 14. The contact hole 54 of this example is not provided in a region corresponding to the well region 11.

[0066] In the diode portion 80, an N+ type cathode region 82 is provided in a region in contact with the lower surface of the semiconductor substrate 10. Figure 2 In FIG. 1 , a region where the cathode region 82 is provided is indicated by a dotted line. In a region in contact with the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region may be provided.

[0067] Figure 3 Yes means Figure 2 1 is a diagram showing an example of the aa cross section in FIG. The aa cross section is an XZ cross section passing through the emitter region 12 in the transistor portion 70 .

[0068] The semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, a barrier metal 110, an emitter 52, and a collector 24 in this cross section. The interlayer insulating film 38 is provided so as to cover at least a portion of the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be provided on the entire upper surface 21. The interlayer insulating film 38 may be a silicate glass such as PSG or BPSG, or may be an oxide film or a nitride film.

[0069] The interlayer insulating film 38 is provided with an opening such as a contact hole 54. The upper surface 21 of the semiconductor substrate 10 is exposed through the contact hole 54. The contact hole 54 may be arranged at the center of the mesa portion 60 in the X-axis direction. The contact hole 54 is arranged apart from the trench portion in the X-axis direction.

[0070] The barrier metal 110 is provided on the interlayer insulating film 38. The barrier metal 110 is also provided inside the contact hole 54, and is in contact with the upper surface 21 of the semiconductor substrate 10 exposed through the contact hole 54. The barrier metal 110 is provided continuously across two or more contact holes 54. The barrier metal 110 of this example is arranged in the entire region where the emitter 52 is provided.

[0071] The emitter 52 is provided on the barrier metal 110. The emitter 52 may also be provided inside the contact hole 54. In this example, a tungsten plug 120 is provided on the barrier metal 110 inside the contact hole 54. The tungsten plug 120 of this example is not provided in a region outside the contact hole 54. The emitter 52 is also provided on the tungsten plug 120. By providing the tungsten plug 120, even when the width of the contact hole 54 becomes fine, the electrical connection between the emitter 52 and the semiconductor substrate 10 can be easily obtained.

[0072] A protective film such as polyimide is formed above the outer peripheral ends of the emitter 52, the gate pad 104, and the emitter pad 106, and above the edge terminal structure 90. In addition, the semiconductor device 100 is sometimes used in a state where it is arranged in a package and covered with a sealing gel or in a state where it is resin molded. At this time, the emitter 52 is in contact with a sealing gel such as silicone gel or a molding resin such as an epoxy resin. If a defect occurs in the emitter 52, resin ions from the sealing gel or the molding resin sometimes pass through the emitter 52 and reach the gate insulating film. If the resin ions are captured in the gate insulating film, the threshold voltage of the semiconductor device 100 will change. By providing a barrier metal on the entire surface of the emitter 52, it is possible to suppress the resin ions from reaching the gate insulating film.

[0073] However, if the barrier metal is provided on the entire surface, the passage of hydrogen ions is suppressed. Although there are damages such as crystal defects caused by the implantation of donor ions or acceptor ions inside the semiconductor substrate 10, the damage can be restored by implanting hydrogen ions and performing annealing. Therefore, if the barrier metal is provided on the entire surface, it is difficult to restore the damage inside the semiconductor substrate 10. In the semiconductor device 100 of this example, the barrier metal 110 has Figure 4 The structure described later in the above-mentioned examples allows hydrogen ions to pass through and thereby restores the damage to the semiconductor substrate 10 .

[0074] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 may not be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter 52 and the collector electrode 24 are formed of a conductive material such as a metal. For example, at least a portion of the emitter 52 and the collector electrode 24 is formed of aluminum or an alloy having aluminum as a main component. As alloys having aluminum as a main component, there are aluminum-silicon alloys, aluminum-copper alloys, and aluminum-silicon-copper alloys. In this specification, the direction connecting the emitter 52 and the collector electrode 24 is referred to as the depth direction (Z-axis direction).

[0075] A P-type base region 14 is provided on the upper surface side of the semiconductor substrate 10. An N-type drift region 18 is arranged below the base region 14 in the semiconductor substrate 10.

[0076] In each mesa portion 60 of the transistor portion 70 of this example, an N+ type emitter region 12, a P- type base region 14, and an N+ type accumulation region 16 are sequentially arranged from the upper surface side of the semiconductor substrate 10. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. The drift region 18 is provided below the accumulation region 16. By providing an accumulation region 16 having a higher concentration than that of the drift region 18 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be improved, thereby reducing the on-state voltage in the transistor portion 70. The accumulation region 16 may also be provided in the mesa portion 60 of the diode portion 80, or may not be provided in the mesa portion 60 of the diode portion 80.

[0077] In the XZ cross section passing through the contact region 15 of the transistor portion 70, the contact region 15 is provided in each mesa portion 60 of the transistor portion 70 instead of the emitter region 12. The contact region 15 can function as a latch-up suppressing layer for suppressing latch-up.

[0078] In the transistor portion 70 , a P+ type collector region 22 is provided in a region adjacent to the lower surface 23 of the semiconductor substrate 10 . In the diode portion 80 , an N+ type cathode region 82 is provided in a region adjacent to the lower surface 23 of the semiconductor substrate 10 .

[0079] In the semiconductor substrate 10 of this example, an N+ type buffer region 20 is provided between the drift region 18 and the collector region 22 and between the drift region 18 and the cathode region 82. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0080] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each groove portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 to reach the drift region 18. In a region where at least one of the emitter region 12, the contact region 15 and the accumulation region 16 is provided, each groove portion also penetrates these regions to reach the drift region 18. The structure in which the groove portion penetrates the doped region is not limited to the structure manufactured in the order of forming the groove portion after forming the doped region. The formation of the doped region between the groove portions after the groove portion is formed is also included in the structure in which the groove portion penetrates the doped region.

[0081] The gate trench portion 40 includes a gate trench provided on the upper surface side of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided in a manner covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position closer to the inner side than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0082] The gate conductive portion 44 includes a region that is at least opposite to the adjacent base region 14 via the gate insulating film 42 in the depth direction. The gate groove portion 40 at the cross section is covered by the interlayer insulating film 38 on the upper surface of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface in contact with the gate groove in the base region 14.

[0083] The dummy groove portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 has a dummy groove, a dummy insulating film 32 and a dummy conductive portion 34 arranged on the upper surface 21 side of the semiconductor substrate 10. The dummy insulating film 32 is arranged in a manner covering the inner wall of the dummy groove. The dummy insulating film 32 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the dummy groove. The dummy conductive portion 34 is arranged inside the dummy groove and is arranged at a position closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. The dummy groove portion 30 at this cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.

[0084] Figure 41 is a cross-sectional view showing an example of the structure of the barrier metal 110. The barrier metal 110 includes a titanium layer 114 and a titanium nitride layer 112. The titanium layer 114 is provided on the interlayer insulating film 38. The titanium nitride layer 112 is provided on the titanium layer 114. In addition, the titanium layer 114 and the titanium nitride layer 112 are also provided inside the contact hole 54. Inside the contact hole 54, a tungsten plug 120 is provided on the titanium nitride layer 112.

[0085] The contact hole 54 of this example has a bottom 55 that exposes the upper surface 21 of the semiconductor substrate 10 and a side wall 53 that extends upward from the upper surface 21 of the semiconductor substrate 10. The titanium layer 114 is provided along the bottom 55 and the side wall 53 of the contact hole 54. However, the titanium layer 114 that is in contact with the semiconductor substrate 10 and is arranged at the bottom 55 is entirely silicided. Figure 4 In the embodiment, the titanium layer 114 which is titanium silicided is used as the titanium silicide layer 116. Titanium silicide refers to a compound composed of titanium and silicon, such as TiSi and / or TiSi2, and these compounds may exist alone or in combination.

[0086] The titanium layer 114 is completely silicided, which means that in the Z-axis direction, the entire area from the portion in contact with the upper surface 21 of the semiconductor substrate 10 to the portion in contact with the titanium nitride layer 112 is silicided. In other words, there is no titanium that has not been silicided in this area. However, in the titanium layer 114 extending upward along the side wall 53, the portion in contact with the upper surface 21 of the semiconductor substrate 10 is silicided with a predetermined thickness T3. The portion of the titanium layer 114 arranged along the side wall 53 that is closer to the upper side than the thickness T3 may remain without being silicided. It should be noted that the entire titanium nitride layer 112 in this example is not silicided and remains.

[0087] The titanium silicide layer 116 can be formed by annealing the semiconductor substrate 10 after the titanium layer 114 is provided. The annealing is performed under conditions that enable the titanium layer 114 of a predetermined thickness to be titanium silicided over the entire region in the thickness direction. As an example, the thickness T1 of the titanium layer 114 in the Z-axis direction is 45 nm or less, and the annealing temperature is 700° C. or more. The annealing temperature may be 750° C. or more, or 800° C. or more. The annealing time may be 5 minutes or more, 10 minutes or more, or 15 minutes or more.

[0088] It should be noted that the thickness of the titanium nitride layer 112 may be more than twice the thickness of the titanium layer 114. As an example, the thickness of the titanium nitride layer 112 is 100 nm. In addition, as an example, the thickness of the emitter 52 is 5 μm. The thickness of the tungsten plug 120 is greater than the thickness of the titanium nitride layer 112 and smaller than the thickness of the emitter 52. As an example, the thickness of the tungsten plug 120 is 700 nm.

[0089] The titanium nitride layer 112 is more difficult to be silicided than the titanium layer 114. Therefore, the semiconductor substrate 10 can be annealed under predetermined conditions after the titanium layer 114 and the titanium nitride layer 112 are provided. Thus, the titanium layer 114 at the bottom 55 can be completely silicided, and the entire titanium nitride layer 112 can be left. In another example, the titanium nitride layer 112 can be formed after the titanium layer 114 at the bottom 55 is silicided. Thus, the entire titanium nitride layer 112 can be easily left. By leaving the entire titanium nitride layer 112, it is easy to suppress the aluminum of the emitter 52 and the like from invading the semiconductor substrate 10.

[0090] By making the titanium layer 114 of the bottom 55 completely titanium silicided, hydrogen can easily pass through the titanium silicide layer 116. Therefore, hydrogen can easily enter the interior of the semiconductor substrate 10, and it is easy to restore the damage caused by crystal defects and the like in the interior of the semiconductor substrate 10. In addition, by providing the titanium silicide layer 116, the contact resistance between the barrier metal 110 and the semiconductor substrate 10 can be reduced.

[0091] For example, in the process of forming the tungsten plug 120, a large amount of hydrogen may be used to remove fluorine, etc. In such a process, hydrogen ions are implanted into the semiconductor substrate 10 via the titanium silicide layer 116 to recover damage in the substrate.

[0092] It should be noted that the titanium layer 114 provided on the interlayer insulating film 38 may not contain a titanium silicided portion. For example, the titanium layer 114 disposed above both ends 61 in the X-axis direction of the mesa portion 60 does not contain a titanium silicided portion. This makes it easy to suppress aluminum of the emitter 52 and the like from invading the interlayer insulating film 38.

[0093] In the area outside the contact hole 54, the thickness T1 of the titanium layer 114 provided on the interlayer insulating film 38 can be greater than 30 nm and less than 45 nm. It should be noted that the thickness of the titanium layer 114 inside the contact hole 54 before titanium silicide is also T1. The thickness T2 of the titanium silicide layer 116 can be the same as or different from the thickness T1.

[0094] If the thickness T1 of the titanium layer 114 is too large, it is difficult to silicide the entire contact portion between the semiconductor substrate 10 and the titanium layer 114. The thickness T1 of the titanium layer 114 may be 40 nm or less. Thus, it is relatively easy to silicide the entire contact portion between the semiconductor substrate 10 and the titanium layer 114. If the thickness T1 of the titanium layer 114 is too small, it is difficult to maintain the uniformity of the film thickness. In addition, if the thickness T1 is too small, when bonding a wire or the like above the emitter 52, the emitter 52 may sometimes penetrate the barrier metal 110. The thickness T1 may be 35 nm or more.

[0095] As described above, the titanium layer 114 disposed along the sidewall 53 of the contact hole 54 is titanium silicided to a predetermined thickness T3 from the upper surface 21 of the semiconductor substrate 10. The thickness T3 may be the same as the thickness T2 or may be greater than the thickness T2. By increasing the thickness T3 of the titanium silicide layer 116 in the titanium layer 114 along the sidewall 53, hydrogen ions can easily pass through the end of the bottom 55 of the contact hole 54. Therefore, hydrogen ions can also easily enter the region of the semiconductor substrate 10 adjacent to the bottom 55 (i.e., the region near the groove portion). Therefore, it is easy to terminate defects in the region near the groove portion and restore damage to the substrate. As an example, the thickness T2 of the titanium silicide layer 116 is the thickness of the titanium silicide layer 116 in the Z-axis direction at the center of the bottom 55 in the X-axis direction, and the thickness T3 is the thickness of the titanium silicide layer 116 in the Z-axis direction in contact with the sidewall 53.

[0096] Figure 5 FIG. 5 is a diagram showing another example of the shape of the contact hole 54. Figure 4 In the example of FIG. 5 , the side wall 53 of the interlayer insulating film 38 at the contact hole 54 has a straight line shape. Figure 5 In the example, at least a portion of the sidewall 53 of the interlayer insulating film 38 at the contact hole 54 has an upwardly convex curved surface. Therefore, the contact hole 54 has a tapered shape in which the opening area increases as it is farther from the upper surface 21 of the semiconductor substrate 10.

[0097] The shape of the side wall 53 can be controlled by a process such as reflow after forming the contact hole 54. Figure 4 The contact hole 54 in the example is formed by anisotropic etching such as dry etching. Figure 5 The contact hole 54 in the example can be formed by melting the interlayer insulating film 38 at a predetermined temperature after forming an opening by anisotropic etching.

[0098] In this example, a titanium silicide layer 116 in which the titanium layer 114 is completely silicided with titanium is also provided at the bottom 55 of the contact hole 54. Since the side wall 53 has a curved surface shape, hydrogen ions can easily reach the bottom 55 of the contact hole 54. Therefore, damage caused by crystal defects and the like in the semiconductor substrate 10 can be easily restored.

[0099] As an example, the side wall 53 of the interlayer insulating film 38 may have a curved surface shape above the two ends 61 in the X-axis direction of the mesa portion 60. The side wall 53 may have a curved surface shape from a position in contact with the upper surface 21 of the semiconductor substrate 10 to a position closer to the outside than the position 39 above the two ends 61 of the mesa portion 60.

[0100] Figure 6 is a diagram showing another structural example of the barrier metal 110. The barrier metal 110 of this example can be applied to Figure 4 and Figure 5 In addition to the barrier metal 110 of this example Figure 4 or Figure 5 In addition to the structure shown, a second titanium layer 115 is further provided.

[0101] The second titanium layer 115 is provided on the titanium nitride layer 112 and the tungsten plug 120. The second titanium layer 115 does not have a portion that is silicided with titanium.

[0102] The second titanium layer 115 of this example is formed after the tungsten plug 120. Therefore, the damage of the semiconductor substrate 10 has been recovered before the second titanium layer 115 is provided. By providing the second titanium layer 115, the strength of the barrier metal 110 can be further improved, and in addition, hydrogen intrusion into the gate insulating film can be suppressed during actual use. Therefore, the change of characteristics over time can be suppressed.

[0103] Figure 7 1 is a diagram showing a part of the steps in the manufacturing method of the semiconductor device 100. The manufacturing method of this example includes an insulating film forming step S600. In the insulating film forming step S600, an interlayer insulating film 38 is formed on the upper surface 21 of the semiconductor substrate 10. Another film such as an oxide film may be provided between the upper surface 21 and the interlayer insulating film 38.

[0104] The manufacturing method of this example includes an opening forming step S602 after the insulating film forming step S600. The opening forming step S602 may include a process of forming a predetermined mask pattern on the interlayer insulating film 38, a process of etching the interlayer insulating film 38 using the mask pattern, and a process of removing the mask pattern. Thus, an opening such as the contact hole 54 is formed.

[0105] The manufacturing method of this example includes a hydrogen annealing step S604 after the opening forming step S602. If there is no ion implantation process after the insulating film forming step S600, the hydrogen annealing step S604 can also be performed before the insulating film forming step S600. In the hydrogen annealing step S604, the semiconductor substrate 10 is annealed in an atmosphere containing hydrogen. The hydrogen annealing step S604 can be performed after forming doped regions such as the emitter region 12, the contact region 15, the base region 14, and the well region 11. Thereby, at least a portion of the damage to the semiconductor substrate 10 generated when forming these doped regions can be restored.

[0106] The manufacturing method of this example includes a titanium layer forming step S606 after the hydrogen annealing step S604. In the titanium layer forming step S606, a titanium layer 114 is formed on the interlayer insulating film 38 and in the opening. The titanium layer 114 can be formed by a method such as sputtering. The thickness T1 of the titanium layer 114 can be greater than 30 nm and less than 45 nm.

[0107] The manufacturing method of this example includes a titanium nitride layer forming step S608 after the titanium layer forming step S606. In the titanium nitride layer forming step S608, a titanium nitride layer 112 is formed on the titanium layer 114. The titanium nitride layer 112 can be formed by a method such as sputtering.

[0108] The manufacturing method of this example includes a titanium silicide step S610 after the titanium nitride layer forming step S608. In the titanium silicide step S610, the titanium layer 114 that is in contact with the semiconductor substrate 10 and disposed at the bottom 55 of the opening is entirely titanium silicided.

[0109] The manufacturing method of this example includes a tungsten plug forming step S612 after the titanium silicide step S610. In the tungsten plug forming step S612, a tungsten plug 120 is formed on the titanium nitride layer 112 in the opening. The tungsten plug 120 can be formed by a CVD method or the like in an atmosphere containing hydrogen. In the tungsten plug forming step S612, hydrogen ions are injected into the interior of the semiconductor substrate 10 through the titanium silicide layer 116, and the damage of the semiconductor substrate 10 is restored.

[0110] It should be noted that hydrogen ions may be implanted into the semiconductor substrate 10 in a process other than the tungsten plug forming step S612. The manufacturing method may include a process of implanting hydrogen ions into the semiconductor substrate 10 and performing annealing after the titanium silicidation step S610.

[0111] Through such a process, it is possible to recover damage inside the semiconductor substrate 10. For example, it is possible to recover damage remaining in the hydrogen annealing step S604 and damage generated after the hydrogen annealing step S604. For example, damage may also be generated inside the semiconductor substrate 10 due to sputtering or the like.

[0112] The temperature at which the semiconductor substrate 10 is annealed in the titanium silicidation step S610 may be higher than the temperature at which the tungsten is formed into a film in the tungsten plug forming step S612. The annealing temperature in the titanium silicidation step S610 is, for example, above 700°C. The film forming temperature in the tungsten plug forming step S612 is, for example, below 500°C. By increasing the annealing temperature in the titanium silicidation step S610, it is easy to titanium silicidate the entire titanium layer 114. The annealing time in the titanium silicidation step S610 may be longer than the film forming time in the tungsten plug forming step S612. The annealing time in the titanium silicidation step S610 is, for example, above 5 minutes. The annealing time may also be above 10 minutes, or may be above 15 minutes. The film forming time in the tungsten plug forming step S612 is, for example, below 3 minutes.

[0113] The temperature at which the semiconductor substrate 10 is annealed in the titanium silicidation step S610 may be higher than the annealing temperature in the hydrogen annealing step S604. The annealing temperature in the hydrogen annealing step S604 is, for example, 500° C. or less. The annealing time in the titanium silicidation step S610 may be shorter than the annealing time in the hydrogen annealing step S604, or longer than the annealing time in the hydrogen annealing step S604. The annealing time in the hydrogen annealing step S604 is, for example, 10 minutes or less.

[0114] The manufacturing method may include a contact plug forming step of forming a P-type contact plug region having a higher doping concentration than the contact region 15 on the upper surface of the semiconductor substrate 10 exposed by the contact hole 54. The contact plug region may be provided only in the transistor portion 70 or in the transistor portion 70 and the diode portion 80.

[0115] The contact plug region can be formed by implanting impurity ions into a range shallower than the contact region 15. By forming the contact plug region, the contact resistance between the barrier metal 110 and the semiconductor substrate 10 can be reduced. The contact plug formation step can be performed between the opening formation step S602 and the titanium layer formation step S606. As described above, the damage generated in the contact plug region formation step can also be restored in the tungsten plug formation step S612 and the like.

[0116] like Figure 5 As described in , the manufacturing method may further include a reflow step of making the side wall 53 of the interlayer insulating film 38 into a curved surface shape. The reflow step is performed after the opening forming step S602. The reflow step may be performed between the opening forming step S602 and the contact plug forming step.

[0117] like Figure 6 As described in , the manufacturing method may further include a second titanium layer forming step of forming the second titanium layer 115. The second titanium layer forming step is performed after the tungsten plug forming step S612. In the second titanium layer forming step, the second titanium layer 115 may be formed by sputtering or the like.

[0118] Figure 8 1 is a graph showing the relationship between the annealing temperature in the titanium silicidation step S610 and the deviation (3σ) of the threshold voltage Vth of the semiconductor device 100. The thickness of the titanium layer 114 in this example is 40 nm. In addition, the annealing time is 10 minutes. The threshold voltage Vth varies according to damage such as crystal defects inside the semiconductor substrate 10. If the damage to the semiconductor substrate 10 is not fully recovered, the degree of recovery of the damage will deviate, and the deviation of the threshold voltage Vth will increase. In this way, residual damage such as crystal defects affects the characteristics of the semiconductor device 100.

[0119] like Figure 8As shown in FIG. 1 , if the annealing temperature reaches 700° C., the deviation of the threshold voltage Vth is suppressed. In addition, even if the annealing temperature is higher than 700° C., the deviation of the threshold voltage Vth does not change much. It is believed that this is because the titanium layer 114 in contact with the upper surface 21 of the semiconductor substrate 10 is completely silicided by setting the annealing temperature to 700° C.

[0120] It should be noted that, when neither the titanium silicide step S610 nor the tungsten plug forming step S612 (i.e., the step of injecting hydrogen after the titanium silicide step S610) is performed, the deviation of the threshold voltage Vth does not decrease. Therefore, it is considered that the damage to the semiconductor substrate 10 is restored by the hydrogen ions passing through the titanium silicide layer 116.

[0121] Fig. 9 1 is a graph showing the relationship between the thickness T1 of the titanium layer 114 and the deviation of the threshold voltage Vth. The annealing time in this example is 10 minutes. Fig. 9 The case where the annealing temperature is 660°C and the case where the annealing temperature is 700°C are shown in FIG.

[0122] When the annealing temperature is 700°C, if the thickness T1 of the titanium layer 114 is less than 45nm, the deviation of the threshold voltage Vth becomes relatively small. In addition, if the thickness T1 of the titanium layer 114 is set to less than 40nm, the deviation of the threshold voltage Vth is approximately constant. It is considered that in the region where the thickness T1 is less than 40nm, the titanium layer 114 in contact with the upper surface 21 of the semiconductor substrate 10 is all titanium silicided. As an example, the thickness T1 of the titanium layer 114 can be less than 40nm, and the annealing temperature can be more than 700°C.

[0123] It should be noted that, when the annealing temperature is 660°C, even if the thickness T1 of the titanium layer 114 is set to 40 nm, the deviation of the threshold voltage Vth does not decrease. It is considered that under this condition, titanium remains in the titanium layer 114 in contact with the semiconductor substrate 10 and is not silicided. Figure 5 As shown in the figure, when the side wall 53 of the interlayer insulating film 38 is curved, even if the annealing temperature is 660° C., the variation in the threshold voltage Vth becomes small.

[0124] It should be noted that the tensile strength test of the emitter 52 was conducted at annealing temperatures of 650° C., 700° C., and 750° C. In the tensile strength test, a lead was bonded to the emitter 52 and then pulled to test whether peeling of the emitter 52 occurred. Even when the annealing temperature was increased to 700° C. or 750° C., no decrease in tensile strength was observed.

[0125] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, it can be known that the various changes or improvements are also included in the technical scope of the present invention.

[0126] It should be noted that as long as the execution order of each process such as work, sequence, step and stage in the device, system, program and method shown in the claims, description and drawings is not specifically specified as "before...", "prior to...", etc., and as long as the result of the previous process is not used in the subsequent process, it can be implemented in any order. Even if the workflow in the claims, description and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be executed in this order.

Claims

1. A semiconductor device, characterized in that: have: Semiconductor substrates; an interlayer insulating film disposed on the upper surface of the semiconductor substrate; a titanium layer disposed on the interlayer insulating film; and a titanium nitride layer disposed on the titanium layer, The interlayer insulating film is provided with an opening for exposing a portion of the upper surface of the semiconductor substrate. The titanium layer and the titanium nitride layer are also disposed in the opening, The titanium layer in contact with the semiconductor substrate and arranged at the bottom of the opening is entirely titanium silicided. The titanium layer arranged along the side wall in the opening is silicided from the upper surface to a thickness greater than a thickness of the titanium layer silicided at the center of the bottom of the opening from the upper surface of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a tungsten plug provided on the titanium nitride layer in the opening.

3. The semiconductor device according to claim 1, wherein: The titanium layer provided on the interlayer insulating film in the region other than the opening is a titanium layer not including a portion subjected to titanium silicide.

4. The semiconductor device according to claim 2, wherein: The titanium layer provided on the interlayer insulating film in the region other than the opening is a titanium layer not including a portion subjected to titanium silicide.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The thickness of the titanium layer provided on the interlayer insulating film in a region other than the opening is greater than or equal to 30 nm and less than or equal to 45 nm.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that At least a portion of a side wall of the interlayer insulating film at the opening has an upwardly convex curved surface shape.

7. The semiconductor device according to claim 5, wherein: At least a portion of a side wall of the interlayer insulating film at the opening has an upwardly convex curved surface shape.

8. The semiconductor device according to claim 6, wherein: The semiconductor substrate has: A plurality of groove portions, which are arranged from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate and are arranged side by side on the upper surface of the semiconductor substrate along a predetermined arrangement direction; as well as a mesa portion sandwiched by two groove portions in the arrangement direction, The interlayer insulating film is provided so as to cover at least a portion of the upper end of the groove portion. The opening is arranged so as to expose at least a portion of the upper surface of the table portion. At least above both ends of the mesa portion in the arrangement direction, the side wall of the interlayer insulating film has the curved surface shape.

9. The semiconductor device according to claim 7, wherein: The semiconductor substrate has: A plurality of groove portions, which are arranged from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate and are arranged side by side on the upper surface of the semiconductor substrate along a predetermined arrangement direction; as well as a mesa portion sandwiched by two groove portions in the arrangement direction, The interlayer insulating film is provided so as to cover at least a portion of the upper end of the groove portion. The opening is arranged so as to expose at least a portion of the upper surface of the table portion. At least above both ends of the mesa portion in the arrangement direction, the side wall of the interlayer insulating film has the curved surface shape.

10. The semiconductor device according to claim 2, wherein: The semiconductor device further includes a second titanium layer, which is provided on the titanium nitride layer and the tungsten plug and is not subjected to titanium silicide.

11. A manufacturing method, characterized in that: include: an insulating film forming step of forming an interlayer insulating film on the upper surface of the semiconductor substrate; an opening forming step of forming an opening in the interlayer insulating film to expose a portion of the upper surface of the semiconductor substrate; a titanium layer forming step of forming a titanium layer on the interlayer insulating film and in the opening; a titanium nitride layer forming step of forming a titanium nitride layer on the titanium layer; as well as a titanium silicide step of silicideing the entire titanium layer that is in contact with the semiconductor substrate and disposed at the bottom of the opening; In the titanium silicide step, the titanium layer arranged along the side wall in the opening is titanium silicided from the upper surface to a thickness greater than the thickness of the titanium layer titanium silicided at the center of the bottom of the opening from the upper surface of the semiconductor substrate.

12. The manufacturing method according to claim 11, characterized in that: In the titanium silicidation step, the semiconductor substrate is annealed at a temperature above 700° C.

13. The manufacturing method according to claim 11, characterized in that: In the titanium layer forming step, the titanium layer is formed to have a thickness of 30 nm or more and 45 nm or less.

14. The manufacturing method according to claim 12, characterized in that: In the titanium layer forming step, the titanium layer is formed to have a thickness of 30 nm or more and 45 nm or less.

15. The manufacturing method according to any one of claims 11 to 14, characterized in that: The manufacturing method further includes a tungsten plug forming step of forming a tungsten plug on the titanium nitride layer in the opening. The temperature at which the semiconductor substrate is annealed in the titanium silicide step is higher than the temperature at which tungsten is formed into a film in the tungsten plug formation step.

16. The manufacturing method according to any one of claims 11 to 14, characterized in that: The manufacturing method further includes a hydrogen annealing step of annealing the semiconductor substrate in an atmosphere containing hydrogen before the titanium layer forming step. The temperature at which the semiconductor substrate is annealed in the titanium silicidation step is higher than the annealing temperature in the hydrogen annealing step.

17. The manufacturing method according to claim 15, characterized in that: The manufacturing method further includes a hydrogen annealing step of annealing the semiconductor substrate in an atmosphere containing hydrogen before the titanium layer forming step. The temperature at which the semiconductor substrate is annealed in the titanium silicidation step is higher than the annealing temperature in the hydrogen annealing step.

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