LED short circuit detection circuit, driver chip and driving method

Abstract

The LED short circuit detection circuit provided by the present invention includes a configurable voltage source, a switch control circuit, a digital control storage circuit and a current amplifier circuit; the configurable voltage source generates a sampling voltage and a bias voltage, and transmits them to the switch control circuit and the current amplifier circuit respectively; the current amplifier circuit converts the bias voltage into a current for amplification, generates a driving current for the LED lamp bead, and after receiving a judgment signal, determines whether to output the driving current; after receiving the sampling voltage, the switch control circuit outputs a judgment signal, and transmits it to the current amplifier circuit, and transmits the judgment signal to the digital control storage circuit; the digital control storage circuit turns off the short circuit detection branch current according to the judgment signal and the power-on reset signal. The circuit solves the defect in the prior art that the LED lamp bead is easily burned due to the short circuit of the VREXT end of the LED driver chip, and realizes the VREXT short circuit detection of the low-power LED driver chip, as well as the self-recovery control function.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit chips, and in particular relates to an LED short circuit detection circuit, a driving chip and a driving method. Background Art

[0002] Common LED driver chips generally use constant current drive method to drive LED lamp beads. The working current of LED lamp beads is adjusted by the VREXT end of LED driver chip through external precision resistor. The smaller the external resistor, the greater the current flowing through the LED lamp beads. Generally, the working current of LED lamp beads is less than 30mA. If too much current flows through the LED lamp beads, the LED lamp beads will appear high brightness. Long-term high brightness will cause the LED lamp beads to burn out, which will affect the display effect of the LED display.

[0003] In order to solve the above problem, the existing method samples the voltage at the VREXT end of the LED driver chip and compares it with the reference voltage to determine whether to turn off the driver circuit. However, the disadvantage of this method is that when the VREXT end is short-circuited, the voltage is low and is easily affected by the power supply voltage and substrate noise, resulting in misjudgment, which in turn affects the display effect of the LED display. Summary of the invention

[0004] In view of the defects in the prior art, the present invention provides an LED short-circuit detection circuit, a driver chip and a driving method to solve the defect in the prior art that LED lamp beads are easily burned out due to a short circuit at the VREXT end of the LED driver chip.

[0005] In a first aspect, an LED short circuit detection circuit includes a configurable voltage source, a switch control circuit, a digital control storage circuit, and a current amplification circuit;

[0006] The configurable voltage source is used to generate a sampling voltage and a bias voltage, and transmit them to the switch control circuit and the current amplification circuit respectively;

[0007] The current amplifier circuit is used to convert the bias voltage into current and amplify it to generate a driving current for the LED lamp bead; the current amplifier circuit is also used to determine whether to output the driving current after receiving a judgment signal;

[0008] The switch control circuit is used to output a judgment signal after receiving the sampled voltage, and transmit it to the current amplification circuit; the switch control circuit is also used to transmit the judgment signal to the digital control storage circuit;

[0009] The digital control storage circuit is used to close the short-circuit detection branch current according to the judgment signal and the power-on reset signal.

[0010] Preferably, the input end of the configurable voltage source is connected to the first reference voltage, the VREXT end of the LED driver chip and the judgment delay output port of the switch control circuit, the bias voltage output end of the configurable voltage source is connected to the first input end of the current amplifier circuit, and the sampling voltage output end of the configurable voltage source is connected to the first input end of the switch control circuit;

[0011] The second input terminal of the switch control circuit is connected to the digital output reset signal output port of the digital control storage circuit, and the judgment output port of the switch control circuit is connected to the second input terminal of the current amplifier circuit;

[0012] The judgment output port of the switch control circuit is connected to the first input terminal of the digital control storage circuit, the second input terminal of the digital control storage circuit is connected to the power-on reset signal, the third input terminal of the digital control storage circuit is connected to the external control signal, and the PWM output port of the digital control storage circuit is connected to the third input terminal of the current amplifier circuit;

[0013] The fourth input terminal of the current amplifier circuit is connected to the second reference voltage, and the output terminal of the current amplifier circuit is connected to the output terminal of the LED driver chip.

[0014] Preferably, the judgment delay output port of the switch control circuit is obtained by delaying and reversing its judgment output port.

[0015] Preferably, the configurable voltage source comprises an operational amplifier OP1, a PMOS transistor PM_1, an NMOS transistor NM_4 and a switch SW2;

[0016] The first reference voltage is connected to the non-inverting input terminal of the operational amplifier OP1, the VREXT terminal of the LED driver chip is connected to the reverse input terminal of the operational amplifier OP1 through a series resistor RINT1, the middle node between the resistor RINT1 and the VREXT terminal of the LED driver chip is connected to the drain of the NMOS tube NM_4, and the source and gate of the NMOS tube NM_4 are grounded;

[0017] The output end of the operational amplifier OP1 is connected to the gate of the PMOS tube PM_1, the source of the PMOS tube PM_1 is connected to a high level, the drain of the PMOS tube PM_1 is connected to a contact end of the switch SW2, the other contact end of the switch SW2 is connected in series with the resistor RINT2 to the middle node between the resistor RINT1 and the VREXT end of the LED driver chip, and the control end of the switch SW2 is connected to the judgment delay output port of the switch control circuit;

[0018] The detection end of the operational amplifier OP1 serves as a sampling voltage output end of the configurable voltage source, and the output end of the operational amplifier OP1 serves as a bias voltage output end of the configurable voltage source.

[0019] Preferably, the operational amplifier OP1 includes a PMOS transistor PM_11, a PMOS transistor PM_12, ​​a PMOS transistor PM_13, a PMOS transistor PM_14, a PMOS transistor PM_15, an NMOS transistor NM_11, an NMOS transistor NM_12, ​​an NMOS transistor NM_13 and an NMOS transistor NM_14;

[0020] The gate of the PMOS tube PM_15 is connected to the reference power supply, the drain of the PMOS tube PM_15 is connected to the source of the PMOS tube PM_11 and the PMOS tube PM_12, ​​the source of the PMOS tube PM_15 is connected to the source of the PMOS tube PM_13 and the PMOS tube PM_14, the drain of the PMOS tube PM_13 is connected to the drain of the NMOS tube NM_13, the drain of the PMOS tube PM_14 is connected to the drain of the NMOS tube NM_14, and the drain of the NMOS tube NM_15 is connected to the drain of the NMOS tube NM_16. The gate of the OS transistor NM_13 is connected to the gate of the NMOS transistor NM_14, the source of the NMOS transistor NM_13 is connected to the drain of the NMOS transistor NM_11, the source of the NMOS transistor NM_14 is connected to the drain of the NMOS transistor NM_12, ​​and the sources of the NMOS transistors NM_11 and NMOS transistors NM_12 are grounded; the drain of the PMOS transistor PM_11 is connected to the drain of the NMOS transistor NM_11, and the drain of the PMOS transistor PM_12 is connected to the drain of the NMOS transistor NM_12;

[0021] The node between the drain of the PMOS tube PM_14 and the drain of the NMOS tube NM_14 serves as the output end of the operational amplifier; the gate of the PMOS tube PM_11 serves as the non-inverting input end of the operational amplifier; the gate of the PMOS tube PM_12 serves as the reverse input end of the operational amplifier; the gate of the PMOS tube PM_13, the gate of the PMOS tube PM_14, and the middle node of the drain of the PMOS tube PM_13 and the drain of the NMOS tube NM_13 are connected to each other as the detection end of the operational amplifier.

[0022] Preferably, the switch control circuit includes a PMOS tube PM_3, a current source Ib, a trigger SMIT1, a delay circuit DLY1 and a NAND gate NAND2;

[0023] The sampling voltage output end of the configurable voltage source is connected to the gate of the PMOS tube PM_3, the source of the PMOS tube PM_3 is connected to a high level, the drain of the PMOS tube PM_3 is grounded by being connected in series with the current source Ib, the drain of the PMOS tube PM_3 is connected to the input end of the trigger SMIT1, and the output end of the trigger SMIT1 serves as the judgment output port; the output end of the trigger SMIT1 is connected to the input end of the delay circuit DLY1, the output end of the delay circuit DLY1 is connected to an input end of the NAND gate NAND2, the other input end of the NAND gate NAND2 is connected to the digital output reset signal, and the output end of the NAND gate NAND2 serves as the judgment delay output port.

[0024] Preferably, the current amplifying circuit includes an operational amplifier OP2, an operational amplifier OP3, a PMOS transistor PM_2, a switch SW1, an NMOS transistor NM_1, an NMOS transistor NM_2 and an NMOS transistor NM_3;

[0025] The bias voltage output terminal of the configurable voltage source is connected to the gate of the PMOS tube PM_2, the source of the PMOS tube PM_2 is connected to a high level, the drain of the PMOS tube PM_2 is connected to the drain of the NMOS tube NM_1, the drain of the PMOS tube PM_2 is also connected to the inverting input terminal of the operational amplifier OP2, the non-inverting input terminal of the operational amplifier OP2 is connected to the second reference voltage, the output terminal of the operational amplifier OP2 is connected to the gate of the NMOS tube NM_1, and the source of the NMOS tube NM_1 is grounded;

[0026] The drain of the PMOS transistor PM_2 is connected to the non-inverting input terminal of the operational amplifier OP3, the output terminal of the operational amplifier OP3 is connected to the gate of the NMOS transistor NM_3, the source of the NMOS transistor NM_3 is connected to the drain of the NMOS transistor NM_2, the source of the NMOS transistor NM_3 is connected to the reverse input terminal of the operational amplifier OP3, the source of the NMOS transistor NM_2 is grounded, and the output terminal of the operational amplifier OP2 is connected to the gate of the NMOS transistor NM_2;

[0027] The judgment output port of the switch control circuit is connected to the control end of the switch SW1, one contact end of the switch SW1 is grounded, and the other contact end of the switch SW1 is connected to the output end of the operational amplifier OP2;

[0028] The drain of the NMOS tube NM_3 is connected to the output end of the LED driving chip; the enable end of the operational amplifier OP3 serves as the third input end of the current amplifying circuit.

[0029] Preferably, the operational amplifier OP3 includes an invertor INV1, a PMOS transistor PM_21, a PMOS transistor PM_22, a PMOS transistor PM_23, a PMOS transistor PM_24, a PMOS transistor PM_25, a PMOS transistor PM_26, an NMOS transistor NM_21, an NMOS transistor NM_22, an NMOS transistor NM_23, an NMOS transistor NM_24, a current source I3 and a current source I2;

[0030] The gate of the PMOS tube PM_21 is used as the inverting input terminal of the operational amplifier; the gate of the PMOS tube PM_22 is used as the non-inverting input terminal of the operational amplifier; the source of the PMOS tube PM_21 and the source of the PMOS tube PM_22 are both connected to the drain of the PMOS tube PM_24, the source of the PMOS tube PM_24 is connected to a high level, the gate of the PMOS tube PM_24 is connected to the gate of the PMOS tube PM_23, the source of the PMOS tube PM_23 is connected to a high level, the drain of the PMOS tube PM_23 is grounded by being connected in series with the current source I3, and the gate of the PMOS tube PM_23 is connected to its drain;

[0031] The drain of the PMOS tube PM_21 is connected to the drain of the NMOS tube NM_21, the source of the NMOS tube NM_21 is grounded, and the drain of the NMOS tube NM_21 is connected to its gate; the drain of the PMOS tube PM_22 is connected to the drain of the NMOS tube NM_22, the source of the NMOS tube NM_22 is grounded, and the gate of the NMOS tube NM_21 is connected to the gate of the NMOS tube NM_22;

[0032] The node between the drain of the PMOS tube PM_22 and the drain of the NMOS tube NM_22 is connected to the gate of the NMOS tube NM_23, the source of the NMOS tube NM_23 is grounded, the drain of the NMOS tube NM_23 is connected to the drain of the PMOS tube PM_26, the source of the PMOS tube PM_26 is connected to the drain of the PMOS tube PM_25, the source of the PMOS tube PM_25 is connected to a high level, and the gate of the PMOS tube PM_26 is connected to the PMOS tube PM_23. The gate of the operational amplifier OP3 is connected to the input end of the invertor INV1, the output end of the invertor INV1 is connected to the gate of the PMOS tube PM_25, the output end of the invertor INV1 is connected to the gate of the NMOS tube NM_24, the source of the NMOS tube NM_24 is grounded by being connected in series with the current source I2, the drain of the NMOS tube NM_24 is connected to the drain of the NMOS tube NM_23, and the drain of the NMOS tube NM_24 is connected in series with the resistor R1 as the output end of the operational amplifier.

[0033] In a second aspect, an LED driver chip is provided.

[0034] It includes the LED short circuit detection circuit described in the first aspect.

[0035] In a third aspect, an LED driving method is performed on the LED short circuit detection circuit in the first aspect, comprising the following steps:

[0036] The first reference voltage is input to the configurable voltage source, the judgment delay signal of the switch control circuit is input to the configurable voltage source through the judgment delay output port, and the VREXT terminal of the LED driver chip generates an external voltage which is input to the configurable voltage source;

[0037] The configurable voltage source generates a sampling voltage, which is transmitted to the switch control circuit through the sampling voltage output terminal;

[0038] The configurable voltage source generates a bias voltage, which is transmitted to the current amplification circuit through the bias voltage output terminal;

[0039] The current amplifier circuit converts the bias voltage into current and amplifies it to generate a driving current for the LED lamp bead;

[0040] The digital output reset signal of the digital control storage circuit is input to the switch control circuit through the digital output reset signal output port;

[0041] The switch control circuit outputs a judgment signal according to the received sampling voltage, and transmits the judgment signal to the current amplifying circuit through the judgment output port; the judgment signal is used to control whether the current amplifying circuit outputs the driving current;

[0042] The switch control circuit transmits the judgment signal to the digital control storage circuit, and the digital control storage circuit turns off the short-circuit detection branch current according to the judgment signal and the power-on reset signal.

[0043] It can be seen from the above technical scheme that the LED short-circuit detection circuit, driver chip and driving method provided by the present invention solve the defect in the prior art that LED lamp beads are easily burned out due to short circuit at the VREXT end of the LED driver chip, and realize VREXT short-circuit detection of low-power LED driver chips and self-recovery control functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0045] Figure 1 This is a schematic diagram of an LED short circuit detection circuit provided in Embodiment 1 of the present invention.

[0046] Figure 2 This is a circuit diagram of an LED short-circuit detection circuit provided in Embodiment 2 of the present invention.

[0047] Figure 3 This is a circuit diagram of an operational amplifier OP1 provided in Embodiment 2 of the present invention.

[0048] Figure 4 This is a circuit diagram of an operational amplifier OP3 provided in Embodiment 2 of the present invention.

[0049] Figure 5 This is a flow chart of an LED driving method provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0050] The embodiments of the technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and the protection scope of the present invention cannot be limited thereto. It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should be the common meanings understood by those skilled in the art to which the present invention belongs.

[0051] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0052] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0053] As used in this specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0054] Embodiment 1:

[0055] An LED short circuit detection circuit includes a configurable voltage source, a switch control circuit, a digital control storage circuit and a current amplification circuit;

[0056] The configurable voltage source is used to generate a sampling voltage and a bias voltage, and transmit them to the switch control circuit and the current amplification circuit respectively;

[0057] The current amplifier circuit is used to convert the bias voltage into current and amplify it to generate a driving current for the LED lamp bead; the current amplifier circuit is also used to determine whether to output the driving current after receiving a judgment signal;

[0058] The switch control circuit is used to output a judgment signal after receiving the sampled voltage, and transmit it to the current amplification circuit; the switch control circuit is also used to transmit the judgment signal to the digital control storage circuit;

[0059] The digital control storage circuit is used to close the short-circuit detection branch current according to the judgment signal and the power-on reset signal.

[0060] See also Figure 1 , the input end of the configurable voltage source is connected to the first reference voltage, the VREXT end of the LED driver chip and the judgment delay output port of the switch control circuit, the bias voltage output end of the configurable voltage source is connected to the first input end of the current amplifier circuit, and the sampling voltage output end of the configurable voltage source is connected to the first input end of the switch control circuit;

[0061] The second input terminal of the switch control circuit is connected to the digital output reset signal output port of the digital control storage circuit, and the judgment output port of the switch control circuit is connected to the second input terminal of the current amplifier circuit;

[0062] The judgment output port of the switch control circuit is connected to the first input terminal of the digital control storage circuit, the second input terminal of the digital control storage circuit is connected to the power-on reset signal, the third input terminal of the digital control storage circuit is connected to the external control signal, and the PWM output port of the digital control storage circuit is connected to the third input terminal of the current amplifier circuit;

[0063] The fourth input terminal of the current amplifier circuit is connected to the second reference voltage, and the output terminal of the current amplifier circuit is connected to the output terminal of the LED driver chip.

[0064] Specifically, the power-on reset signal por is generated by the por module in the LED driver chip, and the por module is a mature module in the LED driver chip. The first reference voltage Vref1 is the reference voltage of the input configurable voltage source. When the circuit is used, the VREXT end of the LED driver chip needs to be connected to an external power supply, and also needs to be connected to an external resistor REXT to the ground, and the voltage input value of the VREXT end is adjusted by the resistor REXT. The output end OUT of the LED driver chip is connected to the cathode of the LED lamp bead to drive the LED lamp bead.

[0065] Preferably, the judgment delay output port of the switch control circuit is obtained by delaying and reversing its judgment output port.

[0066] In the LED short circuit detection circuit, the first reference voltage Vref1 and the delayed and reversed judgment delay signal Short_dly_b are input to the configurable voltage source, and a resistor REXT is externally connected to the ground through the VREXT terminal to generate the VREXT voltage. The configurable voltage source outputs a sampling voltage VS to the switch control circuit, and the switch control circuit outputs a judgment signal Short of whether to turn off the LED constant current drive tube NMOS tube NM_1 and NMOS tube NM_2, the operational amplifier and the digital control storage circuit. The Short signal is input to the configurable voltage source after being delayed and reversed (i.e., Short_dly_b). When the switch control circuit detects that the VREXT pin is short-circuited, it turns off the short-circuit detection branch (i.e., disconnects the switch SW2) to reduce the power consumption of the LED driver chip.

[0067] The switch control circuit outputs the judgment signal Short to the digital control storage circuit. When the digital control storage circuit detects that the VREXT pin is short-circuited, the pulse width modulation signal output by the PWM output port is pulled low, and the short-circuit detection branch current is turned off at the same time, thereby achieving the purpose of power saving to the greatest extent. The Por_dig signal is a power-on reset signal Por or a soft reset signal after a fixed time timing, which is used to restart the VREXT pin short-circuit detection branch current after the VREXT pin returns to normal and connects to an external resistor.

[0068] The configurable voltage source outputs a bias voltage VG1 to the current amplifier circuit. VG1 is converted into a current I2 through PM_2, and amplified by current mirrors NM_1 and NM_2 to generate a constant current driving current for the LED lamp beads.

[0069] The LED short-circuit detection circuit solves the defect in the prior art that LED lamp beads are easily burned out due to a short circuit at the VREXT end of the LED driver chip, and realizes VREXT short-circuit detection of the low-power LED driver chip and a self-recovery control function.

[0070] Embodiment 2:

[0071] Embodiment 2 Based on Embodiment 1, a specific circuit of an LED short circuit detection circuit is provided.

[0072] See also Figure 2 , the configurable voltage source includes an operational amplifier OP1, a PMOS tube PM_1, an NMOS tube NM_4 and a switch SW2;

[0073] The first reference voltage is connected to the non-inverting input terminal of the operational amplifier OP1, the VREXT terminal of the LED driver chip is connected to the reverse input terminal of the operational amplifier OP1 through a series resistor RINT1, the middle node between the resistor RINT1 and the VREXT terminal of the LED driver chip is connected to the drain of the NMOS tube NM_4, and the source and gate of the NMOS tube NM_4 are grounded;

[0074] The output end of the operational amplifier OP1 is connected to the gate of the PMOS tube PM_1, the source of the PMOS tube PM_1 is connected to a high level, the drain of the PMOS tube PM_1 is connected to a contact end of the switch SW2, the other contact end of the switch SW2 is connected in series with the resistor RINT2 to the middle node between the resistor RINT1 and the VREXT end of the LED driver chip, and the control end of the switch SW2 is connected to the judgment delay output port of the switch control circuit;

[0075] The detection end of the operational amplifier OP1 serves as a sampling voltage output end of the configurable voltage source, and the output end of the operational amplifier OP1 serves as a bias voltage output end of the configurable voltage source.

[0076] Specifically, the external control signal SDI is the input control signal of the LED lamp bead, which is processed by the digital control storage circuit to generate a pulse width modulation (PWM) output. The Por signal is a power-on reset signal, Short is a judgment signal generated by the switch control circuit, and the Por_dig output low level is used to close SW2 and restore the VREXT pin short circuit detection branch current.

[0077] Operational amplifier OP1, PMOS tube PM_1, NMOS tube NM_4, resistor RINT1, resistor RINT2 and switch SW2 together form a configurable voltage source. Pin VREXT connects the chip external resistor REXT to ground to generate VREXT voltage, bias voltage VG1 and sampling voltage VS. NMOS tube NM_4 is connected in the form of a diode, and is used together with resistors RINT1 and RINT2 for electrostatic protection. In order to achieve a larger driving current, the resistance of resistor RINT2 is generally small. When the VREXT pin is short-circuited, the output VG1 of the operational amplifier OP1 is driven to a low potential. Since the resistor RINT2 is a smaller resistor, the current flowing through the PMOS tube PM_1 is large, resulting in a large current consumption inside the LED driver chip although the current driving the LED lamp bead can be turned off after the short circuit. Therefore, under normal circumstances, switch SW2 is closed; when the VREXT pin is short-circuited, the switch SW2 is disconnected, which can greatly reduce the power consumption of the LED driver chip and achieve the purpose of maximum power saving.

[0078] See also Figure 3, the operational amplifier OP1 includes a PMOS tube PM_11, a PMOS tube PM_12, ​​a PMOS tube PM_13, a PMOS tube PM_14, a PMOS tube PM_15, an NMOS tube NM_11, an NMOS tube NM_12, ​​an NMOS tube NM_13 and an NMOS tube NM_14;

[0079] The gate of the PMOS tube PM_15 is connected to the reference power supply, the drain of the PMOS tube PM_15 is connected to the source of the PMOS tube PM_11 and the PMOS tube PM_12, ​​the source of the PMOS tube PM_15 is connected to the source of the PMOS tube PM_13 and the PMOS tube PM_14, the drain of the PMOS tube PM_13 is connected to the drain of the NMOS tube NM_13, the drain of the PMOS tube PM_14 is connected to the drain of the NMOS tube NM_14, and the drain of the NMOS tube NM_15 is connected to the drain of the NMOS tube NM_16. The gate of the OS transistor NM_13 is connected to the gate of the NMOS transistor NM_14, the source of the NMOS transistor NM_13 is connected to the drain of the NMOS transistor NM_11, the source of the NMOS transistor NM_14 is connected to the drain of the NMOS transistor NM_12, ​​and the sources of the NMOS transistors NM_11 and NMOS transistors NM_12 are grounded; the drain of the PMOS transistor PM_11 is connected to the drain of the NMOS transistor NM_11, and the drain of the PMOS transistor PM_12 is connected to the drain of the NMOS transistor NM_12;

[0080] The node between the drain of the PMOS tube PM_14 and the drain of the NMOS tube NM_14 serves as the output end of the operational amplifier; the gate of the PMOS tube PM_11 serves as the non-inverting input end of the operational amplifier; the gate of the PMOS tube PM_12 serves as the reverse input end of the operational amplifier; the gate of the PMOS tube PM_13, the gate of the PMOS tube PM_14, and the middle node of the drain of the PMOS tube PM_13 and the drain of the NMOS tube NM_13 are connected to each other as the detection end of the operational amplifier.

[0081] Specifically, in the LED short circuit detection circuit, the operational amplifier OP1, the operational amplifier OP2 and the operational amplifier OP3 are all Figure 3 The structure of the present invention is as follows, wherein the operational amplifier OP1 leads to a detection terminal, while the operational amplifier OP2 and the operational amplifier OP3 do not lead to a detection terminal.

[0082] Figure 3In, VBP1, VBN1, and VBN2 are input bias voltages, In+ and In- are the non-inverting input and reverse input of the operational amplifier, respectively, out is the output of the operational amplifier, and VS is the detection terminal of the operational amplifier. I1 and I2 are the currents flowing through the PMOS tube PM_13 and the PMOS tube PM_14, respectively. Under normal circumstances, according to the negative feedback principle of the operational amplifier, I1 = I2, and it is the preset bias current value. When the VREXT terminal is short-circuited, the non-inverting input terminal of the operational amplifier OP1 is at a low potential, and the output terminal potential of the operational amplifier OP1 is reduced to a low potential, so I1 = I2 = 0, and the voltage at the VS terminal is raised to a high level. In this way, a stable and reliable sampling signal can be generated based on the internal negative feedback mechanism of the operational amplifier.

[0083] In this LED short-circuit detection circuit, the key signal inside the operational amplifier OP1 is brought out as the detection terminal, as the sampling signal of the short circuit of the VREXT pin. This LED short-circuit detection circuit is based on the negative feedback mechanism of the operational amplifier. If the VREXT terminal is connected to the ground with a suitable resistor, the sampling voltage remains unchanged. When the VREXT terminal is short-circuited, the sampling voltage will be raised, and the output of the current comparator composed of the PMOS tube PM_3 and the current source Ib will flip, and then the constant current drive tubes NM_1 and NM_2 will be directly turned off; when the VREXT terminal is restored to connect a suitable resistor to the ground, the constant current drive tubes NM_1 and NM_2 will be quickly restored.

[0084] Preferably, the switch control circuit includes a PMOS tube PM_3, a current source Ib, a trigger SMIT1, a delay circuit DLY1 and a NAND gate NAND2; the key signal VS inside the operational amplifier OP1 is controlled in real time by the system loop, and has high sensitivity as a detection signal, and can self-recover the VREXT short-circuit detection branch current. The output of the switch control circuit directly controls the constant current drive tubes NM_1 and NM_2, further improving the sensitivity of VREXT short-circuit detection.

[0085] The sampling voltage output end of the configurable voltage source is connected to the gate of the PMOS tube PM_3, the source of the PMOS tube PM_3 is connected to a high level, the drain of the PMOS tube PM_3 is connected to the ground through the series connection of the current source Ib, the drain of the PMOS tube PM_3 is connected to the input end of the trigger SMIT1, and the output end of the trigger SMIT1 is used as the judgment output port; the output end of the trigger SMIT1 is connected to the input end of the delay circuit DLY1, the output end of the delay circuit DLY1 is connected to an input end of the NAND gate NAND2, the other input end of the NAND gate NAND2 is connected to the digital output reset signal, and the output end of the NAND gate NAND2 is used as the judgment delay output port. The trigger SMIT1 is a Schmitt trigger.

[0086] Specifically, the PMOS transistor PM_3, the current source Ib, the Schmitt trigger SMIT1, the switch SW1, the delay circuit DLY1 and the NAND gate NAND2 form a switch control circuit. The PMOS transistor PM_3 and the current source Ib form a current comparator. Under normal circumstances, the sampling voltage VS is at a lower level, the output Short_b is at a high level, after the Schmitt trigger is reversed, Short is at a low level, the switch SW1 is disconnected, the NMOS tube NM_1 and the NMOS tube NM_2 form a current mirror amplifier, and the output current drives the LED lamp bead. When the VREXT pin is short-circuited, the sampling voltage VS voltage will be raised, the output Short_b jumps to a low level, after the Schmitt trigger SMIT1 is reversed, Short is at a high level, the switch SW1 is closed, that is, the output VG2 of the operational amplifier OP2 is connected to the ground through the switch SW1, and the gates of the NMOS tubes NM_1 and NMOS tubes NM_2 are pulled to a low potential, and the current driving the LED lamp bead is turned off, thereby avoiding the burning of the LED lamp bead due to the short circuit of the VREXT pin. Short passes through the delay circuit and outputs Short_dly, which is input to the NAND gate together with the Por_dig signal, and outputs the signal Short_dly_b for controlling the switch SW2, which is used as the control signal of the switch SW2. When the VREXT pin is short-circuited, the switch SW2 is disconnected after a delay, which can achieve the purpose of power saving. The Por_dig signal is the power-on reset signal Por or the soft reset signal after a fixed time timing, which is used to restart the VREXT pin short-circuit detection branch current when the VREXT pin returns to normal and is connected to the ground with a suitable external resistor.

[0087] Preferably, the current amplifying circuit includes an operational amplifier OP2, an operational amplifier OP3, a PMOS transistor PM_2, a switch SW1, an NMOS transistor NM_1, an NMOS transistor NM_2 and an NMOS transistor NM_3;

[0088] The bias voltage output terminal of the configurable voltage source is connected to the gate of the PMOS tube PM_2, the source of the PMOS tube PM_2 is connected to a high level, the drain of the PMOS tube PM_2 is connected to the drain of the NMOS tube NM_1, the drain of the PMOS tube PM_2 is also connected to the inverting input terminal of the operational amplifier OP2, the non-inverting input terminal of the operational amplifier OP2 is connected to the second reference voltage, the output terminal of the operational amplifier OP2 is connected to the gate of the NMOS tube NM_1, and the source of the NMOS tube NM_1 is grounded;

[0089] The drain of the PMOS transistor PM_2 is connected to the non-inverting input terminal of the operational amplifier OP3, the output terminal of the operational amplifier OP3 is connected to the gate of the NMOS transistor NM_3, the source of the NMOS transistor NM_3 is connected to the drain of the NMOS transistor NM_2, the source of the NMOS transistor NM_3 is connected to the reverse input terminal of the operational amplifier OP3, the source of the NMOS transistor NM_2 is grounded, and the output terminal of the operational amplifier OP2 is connected to the gate of the NMOS transistor NM_2;

[0090] The judgment output port of the switch control circuit is connected to the control end of the switch SW1, one contact end of the switch SW1 is grounded, and the other contact end of the switch SW1 is connected to the output end of the operational amplifier OP2;

[0091] The drain of the NMOS tube NM_3 is connected to the output end of the LED driving chip; the enable end of the operational amplifier OP3 serves as the third input end of the current amplifying circuit.

[0092] Specifically, the second reference voltage Vref2 is a reference voltage of the output current amplifier circuit. The operational amplifier OP2, the operational amplifier OP3, the PMOS tube PM_2, the NMOS tube NM_1, the NMOS tube NM_2 and the NMOS tube NM_3 form a current amplifier circuit, and the OUT output end of the current amplifier circuit drives the LED lamp bead. Among them, the PMOS tube PM_2 converts the input bias voltage VG1 into a constant current source input, and the NMOS tube NM_1 and the NMOS tube NM_2 constitute a current amplification function. The function of the operational amplifier OP2 is to provide a stable source-drain voltage VDS1 for the NMOS tube NM_1, and the function of the operational amplifier OP3 is to provide a stable source-drain voltage VDS2 for the NMOS tube NM_2. The drain and source voltages of the NMOS tubes NM_1 and NMOS tubes NM_2 are equal and the performance is stable and reliable, which can effectively improve the output constant current effect.

[0093] The enable terminal en of OP3 is controlled by the digital output reset signal output port controlled by the digital control storage circuit. When the VREXT pin is short-circuited, the PWM output is turned off, which can further reduce the power consumption of the LED driver chip.

[0094] See also Figure 4 , the operational amplifier OP3 includes an invertor INV1, a PMOS tube PM_21, a PMOS tube PM_22, a PMOS tube PM_23, a PMOS tube PM_24, a PMOS tube PM_25, a PMOS tube PM_26, an NMOS tube NM_21, an NMOS tube NM_22, an NMOS tube NM_23, an NMOS tube NM_24, a current source I3 and a current source I2;

[0095] The gate of the PMOS tube PM_21 is used as the inverting input terminal of the operational amplifier; the gate of the PMOS tube PM_22 is used as the non-inverting input terminal of the operational amplifier; the source of the PMOS tube PM_21 and the source of the PMOS tube PM_22 are both connected to the drain of the PMOS tube PM_24, the source of the PMOS tube PM_24 is connected to a high level, the gate of the PMOS tube PM_24 is connected to the gate of the PMOS tube PM_23, the source of the PMOS tube PM_23 is connected to a high level, the drain of the PMOS tube PM_23 is grounded by being connected in series with the current source I3, and the gate of the PMOS tube PM_23 is connected to its drain;

[0096] The drain of the PMOS tube PM_21 is connected to the drain of the NMOS tube NM_21, the source of the NMOS tube NM_21 is grounded, and the drain of the NMOS tube NM_21 is connected to its gate; the drain of the PMOS tube PM_22 is connected to the drain of the NMOS tube NM_22, the source of the NMOS tube NM_22 is grounded, and the gate of the NMOS tube NM_21 is connected to the gate of the NMOS tube NM_22;

[0097] The node between the drain of the PMOS tube PM_22 and the drain of the NMOS tube NM_22 is connected to the gate of the NMOS tube NM_23, the source of the NMOS tube NM_23 is grounded, the drain of the NMOS tube NM_23 is connected to the drain of the PMOS tube PM_26, the source of the PMOS tube PM_26 is connected to the drain of the PMOS tube PM_25, the source of the PMOS tube PM_25 is connected to a high level, and the gate of the PMOS tube PM_26 is connected to the PMOS tube PM_23. The gate of the operational amplifier OP3 is connected to the input end of the invertor INV1, the output end of the invertor INV1 is connected to the gate of the PMOS tube PM_25, the output end of the invertor INV1 is connected to the gate of the NMOS tube NM_24, the source of the NMOS tube NM_24 is grounded by being connected in series with the current source I2, the drain of the NMOS tube NM_24 is connected to the drain of the NMOS tube NM_23, and the drain of the NMOS tube NM_24 is connected in series with the resistor R1 as the output end of the operational amplifier.

[0098] Specifically, EN is the enable terminal, which generates ENB_INT through the inverter INV1 to control the PMOS transistor PM_25 and the NMOS transistor NM_25. When EN is at a high level, OP3 is turned on, otherwise, when EN is at a low level, OP3 is turned off. In+ and In- are the same direction and reverse input terminals of OP3, respectively, and OUT is the output terminal of OP3. The size of the current source I3 can be adjusted through the register, thereby adjusting the turn-on speed of OP3. The size of the current source I2 can be adjusted through the register, thereby adjusting the turn-off speed of OP3. R1 is a current limiting resistor, which is used to prevent overshoot during the process of turning on the lamp bead.

[0099] The circuit provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference may be made to the corresponding contents in the aforementioned embodiment.

[0100] Embodiment three:

[0101] An LED driver chip comprises the above-mentioned LED short-circuit detection circuit.

[0102] Specifically, the LED driver chip may be provided with a plurality of OUT output terminals for driving a plurality of LED lamp beads. Preferably, the number of the OUT output terminals may range from 1 to 32.

[0103] Specifically, when the LED driver chip is used, the VREXT terminal needs to be connected to an external power supply, and an external resistor REXT needs to be connected to the ground, and the voltage input value of the VREXT terminal needs to be adjusted by the resistor REXT. The output terminal OUT is connected to the cathode of the LED lamp bead to drive the LED lamp bead. The LED driver chip solves the defect in the prior art that the LED lamp bead is easily burned due to the short circuit of the VREXT terminal of the LED driver chip.

[0104] The chip provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference may be made to the corresponding contents in the aforementioned embodiment.

[0105] Embodiment 4:

[0106] An LED driving method is implemented on the above LED short circuit detection circuit, see Figure 5 , including the following steps:

[0107] S1: The first reference voltage is input to the configurable voltage source, the judgment delay signal of the switch control circuit is input to the configurable voltage source through the judgment delay output port, and the VREXT terminal of the LED driver chip generates an external voltage which is input to the configurable voltage source;

[0108] S2: The configurable voltage source generates a sampling voltage, which is transmitted to the switch control circuit through the sampling voltage output terminal;

[0109] S3: A configurable voltage source generates a bias voltage, which is transmitted to the current amplifier circuit through a bias voltage output terminal;

[0110] S4: The current amplifying circuit converts the bias voltage into a current and amplifies it to generate a driving current for the LED lamp bead;

[0111] S5: The digital output reset signal of the digital control storage circuit is input to the switch control circuit through the digital output reset signal output port;

[0112] S6: the switch control circuit outputs a judgment signal according to the received sampling voltage, and transmits the judgment signal to the current amplifying circuit through the judgment output port; the judgment signal is used to control whether the current amplifying circuit outputs the driving current;

[0113] S7: The switch control circuit transmits the judgment signal to the digital control storage circuit, and the digital control storage circuit turns off the short-circuit detection branch current according to the judgment signal and the power-on reset signal.

[0114] Specifically, in the LED driving method, the first reference voltage Vref1 and the delayed and inverted judgment delay signal Short_dly_b are input to a configurable voltage source, and a resistor REXT is externally connected to the ground through the VREXT terminal to generate a VREXT voltage. The configurable voltage source outputs a sampling voltage VS to the switch control circuit, and the switch control circuit outputs a judgment signal Short of whether to turn off the LED constant current drive tube NMOS tube NM_1 and NMOS tube NM_2, the operational amplifier and the digital control storage circuit. The Short signal is input to the configurable voltage source after being delayed and inverted. When the switch control circuit detects that the VREXT pin is short-circuited, it turns off the short-circuit detection branch (switch SW2) to reduce the power consumption of the LED driver chip.

[0115] The switch control circuit outputs a judgment signal Short to the digital control storage circuit. When the digital control storage circuit detects that the VREXT pin is short-circuited, the pulse width modulation signal output by the PWM output port is pulled low, and the short-circuit detection branch current is turned off at the same time, thereby achieving the purpose of power saving to the greatest extent.

[0116] The configurable voltage source outputs a bias voltage VG1 to the current amplifier circuit, and the current amplifier circuit is used to generate a driving current for the LED lamp bead, and the driving current is a constant current driving signal.

[0117] The LED short-circuit detection method solves the defect in the prior art that LED lamp beads are easily burned out due to a short circuit at the VREXT end of the LED driver chip, and realizes VREXT short-circuit detection of the low-power LED driver chip and a self-recovery control function.

[0118] The method provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference can be made to the corresponding contents in the aforementioned embodiment.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

Claims

1. An LED short circuit detection circuit, characterized in that: It includes a configurable voltage source, a switch control circuit, a digital control storage circuit and a current amplification circuit; The configurable voltage source is used to generate a sampling voltage and a bias voltage, and transmit them to the switch control circuit and the current amplification circuit respectively; The current amplifier circuit is used to convert the bias voltage into current and amplify it to generate a driving current for the LED lamp bead; The current amplifying circuit is also used to determine whether to output the driving current after receiving the determination signal; The switch control circuit is used to output a judgment signal after receiving the sampled voltage, and transmit it to the current amplification circuit; the switch control circuit is also used to transmit the judgment signal to the digital control storage circuit; The digital control storage circuit is used to close the short-circuit detection branch current according to the judgment signal and the power-on reset signal; The input end of the configurable voltage source is connected to the first reference voltage, the VREXT end of the LED driver chip and the judgment delay output port of the switch control circuit, the bias voltage output end of the configurable voltage source is connected to the first input end of the current amplifier circuit, and the sampling voltage output end of the configurable voltage source is connected to the first input end of the switch control circuit; The second input terminal of the switch control circuit is connected to the digital output reset signal output port of the digital control storage circuit, and the judgment output port of the switch control circuit is connected to the second input terminal of the current amplifier circuit; The judgment output port of the switch control circuit is connected to the first input terminal of the digital control storage circuit, the second input terminal of the digital control storage circuit is connected to the power-on reset signal, the third input terminal of the digital control storage circuit is connected to the external control signal, and the PWM output port of the digital control storage circuit is connected to the third input terminal of the current amplifier circuit; The fourth input terminal of the current amplifier circuit is connected to the second reference voltage, and the output terminal of the current amplifier circuit is connected to the output terminal of the LED driver chip; The configurable voltage source includes an operational amplifier OP1, a PMOS transistor PM_1, an NMOS transistor NM_4 and a switch SW2; The first reference voltage is connected to the non-inverting input terminal of the operational amplifier OP1, the VREXT terminal of the LED driver chip is connected to the reverse input terminal of the operational amplifier OP1 through a series resistor RINT1, the middle node between the resistor RINT1 and the VREXT terminal of the LED driver chip is connected to the drain of the NMOS tube NM_4, and the source and gate of the NMOS tube NM_4 are grounded; The output end of the operational amplifier OP1 is connected to the gate of the PMOS tube PM_1, the source of the PMOS tube PM_1 is connected to a high level, the drain of the PMOS tube PM_1 is connected to a contact end of the switch SW2, the other contact end of the switch SW2 is connected in series with the resistor RINT2 to the middle node between the resistor RINT1 and the VREXT end of the LED driver chip, and the control end of the switch SW2 is connected to the judgment delay output port of the switch control circuit; The detection end of the operational amplifier OP1 serves as the sampling voltage output end of the configurable voltage source, and the output end of the operational amplifier OP1 serves as the bias voltage output end of the configurable voltage source; The switch control circuit includes a PMOS tube PM_3, a current source Ib, a trigger SMIT1, a delay circuit DLY1 and a NAND gate NAND2; The sampling voltage output end of the configurable voltage source is connected to the gate of the PMOS tube PM_3, the source of the PMOS tube PM_3 is connected to a high level, the drain of the PMOS tube PM_3 is connected to ground by being connected in series with the current source Ib, the drain of the PMOS tube PM_3 is connected to the input end of the trigger SMIT1, and the output end of the trigger SMIT1 serves as the judgment output port; the output end of the trigger SMIT1 is connected to the input end of the delay circuit DLY1, the output end of the delay circuit DLY1 is connected to an input end of the NAND gate NAND2, the other input end of the NAND gate NAND2 is connected to the digital output reset signal, and the output end of the NAND gate NAND2 serves as the judgment delay output port; The current amplifying circuit includes an operational amplifier OP2, an operational amplifier OP3, a PMOS tube PM_2, a switch SW1, an NMOS tube NM_1, an NMOS tube NM_2 and an NMOS tube NM_3; The bias voltage output terminal of the configurable voltage source is connected to the gate of the PMOS tube PM_2, the source of the PMOS tube PM_2 is connected to a high level, the drain of the PMOS tube PM_2 is connected to the drain of the NMOS tube NM_1, the drain of the PMOS tube PM_2 is also connected to the inverting input terminal of the operational amplifier OP2, the non-inverting input terminal of the operational amplifier OP2 is connected to the second reference voltage, the output terminal of the operational amplifier OP2 is connected to the gate of the NMOS tube NM_1, and the source of the NMOS tube NM_1 is grounded; The drain of the PMOS transistor PM_2 is connected to the non-inverting input terminal of the operational amplifier OP3, the output terminal of the operational amplifier OP3 is connected to the gate of the NMOS transistor NM_3, the source of the NMOS transistor NM_3 is connected to the drain of the NMOS transistor NM_2, the source of the NMOS transistor NM_3 is connected to the reverse input terminal of the operational amplifier OP3, the source of the NMOS transistor NM_2 is grounded, and the output terminal of the operational amplifier OP2 is connected to the gate of the NMOS transistor NM_2; The judgment output port of the switch control circuit is connected to the control end of the switch SW1, one contact end of the switch SW1 is grounded, and the other contact end of the switch SW1 is connected to the output end of the operational amplifier OP2; The drain of the NMOS tube NM_3 is connected to the output end of the LED driving chip; the enable end of the operational amplifier OP3 serves as the third input end of the current amplifying circuit.

2. The LED short circuit detection circuit according to claim 1, characterized in that: The judgment delay output port of the switch control circuit is obtained by delaying and reversing the judgment output port thereof.

3. The LED short circuit detection circuit according to claim 1, characterized in that: The operational amplifier OP1 includes a PMOS transistor PM_11, a PMOS transistor PM_12, ​​a PMOS transistor PM_13, a PMOS transistor PM_14, a PMOS transistor PM_15, an NMOS transistor NM_11, an NMOS transistor NM_12, ​​an NMOS transistor NM_13 and an NMOS transistor NM_14; The gate of the PMOS tube PM_15 is connected to the reference power supply, the drain of the PMOS tube PM_15 is connected to the source of the PMOS tube PM_11 and the PMOS tube PM_12, ​​the source of the PMOS tube PM_15 is connected to the source of the PMOS tube PM_13 and the PMOS tube PM_14, the drain of the PMOS tube PM_13 is connected to the drain of the NMOS tube NM_13, the drain of the PMOS tube PM_14 is connected to the drain of the NMOS tube NM_14, and the drain of the NMOS tube NM_15 is connected to the drain of the NMOS tube NM_16. The gate of the OS transistor NM_13 is connected to the gate of the NMOS transistor NM_14, the source of the NMOS transistor NM_13 is connected to the drain of the NMOS transistor NM_11, the source of the NMOS transistor NM_14 is connected to the drain of the NMOS transistor NM_12, ​​and the sources of the NMOS transistors NM_11 and NMOS transistors NM_12 are grounded; the drain of the PMOS transistor PM_11 is connected to the drain of the NMOS transistor NM_11, and the drain of the PMOS transistor PM_12 is connected to the drain of the NMOS transistor NM_12; The node between the drain of the PMOS tube PM_14 and the drain of the NMOS tube NM_14 serves as the output end of the operational amplifier; the gate of the PMOS tube PM_11 serves as the non-inverting input end of the operational amplifier; the gate of the PMOS tube PM_12 serves as the reverse input end of the operational amplifier; the gate of the PMOS tube PM_13, the gate of the PMOS tube PM_14, and the middle node of the drain of the PMOS tube PM_13 and the drain of the NMOS tube NM_13 are connected to each other as the detection end of the operational amplifier.

4. The LED short circuit detection circuit according to claim 1, characterized in that: The operational amplifier OP3 includes an invertor INV1, a PMOS tube PM_21, a PMOS tube PM_22, a PMOS tube PM_23, a PMOS tube PM_24, a PMOS tube PM_25, a PMOS tube PM_26, an NMOS tube NM_21, an NMOS tube NM_22, an NMOS tube NM_23, an NMOS tube NM_24, a current source I3 and a current source I2; The gate of the PMOS tube PM_21 is used as the inverting input terminal of the operational amplifier; the gate of the PMOS tube PM_22 is used as the non-inverting input terminal of the operational amplifier; the source of the PMOS tube PM_21 and the source of the PMOS tube PM_22 are both connected to the drain of the PMOS tube PM_24, the source of the PMOS tube PM_24 is connected to a high level, the gate of the PMOS tube PM_24 is connected to the gate of the PMOS tube PM_23, the source of the PMOS tube PM_23 is connected to a high level, the drain of the PMOS tube PM_23 is grounded by being connected in series with the current source I3, and the gate of the PMOS tube PM_23 is connected to its drain; The drain of the PMOS tube PM_21 is connected to the drain of the NMOS tube NM_21, the source of the NMOS tube NM_21 is grounded, and the drain of the NMOS tube NM_21 is connected to its gate; the drain of the PMOS tube PM_22 is connected to the drain of the NMOS tube NM_22, the source of the NMOS tube NM_22 is grounded, and the gate of the NMOS tube NM_21 is connected to the gate of the NMOS tube NM_22; The node between the drain of the PMOS tube PM_22 and the drain of the NMOS tube NM_22 is connected to the gate of the NMOS tube NM_23, the source of the NMOS tube NM_23 is grounded, the drain of the NMOS tube NM_23 is connected to the drain of the PMOS tube PM_26, the source of the PMOS tube PM_26 is connected to the drain of the PMOS tube PM_25, the source of the PMOS tube PM_25 is connected to a high level, and the gate of the PMOS tube PM_26 is connected to the PMOS tube PM_23. The gate of the operational amplifier OP3 is connected to the input end of the invertor INV1, the output end of the invertor INV1 is connected to the gate of the PMOS tube PM_25, the output end of the invertor INV1 is connected to the gate of the NMOS tube NM_24, the source of the NMOS tube NM_24 is grounded by being connected in series with the current source I2, the drain of the NMOS tube NM_24 is connected to the drain of the NMOS tube NM_23, and the drain of the NMOS tube NM_24 is connected in series with the resistor R1 as the output end of the operational amplifier.

5. An LED driver chip, characterized in that: The invention comprises the LED short circuit detection circuit as claimed in any one of claims 1 to 4.

6. A LED driving method, characterized in that: The method is performed on the LED short circuit detection circuit according to any one of claims 1 to 4, comprising the following steps: The first reference voltage is input to the configurable voltage source, the judgment delay signal of the switch control circuit is input to the configurable voltage source through the judgment delay output port, and the VREXT terminal of the LED driver chip generates an external voltage which is input to the configurable voltage source; The configurable voltage source generates a sampling voltage, which is transmitted to the switch control circuit through the sampling voltage output terminal; The configurable voltage source generates a bias voltage, which is transmitted to the current amplification circuit through the bias voltage output terminal; The current amplifier circuit converts the bias voltage into current and amplifies it to generate a driving current for the LED lamp bead; The digital output reset signal of the digital control storage circuit is input to the switch control circuit through the digital output reset signal output port; The switch control circuit outputs a judgment signal according to the received sampling voltage, and transmits the judgment signal to the current amplifying circuit through the judgment output port; the judgment signal is used to control whether the current amplifying circuit outputs the driving current; The switch control circuit transmits the judgment signal to the digital control storage circuit, and the digital control storage circuit turns off the short-circuit detection branch current according to the judgment signal and the power-on reset signal.

Images