Memory and method of forming the same
By forming a doped layer with uneven depth distribution on the substrate of the DRAM memory, the leakage current and turn-on current problems of traditional DRAM memory are solved, and the performance of the memory is improved.
Patent Information
- Application Number
- CN201811045784.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2018-09-07
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2038-09-07
AI Technical Summary
The leakage current of traditional DRAM memories is not ideal and the opening current is abnormal, which limits its performance.
The doped layer is formed on the substrate of the memory, the depth of the doped layer between two adjacent word lines of the word line is greater than the depth on the side of the word line, and becomes smaller as it is away from the word line, through ion implantation and Heat treatment forms, reducing leakage current and improving the on-off current.
Effectively reduces leakage current and improves memory performance.
Smart Images
Figure CN110890367B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory and a method for forming the same. Background Art
[0002] Integrated circuits have evolved from integrating dozens of devices on a single chip to integrating millions of devices. The performance and complexity of traditional integrated circuits have far exceeded initial expectations. In order to achieve improvements in complexity and circuit density (the number of devices that can be accommodated on a certain chip area), the feature size of the device, also known as the "geometry", has become smaller with each generation of integrated circuits. Increasing the density of integrated circuits not only improves the complexity and performance of integrated circuits, but also reduces costs for consumers. Making devices smaller is challenging because each process in integrated circuit manufacturing has a limit, that is, if a certain process is to be performed under the condition of being smaller than the feature size, the process or device layout needs to be changed; in addition, due to the increasingly faster device design requirements, traditional processes and materials have process limitations.
[0003] DRAM (Dynamic Random Access Memory) is the most common system memory; the DRAM memory is a semiconductor device, and its performance has been greatly improved, but there is still a need for further development. In the prior art, buried gate DRAM is a common structure, such as a single cell junction depth structure DRAM, but the leakage current of this DRAM is not ideal, and the turn-on current is also prone to abnormality, which limits its performance. Summary of the invention
[0004] The object of the present invention is to provide a memory and a method for forming the same, so as to improve the performance of the memory.
[0005] In order to solve the above technical problems, the present invention provides a memory, comprising:
[0006] A substrate having a first surface and a second surface disposed opposite to each other;
[0007] At least one group of word lines (50) is formed inside the substrate, each group of word lines includes two adjacent word lines; and
[0008] A doping layer extends from the first surface of the substrate to the interior of the substrate and is arranged on both sides of each of the word lines. The depth of the doping layer between two adjacent word lines in each group of word lines is greater than the depth of the doping layer on the opposite sides of the two adjacent word lines, and the depth of the doping layer on the opposite sides of the two adjacent word lines decreases as it moves away from the two adjacent word lines.
[0009] Optionally, for the memory, the doping layer includes a first part, a second part and a third part, the depth of the first part is greater than the depth of the second part, the depth of the second part is greater than the depth of the third part, the first part is located between the two adjacent word lines, the second part is located on the side away from the two adjacent word lines, and the third part is located on the side of the second part away from the word lines.
[0010] Optionally, for the memory, the depth of the first part is between 50nm and 70nm, the depth of the second part is between 40nm and 60nm, the depth of the third part is between 30nm and 50nm, and the width of the second part is between 4nm and 8nm.
[0011] Optionally, for the memory, the doping type of the doping layer is N-type.
[0012] Optionally, for the memory, the doping concentration of the doping layer is between 1E12 / cm 2 ~1E16 / cm 2 .
[0013] Optionally, for the memory, the doped layer includes a source region and a drain region, the source region and the drain region are arranged on both sides of the word line, and the source region or the drain region between two adjacent word lines is shared.
[0014] Optionally, for the memory, the substrate is further formed with an isolation structure layer, and the isolation structure layer surrounds the source region and the drain region.
[0015] Optionally, for the memory, the word line includes a first dielectric layer, a semiconductor layer and a second dielectric layer, the first dielectric layer is formed on the groove wall surface of the groove in the substrate, the semiconductor layer is formed on the first dielectric layer in the groove, the top surface of the semiconductor layer is lower than the first surface, the second dielectric layer is located on the top surface of the semiconductor layer, and the second dielectric layer covers the semiconductor layer and is connected to the first dielectric layer.
[0016] The present invention also provides a method for forming a memory, comprising:
[0017] Providing a substrate, the substrate having a first surface and a second surface disposed opposite to each other;
[0018] forming at least one group of first grooves in the substrate, wherein openings of the first grooves are formed on the first surface, and each group of first grooves includes two adjacent first grooves;
[0019] forming at least one set of word lines in the at least one set of first trenches;
[0020] Performing a first ion implantation on the substrate at both sides of the word line and close to the first surface;
[0021] forming a barrier layer on the substrate and forming an opening, wherein the opening at least exposes a portion of a region between two adjacent word lines of each group of word lines; and
[0022] A second ion implantation is performed obliquely from the opening to the substrate, and a doping layer is formed after performing at least the first ion implantation and the second ion implantation. The doping layer is arranged on both sides of each of the word lines. The depth of the doping layer between two adjacent word lines in each group of word lines is greater than the depth of the doping layer on the side away from the two adjacent word lines, and the depth of the doping layer on the side away from the two adjacent word lines decreases as the distance from the two adjacent word lines increases.
[0023] Optionally, for the method for forming the memory, the first ion implantation is N-type implantation, and the implantation dose is between 1E14 / cm 2 ~1E16 / cm 2 , the injection energy is between 10KeV and 50KeV.
[0024] Optionally, for the method for forming the memory, the second ion implantation is an N-type implantation, and the implantation dose is between 1E12 / cm 2 ~1E13 / cm 2 The implantation energy is between 30KeV and 60KeV, and the implantation angle is between 3° and 20°.
[0025] Optionally, the method for forming the memory further includes, after performing a second ion implantation from the opening: performing a heat treatment to form the doping layer.
[0026] Optionally, for the method of forming the memory, the heat treatment includes spike annealing at a temperature between 900° C. and 1000° C. in a nitrogen environment.
[0027] Optionally, for the method of forming the memory, the doping layer includes a first part, a second part and a third part, the depth of the first part is greater than the depth of the second part, the depth of the second part is greater than the depth of the third part, the first part is located between the two adjacent word lines, the second part is located on the opposite side of the two adjacent word lines, and the third part is located on the side of the second part away from the word lines.
[0028] Optionally, for the method of forming the memory, the depth of the first part is between 50nm and 70nm, the depth of the second part is between 40nm and 60nm, the depth of the third part is between 30nm and 50nm, and the width of the second part is between 4nm and 8nm.
[0029] In the memory and the method for forming the same provided by the present invention, at least one group of word lines is formed in a substrate, and doping layers are arranged on both sides of each word line. The depth of the doping layer between two adjacent word lines in each group of word lines is greater than the depth on the opposite sides of the two adjacent word lines, and the depth of the doping layer on the opposite sides of the two adjacent word lines decreases as it moves away from the two adjacent word lines. Thus, the leakage current is reduced, and the turn-on current is improved, thereby improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic diagram of the structure of a memory;
[0031] Figure 2 A schematic flow chart of a method for forming a memory according to an embodiment of the present invention;
[0032] Figure 3 A schematic diagram of providing a substrate in a method for forming a memory according to an embodiment of the present invention;
[0033] Figure 4 A schematic diagram of forming a word line in a substrate in a method for forming a memory according to an embodiment of the present invention;
[0034] Figure 5 For along Figure 4 Sectional view at A-A';
[0035] Figure 6 A schematic diagram of performing the first ion implantation in a method for forming a memory according to an embodiment of the present invention;
[0036] Figure 7 A schematic diagram of forming a barrier layer and opening an opening in a method for forming a memory according to an embodiment of the present invention;
[0037] Figure 8-Figure 9 A schematic diagram of performing a second ion implantation in a method for forming a memory according to an embodiment of the present invention;
[0038] Fig.10 A schematic diagram of a memory formed according to an embodiment of the present invention;
[0039] The reference numerals are as follows:
[0040] S-source region;
[0041] D-drain region;
[0042] 1,10-substrate;
[0043] 2,20-semiconductor layer;
[0044] 3,30-medium layer;
[0045] 4,40-isolation structure layer;
[0046] 50-word line;
[0047] 60- barrier layer;
[0048] 61-opening;
[0049] 70-second ion implantation;
[0050] 81- first ion implantation layer;
[0051] 82- second ion implantation layer;
[0052] 91-Part I;
[0053] 92-Part II;
[0054] 93-Part III;
[0055] 101- a first surface;
[0056] 102-Second surface. DETAILED DESCRIPTION
[0057] The memory and the method for forming the memory of the present invention will be described in more detail below in conjunction with the schematic diagram, wherein the preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein and still achieve the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.
[0058] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.
[0059] In the following description, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region, pad and / or pattern, it may be directly on another layer or substrate, and / or there may be an intervening layer. In addition, it should be understood that when a layer is referred to as being "under" another layer, it may be directly under another layer, and / or there may be one or more intervening layers. In addition, references to being "on" and "under" each layer may be made based on the accompanying drawings.
[0060] Figure 1 Schematic diagram of a memory structure, specifically, a DRAM with a single cell junction depth structure. Figure 1 As shown, the memory includes a substrate 1, and an isolation structure layer 4 is formed in the substrate 1. The isolation structure layer 4 is formed, for example, by a trenching and filling process. A word line (gate structure) is formed between the isolation structure layers 4, for example, a buried word line, including a semiconductor layer 2 and a dielectric layer 3, wherein the dielectric layer 3 covers the semiconductor layer 2, and active regions are formed on both sides of the word line, for example, a source region S and a drain region D are arranged on both sides of the word line, and the active region can be obtained by ion implantation according to actual needs.
[0061] After research, the inventors found that the junction depth of this buried gate structure is basically the same, which leads to a larger leakage current, such as cell junction leakage and gate induced drain leakage (GIDL leakage), and also has a greater impact on the turn-on current, resulting in performance limitations and reduced reliability.
[0062] To this end, the present invention provides a memory to improve the above-mentioned defects. Specifically, refer to Figure 2 The flowchart of the method for forming a memory in the first embodiment of the present invention is shown. The method for forming includes:
[0063] Step S11, providing a substrate, wherein the substrate has a first surface and a second surface disposed opposite to each other;
[0064] Step S12, forming at least one group of first grooves in the substrate, wherein openings of the first grooves are formed on the first surface, and each group of first grooves includes two adjacent first grooves;
[0065] Step S13, forming at least one group of word lines in the at least one group of first trenches;
[0066] Step S14, performing a first ion implantation on the substrate at both sides of the word line and close to the first surface;
[0067] Step S15, forming a barrier layer on the substrate and forming an opening, wherein the opening at least exposes a portion of a region between two adjacent word lines of each group of word lines; and
[0068] Step S16, performing a second ion implantation at an angle to the substrate from the opening, forming a doping layer after performing at least the first ion implantation and the second ion implantation, wherein the doping layer is arranged on both sides of each of the word lines, and the depth of the doping layer between two adjacent word lines in each group of word lines is greater than the depth of the doping layer on the opposite side of the two adjacent word lines, and the depth of the doping layer on the opposite side of the two adjacent word lines decreases as the distance from the two adjacent word lines increases.
[0069] Figures 3 to 9 It is a structural schematic diagram of each step of an embodiment of a method for forming a memory of the present invention.
[0070] First, refer to Figure 3 , Figure 3 The present invention is a schematic diagram of providing a substrate in a method for forming a memory according to an embodiment of the present invention.
[0071] For step S11, a substrate 10 is provided, wherein the substrate 10 has a first surface 101 and a second surface 102 arranged opposite to each other. Specifically, the constituent material of the substrate 10 may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), etc. As an example, in one embodiment, the substrate 10 is made of single crystal silicon material. A known structure such as a buried layer (not shown in the figure) may also be formed in the substrate 10, and the present invention is not limited to this.
[0072] Next, please refer to Figure 4 and Figure 5 , Figure 4 is a schematic diagram of a word line in a method for forming a memory according to an embodiment of the present invention, Figure 5 For along Figure 4 Specifically, the word line 50 is formed according to the following process:
[0073] For step S12, at least one group of first grooves is formed in the substrate 10, the openings of the first grooves are formed on the first surface 101, and each group of first grooves includes two adjacent first grooves. In one embodiment, it can be formed by photolithography. In one embodiment, before etching to form at least one group of first grooves, a plurality of second grooves can also be formed, the openings of the second grooves are toward the first surface 101, and the bottoms of the second grooves are away from the first surface 101. The first groove and the second groove can have the same specifications. In order to improve the isolation effect, the depth of the second groove is greater than the depth of the first groove, and the second groove is used to surround the first groove, the source region 111 and the drain region 112. Figure 4 As shown, the second trench is filled with an isolation material layer to form an isolation structure layer 40. In one embodiment, multiple trenches can also be formed by etching, with the peripheral portion (e.g., a row or a column) serving as the second trench, and the remaining trenches serving as at least one group of first trenches. The first trench will be used for the subsequent preparation of buried word lines (or gate structures), and the second trench will be used for the subsequent preparation of isolation structure layers.
[0074] Please continue to refer to Figure 5 For step S13, at least one group of word lines is formed in the at least one group of first grooves. A first dielectric layer may be formed on the groove wall surface of the first groove. In one embodiment, the first dielectric layer may be formed by chemical vapor deposition process, and its material may be, for example, silicon oxide, and its depth may be 1nm-200nm. According to actual product requirements, the first dielectric layer may be of other depths.
[0075] In one embodiment, for example, the isolation structure layer 40 has been formed in the second trench, so the formation of the first dielectric layer will not affect the second trench. The first dielectric layer is, for example, a gate oxide layer.
[0076] The first dielectric layer and the isolation structure layer 40 may be made of at least one of silicon oxide, silicon nitride and silicon oxynitride.
[0077] After the first dielectric layer and / or the isolation structure layer 40 is formed, a planarization process may be performed, for example, by using a chemical mechanical polishing process, so that the upper surface of the first dielectric layer and / or the isolation structure layer 40 is flush with the first surface 101 .
[0078] It is understandable that the first dielectric layer and the isolation structure layer 40 can be prepared in any order.
[0079] Afterwards, a semiconductor layer 20 is formed on the first dielectric layer in the first trench, and the top surface of the semiconductor layer 20 is lower than the first surface. The semiconductor layer 20 is, for example, made of metal. Of course, other materials, such as polysilicon, etc., can also be selected. When a metal material is used as a gate, it can be used as a preferred solution because it helps to obtain better thermal stability and a suitable work function. Furthermore, the metal material is not limited to a single metal, but can also be a binary alloy of a metal, a conductive metal oxide, a metal silicide, a metal nitride, a metal nitride silicon, a metal nitride aluminum, etc.
[0080] Afterwards, a second dielectric layer is filled in the first trench, the second dielectric layer is located on the top surface of the semiconductor layer 20, the second dielectric layer covers the semiconductor layer 20 and is connected to the first dielectric layer, thereby, the first dielectric layer and the second dielectric layer serve as the dielectric layer 30 of the word line 50 (or gate structure).
[0081] The second dielectric layer may be formed by a chemical vapor deposition process. For example, the second dielectric layer may be one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, or a combination thereof.
[0082] The word line 50 intersects with the corresponding active area, so that it can contact the gate structure formed in the active area. In this embodiment, the word line 50 extends along the first direction, so the gate structures aligned in the first direction are all connected to the same word line 50. The word line 50 can be a buried word line, that is, the word line 50 is formed in the substrate 10. In this embodiment, the gate structure formed in the active area also constitutes a part of the word line 50, and the isolation structure layer 40 corresponding to the position of the word line 50 is also formed with a word line material, and the word line material located in the isolation structure 40 is connected to the gate structure, thereby jointly constituting the word line 50. Specifically, the word line 50 includes the semiconductor layer 20 and the dielectric layer 30, the semiconductor layer 20 located in the active area constitutes the gate structure, and is connected to the semiconductor layer 20 in the isolation structure layer 40, and the dielectric layer 30 covers the semiconductor layer 20 to prevent the semiconductor layer 20 from being electrically connected to other wires.
[0083] Please refer to Figure 6 , Figure 6 The schematic diagram of the first ion implantation in the method for forming a memory according to an embodiment of the present invention is as follows: In step S14, the first ion implantation is performed on the substrate 10 at both sides of the word line and close to the first surface.
[0084] In one embodiment, the first ion implantation is an N-type implantation, for example, phosphorus may be implanted, and the implantation dose may be 1E14 / cm 2 ~1E16 / cm 2, the injection energy can be 10KeV~50KeV.
[0085] After the first ion implantation, a first ion implantation layer 81 is formed on the substrate 10 near the first surface.
[0086] Afterwards, please refer to Figure 7 , Figure 7 The schematic diagram of forming a barrier layer and an opening in a method for forming a memory according to an embodiment of the present invention is as follows: In step S15, a barrier layer 60 is formed on the substrate 10 and an opening 61 is formed, wherein the opening 61 at least exposes a portion of the area between two adjacent word lines of each word line group.
[0087] In one embodiment, the blocking layer 60 may be made of, for example, photoresist. It is understandable that the blocking layer 60 may also be made of other materials, such as silicon nitride.
[0088] Taking the blocking layer 60 as an example, which is photoresist, the opening 61 can be realized by, for example, a photolithography process.
[0089] In one embodiment, the opening 61 may be, for example, an opening for forming a subsequent bit line.
[0090] It is understandable that the opening 61 will restrict the tilt angle during subsequent ion implantation. Therefore, the actual size of the opening 61 and the depth of the barrier layer 60 may be adaptively adjusted according to actual process requirements.
[0091] Afterwards, please refer to Figure 8-Figure 10 , Figure 8-Figure 9 A schematic diagram of performing a second ion implantation in a method for forming a memory according to an embodiment of the present invention; Fig.10 A schematic diagram of a memory formed by an embodiment of the present invention. For step S16, a second ion implantation 70 is performed on the substrate from the opening at an angle, and after performing at least the first ion implantation and the second ion implantation, a doping layer is formed, the doping layer is arranged on both sides of each word line, the depth of the doping layer between two adjacent word lines in each group of word lines is greater than the depth of the doping layer on the opposite side of the two adjacent word lines, and the depth of the doping layer on the opposite side of the two adjacent word lines decreases as the distance from the two adjacent word lines increases.
[0092] Specifically, Figure 8 As shown, the second ion implantation 70 is an N-type implantation, for example, phosphorus can be implanted, and the implantation dose can be 1E12 / cm 2 ~1E13 / cm 2The implantation energy may be 30 KeV to 60 KeV, and the implantation angle may be 3° to 20°, where the implantation angle is the angle between the implantation direction and the normal to the first surface of the substrate.
[0093] like Fig. 9 As shown, after the second ion implantation, a second ion implantation layer 82 is formed. The second ion implantation layer 82 is mainly concentrated in the substrate 10 below the opening, including between two adjacent word lines and a small portion of the area away from the two adjacent word lines.
[0094] After the second ion implantation 70 is performed from the opening, the method further includes: performing heat treatment to form the doping layer. That is, after the second ion implantation layer 82 is formed, heat treatment is performed to activate the doping ions to obtain the desired doping layer.
[0095] In one embodiment, the heat treatment includes spike (rapid) annealing, and the annealing temperature may be 900° C. to 1000° C., for example, in a nitrogen environment.
[0096] Lattice damage can also be achieved by heat treatment.
[0097] Please refer to Fig.10 , the doped layer includes a first portion 91, a second portion 92 and a third portion 93, the depth of the first portion 91 is greater than the depth of the second portion 92, the depth of the second portion 92 is greater than the depth of the third portion 93, the first portion 91 is located between the two adjacent word lines, the second portion 92 is located on the opposite side of the two adjacent word lines, and the third portion 93 is located on the side of the second portion 92 away from the word line. For example, Fig.10 The first ion implantation layer 81 at the position opposite to the adjacent isolation structure layer 40 shown in the figure may become the third portion at another word line after annealing.
[0098] In one embodiment, the depth H1 of the first portion 91 may be 50nm-70nm, the depth H2 of the second portion 92 may be 40nm-60nm, the depth H3 of the third portion 93 may be 30nm-50nm, and the width W of the second portion 92 may be 4nm-8nm.
[0099] After the doping layer is formed, the doping layer includes the source region S and the drain region D of the present invention, the source region S and the drain region D are formed in the substrate 10, the source region S and the drain region D are respectively located on both sides of the word line, for example, the drain region D includes the second part 92 and the third part 93, the bottom end of the drain region D has a depth position in the substrate 10 relative to the first surface that is higher than the depth position of the top surface of the semiconductor layer 20 in the substrate 10 relative to the first surface, the source region S includes the first part, the bottom end of the source region S has a depth position in the substrate 10 relative to the first surface that is lower than the depth position of the top surface of the semiconductor layer 20 in the substrate 10 relative to the first surface.
[0100] It can be seen that the depth distribution of the doping layer is uneven, and in one embodiment of the present invention, the depth decreases from between two adjacent word lines to the direction away from the two adjacent word lines, thereby reducing the leakage current and improving the turn-on current, thereby improving the performance of the memory.
[0101] In one embodiment, the source region S or the drain region D between adjacent word lines is shared. Fig.10 The source region S is shown to be shared.
[0102] Afterwards, other operations of the memory may be continued, such as completing the preparation of the bit lines.
[0103] At this point, the present invention has obtained a memory, please continue to refer to Figure 3-Figure 10 , it can be seen that the memory in the present invention includes:
[0104] A substrate 10, wherein the substrate 10 has a first surface 101 and a second surface 102 arranged opposite to each other;
[0105] At least one group of word lines 50 is formed inside the substrate 10, and each group of word lines 50 includes two adjacent word lines 50;
[0106] The doped layer extends from the first surface 101 of the substrate 10 to the interior of the substrate 10 and is arranged on both sides of the word line 50. The depth of the doped layer between two adjacent word lines 50 in each group of word lines 50 is greater than the depth of the doped layer on the opposite side of the two adjacent word lines 50, and the depth of the doped layer on the opposite side of the two adjacent word lines 50 decreases as it moves away from the two adjacent word lines 50.
[0107] In one embodiment, the doping layer includes a first portion 91, a second portion 92, and a third portion 93, the depth of the first portion 91 is greater than the depth of the second portion 92, the depth of the second portion 92 is greater than the depth of the third portion 93, the first portion 91 is located between the two adjacent word lines, the second portion 92 is located on the opposite side of the two adjacent word lines, and the third portion 93 is located on the side of the second portion 92 away from the word line. Fig.10 The first ion implantation layer 81 at the position opposite to the adjacent isolation structure layer 40 shown in FIG. 1 may become the third portion at another word line.
[0108] In one embodiment, the depth H1 of the first portion 91 may be 50nm-70nm, the depth H2 of the second portion 92 may be 40nm-60nm, the depth H3 of the third portion 93 may be 30nm-50nm, and the width W of the second portion 92 may be 4nm-8nm.
[0109] A source region S and a drain region D are formed in the substrate 10, and the source region S and the drain region D are respectively located on both sides of the word line. For example, the drain region D includes the second part 92 and the third part 93, and the depth position of the bottom end of the drain region D in the substrate 10 relative to the first surface is higher than the depth position of the top surface of the semiconductor layer 20 in the substrate 10 relative to the first surface, and the source region S includes the first part 91, and the depth position of the bottom end of the source region S in the substrate 10 relative to the first surface is lower than the depth position of the top surface of the semiconductor layer 20 in the substrate 10 relative to the first surface.
[0110] In one embodiment, the doping type of the doping layer is N-type. For example, it can be phosphorus doped. The doping concentration of the doping layer is 1E12 / cm 2 ~1E16 / cm 2 .
[0111] In one embodiment, the source region S or the drain region D between adjacent word lines is shared. Fig.10 The source region S is shown to be shared.
[0112] The word line 50 includes a first dielectric layer, a semiconductor layer 20 and a second dielectric layer, wherein the first dielectric layer is formed on the wall surface of a groove in the substrate, the semiconductor layer is formed on the first dielectric layer in the groove, the top surface of the semiconductor layer is lower than the first surface, the second dielectric layer is located on the top surface of the semiconductor layer, and the second dielectric layer covers the semiconductor layer and is connected to the first dielectric layer.
[0113] For example, the word line 50 is a buried word line, that is, a first dielectric layer formed in the substrate 10, formed on the sidewall of the first trench, and a semiconductor layer 20 formed on the first dielectric layer in the first trench, and the top surface of the semiconductor layer 20 is lower than the first surface. The semiconductor layer 20 is, for example, made of metal. Of course, other materials such as polysilicon can also be selected. When a metal material is used as a gate, it can be used as a preferred solution because it helps to obtain better thermal stability and a suitable work function. Furthermore, the metal material is not limited to a single metal, but can also be a binary alloy of a metal, a conductive metal oxide, a metal silicide, a metal nitride, a metal nitride silicon, a metal nitride aluminum, etc.
[0114] A second dielectric layer is formed on the semiconductor layer 20 in the first groove, the second dielectric layer is located on the top surface of the semiconductor layer 20, the second dielectric layer covers the semiconductor layer 20 and is connected to the first dielectric layer, thereby, the first dielectric layer and the second dielectric layer serve as the dielectric layer 30 of the word line 50 (or gate structure).
[0115] For example, the second dielectric layer may be one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, or a combination thereof.
[0116] The word line 50 intersects with the corresponding active area, so that it can contact the gate structure formed in the active area. In this embodiment, the word line 50 extends along the first direction, so the gate structures aligned in the first direction are all connected to the same word line 50. The word line 50 can be a buried word line, that is, the word line 50 is formed in the substrate 10. In this embodiment, the gate structure formed in the active area also constitutes a part of the word line 50, and the isolation structure layer 40 corresponding to the position of the word line 50 is also formed with a word line material, and the word line material located in the isolation structure 40 is connected to the gate structure, thereby jointly constituting the word line 50. Specifically, the word line 50 includes the semiconductor layer 20 and the dielectric layer 30, the semiconductor layer 20 located in the active area constitutes the gate structure, and is connected to the semiconductor layer 20 in the isolation structure layer 40, and the dielectric layer 30 covers the semiconductor layer 20 to prevent the semiconductor layer 20 from being electrically connected to other wires.
[0117] In one embodiment, the substrate 10 is further formed with an isolation structure layer 40 , and the isolation structure layer 40 surrounds the source region S and the drain region D.
[0118] In summary, in the memory and the method for forming the same provided by the present invention, at least one group of word lines is formed in the substrate, the doping layers are arranged on both sides of the word lines, the depth of the doping layer between two adjacent word lines of each group of word lines is greater than the depth on the opposite sides of the two adjacent word lines, and the depth of the doping layer on the opposite sides of the two adjacent word lines decreases as it moves away from the two adjacent word lines. Thus, the leakage current is reduced, and the turn-on current is improved, thereby improving the performance of the memory.
[0119] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A memory, characterized in that: include: A substrate having a first surface and a second surface disposed opposite to each other; At least one group of word lines is formed inside the substrate, each group of word lines includes two adjacent word lines; and, A doping layer extends from the first surface of the substrate to the interior of the substrate and is arranged on both sides of each of the word lines. The depth of the doping layer between two adjacent word lines in each group of word lines is greater than the depth of the doping layer on the opposite sides of the two adjacent word lines, and the depth of the doping layer on the opposite sides of the two adjacent word lines decreases as it moves away from the two adjacent word lines.
2. The memory according to claim 1, wherein: The doping layer includes a first part, a second part and a third part, the depth of the first part is greater than the depth of the second part, the depth of the second part is greater than the depth of the third part, the first part is located between the two adjacent word lines, the second part is located on the side away from the two adjacent word lines, and the third part is located on the side of the second part away from the word lines.
3. The memory according to claim 2, wherein: The depth of the first portion is between 50nm and 70nm, the depth of the second portion is between 40nm and 60nm, the depth of the third portion is between 30nm and 50nm, and the width of the second portion is between 4nm and 8nm.
4. The memory according to claim 1, wherein: The doping type of the doping layer is N type.
5. The memory according to claim 1, wherein: The doping concentration of the doping layer is between 1E12 / cm 2 ~1E16 / cm 2 .
6. The memory according to claim 1, wherein: The doping layer includes a source region and a drain region, the source region and the drain region are arranged on both sides of the word line, and the source region or the drain region between two adjacent word lines is shared.
7. The memory according to claim 6, wherein: The substrate is also formed with an isolation structure layer, and the isolation structure layer surrounds the source region and the drain region.
8. The memory according to claim 1, wherein: The word line includes a first dielectric layer, a semiconductor layer and a second dielectric layer, wherein the first dielectric layer is formed on a groove wall surface of a groove in a substrate, the semiconductor layer is formed on the first dielectric layer in the groove, the top surface of the semiconductor layer is lower than the first surface, the second dielectric layer is located on the top surface of the semiconductor layer, and the second dielectric layer covers the semiconductor layer and is connected to the first dielectric layer.
9. A method for forming a memory, characterized in that: include: Providing a substrate, the substrate having a first surface and a second surface disposed opposite to each other; forming at least one group of first grooves in the substrate, wherein openings of the first grooves are formed on the first surface, and each group of first grooves includes two adjacent first grooves; forming at least one set of word lines in the at least one set of first trenches; Performing a first ion implantation on the substrate at both sides of the word line and close to the first surface; forming a barrier layer on the substrate and forming an opening, wherein the opening at least exposes a portion of a region between two adjacent word lines of each group of word lines; as well as A second ion implantation is performed obliquely into the substrate from the opening. After performing at least the first ion implantation and the second ion implantation, a heat treatment is performed to form a doping layer. The doping layer is arranged on both sides of each of the word lines. The depth of the doping layer between two adjacent word lines in each group of word lines is greater than the depth of the doping layer on the opposite side of the two adjacent word lines. The depth of the doping layer on the opposite side of the two adjacent word lines decreases as the distance from the two adjacent word lines increases.
10. The method for forming a memory according to claim 9, wherein: The first ion implantation is N-type implantation, with an implantation dose between 1E14 / cm 2 ~1E16 / cm 2 , the injection energy is between 10KeV and 50KeV.
11. The method for forming a memory according to claim 9, wherein: The second ion implantation is N-type implantation, with an implantation dose between 1E12 / cm 2 ~1E13 / cm 2 The implantation energy is between 30KeV and 60KeV, and the implantation angle is between 3° and 20°.
12. The method for forming a memory according to claim 9, wherein: The heat treatment includes spike annealing at a temperature between 900° C. and 1000° C. in a nitrogen environment.
13. The method for forming a memory according to claim 9, wherein: The doping layer includes a first part, a second part and a third part, the depth of the first part is greater than the depth of the second part, the depth of the second part is greater than the depth of the third part, the first part is located between the two adjacent word lines, the second part is located on the opposite side of the two adjacent word lines, and the third part is located on the side of the second part away from the word line.
14. The method for forming a memory according to claim 13, wherein: The depth of the first portion is between 50nm and 70nm, the depth of the second portion is between 40nm and 60nm, the depth of the third portion is between 30nm and 50nm, and the width of the second portion is between 4nm and 8nm.