Adaptive multi-level gate driver circuit and method for switching a half-bridge circuit

Abstract

A gate driver circuit for driving a power switch and a method for switching a half-bridge circuit including a high-side device and a low-side device are disclosed. The gate driver circuit includes: a gate driver having a first input terminal for receiving an input signal and an output terminal coupled to the power switch, the gate driver providing a main gate current and an auxiliary gate current; and a differential voltage sensor having a first input terminal for receiving an input signal, a second input terminal coupled to a power supply voltage, a third input terminal coupled to a terminal of the power switch, and an output terminal coupled to the second input terminal of the gate driver.

Description

Technical Field

[0001] The present invention generally relates to systems and methods for adaptive multi-level gate drivers. Background Art

[0002] FIG. 1A is a schematic diagram 100 of an insulated gate bipolar transistor (“IGBT”) 102 including a parasitic capacitor C coupled between a gate and a collector. GC , C coupled between the gate and the emitter GE and C coupled between the collector and emitter CE .

[0003] FIG. 1B is a graph of the value of the parasitic capacitance shown in FIG. 1A relative to the collector-emitter voltage, where C ISS Represents capacitor C M and C GE and C OSS Represents capacitor C M and C CE The sum of C M represents a Miller capacitor which is highly nonlinear due to the gain of the IGBT 102 as is known in the art. For low collector-emitter voltages, the capacitor C ISS , C OSS and C M The value of is relatively high and decreases rapidly during the initial increase in collector-emitter voltage and then asymptotically approaches a minimum value at high collector-emitter voltages.

[0004] FIG2A is a schematic diagram 200 of a power switch in the prior art, the power switch including a high-side driver 206 and a low-side driver 204, a high-side gate resistor RgHS and a low-side gate resistor RgLS, and a high-side power transistor T1 and a low-side power transistor T2. FIG2A shows a voltage V CE (collector to emitter voltage), V G (gate voltage) and V OUT (voltage from the low-side gate driver) and the current associated with the low-side driver, I G (gate current) and I C (Collector current).

[0005] For a specified gate resistor, it takes a relatively long time to charge and discharge the parasitic capacitance shown in FIG. 1A . Therefore, the propagation delay of the power transistor shown in FIG. 2A is also relatively high. Part of the propagation delay of the power transistor is called the "dead time", which must be considered in half-bridge applications to avoid cross conduction. The large propagation delays of the high-side and low-side devices of the half-bridge power switch mainly occur when the collector-to-emitter voltage ("VCE") or the drain-to-source voltage ("VDS") is low when turning off. As shown in FIG. 1B , in this case, the Miller capacitance is very high. Long propagation delays result in large dead times because the propagation delay when turning on is short. This leads to disadvantages in terms of efficiency and precise timing.

[0006] One solution for addressing propagation delay is through proper selection of gate resistors RgLS and RgHS. The lower the gate resistance, the shorter the propagation delay. However, the gate resistance also specifies the switching speed. Therefore, the selection of gate resistor Rg is limited by other design constraints, such as dv / dt limits for electromagnetic interference ("EMI") limits.

[0007] FIG. 2B is a timing diagram associated with the power switch of FIG. 2A , showing V for given values ​​of RgHS and RgLS. OUT 、V G ,I G 、V CE and I C FIG2B also shows the waveform of the off current I OFF Waveform.

[0008] FIG. 3A is a more detailed timing diagram associated with the turn-on phase of the low side of the power switch in FIG. 2A , and FIG. 3B is a more detailed timing diagram associated with the turn-off phase of the low side of the power switch in FIG. 2A . The waveforms shown in FIG. 3A and FIG. 3B include a gate voltage (V G ), output voltage (V S ), gate current (I G ), collector current (I C ) and energy loss (E). The time parameters along the horizontal time axis of these waveforms include: t TH (time to reach threshold voltage), t1 (time when Miller plateau starts), t2 (time when tail starts in on-mode or ends in off-mode), and t3 (time when Miller plateau ends).

[0009] In the waveforms in FIGS. 3A and 3B showing energy loss (E), the energy consumed during the switching of the power transistor is labeled E. SW , while the energy consumed by conduction is marked as E CONDNote that the energy consumed during the switching of the power transistor includes both the peak portion and the long “tail” portion. S ) The elongated tail can be seen in the clearly marked arrow portion of the waveform. The energy loss indicated by the tail results in large power switching losses.

[0010] It is therefore an object of the present invention to reduce propagation delays and power switch losses during switching of a power switch. Summary of the invention

[0011] According to the method and circuit of the embodiments, both the dead time and the tail phenomenon are minimized, which in turn improves the switching efficiency and allows for more precise switching timing of the power switch.

[0012] According to an embodiment, a gate driver circuit for driving a power switch includes: a gate driver having a first input terminal for receiving an input signal and an output terminal coupled to the power switch, the gate driver being configured to provide a main gate current and an auxiliary gate current; and a differential voltage sensor having a first input terminal for receiving an input signal, a second input terminal coupled to a power supply voltage, a third input terminal coupled to a terminal of the power switch, and an output terminal coupled to the second input terminal of the gate driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0014] FIG. 1A is a schematic diagram of an IGBT including parasitic capacitance as known in the prior art;

[0015] FIG. 1B is a graph of the value of the parasitic capacitance shown in FIG. 1A relative to the collector-emitter voltage;

[0016] FIG. 2A is a schematic diagram 200 of a prior art power switch including a high-side driver and a low-side driver and a high-side gate resistor and a low-side gate resistor;

[0017] FIG2B is a timing diagram associated with the power switch in FIG2A ;

[0018] FIG3A is a timing diagram associated with the conduction phase of the low side of the power switch in FIG2A ;

[0019] FIG3B is a timing diagram associated with the turn-off phase of the low side of the power switch in FIG2A ;

[0020] Figure 4A is a timing diagram associated with a turn-on phase of a low side of a power switch according to an embodiment;

[0021] Figure 4Bis a timing diagram associated with a turn-off phase of a low side of a power switch according to an embodiment;

[0022] Figure 5A is a block diagram of an integrated circuit gate driver and a half-bridge power switch of a power switching system according to an embodiment;

[0023] Figure 5B is a block diagram of a gate driver, a differential voltage sensor, and a single transistor power switch referenced to a first supply voltage according to an embodiment;

[0024] Figure 5C is a block diagram of a gate driver, a differential voltage sensor, and a single transistor power switch referenced to a second supply voltage according to an embodiment;

[0025] Figure 6 is with Figure 5A A block diagram of a low-side differential voltage sensor associated with a power switch system in FIG.

[0026] Figure 7 is during the turn-on event with Figure 6 Timing diagram associated with the low-side differential voltage sensor in;

[0027] Figure 8 is during a shutdown event with Figure 6 Timing diagram associated with the low-side differential voltage sensor in;

[0028] Fig. 9 is during the turn-on event and the turn-off event with Figure 6 Timing diagram associated with the low-side differential voltage sensor in;

[0029] Fig.10 is with Figure 5A A block diagram of a high-side differential voltage sensor associated with a power switch system in FIG.

[0030] Fig.11 is during the turn-on event with Fig.10 The timing diagram associated with the high-side differential voltage sensor in FIG.

[0031] Fig.12 is during a shutdown event with Fig.10 The timing diagram associated with the high-side differential voltage sensor in FIG.

[0032] Fig.13 is during the turn-on event and the turn-off event with Fig.10 The timing diagram associated with the high-side differential voltage sensor in FIG.

[0033] Fig.14 Is suitable for Figure 6A schematic diagram of an input stage used in a low-side differential voltage sensor in; and

[0034] Fig.15 Is suitable for Fig.10 Schematic diagram of the input stage used in the high-side differential voltage sensor in FIG. DETAILED DESCRIPTION

[0035] According to an embodiment, the gate current of the output stage of the gate driver for the power switch is configured to depend on the output voltage V S and the switch supply voltage (V SS and DC+). Typically, V SS is the negative voltage supply or ground, and DC+ is the positive voltage supply. The absolute values ​​of these voltages can range from tens of volts to hundreds of volts as required by the particular application and allowed by the particular switching technology.

[0036] Figure 4A is a timing diagram associated with a turn-on phase of a low side of a power switch according to an embodiment, and Figure 4B is a timing diagram associated with a turn-off phase of a low side of a power switch according to an embodiment.

[0037] Figure 4A and Figure 4B The following waveforms are shown: Gate voltage (V G ); Output voltage (V S ); Gate current (I G ); Collector current (I C ); Energy loss (E). It is shown that the E SW and E COND Part of the energy loss. S Portion 402 of the waveform (between time t2 and time t3) indicates the tail of the erase during the on period. G Portion 404 of the waveform (between time t2 and time t4) shows the increased gate current. S Portion 406 of the waveform (between time t1 and time t2) indicates the tail of the erase during the off period. G Portion 408 of the waveform (between time t0 and time t2) again shows an increased gate current. G The gate current is enhanced during portions 404 and 408 of the waveform, which can erase V S The tails in portions 402 and 406 of the waveform. This minimizes switching losses and dead time while also keeping the dv / dt of the switching devices within the limits imposed by EMI regulations.

[0038] Compare Figure 4A and Figure 4B 3A and 3B, it can be clearly seen that the E obtained by the enhanced gate current provided by the circuit implementation described in further detail below SW Reduction of energy loss.

[0039] Reference Figure 5A , using diode D1 and diode D2 to obtain the output voltage V S and the supply voltage (this difference is denoted as ΔV in the following); on the low side V S -V SS =ΔV LS , while on the high side DC+-V S =ΔV HS Based on these differential voltages and the on / off state of the power transistors (known to the user), the correct level of gate enhancement current is provided at the gates of the high-side power device and the low-side power device during both the turn-on and turn-off phases. Fig.14 and Fig.15 The input stage described in further detail is used to generate the differential voltage ΔV LS and ΔV HS The correct mechanism.

[0040] Through the analysis of previous power switch data sheets and tests, the V S The average value (threshold value) ΔV is found where the tail phenomenon described previously begins to appear (see the arrow portion in FIG. 3A and FIG. 3B ). This threshold value ΔV is hereinafter referred to as ΔV th The initial part of the tail phenomenon corresponds to the peak value of the Miller capacitance. Once ΔV reaches or drops to ΔV th Hereinafter, the gate current increases. These voltage thresholds and their implementation in a gate driver circuit for driving a power switching device are described in further detail below.

[0041] Figure 5A 5 is a block diagram of an integrated circuit gate driver 501 and a half-bridge power switch 503 of a power switch system 500A according to an embodiment. The power switch system is substantially symmetrical in that it consists of similar blocks at both the low side and the high side. The integrated circuit gate driver 501 is described below. The half-bridge power switch 503 includes a high-side power device 526, for example, coupled between DC+ and the output voltage node V S , which is in turn coupled to a load 530. Although an inductive load is shown, other types of loads are known in the art. In an embodiment, a freewheeling diode D3 is coupled across the current path of the power device 526. The half-bridge power switch 503 also includes a low-side power device 528, such as a low-side power device 528 coupled at the output voltage node V SIn the embodiment shown, V is grounded. SS In an embodiment, a freewheeling diode D4 is coupled across the current path of the power device 528 .

[0042] Figure 5A An integrated circuit gate driver 501 of an embodiment is shown in FIG. 5 , which includes the following pins (in clockwise order): DC+ (positive supply voltage), V B (internal bias node), H 01 (first high-side gate driver output), H 02 (second high-side gate driver output), V S (output voltage node), L 02 (second low-side gate driver output), L 01 (first low-side gate driver output), V SS (ground or negative supply voltage), L IN (low-side input signal), H IN (high-side input signal), V CC (Additional positive supply voltage).

[0043] The gate driver integrated circuit 501 includes: a high-side constant current driver 518, which has an input terminal for receiving a high-side input signal HIN and an output terminal coupled to the control node of the high-side power device at pin H01; a high-side boost current driver 520, which has a first input terminal for receiving a HS pull-up boost signal, a second input terminal for receiving a HS pull-down boost signal, and an output terminal (OUTBOOST) coupled to the control node of the high-side power device 526 at pin H02; and a high-side sensor and differentiator circuit 514, which has an input terminal coupled to a positive voltage source DC+ through a diode D1, an output terminal coupled to an output node V S The input terminal of the high-side enhanced current driver 520 is coupled to the positive voltage source DC+ and the input terminal for receiving the high-side input signal HIN, and the first output terminal and the second output terminal are coupled to the first input terminal and the second input terminal of the high-side enhanced current driver 520. Based on the positive voltage source DC+ and the output node V S The high-side sensor and differentiator circuit 514 can obtain the above voltage difference ΔV HS =DC+—VS.

[0044] The gate driver integrated circuit 501 includes a low-side constant current driver 524 having a low-side constant current driver for receiving a low-side input signal L IN The input terminal and the L pin 01The output terminal of the control node coupled to the low-side power device; a low-side enhanced current driver 522 having a first input terminal for receiving an LS pull-up enhanced signal, a second input terminal for receiving an LS pull-down enhanced signal and a 02 An output terminal (OUTBOOST) coupled to the control node of the low-side power device 528; and a low-side sensor and differentiator circuit 516, which has a diode D2 coupled to the output node V S The input terminal is coupled to the negative supply voltage V ss An input terminal for receiving a low-side input signal LIN, and a first output terminal and a second output terminal coupled to a first input terminal and a second input terminal of a low-side enhanced current driver 522. Based on the output nodes V S and negative voltage source V ss The input terminal of the low-side sensor and the differentiator circuit 516 can obtain the above voltage difference ΔV LS =V S —V SS .

[0045] The following blocks are also shown in the integrated circuit gate driver 501: input filter 502, DT+AST block 506 (DT = dead time circuit for inserting a time interval between the high-side switching signal and the low-side switching signal to avoid simultaneous switching of power devices, AST = anti-breakdown circuit used to avoid cross conduction between low-side power devices and high-side power devices), UVLO block 504 (UVLO = undervoltage lockout circuit used to protect the driver circuit in the event of a power supply loss), delay equalizer block 508 (delay equalizer circuit for introducing a delay to equalize the propagation delays in the high voltage domain and the low voltage domain), HVLS block 510 (HVLS = high voltage level converter circuit required to transfer the input signal voltage from the low side to the high side and used to operate normally in a very high voltage domain when necessary). Figure 5A The abbreviation "HZ" is also used in the high-side boost current driver 520 and the low-side boost current driver 522. The abbreviation "HZ" refers to the high impedance output state that the driver 520 and the driver 522 can be placed in when the boost gate current pulse is not supplied as described in further detail below. The auxiliary stage 520 and the auxiliary stage 522 are set to show high impedance (HZ) whenever the auxiliary boost current is not required. The gate driver circuit 501 can be configured to omit some of the above-mentioned functional blocks for a specific application, or can be configured to add additional functional blocks as needed for a specific application.

[0046] Finally, the lower voltage blocks 502, 504, 506, 508, 516, 522, 524 and D2 can all be integrated on the P substrate portion of the gate driver integrated circuit 501. To prevent voltage breakdown on the chip, the high voltage blocks 510, 512, 514, 518, 520 and D1 can all be integrated on the N epitaxial portion of the gate driver integrated circuit 501.

[0047] Although it has been about Figure 5A A half-bridge implementation is shown and described, but a single transistor power switch implementation may also be used. Figure 5B and Figure 5C A single transistor power switch system is described. Depending on the implementation, a full bridge implementation including four power transistors or devices (not shown) may also be used.

[0048] Figure 5B 5 is a block diagram of a power switch system 500B, which includes a gate driver 522, a gate driver 524, a low-side differential voltage sensor 516, a diode D2 and a diode D4, and a power supply having a voltage V SS A single transistor power switch 528 having an emitter referenced to and a collector coupled to a load 530 .

[0049] Figure 5C is a block diagram of a power switch system 500C including a gate driver 518 , a gate driver 520 , a high side differential voltage sensor 514 , diodes D1 and D3 , and a single transistor power switch having a collector referenced to DC+ and an emitter coupled to a load 530 .

[0050] Figure 6 is with Figure 5A 00A is a block diagram of a low-side differential voltage sensor 516 associated with a power switch system 500A in FIG.

[0051] exist Figure 6 The low-side sensor and differentiator circuit 516 is shown in more detail in block diagram form in FIG. The low-side sensor circuit 516 includes the previously described diode D2 and a S_DIODE The input stage 604 has three reference voltages: a reference voltage, a VREF reference voltage, and a REF reference voltage. Fig.14 602 and described in further detail below. The low-side sensor and differentiator circuit 516 also includes a differentiator 608 having a capacitor 602 and a resistor 606, a comparator 610, and a logic circuit 612. The differentiator 608 receives V REF The reference signal is compared with the input IN DER Signal and output OUT DERThe comparator 610 receives the REF reference signal and provides the LS VCESENSE Output signal. Logic circuit 612 receives LS VCESENSE and L IN Signal and provide LS pull-up enhancement signal and LS pull-down enhancement signal. Differentiator 608 and comparator 610 can be of conventional design. Logic circuit 612 can be implemented using logic gates in an integrated circuit or can be implemented as software inside or outside the integrated circuit as needed. The correct logic function of logic circuit 612 can be seen from the various timing diagrams provided and described in further detail below.

[0052] In operation, once the sensed ΔV LS Exceeding the pre-established threshold as described above, diode D2 provides a voltage that follows ΔV LS This signal is then combined with the adaptive voltage reference (V REF ) are provided to the input of the differentiator 608. DER ) there is a REF A pulse centered at a voltage level consistent with the slope of the signal provided by input stage 604.

[0053] At the output of the differentiator 608 (OUT DER ), whenever ΔV LS When it decreases, it exceeds V REF level pulse, and in the opposite case appears below V REF This signal is input to the comparator 610, which combines with the reference voltage (REF) to provide the LS VCESENSE Signal.

[0054] A signal is needed to provide an auxiliary current at the output of the power stage to provide a higher gate current when needed. Therefore, the V REF The signal is controlled to allow the first pulse of the differentiator 608 to continue as long as the power transistor is turned on. This is done because, according to the polarity of the conventional constant gate current currently used, on the rising edge of this output pulse, a negative auxiliary gate current is provided to the power transistor, while on the falling edge, a positive auxiliary gate current is obtained. Based on the square wave pulse from the comparator 610, the power stage 522 provides a square wave pulse to be added at the output to the power transistor provided by the slave driver stage 524. Figure 5A The constant gate current pulses marked as "Constant Current" in the figure are used to reduce V S The duration of the tail and thus improve the power efficiency of the switching system.

[0055] exist Figure 7 , Figure 8 and Fig. 9 The internal waveforms of the low side of the switching system are shown in the timing diagram in FIG. 1 and are described in further detail below.

[0056] Figure 7 is related to the conduction period Figure 6 1, which includes a timing diagram associated with the low-side differential voltage sensor 516 in accordance with an embodiment including an erased tail V S Output signal, V S _ DIODE Signal, V REF Signal, IN DER Signal, OUT DER Signal, REF reference voltage, LS VCESENSE Signal and L IN Input signal.

[0057] Figure 8 is related to the shutdown event during Figure 6 1, which includes a timing diagram associated with the low-side differential voltage sensor 516 in accordance with an embodiment including an erased tail V S Output signal, V S _ DIODE Signal, V REF Signal, IN DER Signal, OUT DER Signal, REF reference voltage, LS VCESENSE Signal and L IN Input signal.

[0058] Fig. 9 is related to the turn-on event and turn-off event Figure 6 The timing diagram associated with the low-side differential voltage sensor 516 includes V G Gate voltage signal, LS VCESENSE Signal, L IN Input signal, LS pull-up enhanced signal, LS pull-down enhanced signal, OUT DRIVER signal (boost driver 522 output) and I G Gate current signal. Note that Fig. 9 The enhanced gate current portion can be clearly seen in FIG. 5 , which includes an enhanced current portion 902 during the second portion of the turn-on event and an enhanced current portion 904 during the first portion of the turn-off event. The non-enhanced gate current portion is provided by the low-side constant current driver 524.

[0059] Fig.10 is with Figure 5A 00A in FIG. 5 is a block diagram of a high-side differential voltage sensor 514 associated with a power switch system 500A in FIG.

[0060] exist Fig.10The high side sensor and differentiator circuit 516 is shown in more detail in block diagram form in FIG. The high side sensor circuit 514 includes the previously described diode D1 and a DIODE The input stage 1004 has three reference voltages: a reference voltage, a VREF reference voltage, and a REF reference voltage. Fig.15 1002 and described in further detail below. The high-side sensor circuit 514 also includes a differentiator 1008 including a capacitor 1002 and a resistor 1006, a comparator 1010, and a logic circuit 1012. The differentiator 1008 receives V REF The reference signal is compared with the input IN DER Signal and output OUT DER The comparator 1010 receives the REF reference signal and provides the HS VCESENSE Output signal. Logic circuit 1012 receives HS VCESENSE Signal and H IN Signal and provide HS pull-up enhancement signal and HS pull-down enhancement signal. Differentiator 1008 and comparator 1010 can be of conventional design. Logic circuit 1012 can be implemented using logic gates in an integrated circuit or can be implemented as software inside or outside the integrated circuit as needed. The exact logic function of logic circuit 1012 can be seen from the various timing diagrams provided and described in further detail below.

[0061] In operation, once the sensed ΔV HS Beyond the pre-established threshold as described above, diode D1 provides a voltage that follows ΔV HS This signal is then combined with the adaptive voltage reference (V REF ) are provided to the input of the differentiator 1008. DER ) there is a REF A pulse centered at a voltage level consistent with the slope of the signal provided by input stage 1004.

[0062] At the output of the differentiator 1008 (OUT DER ), whenever ΔV HS When it decreases, it exceeds V REF level pulse, and in the opposite case appears below V REF This signal is input to the comparator 1010, which combines with the reference voltage (REF) to provide the HS VCESENSE Signal.

[0063] A signal is needed to provide an auxiliary current at the output of the power stage to provide a higher gate current when needed. Therefore, the VREF The signal is controlled to allow the first pulse of the differentiator 1008 to continue as long as the power transistor is turned on. This is done because, according to the polarity of the conventional constant gate current currently used, on the rising edge of this output pulse, a negative auxiliary gate current is provided to the power transistor, while on the falling edge, a positive auxiliary gate current is obtained. Based on the square wave pulse from the comparator 1010, the power stage 520 provides a square wave pulse that will be added to the output provided by the slave driver stage 518. Figure 5A The constant gate current pulses marked as “Constant Current” in the figure are used to reduce V S The duration of the tail and thus improve the power efficiency of the switching system.

[0064] exist Fig.11 , Fig.12 and Fig.13 The internal waveforms on the high side of the switching system are shown in the timing diagram in FIG. 1 and are described in further detail below.

[0065] Fig.11 is related to the conduction period Fig.10 14, which includes a timing diagram associated with the high-side differential voltage sensor 514 in accordance with an embodiment including an erased tail V S Output signal, DC_ DIODE Signal, V REF Signal, IN DER Signal, OUT DER Signal, REF reference voltage, HS VCESENSE Signal and H IN Input signal.

[0066] Fig.12 is related to the shutdown event during Fig.10 14, which includes a timing diagram associated with the high-side differential voltage sensor 514 in accordance with an embodiment including an erased tail V S Output signal, DC_ DIODE Signal, V REF Signal, IN DER Signal, OUT DER Signal, REF reference voltage, HS VCESENSE Signal and H IN Input signal.

[0067] Fig.13 is related to the turn-on event and turn-off event Fig.10 The timing diagram associated with the high-side differential voltage sensor 514 includes V G Gate voltage signal, HS VCESENSE Signal, H IN Input signal, HS pull-up enhanced signal, HS pull-down enhanced signal, OUT DRIVERsignal (boost driver 520 output) and I G Gate current signal. Note that Fig.13 The enhanced gate current portion can be clearly seen in FIG. 1 , which includes an enhanced current portion 1302 during the second portion of the turn-on event and an enhanced current portion 1304 during the first portion of the turn-off event. The non-enhanced gate current portion is provided by the low-side constant current driver 518.

[0068] Fig.14 Is suitable for Figure 6 14 is an exemplary schematic diagram of a low-side input stage 604 used in a low-side differential voltage sensor 516 in FIG. Transistor 1402 and six series-coupled diodes 1404 are used to generate a reference voltage, which is divided by resistors 1406 and 1408 to generate a REF reference voltage. Transistor 1410 and six series-coupled diodes 1412 are used to generate a reference voltage, which is divided by resistors 1414, 1416, and 1418 to generate V REF reference voltage. Switch 1420 can be used to provide V REF The reference voltage generates two values. As described in further detail below, transistor 1422 and four series-coupled diodes 1424 and Zener diode 1426 are used in conjunction with diode D2 to generate V S _ DIODE maximum allowable voltage. It is important to note that the low-side input stage 604 includes (through diode D2) a S and directly to V SS Supply voltage connection for both.

[0069] In operation, the REF reference voltage is higher than V SS A substantially constant reference voltage for the power supply level. V REF The reference voltage is a substantially constant reference voltage having a voltage higher than V SS The power supply level has a first nominal value and in the second operating mode has a value higher than V SS The switch 1420 is used to switch between the first working mode and the second working mode. S _ DIODE Relative to V SS When the voltage of the transistor is higher than the threshold voltage, the switch 1420 is turned on, or when V S _ DIODE Relative to V SS When V drops below the transistor threshold voltage, the switch 1420 is turned off. S _ DIODE The voltage represents V as previously described S Voltage and V SSThe voltage difference between them. When V S V S _ DIODE The maximum allowable voltage correction, V S _ DIODE The voltage is clamped above V SS However, as can be seen in the previous timing diagram, when V S Voltage Ratio V S _ DIODE When the maximum allowable voltage is more negative, V S _ DIODE Voltage follows V S voltage. Therefore, V S _ DIODE is a representative voltage of the voltage across the low-side power device 528 .

[0070] Fig.15 Suitable for use in Fig.10 1004 in the high-side differential voltage sensor 514 of FIG. Transistor 1502 and six series-coupled diodes 1504 are used to generate a reference voltage, which is divided by resistors 1506 and 1508 to generate a REF reference voltage. Transistor 1510 and six series-coupled diodes 1512 are used to generate a reference voltage, which is divided by resistors 1514, 1516, and 1518 to generate V REF reference voltage. Switch 1520 can be used to provide V REF The reference voltage generates two values. As described in further detail below, transistor 1522 and four series-coupled diodes 1524 and Zener diode 1526 are used together with diode D1 to generate DC_ DIODE maximum allowable voltage. It is important to note that the low-side input stage 1004 includes both a voltage to DC+ (through diode D1) and directly to V S Output voltage connection.

[0071] In operation, in addition to the various bias values, power supply and reference voltage, Fig.15 The operation of the high-side input stage 1004 is similar to that previously discussed. Fig.14 The operation described for the low-side input stage 604 shown in FIG. 6 is substantially the same.

[0072] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted as having a limiting meaning. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art upon reference to the description. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A gate driver circuit for driving a power switch, comprising: a gate driver having a first input terminal for receiving an input signal and an output terminal coupled to the power switch, the gate driver being configured to provide a main gate current and an auxiliary gate current; and a differential voltage sensor having a first input for receiving the input signal, a second input coupled to a supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to the second input of the gate driver, wherein the gate driver comprises a main driver configured to provide the main gate current, and an auxiliary driver configured to provide the auxiliary gate current, and The main driver is coupled to a first input terminal of the gate driver, and the auxiliary driver is coupled to a second input terminal of the gate driver.

2. The gate driver circuit according to claim 1, wherein: The differential voltage sensor comprises: a differentiator having an input coupled to the input of the differential voltage sensor and an input coupled to a differentiator reference voltage; a comparator having an input coupled to the output of the differentiator, an input coupled to a comparator reference voltage, and an output; and A logic circuit has a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving the input signal, and an output terminal coupled to the output terminal of the differential voltage sensor.

3. The gate driver circuit according to claim 2, wherein: The differential voltage sensor further includes an input stage for generating the differentiator reference voltage and the comparator reference voltage. 4 . The gate driver circuit of claim 1 , further comprising a diode coupled between the second input terminal of the differential voltage sensor and the power supply voltage. 5 . The gate driver circuit of claim 1 , further comprising a diode coupled between a third input of the differential voltage sensor and a terminal of the power switch.

6. A gate driver circuit for driving a power switch, comprising: a first main driver having an input terminal for receiving a first input signal and an output terminal for providing a first gate current; A first auxiliary driver having an input terminal and an output terminal for providing a first auxiliary gate current; a first differential voltage sensor having a first input for receiving the first input signal, a second input coupled to a first supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to an input of the first auxiliary driver; a second main driver having an input terminal for receiving a second input signal and an output terminal for providing a second gate current; a second auxiliary driver having an input terminal and an output terminal for providing a second auxiliary gate current; as well as a second differential voltage sensor having a first input terminal for receiving the second input signal, a second input terminal coupled to a second supply voltage, a third input terminal coupled to a terminal of the power switch, and an output terminal coupled to an input terminal of the second auxiliary driver.

7. The gate driver circuit according to claim 6, wherein: The first differential voltage sensor comprises: a differentiator having an input coupled to the input of the first differential voltage sensor and an input coupled to a differentiator reference voltage; a comparator having an input coupled to the output of the differentiator and an input coupled to a comparator reference voltage; and A logic circuit has a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving the first input signal, and an output terminal coupled to the output terminal of the first differential voltage sensor.

8. The gate driver circuit according to claim 7, wherein: The first differential voltage sensor further includes an input stage for generating the differentiator reference voltage and the comparator reference voltage.

9. The gate driver circuit according to claim 7, wherein: The logic circuit includes a first output and a second output for driving a first input and a second input of the first auxiliary driver.

10. The gate driver circuit according to claim 6, wherein: The second differential voltage sensor comprises: a differentiator having an input coupled to the input of the second differential voltage sensor and an input coupled to a differentiator reference voltage; a comparator having an input coupled to the output of the differentiator and an input coupled to a comparator reference voltage; and A logic circuit has a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving the second input signal, and an output terminal coupled to the output terminal of the second differential voltage sensor.

11. The gate driver circuit according to claim 10, wherein: The second differential voltage sensor further includes an input stage for generating the differentiator reference voltage and the comparator reference voltage.

12. The gate driver circuit according to claim 10, wherein: The logic circuit includes a first output and a second output for driving a first input and a second input of the second auxiliary driver.

13. A method for switching a half-bridge circuit comprising a high-side device and a low-side device using a gate driver circuit according to any one of claims 1 to 12, the method comprising: driving a control node of the high-side device using a first current pulse having a first pulse width; driving a control node of the high-side device with a second current pulse during a duration of the first current pulse, the second current pulse having a second pulse width shorter than the first pulse width; driving a control node of the low-side device using a third current pulse having a third pulse width; and During the duration of the third current pulse, a control node of the low-side device is driven with a fourth current pulse, the fourth current pulse having a fourth pulse width shorter than the third pulse width.

14. The method according to claim 13, wherein: The first current pulse occurs during a first portion and a second portion of a turn-on event of the high-side device, and the second current pulse occurs only during the second portion of the turn-on event of the high-side device.

15. The method according to claim 13, wherein: The first current pulse occurs during a first portion and a second portion of a turn-off event of the high-side device, and the second current pulse occurs only during the first portion of a turn-off event of the high-side device.

16. The method according to claim 13, wherein: The third current pulse occurs during a first portion and a second portion of a turn-on event of the low-side device, and the fourth current pulse occurs only during the second portion of the turn-on event of the low-side device.

17. The method according to claim 13, wherein: The third current pulse occurs during a first portion and a second portion of a turn-off event of the low-side device, and the fourth current pulse occurs only during the first portion of a turn-off event of the low-side device.

18. The method according to claim 13, wherein: The second pulse width is determined by sensing and differentiating the voltage across the high-side device, and wherein the fourth pulse width is determined by sensing and differentiating the voltage across the low-side device.

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