Body Biasing for Ultra-Low Voltage Digital Circuits

Abstract

The digital circuit includes a logic circuit formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. The body bias generator circuit applies an n-body bias voltage to the n-body bias node of the p-channel MOSFET and applies a p-body bias voltage to the p-body bias node of the n-channel MOSFET. The body bias generator circuit operates to: in a first mode, apply a ground power supply voltage to the n-body bias node of the logic gate as the n-body bias voltage and apply a positive power supply voltage to the p-body bias node of the logic gate as the p-body bias voltage; and in a second mode, apply a positive power supply voltage to the n-body bias node of the logic gate as the n-body bias voltage and apply a ground power supply voltage to the p-body bias node of the logic gate as the p-body bias voltage.

Description

Technical Field

[0001] The present invention relates to body biasing of transistors in digital circuits, and more particularly to the implementation of dynamic forward and reverse body biasing for ultra-low voltage digital circuits. Background Art

[0002] It is well known in the art that body biasing is applied to the well region of a metal oxide semiconductor field effect transistor (MOSFET) to affect the characteristics of the transistor channel. For example, applying a forward body bias (FBB) to the well affects device operation by reducing the threshold voltage (Vt) of the transistor. This results in faster device operation, as the channel current increases at the expense of an increased risk of current leakage. Conversely, applying a reverse body bias (RBB) to the well affects device operation by increasing the threshold voltage (Vt) of the transistor. This results in the device exhibiting lower current leakage at the expense of reduced speed. Thus, it is clear that circuit designers can use body bias selection to modulate the transistor threshold voltage to achieve a trade-off between power and speed of circuit operation.

[0003] There is an increasing interest in circuits operating at ultra-low voltage levels. For example, for digital circuits, voltage levels equal to or less than 0.5 V are now common in many applications, such as Internet of Things (IoT)-oriented devices. Such digital circuits typically operate in a suspended operation mode (such as sleep or deep sleep), and when in this mode, it is important that the risk of current leakage of the transistors in the digital circuit is reduced. To address this issue, when the sleep (or deep sleep) operation mode is active, circuit designers can choose to use a reverse body bias (RBB) applied to the well. When the digital circuit is in the active operation mode, switching speed is required, and circuit designers can choose to use a forward body bias (FBB) applied to the well. Thus, the concept of body bias modulation that depends on the digital circuit operation mode is a well-known strategy to dynamically ensure that the digital circuit can operate at a target frequency while still supporting power consumption reduction.

[0004] The additional circuitry and logic required to support body bias modulation itself consume power. In many cases, the power reduction of digital circuits that utilize body bias modulation depending on the digital circuit operation mode greatly offsets the power consumption of the additional circuitry and logic for supporting body bias modulation. The charge pump circuitry required to generate a negative bias voltage for the reverse body bias (RBB) or a high bias voltage for the forward body bias (FBB) consumes a significant amount of power and real estate on the chip. For relatively small system-on-chips (SoCs), the area and power impact of the additional circuitry and logic are significant. Circuit designers must strive to reduce the area and power impact. Summary of the Invention

[0005] In one embodiment, a circuit includes a digital circuit powered by a power domain having a positive supply voltage and a ground supply voltage, wherein the digital circuit includes a logic circuit formed by a plurality of logic gates, and each of the plurality of logic gates includes at least one p-channel MOSFET having an n-body connected to an n-body bias node and at least one n-channel MOSFET having a p-body connected to a p-body bias node; and a body bias generator circuit configured to apply an n-body bias voltage to the n-body bias node of the p-channel MOSFETs in the plurality of logic gates and to apply a p-body bias voltage to the p-body bias node of the n-channel MOSFETs in the plurality of logic gates, wherein the body bias generator circuit operates to: in a first mode, apply the ground supply voltage to the n-body bias node in the plurality of logic gates as the n-body bias voltage and apply the positive supply voltage to the p-body bias node in the plurality of logic gates as the p-body bias voltage; and in a second mode, apply the positive supply voltage to the n-body bias node in the plurality of logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias node in the plurality of logic gates as the p-body bias voltage.

[0006] In one embodiment, a circuit includes a digital circuit powered by a power domain having a positive supply voltage and a ground supply voltage, wherein the digital circuit includes a logic circuit formed by a plurality of logic gates, and each logic gate includes at least one p-channel MOSFET having an n-body connected to an n-body bias node and at least one n-channel MOSFET having a p-body connected to a p-body bias node; and a body bias generator circuit including: a first CMOS inverter circuit powered by a power domain having a positive supply voltage and a ground supply voltage, the first CMOS inverter circuit having an input configured to receive a first control signal and an output directly connected to the n-body bias node of the p-channel MOSFETs in the plurality of logic gates; and a second CMOS inverter circuit powered by a power domain having a positive supply voltage and a ground supply voltage, the second CMOS inverter circuit having an input configured to receive a second control signal and an output directly connected to the p-body bias node of the n-channel MOSFETs in the plurality of logic gates. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To better understand the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of a system-on-chip (SoC);

[0009] Figure 2A is a cross-section of a CMOS transistor implemented on a bulk substrate;

[0010] Figure 2B is a cross-section of a CMOS transistor implemented on a semiconductor-on-insulator (SOI) substrate;

[0011] Figure 3A is a circuit diagram of a switch body biasing circuit;

[0012] Figure 3B shows additional details of the body biasing configuration;

[0013] Figure 4A is a graph showing possible biasing operating conditions of NMOS and PMOS transistors implemented on a bulk substrate;

[0014] Figure 4B is a graph showing possible biasing operating conditions of NMOS and PMOS transistors implemented on a semiconductor-on-insulator (SOI) substrate; and

[0015] Figure 5 is a circuit diagram of an alternative embodiment of the switch body biasing circuit. DETAILED DESCRIPTION

[0016] Now referring to Figure 1 , Figure 1 shows a block diagram of a system-on-chip (SoC) 10, which includes digital circuitry 12 (also referred to as a digital core) designed to operate at ultra-low voltage levels. The digital circuitry 12 is powered by a voltage power domain that includes a supply voltage Vdd and a ground voltage Gnd. The voltage power domain is typically powered by a power supply (PS) circuit 13 (such as a voltage regulator and / or a power management circuit) present on the chip. The digital circuitry 12 includes logic circuitry 14 made up of complementary MOSFET (CMOS) devices (logic gates), and the CMOS devices form, for example, logic AND, NAND, OR, NOR, XOR, inverter circuits, and flip-flops (FFs). Figure 1 Only the inverter circuit is shown as an example in

[0017] The CMOS devices of logic circuit 14 include an n-channel MOSFET 20 (nMOS) and a p-channel MOSFET 24 (pMOS). The body of the n-channel MOSFET 20 is biased by a p-body bias voltage Vpb, and the body of the p-channel MOSFET 24 is biased by an n-body bias voltage Vnb. For a given biased power domain, all transistors are dynamically body-biased. The granularity of the bias conditions can be applied according to the power domain. On one hand, the core logic of a microprocessor in a first bias domain that requires speed in the active mode can be dynamically biased. On the other hand, the memory can be placed in a second domain with non-dynamic bias. In this case, the digital core will present two biased power domains with its own logic, but one biased power domain has a dynamic bias generator, while the second domain will be statically biased. The voltage level of the p-body bias voltage Vpb can be dynamically selected to configure the n-channel MOSFET 20 as a reverse body bias (RBB) or a forward body bias (FBB) according to the operating mode of the logic circuit 14. Similarly, the voltage level of the n-body bias voltage Vnb can be dynamically selected to configure the p-channel MOSFET 24 as a reverse body bias (RBB) or a forward body bias (FBB) according to the operating mode of the logic circuit 14.

[0018] The n-channel MOSFET 20 (nMOS) and the p-channel MOSFET 24 (pMOS) can be supported in a bulk substrate (see Figure 2A ) or a semiconductor-on-insulator (SOI) substrate (see Figure 2B ). For Figure 2A the bulk substrate implementation, the n-channel MOSFET 20 (nMOS) is formed in a p-well 22, and the p-channel MOSFET 24 (pMOS) is formed in an n-well 26. The p-well 22 provides the body of the n-channel MOSFET 20, and the n-well 26 provides the body of the p-channel MOSFET 24. Trench isolation 28 at the upper surface of the bulk substrate 30 isolates the pMOS devices from the nMOS devices to avoid parasitic currents. Source and drain regions 32 of n-type conductivity are provided in the p-well 22 of the n-channel MOSFET 20. The source and drain regions 32 are separated by a channel region, and an insulating gate 34 is provided above the channel region. A p-type doped contact region 36 is provided in the p-well 22 for applying the p-body bias voltage Vpb to the body of the n-channel MOSFET 20. Source and drain regions 42 of p-type conductivity are provided in the n-well 26 of the p-channel MOSFET 24. The source and drain regions 42 are separated by a channel region, and an insulating gate 44 is provided above the channel region. An n-type doped contact region 46 is provided in the n-well 26 for applying the n-body bias voltage Vnb to the body of the p-channel MOSFET 24 (pMOS).

[0019] For Figure 2B the SOI substrate implementation, an n-channel MOSFET 20 (nMOS) is formed in a first region 52 of a semiconductor layer (e.g., fully depleted - FDSOI) supported by an insulating layer 54 over a support substrate 56. A p-channel MOSFET 24 (pMOS) is formed in a second region 58 of the semiconductor layer. A trench isolation 60 at the upper surface of the semiconductor layer isolates region 52 from region 58. In region 52 of the n-channel MOSFET 20, source and drain regions 62 of n-type conductivity are provided. The source and drain regions 62 are separated by a channel region, and an insulating gate 64 is provided over the channel region. In region 58 of the p-channel MOSFET 24, source and drain regions 72 of p-type conductivity are provided. The source and drain regions 72 are separated by a channel region, and an insulating gate 74 is provided over the channel region.

[0020] Within the support substrate 56, a p-well 82 is provided beneath the n-channel MOSFET 20 (nMOS), where the p-well 82 is isolated from region 52 of the semiconductor layer by the insulating layer 54. The p-well 82 provides the body (also referred to as the back gate in the art) of the n-channel MOSFET 20. The p-well 82 includes a depressed region 82s extending from the upper surface of the SOI substrate. A p-type doped contact region 84 is provided in the depressed region 82s for applying a p-body bias voltage Vpb to the body of the n-channel MOSFET 20.

[0021] Within the support substrate 56, an n-well 86 is provided beneath the p-channel MOSFET 24 (pMOS), where the n-well 86 is isolated from region 58 of the semiconductor layer by the insulating layer 54. The n-well 86 provides the body (also referred to as the back gate in the art) of the p-channel MOSFET 24. The n-well 86 includes a depressed region 86s extending from the upper surface of the SOI substrate. An n-type doped contact region 88 is provided in the depressed region 86s for applying an n-body bias voltage Vnb to the body of the p-channel MOSFET 24.

[0022] Referring again to Figure 1 , the body bias generator circuit 16 generates a p-body bias voltage Vpb and an n-body bias voltage Vnb in response to a control signal CTRL. The logic state of the control signal CTRL can indicate, for example, whether reverse body bias (RBB) or forward body bias (FBB) is to be applied to the transistors of the logic circuit 14. In one embodiment, the logic state of the control signal CTRL can depend on the operating mode (normal mode or sleep mode) of the digital circuit 12 (digital core), where the operating mode can be controlled by a power supply (PS) circuit 13 or other SoC configuration circuits.

[0023] Now refer to Figure 3A , Figure 3A which shows a circuit diagram of the body bias generator circuit 16. The body bias generator circuit 16 includes a first CMOS inverter circuit 16a having an input configured to receive a control signal CTRL and an output configured to generate an n-body bias voltage Vnb. The first CMOS inverter circuit 16a is powered by a voltage power domain including a power supply voltage Vdd and a ground voltage Gnd. If the control signal CTRL has a logic "1" state that configures the body bias generator circuit 16 to a first operating mode, the first CMOS inverter circuit 16a will apply a relatively low voltage (such as the ground voltage Gnd) as the n-body bias voltage Vnb (i.e., Vnb = Gnd). Conversely, if the control signal CTRL has a logic "0" state that configures the body bias generator circuit 16 to a second operating mode, the first CMOS inverter circuit 16a will apply a relatively high voltage (such as the power supply voltage Vdd) as the n-body bias voltage Vnb (i.e., Vnb = Vdd).

[0024] The body bias generator circuit 16 further includes a second CMOS inverter circuit 16b having an input configured to receive a logical inversion of the control signal CTRL (i.e.,!CTRL) (e.g., generated by an inverter 16c) and an output configured to generate a p-body bias voltage Vpb. The second CMOS inverter circuit 16b is also powered by a voltage power domain including a power supply voltage Vdd and a ground voltage Gnd. If the control signal CTRL has a logic "1" state that configures the body bias generator circuit 16 to a first operating mode (i.e.,!CTRL = 0), the second CMOS inverter circuit 16b will apply the power supply voltage Vdd as the p-body bias voltage Vpb (i.e., Vpb = Vdd). Conversely, if the control signal CTRL has a logic "0" state that configures the body bias generator circuit 16 to a second operating mode (i.e.,!CTRL = 1), the second CMOS inverter circuit 16b will apply the ground voltage Gnd as the p-body bias voltage Vpb (i.e., Vpb = Gnd).

[0025] Figure 3BAdditional details are shown. The logic circuit 14 includes, for example, a plurality of logic gates 100, where each logic gate 100 includes at least one p-channel transistor 102 and at least one n-channel transistor 104. The logic gates can be, for example, a logic AND gate, a logic NAND gate, a logic OR gate, a logic NOR gate, a logic XOR gate, or a logic inverter gate. The output of the inverter 16a of the body bias generator 16 that generates the n-body bias voltage Vnb in response to the logic state of the control signal CTRL is connected to the bodies of the p-channel transistors 102 within the plurality of logic gates 100. Thus, a single inverter 16a is provided to dynamically body bias the p-channel transistors 102 within the plurality of logic gates 100. Similarly, the output of the inverter 16b of the body bias generator 16 that generates the p-body bias voltage Vpb in response to the logic state of the control signal!CTRL is connected to the bodies of the n-channel transistors 102 within the plurality of logic gates 100. Thus, a single inverter 16b is provided to dynamically body bias the n-channel transistors 104 within the plurality of logic gates 100.

[0026] Figure 3A The inverter 16c in shows an implementation where the control signals CTRL and!CTRL are logical inverses of each other. However, this is not necessary. It should be understood that the logic state of the control signal CTRL can be generated in a manner that is completely independent of the logic state of the control signal!CTRL.

[0027] Now referring to Figure 4A , Figure 4A it is shown that the available range of forward body biasing is limited. For CMOS transistors implemented on a bulk substrate, the diodes between the source of the NMOS transistor and the p-well and between the drain of the PMOS transistor and the n-well will limit the benefits of FBB. In fact, beyond the threshold voltages Von1 of the NMOS transistor diode and Von2 of the PMOS transistor (commonly defined as approximately 0.6V, but technology dependent), leakage current will occur and increase the power consumption of the system. Thus, the amount of the biases Vpb and Vnb is limited to Vlimit (approximately 0.6V). However, for ultra-low voltage levels, if Vbn and Vpb are limited within the range of 0V to Vdd and Vdd < Von1 (and Von2), then this condition will never be met. This justifies the implementation of a bulk substrate circuit.

[0028] Now referring to Figure 4B , Figure 4BIt is shown that the available range of the forward body bias is limited. For CMOS transistors implemented on a silicon-on-insulator (SOI) substrate, the diode between the p-well and the n-well will limit the benefits of the FBB. In fact, beyond the threshold voltage Vpn of the well diode, leakage current will appear and increase the power consumption of the system. In this case, Vpn is defined by Vnb and Vpb (Vpn = Vpb = Vnb). When Vpn is about 0.6V, assuming symmetric voltages on the n- and p-wells, for the possible bias range, it results in the limit Vlimit = Vdd / 2 + 300mV. However, for ultra-low voltage levels, Vpn will never satisfy this condition. This justifies the implementation of SOI substrate circuits.

[0029] Now refer to Figure 5Let's discuss an alternative implementation of the body bias generator circuit 16. In this embodiment, the logical inverse relationship between the signals CTRL and!CTRL is decoupled to support two additional operating modes. The inverter 16c is omitted, and instead, a control logic circuit 16d is used to independently generate the signals CTRL and!CTRL. Four operating modes are possible: a) The first operating mode, in which the control signal CTRL has a logical "1" state and the control signal!CTRL has a logical "0" state, such that the first CMOS inverter circuit 16a applies the ground voltage Gnd as the n-body bias voltage Vnb (i.e., Vnb = Gnd) and the second CMOS inverter circuit 16b applies the supply voltage Vdd as the p-body bias voltage Vpb (i.e., Vpb = Vdd); b) The second operating mode, in which the control signal CTRL has a logical "0" state and the control signal!CTRL has a logical "1" state, such that the first CMOS inverter circuit 16a applies the supply voltage Vdd as the n-body bias voltage Vnb (i.e., Vnb = Vdd) and the second CMOS inverter circuit 16b applies the ground voltage Gnd as the p-body bias voltage Vpb (i.e., Vpb = Gnd); c) The third operating mode, in which the control signal CTRL has a logical "1" state and the control signal!CTRL also has a logical "1" state, such that both the first CMOS inverter circuit 16a and the second CMOS inverter circuit 16b apply the ground voltage Gnd as the n-body bias voltage Vnb (i.e., Vnb = Gnd) and the p-body bias voltage Vpb (i.e., Vpb = Gnd) respectively (here called the super forward body bias mode: on the one hand, this super forward body bias mode covers other FD-SOI technologies, where the normal operating bias condition is Vpb = Vnb = Gnd; on the other hand, this super forward body bias mode can be used to asymmetrically apply body bias on the pMOS or nMOS network to cover potential PVT variations); d) The fourth operating mode, in which the control signal CTRL has a logical "0" state and the control signal!CTRL also has a logical "0" state, such that both the first CMOS inverter circuit 16a and the second CMOS inverter circuit 16b apply the supply voltage Vdd as the n-body bias voltage Vnb (i.e., Vnb = Vdd) and the p-body bias voltage Vpb (i.e., Vpb = Vdd) respectively (here called the super reverse body bias mode: on the one hand, this super reverse body bias mode covers other FD-SOI technologies, where the normal operating bias condition is Vpb = Vnb = Vdd; on the other hand, this super reverse body bias mode can be used to asymmetrically apply body bias on the pMOS or nMOS network to cover potential PVT variations). The logic circuit 16d is controlled by the mode selection signal MODE to select one of the four possible operating modes.

[0030] The foregoing applies to Figure 3B the circuit implementation shown

[0031] Although the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. An electronic circuit, comprising: A digital circuit powered by a power domain having a positive power supply voltage and a ground power supply voltage, wherein the digital circuit includes a logic circuit formed by a plurality of logic gates, and each of the plurality of logic gates includes at least one p-channel MOSFET and at least one n-channel MOSFET, the at least one p-channel MOSFET having an n-body connected to an n-body bias node, and the at least one n-channel MOSFET having a p-body connected to a p-body bias node; And A body bias generator circuit configured to apply an n-body bias voltage to the n-body bias node of the p-channel MOSFETs in the plurality of logic gates and apply a p-body bias voltage to the p-body bias node of the n-channel MOSFETs in the plurality of logic gates, wherein the body bias generator circuit operates to: In a first mode, apply the ground power supply voltage to the n-body bias node in the plurality of logic gates as the n-body bias voltage and apply the positive power supply voltage to the p-body bias node in the plurality of logic gates as the p-body bias voltage; And In a second mode, apply the positive power supply voltage to the n-body bias node in the plurality of logic gates as the n-body bias voltage and apply the ground power supply voltage to the p-body bias node in the plurality of logic gates as the p-body bias voltage.

2. The electronic circuit according to claim 1, wherein the mode of the body bias generator circuit is selected by the logic state of a control signal.

3. The electronic circuit according to claim 2, wherein the body bias generator circuit includes: A first CMOS inverter circuit powered by the power domain having the positive power supply voltage and the ground power supply voltage, the first CMOS inverter circuit having an input configured to receive the control signal and an output directly connected to the n-body bias node of the p-channel MOSFETs in the plurality of logic gates; And A second CMOS inverter circuit powered by the power domain having the positive power supply voltage and the ground power supply voltage, the second CMOS inverter circuit having an input that receives a logical inversion of the control signal and an output directly connected to the p-body bias node of the n-channel MOSFETs in the plurality of logic gates.

4. The electronic circuit according to claim 2, wherein the logic state of the control signal indicates whether the digital circuit is in a paused operation mode.

5. The electronic circuit according to claim 1, wherein each p-channel MOSFET is formed in an n-well of a body substrate, and the n-well forms the n-body biased by the n-body bias voltage; and wherein each n-channel MOSFET is formed in a p-well of the body substrate, and the p-well forms the p-body biased by the p-body bias voltage.

6. The electronic circuit according to claim 1, Each of the p-channel MOSFETs is formed in a first semiconductor region of a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate including a support substrate insulated from the first semiconductor region by an insulating layer, the support substrate including an n-well forming the n-body biased by the n-body bias voltage; and Each of the n-channel MOSFETs is formed in a second semiconductor region of the semiconductor-on-insulator substrate, wherein the support substrate is insulated from the first semiconductor region by an insulating layer, the support substrate including a p-well forming the p-body biased by the p-body bias voltage.

7. The electronic circuit according to claim 1, wherein the body bias generator circuit is further operative to: In a third mode, apply the ground supply voltage to the n-body bias node in the plurality of logic gates as the n-body bias voltage and to the p-body bias node in the plurality of logic gates as the n-body bias voltage.

8. The electronic circuit according to claim 7, wherein in response to a control signal, a selection is made among the first mode, the second mode, and the third mode of the body bias generator circuit.

9. The electronic circuit according to claim 1, wherein the body bias generator circuit is further operative to: In a fourth mode, apply the positive supply voltage to the n-body bias node in the plurality of logic gates as the n-body bias voltage and to the p-body bias node in the plurality of logic gates as the n-body bias voltage.

10. The electronic circuit according to claim 9, wherein in response to a control signal, a selection is made among the first mode, the second mode, and the fourth mode of the body bias generator circuit.

11. An electronic circuit, comprising: A digital circuit powered by a power domain having a positive supply voltage and a ground supply voltage, wherein the digital circuit includes a logic circuit formed by a plurality of logic gates, each logic gate including at least one p-channel MOSFET and at least one n-channel MOSFET, the at least one p-channel MOSFET having an n-body connected to an n-body bias node, the at least one n-channel MOSFET having a p-body connected to a p-body bias node; And A body bias generator circuit, comprising: A first CMOS inverter circuit powered by the power domain having the positive supply voltage and the ground supply voltage, the first CMOS inverter circuit having an input configured to receive a first control signal and an output directly connected to the n-body bias node of the p-channel MOSFETs in the plurality of logic gates; And A second CMOS inverter circuit powered by the power domain having the positive supply voltage and the ground supply voltage, the second CMOS inverter circuit having an input configured to receive a second control signal and an output directly connected to the p-body bias node of the n-channel MOSFETs in the plurality of logic gates.

12. The electronic circuit according to claim 11, wherein the second control signal is a logical inversion of the first control signal.

13. The electronic circuit according to claim 11, wherein the first control signal and the second control signal have logical states that are not mutually dependent.

14. The electronic circuit according to claim 11, wherein the logic circuit is configured to generate the first control signal and the second control signal, and the logic circuit operates to control the body bias generator circuit to operate to: In a first mode, apply the ground supply voltage to the n body bias node among the plurality of logic gates as the n body bias voltage, and apply the positive supply voltage to the p body bias node among the plurality of logic gates as the p body bias voltage; and In a second mode, apply the positive supply voltage to the n body bias node among the plurality of logic gates as the n body bias voltage, and apply the ground supply voltage to the p body bias node among the plurality of logic gates as the p body bias voltage.

15. The electronic circuit according to claim 14, wherein the mode of the body bias generator circuit is selected by a mode selection signal.

16. The electronic circuit according to claim 15, wherein the mode selection signal indicates whether the digital circuit is in a paused operation mode.

17. The electronic circuit according to claim 14, wherein the logic circuit further operates to control the body bias generator circuit to operate to: In a third mode, apply the ground supply voltage to the n body bias node among the plurality of logic gates as the n body bias voltage and apply it to the p body bias node among the plurality of logic gates as the n body bias voltage.

18. The electronic circuit according to claim 17, wherein in response to the mode selection signal, a selection is made among the first mode, the second mode, and the third mode of the body bias generator circuit.

19. The electronic circuit according to claim 14, wherein the logic circuit further operates to control the body bias generator circuit to operate to: In a fourth mode, apply the positive supply voltage to the n body bias node among the plurality of logic gates as the n body bias voltage and apply it to the p body bias node among the plurality of logic gates as the n body bias voltage.

20. The electronic circuit according to claim 19, wherein in response to the mode selection signal, a selection is made among the first mode, the second mode, and the fourth mode of the body bias generator circuit.

21. The electronic circuit according to claim 11, wherein each p-channel MOSFET is formed in an n-well of a body substrate, and the n-well forms an n body biased by an n body bias voltage; and wherein each n-channel MOSFET is formed in a p-well of the body substrate, and the p-well forms a p body biased by a p body bias voltage.

22. The electronic circuit according to claim 11, Each of the p-channel MOSFETs is formed in a first semiconductor region of a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate including a support substrate insulated from the first semiconductor region by an insulating layer, the support substrate including an n-well forming an n-body biased by an n-body bias voltage; and Each of the n-channel MOSFETs is formed in a second semiconductor region of the semiconductor-on-insulator substrate, wherein the support substrate is insulated from the first semiconductor region by an insulating layer, the support substrate including a p-well forming a p-body biased by a p-body bias voltage.

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