Semiconductor devices with SiC semiconductor body and methods for manufacturing semiconductor devices

Abstract

This invention relates to semiconductor devices having a SiC semiconductor body and methods for manufacturing semiconductor devices. The invention provides a silicon carbide substrate (700) having a trench (750) extending from a main surface (701) of the silicon carbide substrate (700) into the substrate and having a trench width (wg) at the bottom (751). A shielding region (140) is constructed in the silicon carbide substrate (700), wherein the shielding region (140) extends along the bottom (751) of the trench. In at least one dopant plane (105) extending substantially parallel to the bottom (751) of the trench, the dopant concentration in the shielding region (140) at a first transverse width (w1) deviates from the maximum value of the dopant concentration by no more than 10%. The first width (w1) is less than the trench width (wg) and is at least 30% of the trench width (wg).

Description

Technical Field

[0001] The present invention relates to semiconductor devices having a SiC semiconductor body, particularly semiconductor switches having low on-resistance and high voltage resistance, and methods for manufacturing semiconductor devices. Background Technology

[0002] Power semiconductor devices carry relatively high load currents under high breakdown strength. In vertically structured power semiconductor devices, the load current flows between two opposing main surfaces of the semiconductor body, where the current carrying capacity can be adjusted by the breakdown voltage across the horizontal range of the semiconductor body and the vertical range of the drift region constructed within the semiconductor body. In power semiconductor switches, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate Bipolar Transistors), the gate electrode is capacitively coupled to the body region via the gate dielectric and switches the load current, for example, through an inversion channel temporarily formed in the body region. In semiconductor bodies made of materials with inherently high breakdown field strength, such as silicon carbide (SiC), the gate dielectric is subjected to a strong electric field in the off-state, allowing the breakdown strength of the gate dielectric to be specified. The breakdown voltage of the semiconductor switch can be adjusted up to this breakdown voltage by the vertical range of the drift region.

[0003] The usual goal is to further improve the breakdown strength of semiconductor devices without sacrificing on-resistance. Summary of the Invention

[0004] This disclosure relates to a method for manufacturing a semiconductor device. A silicon carbide substrate is provided, wherein the silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate and having a trench width at the bottom of the trench. A shielding region is constructed in the silicon carbide substrate, wherein the shielding region extends along the bottom of the trench. In at least one dopant plane extending substantially parallel to the bottom of the trench, the dopant concentration in the shielding region over a first transverse width deviates from the maximum value of the dopant concentration in the shielding region within the dopant plane by no more than 10%. The first width is less than the trench width and is at least 30% of the trench width.

[0005] This disclosure also relates to semiconductor devices that may include a SiC semiconductor body and a gate electrode structure. The gate electrode structure may extend from a first surface of the SiC semiconductor body into the SiC semiconductor body and may have a conductive connection structure. At the bottom, the gate electrode structure has a structural width. In the SiC semiconductor body, a shielding region may be constructed along the bottom. The conductive connection structure and the shielding region may form a contact. The shielding region may have a central segment of a first width. Within at least one dopant plane extending approximately parallel to the bottom, the dopant concentration in the central segment of the shielding region deviates from the maximum dopant concentration in the shielding region within the dopant plane by no more than 10%. The central segment of the shielding region has a first width that is less than the structural width and is at least 30% of the structural width.

[0006] Those skilled in the art will perceive other features and advantages of the disclosed subject matter based on the following detailed description and accompanying drawings. Attached Figure Description

[0007] The accompanying drawings facilitate a deeper understanding of embodiments of the semiconductor devices and embodiments of methods for manufacturing the semiconductor devices. Figure 1 This information is included within and constitutes a part of this disclosure. The accompanying drawings illustrate only embodiments and, together with the description, explain the principles of the embodiments. The semiconductor devices and methods described herein are therefore not limited to the descriptions of these embodiments. Other embodiments and anticipated advantages arise from understanding the following detailed description and combinations of embodiments described below, even if these combinations are not explicitly described. The elements and structures shown in the drawings are not necessarily shown strictly to scale. The same reference numerals denote the same or corresponding elements and structures.

[0008] Figure 1 This is a simplified schematic flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment.

[0009] Figure 2A-2D The diagram schematically illustrates a vertical cross-sectional view of a silicon carbide substrate and the lateral dopant distribution in the shielding region of the dopant plane to illustrate a method for fabricating a SiC semiconductor device according to one embodiment.

[0010] Figure 3A-3L A schematic vertical cross-sectional view of a silicon carbide substrate is shown to illustrate a method according to one embodiment, wherein dopant atoms for constructing a shielding region are introduced into the gate trench using an injection mask.

[0011] Figures 4A-4B A schematic vertical cross-sectional view of a silicon carbide substrate is shown to illustrate a method according to one embodiment, wherein dopant atoms for constructing the shielding region and JFET sub-region are introduced into the gate trench using an injection mask.

[0012] Figures 5A-5B The horizontal and vertical cross-sections of a SiC semiconductor device according to another embodiment are shown.

[0013] Figure 6-8 Vertical cross-sections of SiC semiconductor devices according to other embodiments are shown respectively.

[0014] Figures 9A-9B The electric field in a SiC semiconductor device according to one embodiment and the electric field in a comparative device are illustrated by means of a vertical cross-section. Detailed Implementation

[0015] Referring in the following detailed description to the accompanying drawings, which form part of this disclosure, specific embodiments of semiconductor devices and methods for manufacturing semiconductor devices are illustrated for illustrative purposes. It will be understood that other embodiments exist. It will also be understood that structural and / or logical changes may be made to the embodiments without departing from the scope of the claims. In this respect, the description of the embodiments is non-limiting. In particular, unless the context otherwise requires, features of the embodiments described below may be combined with features of other embodiments described in the description.

[0016] The terms “have,” “comprise,” “include,” “have,” and similar terms are open-ended terms in this context, indicating, on the one hand, the presence of the stated element or feature, but not excluding the presence of other elements or features. Unless the context clearly indicates otherwise, both indefinite and definite articles include both plural and singular forms.

[0017] The safe operating area (SOA) defines the environment and operating conditions under which reliable operation of a semiconductor device can be expected. Typically, the SOA is defined by specifying the maximum values ​​of the environment and operating conditions listed in the semiconductor device datasheet, such as maximum continuous load current, maximum pulsed load current, maximum gate voltage, and maximum reverse voltage.

[0018] The term or expression “electrical connection” describes a low-resistance connection between electrically connected elements, such as direct contact between related elements or a connection via a metal and / or heavily doped semiconductor. The term “electrical coupling” includes one or more elements located between “electrically coupled” elements and suitable for signal transmission, such as elements that are controllable such that the elements can temporarily establish a low-resistance connection in a first state and produce a high-resistance decoupling in a second state.

[0019] In the following text, the expression "forming a contact" should be understood as meaning that, during the operation of a semiconductor device within an SOA, at least one charge carrier can flow from one structure to the other between two structures that form a contact. In other words, a contact exists between two structures. Typically, the structures are directly adjacent to each other. The following region is also referred to as the "contact region": the region in which the structures form a contact, for example, being adjacent to each other.

[0020] An ohmic contact represents, for example, a transition between two structures that has low resistance and no rectification. For instance, an ohmic contact can be formed between a metallic structure and a sufficiently highly doped semiconductor material. An ohmic contact region refers to the contact area, such as the contact surface of an ohmic contact.

[0021] As a Schottky contact, hereinafter referred to as a rectifying transition between a semiconductor material and a metal structure, wherein, for example, the doping of the semiconductor material and the work function of the metal structure are selected such that a depletion region is formed in the semiconductor material under conditions of interface equilibrium. The Schottky contact region refers to the contact region, such as the contact surface of a Schottky contact.

[0022] In addition to the dopant type, some figures also indicate the relative dopant concentration using "-" or "+" symbols. For example, the designation "n-" indicates a dopant concentration lower than that of the "n" doped region, while the "n+" doped region has a higher dopant concentration than the "n" doped region. Unless otherwise stated, the description of relative dopant concentration does not imply that doped regions with the same relative dopant concentration description must have the same absolute dopant concentration. Therefore, two different "n" doped regions can have the same or different absolute dopant concentrations.

[0023] If a physical parameter is specified with a range of values ​​having one or two limit values, then the terms "from" and "to" or "less than" and "greater than" together include the corresponding limit values. Therefore, a specification of the type "from...to" is understood as "from at least...to at most". Correspondingly, a specification of the type "less than..." ("greater than...") is understood as "at most..." ("at least...").

[0024] The abbreviation IGFET (Insulated Gate Field Effect Transistor) refers to a voltage-controlled semiconductor switch, and in addition to MOSFET (Metal-Oxide-Semiconductor FET), it also includes FETs whose gate electrode has a doped semiconductor material and / or whose gate dielectric does not have oxide or is composed of more than just oxide.

[0025] Two adjacent doped regions with the same doping type (conductivity type) but different dopant concentrations form a unipolar junction along a transition surface, such as an n / n+ or p / p+ junction. At the unipolar junction, the dopant distribution perpendicular to the junction extension has a step or inflection point, where the dopant distribution changes from a concave curve to a convex curve or vice versa.

[0026] One embodiment relates to a method for manufacturing a semiconductor device. The method may include providing a silicon carbide substrate having trenches extending from a main surface of the silicon carbide substrate into the substrate and having a trench width at the bottom of the trenches. Shielding regions may be constructed within the silicon carbide substrate, wherein the shielding regions may extend along the bottom of the trenches.

[0027] The statement that the shielding area “extends” along the bottom of the trench does not limit the primary direction of extension of the shielding area. More precisely, this can be interpreted as: the shielding area extends along the bottom of the trench and / or the total lateral width of the shielding area corresponds to at least 80% of the trench width. The primary direction of extension of the shielding area can be vertical. For example, the shielding area can extend vertically through a large portion, such as at least 60%, of the drift region of the semiconductor device to be manufactured.

[0028] Within at least one dopant plane extending generally parallel to the bottom of the trench, the deviation of the dopant concentration within the shielding region over a first transverse width from the maximum dopant concentration within the shielding region in the dopant plane shall not exceed ±10%. Typically, the deviation of the dopant concentration within the shielding region over the first transverse width from the maximum dopant concentration within the shielding region in the dopant plane shall not exceed ±5% or ±1%. In other words, at least one horizontal dopant distribution within the shielding region has a mesa of a first width, wherein within the mesa, the dopant concentration fluctuates by a maximum of ±10%, for example, a maximum fluctuation of ±5% or ±1%. The region of the shielding region over the first transverse width may be a central segment of the shielding region.

[0029] The bottom of the trench may have a flat section in the bottom plane. The bottom plane may extend parallel to the main surface or the bottom plane and the main surface may form an angle between 0° and 10°, such as an angle between 0° and 5°. The dopant plane may extend parallel to the bottom plane, or the bottom plane and the dopant plane may form an angle between 0° and 10°, such as an angle between 0° and 5°.

[0030] The first width can be smaller than the trench width, for example, at least 50 nm or at least 150 nm smaller and / or at least 2% or at least 5% smaller than the trench width. For example, the first width can be at most 99%, at most 95%, or at most 90% of the trench width. The first width can be at least 30% of the trench width.

[0031] Outside the central section, the dopant concentration within the shielded region can decrease sharply in the lateral direction, preventing or limiting the lateral protrusion of the shielded region beyond the gate electrode structure. For example, the total lateral width of the shielded region deviates from the trench width by at most ±20% or at most ±10%. The shielded region does not reduce or only slightly reduces the cross-section of the current distribution region, which can laterally adjoin the gate electrode structure.

[0032] According to one embodiment, the dopant plane can connect the laterally adjacent local maxima of the vertical dopant distribution in the shielding region. The distance between the trench bottom and the dopant plane can here correspond to the penetration depth of the dopant atoms into the silicon carbide substrate, where the penetration depth (projected range) depends on the kinetic energy of the dopant atoms and describes the average range of action of the dopant atoms from the irradiated surface. For example, this distance can be in the range of 20 nm to 500 nm, typically in the range of 50 nm to 300 nm.

[0033] According to this embodiment, for example, the maximum dopant concentration in the shielding region that extends beyond the first transverse width can have a dopant mesa in which the dopant concentration fluctuates by up to ±10% of the maximum value in the shielding region, for example, up to ±5% or ±1%.

[0034] According to one embodiment, a field dielectric can be constructed in a trench, wherein the field dielectric at the bottom of the trench has an opening with a second lateral width. The second width may be smaller than the first width. The first and second widths may be defined along the same lateral direction.

[0035] The edge of the field dielectric facing the opening can be completely shielded by at least a portion of the central section of the shielded region. Therefore, the potential of the field dielectric section facing the opening can be effectively shielded relative to the back electrode. High electric field strength in the section of the field dielectric directly adjacent to the opening can be avoided.

[0036] According to one embodiment, the field dielectric along the sidewall of the trench may have a sidewall section having a first layer thickness th1, and the opening may have a second width w2, to which the following can be applied:

[0037] w2 < (wg - 2 * th1),

[0038] Where wg equals the trench width. In other words, the second width is less than twice the difference between the trench width and the first layer thickness. This allows the edge of the field dielectric facing the opening to be effectively shielded by the following section of the shielding region, where the dopant concentration does not decrease.

[0039] The sidewall sections of the field dielectric can extend to the bottom of the trench. Therefore, a portion of the sidewall section can cover and / or terminate at the bottom of the trench. The field dielectric can have two, for example, identically constructed sidewall sections, each extending along the sidewall of the field dielectric.

[0040] Possibly, the bottom segment of the field dielectric extends laterally along the bottom of the trench, starting from a sidewall segment. The bottom segment can be associated with, i.e., directly connected to, the sidewall segments. In the case of multiple sidewall segments, the bottom segment can be associated with each sidewall segment, wherein the bottom segment extends along the bottom of the trench from the associated sidewall segment. The field dielectric can have, for example, two sidewall segments and two bottom segments.

[0041] The sidewall section, together with its associated bottom section, can form an L-shape. The portion of the field dielectric extending along the bottom of the trench can be formed by the portions of the bottom section and the sidewall section covering the bottom of the trench. The bottom section can be arranged between the sidewall section and the opening in the bottom of the trench. For example, the distance between the opening and the sidewall section can be bridged by the bottom section.

[0042] The bottom section may have a transverse bottom width along the bottom of the trench. Perpendicular to the bottom width, the bottom section may have a second layer thickness. The bottom width may at least partially, and particularly completely, compensate for the difference between the second width of the opening and twice the trench width and the first layer thickness. The bottom width may correspond to half the difference between the trench width and the second width minus the first layer thickness.

[0043] wb = 1 / 2 * (wg - w2) - th1,

[0044] Where wb is the bottom width of the bottom segment. In other words, the sum of the bottom width and the first layer thickness can correspond to half the difference between the trench width and the second width.

[0045] The corresponding factor 2 and the opposite factor 1 / 2 in the above relationship between the trench width, the second width, the first layer thickness and (optionally) the bottom width can be based on the fact that the field dielectric can have two sidewall sections, wherein the sidewall sections can be constructed at opposite sidewalls of the trench.

[0046] The two sidewall sections of a trench can be constructed differently. Regardless of the number of sidewall sections in a trench, the sidewall sections of different trenches can be constructed differently, wherein if a trench has multiple sidewall sections, the sidewall sections of the trench can be constructed in the same or different ways.

[0047] For example, the two sidewall sections can have different first layer thicknesses, wherein for each first layer thickness, the above relationship of the difference between the trench width and the second width can be satisfied independently.

[0048] Each sidewall segment can be associated with a bottom segment. The bottom segments of different sidewall segments can have different or the same bottom width. In the first case, it is possible that the first layer thickness of the sidewall segment remains constant, as does the sum of the bottom widths of the bottom segments associated with the sidewall segments for different sidewall segments (and therefore different bottom segments). Thus, a thicker sidewall segment can be compensated for, for example, by a narrower bottom segment, and vice versa. In the second case, where different bottom segments have the same bottom width, it is possible that the first layer thickness of the sidewall segment is different from the sum of the bottom widths of the bottom segments associated with the sidewall segments for different sidewall segments. For example, in this case, the opening is not centered relative to the trench.

[0049] The central segment of the shielding region, with a uniformly high dopant concentration, can extend laterally beyond the opening in the field dielectric. The edge of the field dielectric facing the opening can be completely covered by the central segment of the shielding region. This effectively shields the conductive structure adjacent to the shielding region in the opening region of the field dielectric, as well as the edge between the shielding region and the field dielectric. The central segment of the shielding region can reduce the maximum electric field strength in the field dielectric and / or the probability of field dielectric breakdown.

[0050] According to one embodiment, constructing a shielding region may include constructing an injection mask, wherein the injection mask is constructed thinner at the bottom of the trench than at the sidewalls of the trench, and wherein dopant atoms are introduced through the bottom of the trench and / or through the injection mask at the bottom of the trench.

[0051] For example, constructing an injection mask can include thermal growth of oxides, where the thermal oxides grow at a slower rate at the bottom of the trench than at the sidewalls. The shielding region can be constructed without additional photolithography processes.

[0052] When dopant atoms are introduced into a shielded region, an implantation mask can largely prevent the dopant atoms from spreading through the trench sidewalls. For example, such dopant atoms spread into the bulk region can affect the threshold voltage used to form an inversion channel in the bulk region. Dopant atoms spread into the current distribution region can increase the resistance of the current distribution region, thereby increasing the on-resistance of the semiconductor device. An implantation mask can prevent dopant atoms from being loaded into such doped regions where the amount and precise positioning of the dopant atoms are subjected to large fluctuations in the silicon carbide substrate. The first width in the shielded region can also be precisely adjusted by the implantation mask, for example, in conjunction with the implantation energy used.

[0053] According to one embodiment, constructing the shielding region may include constructing an implantation mask, wherein the implantation mask at the bottom of the trench may have an implantation mask opening of a third width, and dopant atoms may be introduced through the implantation mask opening. The third width is greater than a first width, wherein the first width may be precisely adjusted by the third width and the implantation process parameters.

[0054] Introducing dopant atoms can include one or more ion implantation processes, wherein each ion implantation process can include multiple implantations at different implantation angles and with the same acceleration energy, and wherein the ion implantation processes differ with respect to the acceleration energy used. Each implantation process can include implantations at at least two different implantation angles, which may be symmetrical about the midplane of the trench.

[0055] According to one embodiment (in which the local maximum value of the laterally adjacent vertical dopant distribution in the dopant plane connected to the shielding region), it is possible that the deviation between the first width and the third width and twice the average distance from the dopant plane to the bottom of the trench does not exceed ±10%. The average distance between the bottom of the trench and the dopant plane can correspond to the average penetration depth of dopant ions during ion implantation. By using the third width and the penetration depth, the lateral extent of the first width and thus the uniformly and heavily doped central segment of the shielding region below the bottom of the trench can be precisely adjusted, and adjusted for the opening in the field dielectric.

[0056] According to one embodiment, constructing an injection mask may include constructing an injection mask layer on the sidewalls and at the bottom of the trench and removing a segment of the injection mask layer at the bottom of the trench, wherein the remaining segment of the injection mask layer may form an injection mask.

[0057] Constructing an implantation mask can, in particular, include anisotropic etching of a conformal implantation mask layer, where a first width can be precisely adjusted via the layer thickness of the conformal implantation mask layer and the width of the trenches. A conformal layer covers a structured underlying layer with a uniform layer thickness that is largely independent of the orientation of the sub-segments of the underlying layer. The layer thickness of the conformal layer can have slight fluctuations, which are small relative to the average layer thickness (e.g., at most ±10% of the average layer thickness). Conformal layers can be constructed, for example, by thin-film deposition methods such as CVD (chemical vapor deposition).

[0058] According to one implementation, the introduction of dopant atoms may include injection at at least two different acceleration energies, wherein the width of the injection mask opening may be varied between these injections.

[0059] In particular, when the width of the injection mask opening is small, injection can be performed with higher acceleration energy, and when the width of the injection mask opening is large, injection can be performed with lower acceleration energy.

[0060] Higher acceleration energy injection can construct vertically extended JFET (Junction Field-Effect Transistor) structures. Lower acceleration energy injection can be designed to ensure sufficient distance between the opening of the field dielectric and the lateral outer edge of the shielding region.

[0061] According to one embodiment, the injection mask can be removed before constructing the field dielectric. The field dielectric and the injection mask can be constructed independently of each other and selected according to the respective requirements.

[0062] According to one embodiment, constructing a field dielectric may include constructing a field dielectric layer, wherein the field dielectric layer padded with trenches and a section of the field dielectric layer at the bottom of the trenches is removed.

[0063] According to one embodiment, removing a section of the field dielectric layer may include constructing an etch mask on the field dielectric layer, wherein the etch mask at the bottom of the trench may have an etch mask opening of a second width. The second width can be precisely adjusted by the layer thickness of the etch mask.

[0064] For example, the etching mask can be a layer, particularly a conformal layer, that covers, for example, completely covers the sidewall sections of the field dielectric and the bottom section of the field dielectric to be generated at the bottom of the trench. The layer thickness of the etching mask can correspond to the bottom width of the bottom section.

[0065] According to one embodiment, the conductive connection structure can be constructed in a trench, wherein the connection structure and the shielding area can form contact.

[0066] The interconnect structure can be formed using conductive materials such as metals or semiconductors (e.g., heavily doped or modified semiconductors, such as polycrystalline silicon). The interconnect structure can comprise multiple layers, with directly adjacent layers made of different materials.

[0067] The contact between the connection structure and the shielding region can be an ohmic contact, which enables charge carriers to be drawn from the shielding region to the load electrode through the connection structure.

[0068] Another embodiment relates to a semiconductor device that may include a SiC semiconductor body and a gate electrode structure. The gate electrode structure extends from a first surface of the SiC semiconductor body into the SiC semiconductor body and has a conductive connection structure. At the bottom, the gate electrode structure has a structural width. Within the SiC semiconductor body, a shielding region may be constructed along the bottom. A contact, such as an ohmic contact or a contact with a non-linear characteristic curve, such as a Schottky contact, may be formed between the conductive connection structure and the shielding region.

[0069] The shielding region may have a central segment of a first width. In at least one doped plane extending generally parallel to the bottom of the trench, the dopant concentration in the central segment deviates from the maximum value in the doped plane by no more than ±10%, typically no more than ±5% or no more than ±1%. The first width is less than the structure width and is at least 30% of the structure width.

[0070] Embodiments of semiconductor devices can be fabricated using the embodiments of the method described herein. That is, all features described in conjunction with the embodiments of the method can be disclosed accordingly for semiconductor devices, and vice versa. For example, the bottom of the gate electrode structure can be derived from the bottom of the trench in the fabrication method. The SiC semiconductor body can be derived from a silicon carbide substrate. The structure width can correspond to the trench width.

[0071] The first width of the central segment can be adjusted by the width of an opening in the injection mask, which is used in a method for manufacturing semiconductor devices to introduce dopant atoms through the bottom of a trench to construct a shielded region, wherein a gate electrode structure is constructed in the trench.

[0072] Outside the central section, the dopant concentration in the shielding region can decrease sharply in the lateral direction, causing the shielding region to not, or only to a very small extent, protrude laterally beyond the gate electrode structure. The shielding region does not reduce, or only slightly reduces, the cross-section of the current distribution region, which can laterally adjoin the gate electrode structure.

[0073] During the introduction of dopant atoms to construct the shielding region, the dispersion of dopant atoms through the trench sidewalls into the doped region of the lateral adjacent gate electrode structure constructed in the trench can be suppressed.

[0074] According to one embodiment, the dopant plane can connect the local maximum value of the vertical dopant distribution in the shielding region. The average distance between the trench bottom and the dopant plane can here correspond to the penetration depth of dopant atoms into the silicon carbide substrate. According to this embodiment, the maximum dopant concentration in the shielding region across a first lateral width can have a dopant mesa, in which the dopant concentration fluctuates by at most ±10% of the maximum value in the dopant plane, for example, at most ±5% or at most ±1%.

[0075] According to one embodiment, the first width may be less than the difference between the structure width and twice the average distance between the dopant plane and the bottom, for example, equal to or less than the difference between the structure width and two and a half or three times the average distance between the dopant plane and the bottom. Therefore, constructing a shielding region may include ion implantation, wherein the implantation mask covers the sidewalls of the trench and at least partially prevents the introduction of dopant ions at undesirable locations. For example, in the case where the shielding region is constructed after the trench for constructing the gate electrode and before the gate electrode is constructed in the trench, the intrusion of dopant through the trench sidewalls and through the outer sections of the trench bottom into the body region or into the drift region or current distribution region connected to the body region towards the drain side can be reduced or completely avoided.

[0076] According to one embodiment, the gate electrode structure may have a field dielectric. The field dielectric may have a sidewall section with a first layer thickness th1 along the sidewall of the gate electrode structure. The connection structure may have a second width w2 at the bottom, which may be less than the difference between the structural width w0 of the bottom gate electrode structure and twice the first layer thickness: w2 < (w0 - 2 * th1).

[0077] The contact between the connecting structure and the shielding area can be formed entirely by the central section of the shielding area and / or by the end region of the connecting structure at the bottom. In this case, the contact area between the connecting structure and the shielding area can extend entirely along the end regions of the shielding area and / or the connecting structure.

[0078] The central section of the shielding region is the section between the potential shielding contact area of ​​the back electrode and the directly adjacent contact area of ​​the field dielectric. This section of the field dielectric can, for example, be the bottom section. High electric field strength in the section directly adjacent to the field dielectric can be avoided. When the semiconductor device operates in SOA, the lateral contraction of the contact area relative to the outer edge of the shielding region can reduce the maximum electric field strength in the field dielectric, reduce the breakdown probability of the field dielectric, and improve the reliability of the semiconductor device.

[0079] According to one embodiment, the bottom section of the field dielectric may have a second layer thickness, equal to or less than the first layer thickness. The bottom section may be constructed in the outer section of the bottom between a portion of the connection structure and the shielding region. The shielding region, particularly its central region, may laterally overlap with the field dielectric, particularly the bottom section of the field dielectric. The bottom section may cause the contact area between the connection structure and the shielding region to contract from the lateral outer edge of the central section of the shielding region, thereby reducing the electric field appearing along the contact area in the section of the field dielectric. The second layer thickness of the field dielectric may vary in distance; for example, the layer thickness may decrease towards the connection structure.

[0080] According to one embodiment, a JFET sub-region can be constructed within a SiC semiconductor body. The JFET sub-region and a shielding region can form a unipolar junction. The shielding region is constructed between the gate electrode structure and the JFET sub-region. At the unipolar junction, the JFET sub-region has a fourth lateral width smaller than the first width.

[0081] By laterally shrinking the JFET subregion, a JFET subregion with a relatively large vertical range can be achieved without reducing or by reducing the cross-section of the current distribution area that can be laterally adjacent to the JFET subregion by more than just a smaller range.

[0082] According to another embodiment, the gate electrode structure may have a gate electrode and a discrete dielectric, wherein the gate electrode is constructed between a first surface and a connection structure, and wherein the discrete dielectric is constructed between the gate electrode and the connection structure.

[0083] In at least one embodiment of the methods and / or semiconductor devices described herein, at least one of the following features may be applicable (if applicable):

[0084] (i) The bottom section of the field dielectric may extend from the sidewall section along the bottom and / or along the bottom of the trench.

[0085] (ii) The bottom section may be arranged between the sidewall section and the opening in the bottom of the trench.

[0086] (iii) The difference between the bottom width of the bottom section and the first layer thickness of the sidewall section can correspond to half the difference between the trench width and the second width.

[0087] (iv) The sidewall section of the field dielectric can form an L-shape together with the bottom section of the field dielectric.

[0088] (v) The sidewall section of the field dielectric can be constructed integrally with the bottom section of the field dielectric.

[0089] (vi) The shielding area, such as its central section, may laterally overlap with the field dielectric, such as the bottom section of the field dielectric.

[0090] (vii) The bottom section may partially cover the central section of the shielded area.

[0091] (viii) The connection structure and the shielding area can be directly adjacent to each other.

[0092] according to Figure 1A method for manufacturing a semiconductor device includes: providing a silicon carbide substrate (902), wherein the silicon carbide substrate has trenches extending from a main surface of the silicon carbide substrate into the silicon carbide substrate and having a trench width at the bottom of the trenches. In the silicon carbide substrate, a shielding region (904) is constructed, wherein the shielding region extends along the bottom of the trenches. In at least one dopant plane extending substantially parallel to the bottom of the trenches, the dopant concentration in the shielding region over a first transverse width deviates from the maximum dopant concentration in the dopant plane by no more than 10%, no more than 5%, or no more than 1%. The first width is less than the trench width and is at least 30% of the trench width.

[0093] Figures 2A to 2D The invention relates to a method for manufacturing semiconductor devices from a silicon carbide substrate 700.

[0094] The silicon carbide substrate 700 may have SiC crystals or be composed of such SiC crystals. The polymorphism of the SiC crystal may be, for example, 15R or hexagonal polymorphisms, such as 2H, 4H, or 6H. In addition to the main components, silicon and carbon, the silicon carbide substrate 700 may have dopant atoms, such as nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al), and / or gallium (Ga). Furthermore, the silicon carbide substrate 700 may have impurities, such as oxygen, hydrogen, fluorine, and / or bromine.

[0095] The silicon carbide substrate 700 can be used to form a so-called semiconductor wafer, namely a flat disk that is approximately circular, having a main surface 701 on the front side and a back side surface 702 on the back side, wherein the back side surface 702 and the main surface 701 are oriented parallel to each other.

[0096] The main surface 701 can be flat or ribbed. In the case of a ribbed main surface, the intermediate plane passing through the ribbed main surface is suitable as the main surface 701 in the following text.

[0097] The surface normal 704 of the main surface 701 defines the vertical direction. Directions orthogonal to the surface normal 704 are the transverse and horizontal directions. The diameter of the silicon carbide substrate 700 may correspond to industry standards for semiconductor wafers, such as 2 inches (51 mm), 3 inches (76 mm), 4 inches (100 mm), 125 mm, or 200 mm.

[0098] The silicon carbide substrate 700 may, for example, have a heavily doped base substrate and an epitaxial layer grown on the base substrate, wherein the epitaxial layer may have multiple sublayers and doped regions with different doping. Doped regions may be constructed in segments of one or more sublayers.

[0099] A trench 750 is constructed in the silicon carbide substrate 700, extending from the main surface 701 into the silicon carbide substrate 700.

[0100] Figure 2A A groove 750 is shown having a groove bottom 751 and sidewalls 752, the sidewalls connecting the groove bottom 751 to a first main surface 701. The sidewalls 752 may be vertically oriented or vertically inclined. The groove 750 may be constructed in a strip-like manner, wherein the length of the groove 750 along a direction orthogonal to the cross-sectional plane is greater than the groove width wg of the groove 750 parallel to the cross-sectional plane. Adjacent grooves 750 may be constructed with the same center-to-center distance p1.

[0101] A shielding region 140 is constructed below the trench 140, and a field dielectric 159 is constructed in the trench 750, the field dielectric having an opening 158 at the bottom 751 of the trench.

[0102] Figure 2B and 2C A shielding region 140 is shown, which can extend vertically from the trench bottom 751 into the silicon carbide substrate 700 and is constructed symmetrically with respect to the central axis of the trench 750. The shielding region 140 and the drift structure constructed in the silicon carbide substrate 700 can form a pn junction. The shielding region 140 each has a central segment 145 with a first width w1. In a dopant plane 105 parallel or substantially parallel to the trench bottom 751, within the central segment 145, the deviation of the dopant concentration from the maximum value within the central segment 145 of the dopant plane 105 is at most 10%, at most 5%, or at most 1%.

[0103] Outside the central section 145, the dopant concentration in the shielding region 140 can decrease sharply in the lateral direction. The first width w1 is less than the trench width wg and less than the total lateral width w11 of the shielding region 140 in the plane of the trench bottom 751. The total width w11 of the shielding region 140 can be less than or equal to the trench width wg. The total width w11 of the shielding region 140 can take values ​​in the range of 500 nm to 3 micrometers.

[0104] The field dielectric 159 covers at least the lower section of the trench 750 and the outer section of the sidewall 752 and the trench bottom 751. An opening 158, which may be symmetrically configured relative to the central axis of the trench 750, exposes the central section of the trench bottom 751. The opening 158 has a second width w2, which is smaller than a first width w1. A conductive connection structure 157 constructed in the trench 750 directly adjoins the shielding region 140 in the region of the opening 158.

[0105] according to Figure 2CThe field dielectric 159 may have at least one sidewall segment 1593 constructed along one of the sidewalls 752 of the trench 750. The sidewall segment 1593 has a first layer thickness th1 and, in a segment of the trench bottom 751, extends from the sidewall 752 to a distance corresponding to the first layer thickness th1, directly adjacent to the trench bottom 751. The field dielectric 159 may have two sidewall segments 1593 constructed on two opposing sidewalls 752 of the trench 750, wherein the two sidewall segments 1593 may have different first layer thicknesses th1 or the same first layer thickness th1.

[0106] The field dielectric 159 may have at least one bottom segment 1592 that extends laterally along the trench bottom 751 from one of the sidewall segments 1593, wherein the bottom segment 1593 may be directly connected to the sidewall segment 1593. The bottom segment 1592 extends through a bottom width wb from the edge of the opening 158 to the sidewall segment 1593 and has a second layer thickness th2, which may be equal to, greater than or less than the first layer thickness th1. The lateral bottom width wb may take a value in the range of 30 nm to 400 nm, for example, a value in the range of 100 nm to 300 nm.

[0107] The sidewall section 1593 and the bottom section 1592 can be integral, forming a continuous section of a single structure. The bottom section 1592 and the sidewall section 1593 can be made of the same material or different materials. In a vertical cross-section perpendicular to the trench 750, the sidewall section 1593 and the bottom section 1592 can together have an L-shaped cross-sectional area.

[0108] The field dielectric 159 may have two bottom segments 1592, wherein the two bottom segments 1592 may have different second layer thicknesses th2 or the same second layer thickness th2. The bottom segments 1592 may be constructed asymmetrically or symmetrically with respect to the opening 158.

[0109] The total bottom width of all bottom segments 1592 in the trench 750 with a trench width wg is obtained by subtracting the first layer thickness th1 of the sidewall segment 1593 and the second width w2 of the opening 158 from the trench width wg. For sidewall segments 1593 and symmetrical openings 158 with the same first layer thickness th1, the bottom width wb of each bottom segment 1592 is obtained by subtracting the first layer thickness th1 from half the difference between the trench width wg and the second width w2.

[0110] wb = 1 / 2 * (wg - w2) - th1,

[0111] The distance Δw between the outer edge of the central segment 145 of the shielding region 140 and the opening 158 in the field dielectric 159 is at least 25 nm and at most 300 nm, for example at least 75 nm.

[0112] Constructing the shielded region 140 may include ion implantation at one or more accelerating voltages for dopant ions. The average effective range of the implanted dopant ions in the silicon carbide substrate 700 defines the penetration depth. The vertical dopant distribution in the shielded region 140 can be described by a Gaussian distribution or by the superposition of two or more Gaussian distributions. The distance from the local or global maximum of the vertical dopant distribution to the trench bottom 751 corresponds to the penetration depth pre-given by the implanted accelerating voltage.

[0113] The dopant plane 105 can connect the positions of laterally adjacent local maxima of the vertical dopant distribution in the shielding region 140 to each other at a certain distance from the bottom of the trench 751, for example, connecting the positions of the absolute maximum values ​​in the shielding region 140 or the positions of such local maxima generated by the same injection to each other.

[0114] Figure 2D It shows Figure 2C The lateral dopant distribution in the dopant plane 105. The type of dopant injected into the shielding region 140 can exceed the total lateral width w11 of the shielding region 140. On the first lateral width w1, the deviation of the dopant concentration from the maximum dopant concentration in the dopant plane 105 does not exceed 10%.

[0115] The first lateral width w1 is less than the total lateral width w11, and can be equal to or less than the difference between the trench width wg and twice the intrusion depth d3, for example, equal to or less than the difference between the trench width wg and 2.5 or 3 times the intrusion depth.

[0116] The relatively highly and uniformly doped central section 145 of the shielding region 140 effectively shields the edge between the field dielectric 159, the connection structure 157 and the shielding region 140 relative to the potential of the load electrode, which is located on the back side of the back main surface 701 of the silicon carbide substrate.

[0117] Figure 3A-3L An embodiment with a gate electrode structure is shown, which, in addition to a conductive gate electrode, also has a conductive connection structure that is electrically connected or electrically coupled to a doped shielding region below the gate electrode structure and to a front metallization on the front side of a silicon carbide substrate.

[0118] Figure 3AA silicon carbide substrate 700 is shown, which is based on a hexagonal SiC crystal type, such as 4H-SiC, and its <0001> The crystal orientation is tilted by an angle α relative to the surface normal 704 on the main surface 701. The angle α can be between 2° and 8°, for example, about 4°.

[0119] choose Figure 3A-3L The cross-sectional plane makes... <0001> The crystal orientation is tilted by an angle deviation α relative to the surface normal 704 in a plane orthogonal to the cross-sectional plane and orthogonal to the orientation of the principal surface 701. <11-20> The crystal orientation is tilted by an angle deviation α relative to the surface normal of the cross-sectional plane in a plane orthogonal to the cross-sectional plane and orthogonal to the orientation of the principal surface 701. <1-100> The crystal orientation extends parallel to the cross-sectional plane and parallel to the principal surface 701. In Figure 2A-2C In the embodiments shown in 3A-3L, 4A-4B, 5A-5B, 6, and 8, the <1-100> crystal directions extend perpendicular to the main extension directions of the trench and / or gate electrode structures, respectively. However, alternatively, the <11-20> crystal directions may extend perpendicular to the main extension directions of the trench and / or gate electrode structures (see, for example, see...). Figure 7 For other characteristics of the silicon carbide substrate 700, please also refer to the section on... Figures 2A to 2C The description.

[0120] The silicon carbide substrate 700 may have a base substrate 705 and / or an epitaxial layer 707. The base substrate 705 may be a silicon carbide wafer separated from a single-crystal silicon carbide crystal, for example, by sawing or by wafer separation methods. The base substrate 705 may be heavily doped, for example, heavily n-doped. However, the silicon carbide substrate 700 may also be without a base substrate 705, for example, because the base substrate has been removed from the epitaxial layer after the epitaxial layer 707 has been grown.

[0121] The epitaxial layer 707 can be constructed on the process surface of the base substrate 705 by an epitaxial method. The epitaxial layer 707 may have a drift layer structure 730, which may have the same conductivity type as the base substrate 705 or a conductivity type complementary to the conductivity type of the base substrate 705.

[0122] The drift layer structure 730 may have a lightly doped drift layer 731 and an optional current distribution layer 737, wherein the drift layer 731 may be constructed between the base substrate 705 and the current distribution layer 737. The drift layer 731 and the optional current distribution layer 737 have the same conductivity type. The average dopant concentration in the optional current distribution layer 737 is higher than the average dopant concentration in the drift layer 731. For example, the average dopant concentration in the optional current distribution layer 737 may be at least twice the average dopant concentration in the drift layer 731.

[0123] On the side of the drift layer structure 730 opposite to the base substrate 705, a body structure 720 having a conductivity type opposite to that of the drift layer structure 730 can be constructed. For example, the body structure 720 can be constructed by epitaxial growth on the drift layer structure 730, or by introducing dopant atoms into a previously grown upper segment of the epitaxial layer 707. The body structure 120 can form a continuous layer or comprise a plurality of laterally separated body wells. The lateral extent of the body wells can be relatively large compared to the width of the trenches constructed below.

[0124] Along a segment of the main surface 701, a heavily doped source well 711 of the conductivity type of the drift layer 731 can be constructed between the main surface 701 and the bulk structure 720. The segment of the main surface 701 with the source well 711 can correspond to a transistor cell region of the final SiC semiconductor device. Another segment of the main surface 701 can laterally separate the segments with the source well 111 from each other. This other segment may include a kerf region and an edge-termination region of the final semiconductor device, wherein structures for lateral field reduction can be constructed in the edge-termination region.

[0125] According to the illustrated embodiment, the body structure 720 is p-conductive and the drift layer structure 730 is n-conductive. According to other embodiments, the body structure 720 may be n-conductive and the drift layer structure 730 may be p-conductive.

[0126] On the main surface 701, a trench mask 790 with a mask opening 791 is constructed using a photolithography method. Using an anisotropic etching method, such as a chemical physical dry etching method, the structural dimensions of the trench mask 790 are stably transferred to the silicon carbide substrate 700, wherein trenches 750 are constructed. These trenches can extend below the mask opening 791 from the plane 791 defined by the plane of the main surface 701 through the source structure 111 and the bulk structure 720 into the drift layer structure 730.

[0127] Figure 3B A trench mask 790 with a mask opening 791 is shown. The trench mask 790 may have a single layer made of one material or two or more sublayers made of different materials. According to one embodiment, the trench mask 790 has carbon, such as graphite, silicon, silicon oxide, and / or silicon nitride.

[0128] The trench 750 can be constructed in a strip-like shape, wherein the length of the trench 750 along the direction orthogonal to the cross-sectional plane is greater than the trench width wg of the trench 750 parallel to the cross-sectional plane. Adjacent trenches 750 can be constructed with a center-to-center distance from each other, wherein the center-to-center distance of each adjacent trench 750 along the silicon carbide substrate can be the same or can vary. Figure 3AThe body structure 720 forms body region 120 in the section between the grooves 750. Figure 3A The source well 711 forms a source structure 111 in the section between trenches 750. The trench bottom 751 may have a section parallel to the main surface 701. The sidewalls 752 of the trench 750 may be oriented vertically and / or parallel to a (1-100) lattice plane having a relatively high carrier mobility. The transition between the sidewalls 752 and the trench bottom 751 may be rounded.

[0129] An implantation mask 740 is constructed, with sidewalls 752 shielding against the introduction of dopant atoms and allowing implantation through at least one segment of the trench bottom 751. For example, constructing the implantation mask 740 includes thermal oxidation and / or deposition and structuring of a mask layer.

[0130] Figure 3C An injection mask 740 is shown, which covers a trench bottom 751 having a layer thickness d1 and a sidewall 752 having a layer thickness d2, wherein the layer thickness d1 at the trench bottom may be less than the layer thickness d2 at the sidewall. According to other embodiments, the injection mask 740 can be constructed to selectively cover only the sidewall 752 and expose the trench bottom 751. This can be considered as an injection mask 740 having a vanishing layer thickness d1 at the trench bottom 751, as in... Figure 3D As shown in the right half. This injection mask can, for example, be created through... Figure 3C Isotropic etching of the injection mask 740, by removing from it Figure 3C The implantation mask 740 (spacer etching) is constructed either by depositing a conformal implantation mask layer along with subsequent spacer etching.

[0131] With the implantation mask 740 covering the area, dopant atoms are introduced through the trench bottom 751. The introduction of dopant atoms can include multiple implantations at different implantation energies, wherein the opening of the implantation mask 740 at the trench bottom 751 can vary between the different implantations.

[0132] The injection mask 740 prevents dopant atoms from being dispersed into the body region 120 and the current distribution layer 737 through the sidewall 752.

[0133] The section at the bottom 751 of the trench, used for introducing dopant atoms, has a third lateral width w3. According to... Figure 3DIn one embodiment, the third width w3 may correspond to the lateral distance between two segments of the implantation mask 740 at opposite sidewalls 752 at the trench bottom 751, wherein the two segments of the implantation mask 740 define a mask opening therebetween. The third width w3 of the mask opening of the implantation mask 740, and / or the width of the thinned segment of the implantation mask 740 at the trench bottom 751 and the penetration depth of the implanted dopant atoms define the first lateral width w1 of the central segment of the shielding region 140. In the central segment 145 of the shielding region, in the dopant plane 105 extending at a distance from the trench bottom 751 parallel or substantially parallel to the trench bottom 751, the deviation of the dopant concentration from the maximum value in the dopant plane 105 of the central segment 145 does not exceed 10%, 5%, or 1%.

[0134] Figure 3D The shielding region 140 extends from the bottom of the trench 751 into the silicon carbide substrate 700. Figure 3C The current distribution layer 737 forms a current distribution region 137 in the sections between the trenches 750 and between the shielding regions 140. The central section 145 of the shielding region 140 has a first width w1, which is smaller than the trench width wg. Heat treatment, which can be performed at at least 800°C and at most 2200°C or at most 1900°C, can activate dopant atoms introduced into the shielding region 140 and anneal implantation damage. During heat treatment, the implantation mask 740 can be deactivated or replaced with a sacrificial mask made of a heat-resistant material. The implantation mask 740 is then removed.

[0135] Figure 3E It shows the removal Figure 3D The trench 750 after the injection mask 740 and the shielding area 140 below the trench 750.

[0136] In trench 750, a field dielectric layer 259 may be formed covering the sidewalls 752 and the bottom 751 of the trench. The formation of the field dielectric layer 259 may include thermal oxidation and / or the deposition of one or more dielectric layers.

[0137] Figure 3F A field dielectric layer 259 is shown covering the sidewalls 752 and the trench bottom 751 with a uniform layer thickness. According to another embodiment, the layer thickness of the field dielectric layer 259 at the trench bottom 751 may be less than the layer thickness at the sidewalls 752.

[0138] A conformal etch mask layer 260 covering the field dielectric layer 259 can be constructed. The layer thickness of the etch mask layer 260 is selected such that the etch mask layer 260 does not completely fill the trench 750. Constructing the etch mask layer 260 may include depositing one or more layers.

[0139] Figure 3GA conformal etch mask layer 260 is shown, which covers a segment of the field dielectric layer 259 in the trench 750 and the trench mask 790 with a uniform layer thickness. The layer thickness may correspond to the bottom width following the bottom segment of the field dielectric. The material of the etch mask layer may be silicon oxide, silicon nitride, carbon, polycrystalline silicon, and / or amorphous silicon. The etch mask layer 260 and the field dielectric layer 259 may be formed of different materials. For example, an anisotropic etching method of a chemical physical dry etching process can remove the material of the etch mask layer 260 from above. The removal of the etch mask layer 260 ends after the segment of the field dielectric layer 259 at the bottom 751 of the trench has been exposed and before the material of the etch mask layer 260 has been completely removed.

[0140] Figure 3H It shows the result of Figure 3G The remaining portion of the etch mask layer 260 forms an etch mask 760, which has an etch mask opening 761 in the central portion of the trench 750. The width of the etch mask opening 761 defines a second width w2.

[0141] With the etch mask 760 covering the area, the section of the field dielectric layer 259 exposed by the etch mask opening 761 is removed. Thereafter, the etch mask 760 is removed.

[0142] Figure 3I The field dielectric layer 259 is shown after etching of the central section of the trench bottom 751, exposed by opening 158. Opening 158 has a second width w2, which is smaller than the first width w1 of the central section 145 of the shielding region 140. Heavily doped polysilicon and / or one or more metal layers are deposited, filling the trench 750.

[0143] Figure 3J A first doped semiconductor material 257 is shown filling trench 750. The first doped semiconductor material 257 regresses in trench 750 below the lower edge of body region 120. The regressed first semiconductor material 257 forms a conductive interconnect structure 157. A separation dielectric 156 is constructed on the interconnect structure 157. Constructing the separation dielectric 156 may include thermal oxidation of the upper portion of the interconnect structure 157 and / or deposition of one or more dielectric layers.

[0144] In the upper section of trench 750, after the first doped semiconductor material 257 has returned, the upper section of the field dielectric layer 259 is removed and a gate dielectric 151 is formed. Forming the gate dielectric 151 may include thermal oxidation and / or the deposition of one or more dielectric layers.

[0145] Figure 3K The conductive connection structure 157 in the lower section of the trench 750 is shown. Figure 3JA section of the field dielectric layer 259 in the lower section of the trench 750 forms the field dielectric 159. A conductive connection structure 157 directly adjoins the shielding region 140. The shielding region 140 and the connection structure 157 form an ohmic contact. The connection structure 157 may include a metallic structure, such as silicide at the interface with the shielding region 140. A separating dielectric 156 covers the connection structure 157.

[0146] Deposit a second doped semiconductor material. Remove the section of the second doped semiconductor material outside the trench 750.

[0147] Figure 3L The gate electrode 155, formed by depositing a second doped semiconductor material, is shown in the upper section of trench 750.

[0148] Figures 4A-4B An embodiment involving multiple injections disposed at the bottom 751 of a trench, wherein the injections utilize injection masks with injection mask openings of varying sizes.

[0149] According to Figure 3B In the trench 750, a first injection mask 7401 having a first injection mask opening 7411 is constructed, for example, by etching the spacers of the conformal mask layer. The first injection mask opening 7411 has a third width w3 at the bottom 751 of the trench. Dopant atoms for the shielding region 140 are introduced through the first injection mask opening 7411.

[0150] Figure 4A The shielding region 140 below the trench 750 is shown. Within the trench 750, a second injection mask 7402 is constructed having a second injection mask opening 7412, which has a fourth width w4 at the trench bottom 751, wherein the fourth width w4 is smaller than a third width w3. Constructing the second injection mask 7402 may, for example, involve etching spacers for another conformal mask layer, wherein the second mask layer may be constructed on the first injection mask 7401 or wherein the first injection mask 7401 may have been previously removed. Dopant atoms for constructing the JFET sub-region 148 can be introduced through the second injection mask opening 7412.

[0151] Figure 4B JFET sub-regions 148 are shown, which can form unipolar junctions with shielding region 140 and extend further from shielding region 140 into drift region layer 731. According to other embodiments, dopant atoms for JFET sub-regions 148 may be introduced first, and dopant atoms for shielding region 140 may be introduced later.

[0152] The narrower injection mask opening for injection with high acceleration energies and penetration depths allows for the construction of a JFET subregion 148 with a relatively large vertical extent, which does not reduce the lateral cross-sectional area of ​​the current distribution region 137 through lateral diffusion. Even at high acceleration energies, the relatively thick second injection mask 7402 prevents dopant atoms from dispersing through the sidewalls of the trench 750 into the body region 120 and the current distribution region 137.

[0153] The wider injection mask opening for injection with low acceleration energy and shallow penetration depth allows for the construction of an effective shielding region 140 at the bottom 152 of the gate electrode structure 150 for the critical sub-region of the field dielectric 159.

[0154] Figures 5A-5B Figures 6-8 show a semiconductor device 500, which may be derived, for example, from references. Figure 1 , 2A The methods described in -2B, 3A-3L and 4A-4B.

[0155] exist Figures 5A-5B In this embodiment, the semiconductor device 500 has a SiC semiconductor body 100. According to other embodiments, a semiconductor body made of other semiconductor materials, having a different bandgap, may be provided. The semiconductor device 500 may be an IGFET, IGBT, or MCD (MOS controlled diode). The semiconductor material may, for example, be crystalline silicon carbide with a hexagonal lattice, such as 2H-SiC, 6H-SiC, or 4H-SiC.

[0156] A first surface 101 on the front side of the SiC semiconductor body 100 may be coplanar with the principal lattice plane of the SiC crystal, wherein the first surface 101 is planar. According to another embodiment, the first surface 101 is tilted relative to the orientation of the principal lattice plane by an angle deviation α, wherein the absolute value of the angle deviation may be at least 2° and at most 8°, for example, about 4°. The first surface 101 may then be flat or ribbed. In the case of a ribbed first surface 101, the first surface 101 may have parallel first surface segments and parallel second surface segments. The first surface segments are offset from each other and tilted by an angle deviation α relative to a horizontal intermediate plane. The second surface segments extend obliquely relative to the first surface segments and connect to the first surface segments, such that the cross-sectional lines of the first surface form serrated lines.

[0157] The direction parallel to the flat first surface 101 or the intermediate plane of the ribbed first surface 101 is the horizontal direction and the transverse direction. The normal 104 on the flat first surface 101 or the intermediate plane of the ribbed first surface 101 defines the vertical direction. <0001> The crystal orientation is tilted at an angle α in a plane orthogonal to the cross-sectional plane of FIG5B. <1-100> The crystal orientation extends in the cross-section and parallel to the first surface 101.

[0158] On the back side of the SiC semiconductor body 100, the second surface 102 extends parallel to the first surface 101. The total thickness of the SiC semiconductor body 100 between the first surface 101 and the second surface 102 can be in the range of several hundred nm to several hundred μm.

[0159] On the front side, a transistor cell TC is constructed along the first surface 101. A drift structure 130 is constructed between the transistor cell TC and the second surface 102. The drift structure 130 may have a heavily doped base segment 139 and a lightly doped drift region 131. The base segment 139 is directly adjacent to the second surface 102. The drift region 131 is constructed between the transistor cell TC and the base segment 139. Along the second surface 102, the dopant concentration in the base segment 139 is sufficiently high to form an ohmic contact with the metal.

[0160] If the semiconductor device 500 is an IGFET or MCD, the base segment 139 and the drift region 131 have the same conductivity type. If the semiconductor device 500 is a reverse-block IGBT, the base segment 139 and the drift region 131 have complementary conductivity types. If the semiconductor device 500 is a reverse-conducting IGBT, the base segment 139 may include regions of two conductivity types, which extend from the drift region 131 to the second surface 102, respectively.

[0161] Drift region 131 can be constructed in the epitaxial layer. The average dopant concentration in drift region 131 can be 1E15cm. -3 Up to 5E16cm -3 Within the range. The drift structure 130 may have additional doped regions, such as field stop regions, barrier regions of the conductivity type of drift region 131, and / or anti-doped regions.

[0162] In the illustrated embodiment, the drift structure 130 has a current distribution region 137 that may be directly adjacent to the drift region 131 and constructed between the drift region 131 and the first surface 101. The average dopant concentration in the current distribution region 137 is at least 150% of the average dopant concentration in the drift region 131, or, for example, at least twice as high. However, the drift structure 130 may also lack the current distribution region 137. In this case, the drift region 131 may be directly adjacent to the body region 120.

[0163] Drift region 131 can be directly adjacent to base section 139 or buffer layer, where the buffer layer and drift region 131 form a unipolar junction. The vertical extent of the buffer layer can be approximately 1 μm. The average dopant concentration in the buffer layer can be 3E17 cm⁻¹. -3 Up to 1E18cm -3 Within the range. The buffer layer can reduce mechanical stress in the semiconductor body 100, help reduce defect density in the semiconductor body, and / or can help form a desired electric field distribution in the drift structure 130.

[0164] The transistor cell TC is constructed along the gate electrode structure 150, which extends from the first surface 101 into the SiC semiconductor body 100 and the drift structure 130. The SiC semiconductor body 100 forms a semiconductor mesa 170 in the section between adjacent gate electrode structures 150.

[0165] Gate electrode structure 150 along perpendicular to Figure 5B The longitudinal extent of the first horizontal direction of the cross-sectional plane is greater than that of the gate electrode structure 150 along the Figure 5B The width in the second horizontal direction in the cross-sectional plane. The gate electrode structure 150 can be configured, for example, as a long strip extending from one side of the transistor cell region to the opposite side, wherein the length of the gate electrode structure 150 can be up to several hundred μm or several mm.

[0166] The gate electrode structures 150 can be constructed at equal distances from each other, wherein the center-to-center distance between adjacent gate electrode structures 150 can be in the range of 1 μm to 10 μm, for example, from 2 μm to 5 μm. The vertical range of the gate electrode structures 150 can be in the range of 300 nm to 5 μm, for example, in the range of 500 nm to 2 μm.

[0167] In the illustrated embodiment, the sidewalls on the longitudinal side of the gate electrode structure 150 are oriented perpendicularly to the first surface 101. According to other embodiments where the longitudinal axis of the gate electrode structure 150 has a different orientation from the crystal axis, the sidewalls may be tilted relative to the vertical direction such that the angle between one of the sidewalls and the normal 104 is equal to an angle deviation α or a deviation from that angle deviation α not exceeding ±1° (see, for example, [reference needed]). Figure 7 At least one longitudinal sidewall of the gate electrode structure 150 is located in a principal lattice plane with high carrier mobility. Typically, at least one longitudinal sidewall of the gate electrode structure 150 may be located in one of the lattice planes (11-20), (-1-120), (1-100) and / or (-1100).

[0168] In the semiconductor mesa 170, a source region 110 extending from the first surface 101 into the semiconductor body 100 may be constructed along the sidewalls of adjacent gate electrode structures 150. In each semiconductor mesa 170, a body region 120 is constructed that separates the source region 110 from a current distribution region 137 constructed at least partially in the semiconductor mesa 170. The body region 120 may be adjacent to two adjacent gate electrode structures 150, respectively.

[0169] Body region 120 and current distribution region 137 form the first pn junction pn1. Body region 120 and source region 110 form the second pn junction pn2.

[0170] The gate electrode structure 150 has a conductive gate electrode 155. The gate electrode 155 may, for example, have heavily doped polysilicon and / or a metal-containing layer. The gate electrode 155 may be connected to a gate metallization, wherein the gate metallization may form a gate terminal or may be connected to a gate terminal.

[0171] Gate dielectric 151 separates gate electrode 155 from body region 120. Gate dielectric 151 may have a semiconductor dielectric or be composed of a semiconductor dielectric. The semiconductor dielectric may be, for example, a thermally grown or deposited semiconductor oxide, such as silicon oxide, a semiconductor nitride, such as deposited or thermally formed silicon nitride, and / or a semiconductor oxide oxynitride, such as silicon oxynitride. Gate dielectric 151 may also have another deposited dielectric material or any combination of the aforementioned materials.

[0172] According to one embodiment, the gate dielectric 151 has silicon oxide, which is sealed and / or partially nitrided after deposition. The material and thickness th0 of the gate dielectric 151 can be selected such that the threshold voltage of the transistor cell TC is in the range of 1 to 8V.

[0173] Interlayer dielectric 210 can separate gate electrode 155 from first load electrode 310. Contact structure 315 can extend from first load electrode 310 through an opening in interlayer dielectric 210 to reach or enter SiC semiconductor body 100. Contact structure 315 forms a low-resistance electrical connection between source region 110, body region 120 and first load electrode 310 on the front side of the component. Base segment 139 and second load electrode 320 on the back side of SiC semiconductor body 100 form an ohmic contact along second surface 102 on the back side of the component.

[0174] The gate electrode structure 150 also has a conductive connection structure 157. The conductive connection structure 157 may, for example, have heavily doped polysilicon and / or a metal-containing layer, such as silicide. The connection structure 157 is connected to a potential or network node whose potential differs from the potential at the gate terminal and the second load terminal L2 during device operation. For example, the connection structure 157 is connected to the first load terminal L1, to an auxiliary terminal of the semiconductor device 500, or to an internal network node.

[0175] The separating dielectric 156 separates the gate electrode 155 from the connection structure 157. The separating dielectric 156 may have deposited silicon oxide, thermally formed silicon oxide, silicon nitride, silicon oxynitride, and / or another deposited dielectric material.

[0176] The field dielectric 159 separates the connection structure 157 from the drift structure 130 in the lateral direction. The field dielectric 159 may have deposited silicon oxide, thermally formed silicon oxide, silicon nitride, silicon oxynitride, and / or another deposited dielectric material.

[0177] The field dielectric 159 may have a sidewall segment 1593 constructed along the sidewall of the gate electrode structure 150 and separating the connection structure 157 from the current distribution region 137. The first layer thickness th1 of the sidewall segment 1593 may be greater than the thickness th0 of the gate dielectric 151. For example, the first layer thickness th1 of the sidewall segment 1593 of the field dielectric 159 is at least 120%, for example, at least 150%, of the thickness th0 of the gate dielectric 151.

[0178] The field dielectric 159 may have a bottom section 1592 with a second layer thickness th2, wherein the second layer thickness th2 may be equal to or less than the first layer thickness th1. The bottom section 1592 may be constructed in the outer section of the bottom 152 between the connection structure 157 and the shielding region 140, and has a central opening 158.

[0179] The bottom section 1592 and the side wall section 1593 can be directly connected to each other. For example, the bottom section 1592 and the side wall section 1593 can be constructed integrally with each other, i.e., made in one piece. For example, the bottom section 1592 and the side wall section 1593 can be made of one or more of the same materials. The bottom section 1592 can have a bottom width wb.

[0180] A shielding region 140 can be constructed along the bottom of the gate electrode structure 150, directly adjacent to the gate electrode structure 150. The shielding region 140 forms a pn junction with the drift structure 130, for example, with the drift region 131. The average dopant concentration in the shielding region 140 can be 1E17 cm⁻¹. -3 Up to 2E19 cm -3Within the range, for example, in 8E17cm -3 up to 8E18 cm -3 Within the range.

[0181] The shielding region 140 has a central segment 145 having a first width w1 along the bottom 152 of the gate electrode structure 150. In the central segment 145, the dopant concentration in the shielding region 140 in a dopant plane parallel or substantially parallel to the bottom 152 deviates from the maximum dopant concentration in the dopant plane by no more than 10%, for example, no more than 5% or no more than 1%. The central segment 145 may be constructed symmetrically with respect to the central axis of the gate electrode structure 150. Outside the central segment 145, the dopant concentration in the shielding region 140 decreases sharply in the lateral direction. The first width w1 is smaller than the structural width w0 of the gate electrode structure 150, where the structural width w0 corresponds to the lateral extent of the bottom 152. The shielding region 140 may lie entirely within the vertical projection of the gate electrode structure 150, such that the lateral cross-sectional area of ​​the current distribution region 137 does not decrease through the shielding region 140.

[0182] In the contact region OC with a second width w2, the connection structure 157 of the gate electrode structure 150 forms an ohmic contact with the shielding region 140 adjacent to the gate electrode structure 150. The second width w2 can be less than the difference between the structure width w0 and twice the first layer thickness th1 of the sidewall segment 1593 of the field dielectric 159. Therefore, the central segment 145 of the shielding region 140 not only completely covers the contact region OC but also completely covers the following segment of the field dielectric 159, which is directly connected to the contact region OC and reduces the maximum electric field strength in the bottom segment 1592 of the field dielectric 159.

[0183] The contact area OC may be laterally limited by the bottom segment 1592. The bottom segment 1592 may be directly adjacent to the central segment 145 of the shielding area 140. For example, the bottom segment 1592 may cover the area of ​​the central segment 145 of the shielding area 140 in the vertical direction and / or overlap with the central segment 145 of the shielding area 140 laterally.

[0184] Specifically, the contact area OC does not extend to the transition between the sidewall and the bottom. The contact area OC contracts due to the reduced opening at the bottom, through which the connection structure 157 contacts the shielding area 140.

[0185] The first load electrode 310 can form a first load terminal L1 or be electrically connected to the first load terminal L1. The first load terminal L1 can be the anode terminal of the MCD, the source terminal of the IGFET, or the emitter terminal of the IGBT. The second load electrode 320 can form a second load terminal L2 or be electrically connected to the second load terminal L2. The second load terminal L2 can be the cathode terminal of the MCD, the drain terminal of the IGFET, or the collector terminal of the IGBT.

[0186] In the event of avalanche breakdown, the conductive connection structure 157 efficiently transports charge carriers, such as holes, from the n-type doped drift region 131 to the first load electrode 310, wherein the holes pass through a pn junction pn between the shielding region 140 and the drift structure 130. Avalanche current is conducted adjacent to the body region 120 and does not contribute to biasing the conduction of the parasitic bipolar transistor, which can be formed by the source region 110, the body region 120, and the drift structure 130.

[0187] exist Figure 6 In the semiconductor device 500, the second layer thickness th2 of the bottom segment 1592 of the field dielectric 159 is less than the first layer thickness th1 of the sidewall segment 1593. For example, the second layer thickness th2 is approximately one-third of the first layer thickness th1. A shielding region 140 forms a unipolar junction jn with a JFET sub-region 148 extending from the shielding region 140 into the drift structure 130. The lateral width w5 of the JFET sub-region 148 along the unipolar junction jn can be less than the first width w1.

[0188] Dopant atoms for the JFET sub-region 148 and dopant atoms for the shielding region 140 can be introduced by implantation using implantation mask openings of varying widths. Narrower implantation mask openings for implantation with high acceleration energies and penetration depths allow for the construction of a JFET sub-region 148 with a relatively large vertical extent, which does not reduce the lateral cross-sectional area of ​​the current distribution region 137. Wider implantation mask openings for implantation with low acceleration energies and shallow penetration depths allow for the construction of an effective shielding region 140 for a critical sub-region of the field dielectric 159 at the bottom 152 of the gate electrode structure 150.

[0189] Figure 7 One embodiment is shown in which the sidewalls of the gate electrode structure 150 are located in the (11-20) lattice planes. The gate electrode structure 150 extends along the <1-100> crystal direction, which is orthogonal to the cross-sectional plane and parallel to the first surface 101. The sidewalls of the gate electrode structure 150 may be constructed at an angle, i.e., the angle between the sidewall and the surface normal 104 of the first surface 101 is not zero.

[0190] The shielding region 140 can be constructed along the entire longitudinal range of the gate electrode structure 150 or only in segments. Alternatively or additionally, the entire gate electrode structure 150 can be provided without the shielding region 140. In the absence of the shielding region 140, the connection structure 157 and the drift structure 130 (e.g., a segment of the connection structure 157 and the current distribution region 137) can form a Schottky contact in the Schottky contact region SC. The lateral range w6 of the Schottky contact region SC can correspond to the second width w2 of the contact region OC, or can be selected independently of the second width w2.

[0191] The Schottky contact has a lower startup voltage than a body diode including the first pn junction pn1. In the reverse-biased state of the semiconductor device 500, unipolar carrier current flows through the Schottky contact and connection structure 157 to the first load electrode 310. When the semiconductor device 500 operates in an SOA, bipolar current can be avoided by the drift structure 130, and for example, degradation of the SiC crystal caused by bipolar current can be prevented. Simultaneously, at least when the current value is not too high, the voltage drop during current flow in the reverse-biased state of the semiconductor device 500 is reduced. However, at high current values, the pn junction also begins to conduct, and further voltage rise is reduced due to bipolar injection.

[0192] Figure 8 A gate electrode structure 150 with a rounded transition between the sidewalls and the bottom 152 is shown. The structure width w0 at the bottom 152 is measured in a plane in which the curve begins to bend from the first surface 101.

[0193] Figure 9A It is shown in accordance with Figure 8 An effective electric field in the field dielectric 159 of the semiconductor device 500. Figure 9B The effective electric field in the field dielectric 159 of the comparative device at the same cutoff voltage is shown. In the comparative device, the first width w1 is approximately equal to the second width w2, making the ohmic contact region OC excessively wide so that it can be adequately shielded by the shielding region 140 at high cutoff voltages. A critical field strength is reached in the end section of the field dielectric 159. Conversely, if the outer edge of the contact region OC is laterally wide enough to contract from the outer edge of the shielding region 140, the electric field in the field dielectric 159 remains non-critical.

[0194] Although specific embodiments have been illustrated and described herein, it will be apparent to those skilled in the art that various alternatives and / or equivalent designs may be made with respect to the specific embodiments shown and described without departing from the scope of the invention. Therefore, this application should cover any modifications or variations of the specific embodiments discussed herein. It is therefore intentional that the invention be limited only by the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: A silicon carbide substrate (700) is provided, wherein the silicon carbide substrate (700) has a trench (750) extending from a main surface (701) of the silicon carbide substrate (700) into the silicon carbide substrate (700) and having a trench width (wg) at the bottom (751) of the trench. A shielding region (140) is constructed in the silicon carbide substrate (700), wherein the shielding region (140) extends along the bottom of the trench (751), and in at least one doped plane (105) extending substantially parallel to the bottom of the trench (751), the deviation of the dopant concentration in the shielding region (140) on a first lateral width (w1) from the maximum value of the dopant concentration in the doped plane (105) does not exceed 10%; and The first width (w1) is less than the trench width (wg) and is at least 30% of the trench width (wg); The construction of the shielding area (140) includes: Construct an injection mask (740) having an injection mask opening (741) of a third width (w3) at the bottom (751) of the trench, wherein the third width (w3) is greater than the first width (w1); and Dopant atoms are introduced through the injection mask opening (741); The dopant plane (105) connects the laterally adjacent local maximum values ​​of the vertical dopant distribution in the shielding region (140), and the deviation between the first width (w1) and the third width (w3) and twice the distance (d3) of the dopant plane (105) from the bottom of the trench (751) does not exceed ±10%.

2. The method according to claim 1, wherein the dopant plane (105) connects the laterally adjacent local maxima of the vertical dopant distribution in the shielding region (140).

3. The method according to claim 1 or 2, further comprising: A field dielectric (159) is constructed in the trench (750), wherein the field dielectric (159) has an opening (158) of a second width (w2) at the bottom (751) of the trench, and the second width (w2) is smaller than the first width (w1).

4. The method according to claim 3, wherein the field dielectric (159) has a sidewall segment (1593) of a first layer thickness (th1) along the sidewall (752) of the trench (750), the opening (158) has a second width (w2), and wherein the second width (w2) is less than the difference between the trench width (wg) and twice the first layer thickness (th1).

5. The method according to claim 1 or 2, wherein constructing the shielding region (140) comprises: An injection mask (740) is constructed, wherein the injection mask (740) is constructed to be thinner at the bottom (751) of the trench than at the sidewalls (752) of the trench (750), and Dopant atoms are introduced through the bottom (751) of the trench.

6. The method according to claim 1 or 2, wherein constructing the injection mask (740) comprises: An injection mask layer is constructed on the sidewall (752) and bottom (751) of the trench (750); and Remove the section of the injection mask layer at the bottom (751) of the trench, wherein the remaining section of the injection mask layer forms the injection mask (740).

7. The method of claim 5, wherein the introduction of dopant atoms comprises injection at at least two different acceleration energies, and the width of the injection mask opening (741) is varied between the injections.

8. The method of claim 5, wherein the injection mask (740) is removed before constructing the field dielectric (159).

9. The method of claim 8, wherein constructing the field dielectric (159) comprises: Construct a field dielectric layer (259) that line the trench (750), and remove a section of the field dielectric layer (259) at the bottom (751) of the trench.

10. The method of claim 9, wherein removing the segment of the field dielectric layer (259) comprises: An etching mask (760) is constructed on the field dielectric layer (259), wherein the etching mask (760) has an etching mask opening (761) of a second width (w2) at the bottom (751) of the trench, and Remove the section of the field dielectric layer (259) below the etch mask opening (761).

11. The method according to claim 1 or 2, further comprising: A conductive connection structure (157) is constructed in the trench (750), wherein a contact is formed between the connection structure (157) and the shielding area (140).

12. A semiconductor device having: The SiC semiconductor body (100) and gate electrode structure (150), wherein the gate electrode structure (150) extends from a first surface (101) of the SiC semiconductor body (100) into the SiC semiconductor body (100), and conductive connection structure (157), wherein the conductive connection structure (157) has a structural width (w0) at the bottom (152). A shielding region (140) is formed in the SiC semiconductor body (100) along the bottom (152). The shielding area (140) has a central section (145) with a first lateral width (w1). In at least one dopant plane (105) extending substantially parallel to the bottom (152), the deviation of the dopant concentration in the central segment (145) from the maximum dopant concentration in the shielding region (140) of the dopant plane (105) does not exceed 10%. A contact (OC) is formed between the conductive connection structure (157) and the shielding area (140), and the first width (w1) is smaller than the structure width (w0) and is at least 30% of the structure width (w0). A JFET sub-region (148) is constructed in the SiC semiconductor body (100), the JFET sub-region (148) and the shielding region (140) form a unipolar junction (jn), the shielding region (140) is constructed between the gate electrode structure (150) and the JFET sub-region (148), the JFET sub-region (148) has a fifth lateral width (w5) along the unipolar junction (jn), and the fifth width (w5) is smaller than the first width (w1).

13. The semiconductor device of claim 12, wherein the dopant plane (105) connects the laterally adjacent local maxima of the vertical dopant distribution in the shielding region (140).

14. The semiconductor device of claim 13, wherein the first width (w1) is less than the difference between the structure width (w0) and twice the average distance between the dopant plane (105) and the bottom (152).

15. The semiconductor device according to any one of claims 12-14, wherein the gate electrode structure (150) has a field dielectric (159), the field dielectric (159) having a sidewall segment (1593) of a first layer thickness (th1) along the sidewall (153) of the gate electrode structure (150), and the connection structure (157) having a second width (w2) at the bottom (152), wherein the second width (w2) is less than the difference between the structural width (w0) of the gate electrode structure (150) at the bottom (152) and twice the first layer thickness (th1).

16. The semiconductor device of claim 15, wherein the field dielectric (159) has a bottom segment (1592) with a second layer thickness (th2) along the bottom (152), the second layer thickness (th2) being at most equal to the first layer thickness (th1), and wherein the bottom segment (1592) is formed in an outer segment of the bottom (152) between a portion of the connection structure (157) and the shielding region (140).

17. The semiconductor device according to any one of claims 12-14, wherein the gate electrode structure (150) has a gate electrode (155) and a separation dielectric (156), wherein the gate electrode (155) is configured between the first surface (101) and the connection structure (157), and the separation dielectric (156) is configured between the gate electrode (155) and the connection structure (157).

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