Embedded component package structure and method of manufacturing the same

Abstract

A method for manufacturing an embedded component package structure includes the following steps. A carrier is provided, and a semi-cured first dielectric layer is formed on the carrier, the semi-cured first dielectric layer having a first surface. A component is provided on the semi-cured first dielectric layer, and a heat source is provided above and below the component, respectively, to cure the first dielectric layer. A second dielectric layer is formed on the first dielectric layer to cover the component. A patterned wiring layer is formed on the second dielectric layer, the patterned wiring layer being electrically connected to the component.

Description

Technical Field

[0001] This invention relates to a component packaging structure and a method for manufacturing the same, and more particularly to an embedded component packaging structure and a method for manufacturing the same. Background Technology

[0002] In system-in-package (SiP) architectures, the technology of embedding semiconductor chips within the packaging substrate (SESUB) has become a key research focus for manufacturers in recent years due to its advantages of reducing noise interference to the packaging substrate and minimizing product size. To improve production yield, embedded components must be fixed within the packaging substrate to facilitate electrical connection between the subsequently fabricated patterned conductive lines and the embedded components. Therefore, improving the reliability of die bonding and packaging processes for embedded components, and preventing their detachment, is a pressing issue that the industry needs to address. Summary of the Invention

[0003] This invention relates to an embedded component packaging structure and its manufacturing method, which can improve the reliability of the packaging process.

[0004] According to one aspect of the present invention, a method for manufacturing an embedded component package structure is provided, comprising the following steps: providing a carrier board and forming a semi-cured first dielectric layer on the carrier board, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and providing heat sources from above and below the component respectively to cure the first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

[0005] According to one aspect of the present invention, an embedded component packaging structure is provided. The embedded component packaging structure includes a first dielectric layer, a component, a second dielectric layer, and a patterned wiring layer. The first dielectric layer has a first surface. The component is disposed on the first dielectric layer, wherein the first dielectric layer covers one side of the component, and the first dielectric layer has a coverage height relative to the first surface, the coverage height being greater than 3 micrometers. The second dielectric layer is disposed on the first dielectric layer and covers the component. The patterned wiring layer is disposed on the second dielectric layer and is electrically connected to the component.

[0006] According to one aspect of the present invention, an embedded component packaging structure is provided. The embedded component packaging structure includes a first dielectric layer, a component, a second dielectric layer, and a patterned circuit layer. The first dielectric layer has a first surface. The component is disposed on the first dielectric layer, wherein the bottom surface of the component is lower than the first surface. The second dielectric layer is disposed on the first dielectric layer and covers the component. The patterned circuit layer is disposed on the second dielectric layer and is electrically connected to the component.

[0007] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0008] Figure 1 and 2 A schematic diagram illustrating the manufacturing method of the embedded component package structure.

[0009] Figure 3 A schematic diagram and a partial enlarged view of an embedded component packaging structure according to an embodiment of the present invention are shown.

[0010] Figures 4 to 8 A schematic diagram illustrating a method for manufacturing an embedded component packaging structure according to an embodiment of the present invention.

[0011] Figure 9 A schematic diagram showing a patterned circuit layer formed on a carrier board.

[0012] Figure 10A and 10B A schematic diagram illustrating the formation of another patterned circuit layer on a carrier board.

[0013] Figure 11 A schematic diagram illustrating an embedded component packaging structure according to another embodiment of the present invention is shown.

[0014] Symbol Explanation

[0015] 100: Carrier board

[0016] 110: First dielectric layer

[0017] 120: Components

[0018] 130: Second dielectric layer

[0019] 200A-200D: Embedded component packaging structure

[0020] 200: Carrier board

[0021] 202: Conductive circuit layer

[0022] 210: First dielectric layer

[0023] 212: First Surface

[0024] 220: Components

[0025] 222: Connecting pad

[0026] 230: Second dielectric layer

[0027] 240, 250: Patterned circuit layers

[0028] 242, 252: Electrical contacts

[0029] 260, 270: Patterned insulating protective layer

[0030] B: Bottom surface

[0031] S1: Side view

[0032] H1: Coverage height

[0033] H2: Height difference

[0034] W: Thickness

[0035] Ha, Hb: Thermal energy

[0036] VO: Hollow

[0037] V1, V2, V3: Openings Detailed Implementation

[0038] The following are detailed descriptions of embodiments. These embodiments are merely illustrative and are not intended to limit the scope of protection of this invention. The same / similar symbols are used to denote the same / similar elements in the following descriptions.

[0039] Please refer to Figure 1 and 2 Before embedding a component 120 (e.g., a semiconductor chip) into the package structure, the component 120 is first placed on a first dielectric layer 110 of a carrier substrate 100. The first dielectric layer 110 is, for example, a prepreg. The carrier substrate 100 is supported by a support platform (not shown) and heated by a heating machine (not shown) to bring the first dielectric layer 110 to a predetermined temperature. The high temperature provided by the heating machine (approximately 80°C) allows the preheated first dielectric layer 110 to have predetermined adhesive creep characteristics and flowability, which is beneficial for die bonding between the component 120 and the first dielectric layer 110, thus fixing the component 120 onto the first dielectric layer 110. However, the high temperature of the first dielectric layer can also cause the curing speed to be too fast. Figure 2 As shown, after the first dielectric layer 110 is completely cured, a second dielectric layer 130 is formed on the first dielectric layer 110. The second dielectric layer 130 covers the top of the component 120.

[0040] In the aforementioned packaging process, when the adsorption head 10 adsorbs the component 120, the component 120 warps due to internal stress, resulting in insufficient adhesion between the bottom surface of the component 120 and the first dielectric layer 110 (incomplete adhesion). Simultaneously, in the subsequent curing process, the first dielectric layer 110 cures too quickly due to excessively high temperatures (e.g., approximately 80°C or higher), failing to effectively cover the surrounding surface (i.e., sides) of the component 120. This results in insufficient coverage of the component 120 by the first dielectric layer 110, making it prone to detachment. Consequently, the subsequent lamination of the second dielectric layer 130 and the patterning of the circuit cannot be performed.

[0041] To address the aforementioned problems, this embodiment proposes an embedded component packaging structure. Please refer to... Figure 3 The embedded component package structure 200A includes a carrier board 200, a first dielectric layer 210, a component 220, a second dielectric layer 230, a patterned circuit layer 240, and a patterned insulating protective layer 260. The carrier board 200 is, for example, a circuit board having a conductive circuit layer 202. The first dielectric layer 210 is disposed on the carrier board 200 and has a first surface 212. The component 220 is disposed on the first surface 212 of the first dielectric layer 210. The bottom surface B of the component 220 is lower than the first surface 212 so that the component 220 (e.g., a semiconductor chip) can be stably held on the first dielectric layer 210. The second dielectric layer is disposed on the first dielectric layer and covers the component. The patterned circuit layer 240 electrically connects to the component 220. The patterned insulating protective layer 260 covers the patterned circuit layer 240.

[0042] In one embodiment, a first dielectric layer 210 covers one side S1 surrounding the element 220, and the first dielectric layer 210 has a coverage height H1 relative to the first surface 212, which may be greater than 3 micrometers, so that the element 220 (e.g., a semiconductor chip) can be stably held on the first dielectric layer 210. In one embodiment, the bottom surface B of the element 220 and the first surface 212 have a height difference H2, which is, for example, greater than 3 micrometers. In one embodiment, the coverage height H of the first dielectric layer 210 is, for example, greater than or equal to 5 micrometers, and less than the thickness W of the element 220.

[0043] To address the aforementioned issues, this embodiment proposes a method for manufacturing an embedded component encapsulation structure. This method can simultaneously provide heat energy to the first dielectric layer from both above and below the embedded component. Furthermore, the embedded component is adsorbed by a preheated adsorption head and heated, which can improve the warping phenomenon. Therefore, the embedded component can be made to be closer to or completely bonded to the first dielectric layer, increasing the area and height of the embedded component coverage and making it less likely for the embedded component to fall off.

[0044] Please refer to Figures 4 to 9 According to an embodiment of the present invention, a method for manufacturing an embedded component package structure 200B includes the following steps: A carrier board 200 is provided, and a semi-cured first dielectric layer 210 is formed on the carrier board 200, the semi-cured first dielectric layer 210 having a first surface 212. An component 220 is provided on the semi-cured first dielectric layer 210, and heat energy Ha and Hb are simultaneously provided from above and below the component 220 respectively to cure the first dielectric layer 210. A second dielectric layer 230 is formed on the first dielectric layer 210 to cover the component 220. A patterned circuit layer 240 is formed on the second dielectric layer 230, the patterned circuit layer 240 being electrically connected to the component 220. The various process steps are described below with reference to the drawings.

[0045] Please refer to Figure 4 The carrier board 200 is, for example, a circuit board having a conductive circuit layer 202. The circuit board can be a copper foil substrate (CCL), a metal core PCB (MCPCB), or a ceramic substrate, etc. In another embodiment, the carrier board 200 is, for example, a glass substrate or a stainless steel substrate, serving only as a temporary support substrate and without conductive circuitry.

[0046] Please refer to Figure 5 A semi-cured first dielectric layer 210 is formed on a carrier plate 200, while a heating machine (not shown) below the carrier plate 200 provides stable heat energy Ha to maintain the first dielectric layer 210 at a predetermined temperature. In this embodiment, the temperature of the heat energy Ha is reduced from 80°C to 50°C, which avoids the first dielectric layer 210 curing too quickly and failing to effectively cover the sides of the component. On the other hand, after reducing the temperature of the heat energy Ha, the adhesive crawling characteristics and flowability of the semi-cured first dielectric layer 210 can still be maintained within a predetermined range to facilitate subsequent die bonding processes. Generally, the material of the first dielectric layer 210 can be a glass fiber-free resin material, such as one selected from the group consisting of liquid crystal polymers, BT (bismaleimide triazine) resin, semi-cured prepreg, ABF (Ajinomoto build-up) film, epoxy resin, and polyimide resin, but the present invention does not limit this.

[0047] Please refer to Figure 6A and 6B The preheated adsorption head 20 adsorbs the element 220, and the adsorption head 20 provides another heat energy Hb to the top of the element 220. The temperature of the other heat energy Hb is between 100-150°C, for example 130°C, which is higher than the temperature of the heat energy Ha transferred from below the carrier plate 200 to the first dielectric layer 210. Figure 6B As shown, after the element 220 absorbs the heat energy Hb transmitted from the preheated adsorption head 20, it can reduce the warping caused by the internal stress of the element 220 itself, so that the bottom surface B of the element 220 can remain flat, which is conducive to the subsequent fixation of the element 220 onto the first dielectric layer 210.

[0048] Please refer to Figure 7 After absorbing heat energy Hb, component 220 no longer warps (becomes planar), and its bottom surface B can be directly and flatly placed on the first dielectric layer 210 by being pressed down by the adsorption head 20. Furthermore, component 220 can directly transfer heat energy Hb to the first surface 212, causing the first dielectric layer 210 beneath component 220 to absorb heat energy Hb and melt, thereby increasing the fluidity of the first dielectric layer 210 and facilitating its effective coverage of one side S1 surrounding component 220. Please refer to... Figure 6C and 7 After the first dielectric layer 210 below component 220 absorbs heat energy Hb, the temperature of the first dielectric layer 210 surrounding component 220 can be raised from a predetermined temperature (e.g., 50°C) to about 130°C. Therefore, the adhesive creep characteristics and fluidity of the first dielectric layer 210 are relatively increased. Figure 6C As shown. When the heated component 220 comes into contact with the first dielectric layer 210, the adhesive creep and adhesion of the first dielectric layer 210 are better than when the first dielectric layer 110 comes into contact with the unheated component 120. Therefore, in this embodiment, the covering height of the first dielectric layer 210 is relatively increased.

[0049] like Figure 7 As shown, in one embodiment, the coverage height H1 of the first dielectric layer 210 on the side surface S1 of the element 220 is, for example, greater than 3 micrometers, or even greater than or equal to 5 micrometers, relative to the first surface 212. In this way, the element 220 can be securely fixed to the first dielectric layer 210. In one embodiment, the coverage height H1 of the first dielectric layer 210 is, for example, less than the thickness W of the element 220, but the present invention does not limit this.

[0050] Please refer to Figure 2 and 7 , Figure 1 and 2The current packaging process only heats the first dielectric layer 110 from one side, and the component 120 warps improperly without heating, causing the first dielectric layer 110 to fail to effectively cover the sides of the component 120. Furthermore, when the second dielectric layer 130 covers the first dielectric layer 110, a void VO easily forms around the component 120 (the area near the sides not covered by the first dielectric layer 110), and the second dielectric layer 130 cannot completely fill this void VO. Therefore, the component 120 can only contact the first dielectric layer 110 with its bottom surface, resulting in poor reliability after packaging. Conversely, Figure 7 The packaging process heats the first dielectric layer 210 using double-sided heating. Specifically, a predetermined temperature (e.g., 130°C) of heat energy Hb is provided above the first dielectric layer 210 to aid in localized heating and melting. Furthermore, preheating the component 220 with heat energy Hb prevents warping, allowing the first dielectric layer 210 to effectively cover the side surface S1 of the component 220 and control the coverage height H1 to be greater than a predetermined value. Therefore, the side surface S1 of the component 220 can be tightly covered by the first dielectric layer 210, which exhibits good adhesion or creepage, thereby improving the reliability of the packaged component 220. Simultaneously, after the component 220 is fixed to the first dielectric layer 210, it can be placed in an oven at a predetermined temperature (e.g., 180°C) and for a predetermined time (e.g., more than 30 minutes) to fully cure the first dielectric layer 210.

[0051] Furthermore, when component 220 is preheated by adsorption head 20 and placed on the first dielectric layer 210, the increased fluidity of the heat-melted first dielectric layer 210 allows the bottom surface B of component 220 to preferably be flush with or recessed below the first surface 212. In one embodiment, the height difference H2 between the bottom surface B of component 220 and the first surface 212 is preferably, for example, greater than 3 micrometers. Therefore, the manufacturing method of the present invention does not require the fabrication of a groove or opening on the first surface 212 to accommodate component 220, thereby reducing the opening process, nor does it require additional adhesive to be applied to the bottom surface B of component 220 to fix component 220. Instead, the dielectric material of the carrier plate 200 itself (i.e., the first dielectric layer 210) is directly bonded to the bottom surface B of component 220. Therefore, the reliability of component 220 after packaging is relatively improved, and the position of component 220 is accurately aligned, reducing alignment errors.

[0052] Please refer to Figure 8A second dielectric layer 230 is formed on the first dielectric layer 210 and covers the element 220. Specifically, the second dielectric layer 230 can completely cover the first dielectric layer 210 and the area surrounding the element 220. After the second dielectric layer 230 is fully cured, the element 220 is embedded between the first dielectric layer 210 and the second dielectric layer 230 to form an embedded element package structure. The embedded element 220 can be an active element (e.g., a transistor, IC chip, logic circuit element, power amplifier), a passive element (capacitor, inductor, resistor), or a combination thereof. The number of embedded elements is not limited to one; the first dielectric layer 210 and the second dielectric layer 230 can be a single-layer or multi-layer structure; the first dielectric layer 210 and the second dielectric layer 230 can be made of the same or different insulating materials, and the present invention does not impose any limitations on this.

[0053] Please refer to Figure 9 A patterned circuit layer 240 is formed on the second dielectric layer 230, and the patterned circuit layer 240 is electrically connected to the component 220. In one embodiment, the component 220 has at least one pad 222 located in an opening V1, and the patterned circuit layer 240 extends from the pad 222 of the component 220 into the opening V1 and onto the second dielectric layer 230. The method for manufacturing the patterned opening V1 is detailed below: First, after forming the second dielectric layer 230, an opening V1 is formed through the second dielectric layer 230 by wet etching or dry etching to expose at least one pad 222 of the component 220. Next, a patterned circuit layer 240 is formed on the second dielectric layer 230, and the patterned circuit layer 240 is electrically connected to the component 220 via the pad 222 in the opening V1. In one embodiment, the patterned circuit layer 240 may also be electrically connected to the conductive circuit layer 202 via another opening V2 penetrating the first dielectric layer 210 and the second dielectric layer 230 to form an embedded component package structure 200B. The patterned circuit layer 240 may be a copper layer or an aluminum layer. A patterned insulating protective layer 260 may also be covered on the patterned circuit layer 240 (see...). Figure 10B and Figure 3 For example, green paint or other insulating materials.

[0054] Please refer to Figure 10A and 10BAfter completing the patterned circuit layer 240 described above, another patterned circuit layer 250 can be formed on the carrier 200 to create an embedded component package structure 200C with double-sided (top and bottom) conductive lines. The manufacturing method of the patterned aperture V3 is similar to that of the aperture V1, except that the aperture V3 penetrates through the carrier 200 to expose the conductive circuit layer 202 of the carrier 200. Next, the patterned circuit layer 250 is formed on the other surface (i.e., the lower surface) of the carrier 200, and the lower patterned circuit layer 250 is electrically connected to the conductive circuit layer 202 via the aperture V3. In addition, in another embodiment, the lower patterned circuit layer 250 can also be electrically connected to the upper patterned circuit layer 240 via an interlayer conductive via or directly via a vertically connected through hole (not shown in the figure), and the present invention does not limit this.

[0055] Please refer to Figure 10B Patterned insulating protective layers 260 and 270 are formed on the upper and lower patterned circuit layers 240 and 250, respectively, exposing the upper and lower electrical contacts 242 and 252. The pads 222 of component 220 can be electrically connected to the upper and lower electrical contacts 242 and 252 via these two patterned circuit layers 240 and 250. The electrical contacts 242 and 252 are used, for example, to provide solder bumps, lead-free bumps, copper bumps, or gold bumps for electrical connection with external electronic signals; this invention is not limited thereto.

[0056] Please refer to Figure 9 and 11 In one embodiment, in Figure 9 The carrier 200 in the package may serve as a substrate for temporary support only, and the carrier 200 may be removed or detached to expose the conductive layer 202 of the embedded component package structure 200D, such as... Figure 11 As shown. In Figure 11 In this context, the conductive circuit layer 202 is not limited to a single layer; it can also be a multi-layer structure. Furthermore, a structure such as [missing information] can be fabricated beneath the conductive circuit layer 202. Figure 10B The patterned insulating protective layer 270 and electrical contacts 252 shown are not limited in this invention.

[0057] Although the embedded component packaging structure disclosed in the above embodiments of the present invention takes the laminated first dielectric layer 210 and the second dielectric layer 230 as an example, the embedded component can also be disposed in multiple laminated dielectric layers, and is not limited to only two layers. In addition, the embedded component 220 is not limited to being located only in the laminated first dielectric layer 210 and the second dielectric layer 230, and more embedded components can also be disposed between any two adjacent dielectric layers according to packaging requirements.

[0058] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for manufacturing an embedded component package structure, comprising: A first dielectric layer is formed on a carrier plate, the first dielectric layer having a first surface; An element is provided on the first dielectric layer, and a first heat source is provided above the element and a second heat source is provided below the element to cure the first dielectric layer; A second dielectric layer is formed on the first dielectric layer to cover the component, wherein the first heat source is removed before the second dielectric layer is formed on the first dielectric layer; A first opening is formed to penetrate the second dielectric layer to expose the pads of the component; as well as A patterned circuit layer is formed on the second dielectric layer, and the patterned circuit layer is electrically connected to the component.

2. The manufacturing method as described in claim 1, characterized in that, The first opening is formed by wet etching or dry etching.

3. The manufacturing method as described in claim 1, characterized in that, The patterned circuit layer extends from the pad of the element into the opening and onto the second dielectric layer.

4. The manufacturing method as described in claim 1, characterized in that, The patterned circuit layer is partially surrounded by the second dielectric layer.

5. The manufacturing method as described in claim 1, characterized in that, Before the element is provided on the first dielectric layer, a second heat source is provided from below the first dielectric layer to maintain the first dielectric layer at a predetermined temperature.

6. The manufacturing method as described in claim 5, characterized in that, Before the element is provided on the first dielectric layer, the second heat source is cooled from 80°C to 50°C.

7. The manufacturing method as claimed in claim 1, further comprising: A second opening is formed that penetrates the second dielectric layer and the first dielectric layer.

8. An embedded component packaging structure, comprising: A first dielectric layer having a first surface; A component is disposed on the first dielectric layer, wherein the first surface is substantially parallel to the bottom surface of the component, and wherein the first dielectric layer directly contacts the side surface of the component, and the first dielectric layer has a coverage height relative to the first surface, the coverage height being greater than 3 micrometers; A second dielectric layer is disposed on the first dielectric layer and covers the component; as well as A patterned circuit layer is disposed on the second dielectric layer, and the patterned circuit layer is electrically connected to the component. The first dielectric layer has bumps that protrude relative to the first surface, and the interface between the first dielectric layer and the bottom surface of the element is spaced apart from the first surface by the bumps.

9. The embedded component packaging structure as described in claim 8, characterized in that, The coating height is greater than or equal to 5 micrometers and less than the thickness of the element.

10. The embedded component packaging structure as described in claim 8, characterized in that, It further includes a circuit board, wherein the first dielectric layer is located on the circuit board.

11. The embedded component packaging structure as described in claim 8, characterized in that, The element has at least one pad, and the second dielectric layer has a first opening to expose the at least one pad, wherein the patterned circuit layer extends from the at least one pad of the element into the first opening and onto the second dielectric layer.

12. The embedded component packaging structure as described in claim 10, characterized in that, It also includes a second opening that penetrates through the first dielectric layer and the second dielectric layer.

13. The embedded component packaging structure as described in claim 12, characterized in that, The patterned circuit layer extends into the second opening and is electrically connected to the circuit board.

14. The embedded component packaging structure as described in claim 12, characterized in that, The second opening extends beyond the bottom surface of the element.

15. The embedded component packaging structure as described in claim 8, characterized in that, The thickness of the second dielectric layer on the top surface of the element is greater than the thickness of the element.

16. The embedded component packaging structure as described in claim 8, characterized in that, The second dielectric layer has a concave surface located between the first surface and the side surface of the element.

17. The embedded component packaging structure as described in claim 8, characterized in that, The second dielectric layer covers a first region of the side of the element and exposes a second region of the side of the element.

18. An embedded component packaging structure, comprising: A first dielectric layer having a first surface; A component is disposed on the first dielectric layer, wherein the first surface is substantially parallel to the bottom surface of the component, and wherein the bottom surface of the component is lower than the first surface; A second dielectric layer is disposed on the first dielectric layer and covers the component; as well as A patterned circuit layer is disposed on the second dielectric layer, and the patterned circuit layer is electrically connected to the component. The first dielectric layer has bumps that protrude relative to the first surface, and the interface between the first dielectric layer and the bottom surface of the element is spaced apart from the first surface by the bumps.

19. The embedded component packaging structure as described in claim 18, characterized in that, The bottom surface of the element has a height difference from the first surface, and the height difference is greater than 3 micrometers.

20. The embedded component packaging structure as described in claim 18, characterized in that, The patterned circuit layer extends below the bottom surface of the element.

21. The embedded component packaging structure as described in claim 18, characterized in that, The height of the bump is greater than or equal to 5 micrometers and less than the thickness of the element.

22. The embedded component packaging structure as described in claim 18, characterized in that, It further includes a circuit board, wherein the first dielectric layer is located on the circuit board, and the patterned circuit layer is electrically connected to the circuit board.

23. The embedded component packaging structure as described in claim 18, characterized in that, The element has at least one pad, and the second dielectric layer has an opening to expose the at least one pad, wherein the patterned circuit layer extends from the at least one pad of the element into the opening and onto the second dielectric layer.

24. The embedded component packaging structure as described in claim 18, characterized in that, The bottom surface of the element is directly connected to the first dielectric layer.

25. The embedded component packaging structure as described in claim 18, characterized in that, The portion of the patterned circuit layer tapers toward the bottom surface of the element.

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