Carrier substrate and packaging method using carrier substrate

Abstract

The present application provides a carrier substrate and a packaging method, the carrier substrate comprising a first layer, a second layer, and a first adhesive layer between the first layer and the second layer, wherein the first adhesive layer is removably attached to the first layer.

Description

[0001] Cross-reference to related applications

[0002] The entire contents of Korean Patent Application No. 10-2018-0127159, entitled "Carrier substrate and packaging method using carrier substrate", filed with the Korean Intellectual Property Office on October 24, 2018, are incorporated herein by reference. Technical Field

[0003] The embodiments relate to a carrier substrate and a packaging method using the carrier substrate. Background Technology

[0004] Semiconductor packages can be provided to realize integrated circuit chips suitable for electronic products. The semiconductor package can be configured to mount the semiconductor chip on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chip to the PCB.

[0005] Semiconductor packaging can be performed in several steps. In some steps, the components may be heated. The heated components can then be cooled again. Semiconductor packaging can be performed on a carrier substrate. Summary of the Invention

[0006] An embodiment can be implemented by providing a carrier substrate including a first layer, a second layer, and a first adhesive layer between the first layer and the second layer, wherein the first adhesive layer is removably attached to the first layer.

[0007] An embodiment can be implemented by providing a packaging method comprising: preparing a carrier substrate such that the carrier substrate includes a first layer and a second layer on the first layer; performing a first processing on the carrier substrate; and removing the second layer from the first layer.

[0008] An embodiment can be implemented by providing a packaging method comprising: preparing a carrier substrate such that the carrier substrate includes a first layer; performing a first treatment on the carrier substrate; and adding a second layer on the first layer. Attached Figure Description

[0009] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A flowchart of a packaging method using a carrier substrate according to some exemplary embodiments is shown.

[0011] Figure 2 The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 1 A cross-sectional view of the step in the packaging method for preparing the carrier substrate.

[0012] Figure 3A The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 1 A cross-sectional view of the first processing step performed in the encapsulation method.

[0013] Figure 3B It shows Figure 3A Enlarged cross-sectional view of part C.

[0014] Figure 3C It shows Figure 3A Enlarged cross-sectional view of part C.

[0015] Figure 4 The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 1 A cross-sectional view of the step of removing the third layer in the encapsulation method.

[0016] Figure 5 The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 1 A cross-sectional view of the second processing step performed in the encapsulation method.

[0017] Figure 6 The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 1 A cross-sectional view of the step of removing the second layer in the encapsulation method.

[0018] Figure 7 A flowchart of a packaging method using a carrier substrate according to some exemplary embodiments is shown.

[0019] Figure 8 The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 7 A cross-sectional view of the step in the packaging method for preparing the carrier substrate.

[0020] Figure 9 The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 7 A cross-sectional view of the first processing step performed in the encapsulation method.

[0021] Figure 10 The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 7 A cross-sectional view of the step of adding a second layer in the encapsulation method.

[0022] Figure 11 The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 7 A cross-sectional view of the second processing step performed in the encapsulation method.

[0023] Figure 12The following are examples illustrating the use of a carrier substrate according to some exemplary embodiments. Figure 7 A cross-sectional view of the step of adding a third layer in the encapsulation method. Detailed Implementation

[0024] Figure 1 A flowchart of a packaging method using a carrier substrate according to some exemplary embodiments is shown.

[0025] Reference Figure 1 The semiconductor packaging method S may include the steps of preparing a carrier substrate, S1, performing a first process, S2, removing a third layer, S3, performing a second process, S4, removing a second layer, S5, performing a third process, and removing a first layer.

[0026] Figure 2 It shows that according to Figure 1 The flowchart shows a cross-sectional view of step S1 in the process of preparing the carrier substrate.

[0027] exist Figure 2 In the accompanying drawings, the direction to the right can be referred to as the first direction D1, the upward direction can be referred to as the second direction D2, and the forward direction can be referred to as the third direction D3 (perpendicular to the first direction D1 and the second direction D2). The first direction D1 can also be referred to as the right side, the second direction D2 can also be referred to as the upper side, the third direction D3 can also be referred to as the front side, and the direction opposite to the second direction D2 can be referred to as the lower side.

[0028] Reference Figure 2 In step S1, a carrier substrate 1 may be provided. A substrate 3 (e.g., a buffer) may be disposed on the carrier substrate 1, on which semiconductor chips (see [reference]) will be stacked. Figure 3A (5). The substrate 3 may be or may include a printed circuit board (PCB), etc. The substrate 3 may include, for example, other suitable components on which the semiconductor chip 5 will be stacked. In an embodiment, the semiconductor chip 5 may be stacked on a carrier substrate 1 on which the substrate 3 is not provided.

[0029] In one embodiment, an adhesive layer 4 may be provided between the carrier substrate 1 and the substrate 3. The adhesive layer 4 can rigidly place or attach the substrate 3 to the carrier substrate 1. In another embodiment, the substrate 3 may be placed directly on the carrier substrate 1 without the adhesive layer 4 being provided therebetween.

[0030] The carrier substrate 1 may have a multilayer structure. In an embodiment, the carrier substrate 1 may include a first layer 111, a second layer 113, a third layer 115, a first adhesive layer 131, and a second adhesive layer 133.

[0031] The first layer 111 can be disposed on the second layer 113. The second layer 113 can be disposed on the third layer 115. For example, the first layer 111, the second layer 113, and the third layer 115 can be arranged in the aforementioned order in a downward direction. In the embodiment, as... Figure 2 As shown, three layers 111, 113, and 115 can be provided. In one embodiment, only two layers may be provided. In another embodiment, four or more layers may be provided.

[0032] The coefficient of thermal expansion (CTE) of the first layer 111 can be greater than that of the second layer 113. The coefficient of thermal expansion of the second layer 113 can be greater than that of the third layer 115. For example, the coefficients of thermal expansion can decrease in the order of the first layer 111, the second layer 113, and the third layer 115.

[0033] In one embodiment, the first layer 111, the second layer 113, and the third layer 115 may comprise glass. In another embodiment, the first layer 111 may comprise metal, and the second layer 113 and the third layer 115 may comprise glass. The coefficient of thermal expansion of the metal may be greater than that of the glass. In yet another embodiment, the first layer 111 may comprise an organic material, the second layer 113 may comprise metal, and the third layer 115 may comprise glass. The coefficient of thermal expansion of the organic material may be greater than that of the metal. In yet another embodiment, the first layer 111, the second layer 113, and the third layer 115 may comprise other suitable materials, wherein the coefficient of thermal expansion of the other suitable materials decreases in the order of the first layer 111, the second layer 113, and the third layer 115.

[0034] A first adhesive layer 131 may be disposed on the second layer 113. The first adhesive layer 131 may be located between the first layer 111 and the second layer 113. The first adhesive layer 131 may couple the first layer 111 to the second layer 113. The first adhesive layer 131 may include, for example, silicone resin, epoxy resin, acrylic resin, or other resins. The first adhesive layer 131 may be removably attached to the first layer 111. For example, the first adhesive layer 131 may be separated from and removed from the first layer 111 using various physical and / or chemical methods. A detailed description thereof will be discussed further below.

[0035] The second adhesive layer 133 may be disposed on the third layer 115. The second adhesive layer 133 may be located between the second layer 113 and the third layer 115. The second adhesive layer 133 may couple the second layer 113 to the third layer 115. The second adhesive layer 133 may include, for example, silicone resin, epoxy resin, acrylic resin, resin, etc. The second adhesive layer 133 may be removably attached to the second layer 113. For example, the second adhesive layer 133 may be detached and removed from the second layer 113 by various physical and / or chemical methods. Further details will be discussed below.

[0036] Figure 3A It shows that according to Figure 1 The flowchart shows a cross-sectional view of step S2 of the first processing step.

[0037] Reference Figure 3A The first process can be performed in step S2. The first process can be performed on the carrier substrate 1. The first process may include heating and / or cooling the carrier substrate 1 and / or the components on the carrier substrate 1. The first process may raise or lower the temperature of the carrier substrate 1 and / or the components on the carrier substrate 1.

[0038] The first process may include stacking semiconductor chips 5. Semiconductor chips 5 may include logic chips and / or memory chips. Semiconductor chips 5 may be stacked on substrate 3 and / or carrier substrate 1. The first process may further include heating or cooling the stacked semiconductor chips 5. For example, after stacking semiconductor chips 5, semiconductor chips 5 may be heated. The heated semiconductor chips 5 may then be cooled down.

[0039] Figure 3B It shows Figure 3A Enlarged cross-sectional view of part C.

[0040] Reference Figure 3B The semiconductor chip 5 may include a single die or chip 51. The chip 51 and the substrate 3 may be electrically connected to each other via one or more conductive terminals 53. The chip 51 may be adhered to the substrate 3 via an adhesive pattern 55. The adhesive pattern 55 may surround the conductive terminals 53. The adhesive pattern 55 may include a dielectric material. The adhesive pattern 55 may include polymers, resins, etc.

[0041] Figure 3C It shows Figure 3A Enlarged cross-sectional view of part C.

[0042] Reference Figure 3C The semiconductor chip 5 may include a chip 51, which comprises two or more chips 511, 513, 515, 517, and 519 stacked along a second direction D2. The chips 511, 513, 515, 517, and 519 stacked along the second direction D2 may be electrically connected to the substrate 3 via through electrodes and conductive terminals 53. In an embodiment, the chips 511, 513, 515, 517, and 519 may be electrically wired to the substrate 3. An adhesive pattern 55 may be provided between the chips 511, 513, 515, 517, and 519. The adhesive pattern 55 may couple the chips 511, 513, 515, 517, and 519 to each other, and / or couple the bottommost chip 519 to the substrate 3.

[0043] Return to reference Figure 3AMultiple semiconductor chips 5 can be provided on the first direction D1. These multiple semiconductor chips 5 can be arranged on the first direction D1 and spaced apart from each other. In one embodiment, three semiconductor chips 5 can be spaced apart from each other on the first direction D1. In another embodiment, more than one semiconductor chip 5 can be arranged on the first direction D1.

[0044] When one or more semiconductor chips 5 are on the carrier substrate 1 and / or substrate 3, the carrier substrate 1 and / or its overlying components can be heated. For example, the adhesive pattern 55 can be heated and cured to bond the semiconductor chip 5. In one embodiment, the adhesive pattern 55 can be heated and melted to bond the semiconductor chip 5. In another embodiment, the carrier substrate 1 and / or its overlying components can be heated for other purposes. One or more of the carrier substrate 1 and / or its overlying components can be heated and expanded.

[0045] Heat can be removed from the carrier substrate 1 and / or its covering components. One or more of the carrier substrate 1 and / or its covering components can be cooled and contracted.

[0046] In an implementation, the first process can be performed in such a way that one or more semiconductor chips 5 are stacked, heated, and / or cooled. For example, the first process may include a suitable process involving heating and / or cooling the carrier substrate 1 and / or its overlying components.

[0047] The coefficient of thermal expansion of the carrier substrate 1 may differ from that of the covered component. For example, the coefficient of thermal expansion of the carrier substrate 1 may be less than that of the adhesive pattern 55.

[0048] Figure 4 It shows that according to Figure 2 The flowchart shows a cross-sectional view of step S3, which involves removing the third layer.

[0049] Reference Figure 4 The third layer can be removed in step S3 (see...) Figure 3A (115). The third layer 115 can be separated from the first layer 111 and the second layer 113 and removed from the carrier substrate 1.

[0050] The third layer 115 can be attached to the bottom of the second layer 113 via the second adhesive layer 133 and can then be removed together with the second adhesive layer 133. Various suitable methods can be used to separate the second adhesive layer 133 from the second layer 113. The second adhesive layer 133 can be physically and / or chemically separated from the second layer 113. In one embodiment, a laser can be used to separate the second adhesive layer 133 from the second layer 113. In another embodiment, physical impact can be used to separate the second adhesive layer 133 from the second layer 113. In this case, the physical impact can create cracks between the second adhesive layer 133 and the second layer 113, and these cracks can lead to the removal of the second adhesive layer 133 from the second layer 113. In yet another embodiment, other suitable methods can be used to separate the second adhesive layer 133 from the second layer 113.

[0051] In one implementation, the third layer 115 may be attached to the second layer 113 without the second adhesive layer 133 located between the third layer and the second layer, and the third layer 115 can then be removed from the second layer 113. Various suitable methods can be performed to remove the third layer 115. For example, various physical and / or chemical methods can be used to separate the third layer 115 from the second layer 113.

[0052] The coefficient of thermal expansion of the removed third layer 115 can be less than that of the first layer 111 and / or the second layer 113. The coefficient of thermal expansion of the carrier substrate 1 from which the third layer 115 has been removed can be greater than that of the carrier substrate 1 still including the third layer 115. For example, the coefficient of thermal expansion of the carrier substrate 1 from which the third layer 115 has been removed can become close to the coefficient of thermal expansion of the components on the carrier substrate 1. The thickness and coefficient of thermal expansion of the third layer 115 to be removed can be appropriately selected taking into account the coefficient of thermal expansion of the components on the carrier substrate 1.

[0053] The carrier substrate 1, from which the third layer 115 has been removed, can have an upwardly moving neutral axis. For example, the entire structure including the carrier substrate 1 and the semiconductor chip 5 coupled thereto can also have a similarly upwardly moving neutral axis. In embodiments, the neutral axis can be an axis along which there is no stress when a bending moment is applied. As the neutral axis moves upward, the difference in the coefficients of thermal expansion between components above and below the neutral axis can be reduced. Warpage of the carrier substrate 1 and its overlying components can be reduced or prevented. The carrier substrate 1 and its overlying components can maintain their function.

[0054] In one implementation, the removed third layer 115 may be discarded. In another implementation, the removed third layer 115 may be retained and reused in other processes.

[0055] Figure 5 It shows that according to Figure 2The flowchart shows a cross-sectional view of step S4 of the second processing step.

[0056] Reference Figure 5 A second process can be performed in step S4. This second process can be performed on the carrier substrate 1. The second process may include heating and / or cooling the carrier substrate 1 and / or its covering components. The second process may raise or lower the temperature of the carrier substrate 1 and / or its covering components.

[0057] The second process may include molding. Molding can form a molding layer 7 to encapsulate the stacked semiconductor chips 5. Molding can be performed using a molding frame or the like.

[0058] The molding layer 7 helps protect the packaged semiconductor chip 5 from the influence of the external environment. The molding layer 7 helps protect the semiconductor chip 5 from external heat, moisture, impact, etc. The molding layer 7 can dissipate heat generated from the semiconductor chip 5 and / or the substrate 3. In some embodiments, the molding layer 7 may include, for example, an epoxy molding compound (EMC). In some embodiments, the molding layer 7 may include other dielectric materials.

[0059] Heat can be supplied to the carrier substrate 1 and / or its covering components to form the molding layer 7. One or more of the carrier substrate 1 and / or its covering components can be heated and expanded. Heat can be removed from the carrier substrate 1 and / or its covering components to form the molding layer 7. One or more of the carrier substrate 1 and / or its covering components can be cooled and contracted.

[0060] In one embodiment, the second process can be performed by heating and / or cooling the carrier substrate 1 and its overlying components to form the molding layer 7. In another embodiment, the second process may include a suitable process involving heating and / or cooling the carrier substrate 1 and / or its overlying components.

[0061] The coefficient of thermal expansion of the carrier substrate 1 may differ from that of the components on the carrier substrate 1. The coefficient of thermal expansion of the carrier substrate 1 may be smaller than that of the adhesive pattern (see...). Figure 3A or Figure 3B The coefficient of thermal expansion of the molding layer 7 and the coefficient of thermal expansion of the adhesive pattern 55 are considered. In this embodiment, the coefficient of thermal expansion of the molding layer 7 may be greater than the coefficient of thermal expansion of the adhesive pattern 55, and the coefficient of thermal expansion of the adhesive pattern 55 may be greater than the coefficient of thermal expansion of the carrier substrate 1. For example, the coefficient of thermal expansion of the components on the carrier substrate 1 may be greater than the coefficient of thermal expansion of the carrier substrate 1.

[0062] Figure 6 It shows that according to Figure 2 The flowchart shows a cross-sectional view of step S5, which involves removing the second layer.

[0063] Reference Figure 6The second layer can be removed in step S5 (see...) Figure 5 (113). The second layer 113 can be separated from the first layer 111, and therefore can be removed from the carrier substrate 1.

[0064] The second layer 113 can be attached to the bottom of the first layer 111 via the first adhesive layer 131 and can then be removed together with the first adhesive layer 131. Various suitable methods can be used to separate the first adhesive layer 131 from the first layer 111. The first adhesive layer 131 can be physically and / or chemically separated from the first layer 111. In one embodiment, a laser can be used to separate the first adhesive layer 131 from the first layer 111. In another embodiment, physical impact can be used to separate the first adhesive layer 131 from the first layer 111. In this case, the physical impact can create cracks between the first adhesive layer 131 and the first layer 111, and these cracks can lead to the removal of the first adhesive layer 131 from the first layer 111. In yet another embodiment, other suitable methods can be used to separate the first adhesive layer 131 from the first layer 111.

[0065] The second layer 113 may be attached to the first layer 111 without the first adhesive layer 131 located between the second layer and the first layer, and the second layer 113 may be removed from the first layer 111. Various suitable methods may be performed to remove the second layer 113. For example, various physical and / or chemical methods may be used to separate the second layer 113 from the first layer 111.

[0066] The coefficient of thermal expansion of the removed second layer 113 can be less than that of the first layer 111. The coefficient of thermal expansion of the carrier substrate 1 from which the second layer 113 has been removed can be greater than that of the carrier substrate 1 still containing the second layer 113. For example, the coefficient of thermal expansion of the carrier substrate 1 from which the second layer 113 has been removed may become close to that of the components on the carrier substrate 1. The thickness and coefficient of thermal expansion of the second layer 113 to be removed can be appropriately selected by taking into account the coefficient of thermal expansion of the components on the carrier substrate 1.

[0067] The carrier substrate 1, from which the second layer 113 has been removed, can have an upwardly moving neutral axis. Therefore, the entire structure including the carrier substrate 1 and the semiconductor chip 5 coupled thereto can also have an upwardly moving neutral axis. As the neutral axis moves upward, the difference in the coefficient of thermal expansion between components above and below the neutral axis can be reduced. Warpage of the carrier substrate 1 and its overlying components can be reduced or prevented. The carrier substrate 1 and its overlying components can maintain their function.

[0068] In one implementation, the removed second layer 113 may be discarded. Alternatively, the removed second layer 113 may be retained and reused in other processes.

[0069] In step S6, a third process can be performed to complete the semiconductor package. The carrier substrate 1 and / or its covering components can be heated and / or cooled.

[0070] In step S7, the first layer 111 can be removed. The first layer 111 can be separated from the substrate 3 and / or the adhesive layer 4, and therefore can be removed from the semiconductor package.

[0071] In one embodiment, the carrier substrate 1 may include three layers 111, 113, and 115. In another embodiment, the number of layers to be removed from the carrier substrate 1 may be determined differently, taking into account the coefficient of thermal expansion of the components on the carrier substrate 1 and the number of processes.

[0072] In a semiconductor packaging method S according to some exemplary embodiments, warping of the carrier substrate 1 and its covered components can be prevented even though the carrier substrate 1 and / or its covered components are heated or cooled during the packaging process.

[0073] The carrier substrate 1 may include a material different from that of the components on the carrier substrate 1. The coefficient of thermal expansion of the carrier substrate 1 may differ from that of the components on the carrier substrate 1. For example, the coefficient of thermal expansion of the components on the carrier substrate 1 may be greater than that of the carrier substrate 1. For example, when heating and / or cooling processes are performed, the carrier substrate 1 and its covered components may expand and / or contract at different rates. When the carrier substrate 1 and its covered components expand and / or contract at different rates, bending can be applied to the entire structure, including the carrier substrate 1 and its covered components.

[0074] In a semiconductor packaging method S according to some exemplary embodiments, when heating and / or cooling are performed, one or more components constituting the carrier substrate 1 can be removed to change the coefficient of thermal expansion of the carrier substrate 1. For example, the coefficient of thermal expansion of the carrier substrate 1 can be increased. Therefore, a large difference in the coefficient of thermal expansion between the carrier substrate 1 and its covered components can be avoided. The carrier substrate 1 and its covered components will not warp. The stress on the semiconductor package can be reduced. The semiconductor package can maintain its structure and function. The packaging process can be performed continuously, and subsequent processing can be performed. The packaging process can be performed at high speed. The packaging process can increase throughput. The semiconductor package can reduce processing costs.

[0075] In a semiconductor packaging method S according to some exemplary embodiments, the carrier substrate 1 can control its coefficient of thermal expansion at each step by removing materials with different coefficients of thermal expansion, which overcomes the limitations in developing raw materials for the carrier substrate 1. The carrier substrate 1 can be formed from various materials. The carrier substrate 1 can reduce processing costs. Furthermore, the materials of the substrate and molding layer constituting the semiconductor package can be freely selected. The semiconductor package can be unrestricted in the selection of raw materials.

[0076] Figure 7 A flowchart of a packaging method using a carrier substrate according to some exemplary embodiments is shown.

[0077] In the following embodiments, for ease of explanation, references to the above will be omitted. Figures 1 to 6 The components and / or processes discussed are substantially the same or similar to those components and / or processes.

[0078] Reference Figure 7 The semiconductor packaging method S' may include the steps of preparing a carrier substrate S1', performing a first process S2', adding a second layer S3', performing a second process S4', adding a third layer S5', performing a third process S6', and removing the carrier substrate S7'.

[0079] Figure 8 It shows that according to Figure 7 The flowchart shows a cross-sectional view of step S1' in the process of preparing the carrier substrate.

[0080] Reference Figure 8 In step S1', a carrier substrate 1' may be provided. A substrate 3 may be disposed on the carrier substrate 1', and semiconductor chips (see [reference]) may be stacked on the substrate 3. Figure 9 (5) In an embodiment, an adhesive layer 4 may also be provided between the carrier substrate 1' and the substrate 3. In an embodiment, the substrate 3 may be placed on the carrier substrate 1' without the adhesive layer 4 being provided therebetween. In contrast, semiconductor chips (see...) Figure 9 5) can be directly stacked on the carrier substrate 1' on which no substrate 3 is provided.

[0081] The carrier substrate 1' provided in step S1' may have a single-layer structure. The carrier substrate 1' may include a first layer 111'. The first layer 111' may include glass, etc.

[0082] Figure 9 It shows that according to Figure 7 The flowchart shows a cross-sectional view of step S2' of the execution of the first processing step.

[0083] Reference Figure 9 The first process can be performed in step S2'. The first process can be performed on the carrier substrate 1'. The first process may include heating and / or cooling the carrier substrate 1' and / or the components on the carrier substrate 1'. The first process may raise or lower the temperature of the carrier substrate 1' and / or its covered components.

[0084] The first process may include stacking one or more semiconductor chips 5. The stacking of semiconductor chips 5 may be related to a reference. Figure 3A The stacks discussed are essentially the same or similar.

[0085] In an implementation, the first process may be performed in such a way that one or more semiconductor chips 5 are stacked, heated, and / or cooled. For example, the first process may include any process involving heating and / or cooling the carrier substrate 1' and / or its overlying components. The coefficient of thermal expansion of the first layer 111' may be different from the coefficient of thermal expansion of the components on the first layer 111'. For example, the coefficient of thermal expansion of the first layer 111' may be smaller than the coefficient of thermal expansion of the components on the first layer 111'.

[0086] Figure 10 It shows that according to Figure 7 The flowchart adds a second layer to the cross-sectional view of step S3'.

[0087] Reference Figure 10 In step S3', a second layer 113' can be added below, for example, the first layer 111'. In an embodiment, the second layer 113' can be directly coupled to the bottom of the first layer 111' (e.g., the side of the first layer 111' away from the semiconductor chip 5). In an embodiment, the first adhesive layer 131' can be coupled to the bottom of the first layer 111', and the second layer 113' can be coupled to the first layer 111' through the first adhesive layer 131'. The first adhesive layer 131' can be configured to... (The sentence is incomplete and requires further context to be translated accurately.) Figure 2 The first adhesive layer 131 discussed is substantially the same as or similar to the first adhesive layer 131 discussed.

[0088] The coefficient of thermal expansion of the added second layer 113' can be greater than that of the first layer 111'. The coefficient of thermal expansion can increase in the order of the first layer 111' and the second layer 113' (e.g., below or on the bottom side of the carrier substrate 1'). The coefficient of thermal expansion of the carrier substrate 1' to which the second layer 113' has been added can be greater than that of the carrier substrate 1' before the addition of the second layer 113'. Therefore, the coefficient of thermal expansion of the carrier substrate 1' to which the second layer 113' has been added can be made close to the coefficient of thermal expansion of the components on the carrier substrate 1'. The thickness and coefficient of thermal expansion of the second layer 113' to be added can be appropriately selected by taking into account the coefficient of thermal expansion of the components on the carrier substrate 1'.

[0089] In one embodiment, the second layer 113' may include glass or metal. In another embodiment, the second layer 113' may include other suitable materials that give it a coefficient of thermal expansion greater than that of the first layer 111'.

[0090] Figure 11 It shows that according to Figure 7 The flowchart shows a cross-sectional view of step S4' of the second processing step.

[0091] Reference Figure 11A second process can be performed in step S4'. This second process can be performed on the carrier substrate 1'. The second process may include heating and / or cooling the carrier substrate 1' and / or its covering components. The second process may raise or lower the temperature of the carrier substrate 1' and / or its covering components.

[0092] In an implementation, the second process may include a molding process. The molding process may be related to the above-mentioned reference process. Figure 5 The molding processes discussed are substantially the same or similar. For example, a molding layer 7 can be formed to encapsulate a semiconductor chip 5.

[0093] In one embodiment, the second process can be performed by heating and / or cooling the carrier substrate 1' and its overlying components to form the molding layer 7. In another embodiment, the second process may include suitable processes involving heating and / or cooling the carrier substrate 1' and / or its overlying components. The coefficient of thermal expansion of the carrier substrate 1' may differ from that of the components on the carrier substrate 1'. For example, the coefficient of thermal expansion of the carrier substrate 1' may be less than that of the molding layer 7.

[0094] Figure 12 It shows that according to Figure 7 The flowchart shows the cross-sectional view of step S5', which adds a third layer.

[0095] Reference Figure 12 In step S5', the third layer 115' can be added below the second layer 113' (e.g., on the side of the second layer 113' away from the semiconductor chip 5). In an embodiment, the third layer 115' can be directly coupled to the bottom of the second layer 113'. In an embodiment, the second adhesive layer 133' can be coupled to the bottom of the second layer 113', and the third layer 115' can be coupled to the second layer 113' through the second adhesive layer 133'. The second adhesive layer 133' can be configured to be connected to the aforementioned reference layer. Figure 2 The second adhesive layer 133 discussed is substantially the same as or similar to the second adhesive layer 133.

[0096] The coefficient of thermal expansion of the added third layer 115' can be greater than that of the second layer 113'. The coefficient of thermal expansion of the second layer 113' can be greater than that of the first layer 111', and the coefficient of thermal expansion of the third layer 115' can be greater than that of the second layer 113'. The coefficients of thermal expansion can increase in the order of the first layer 111', the second layer 113', and the third layer 115' below the carrier substrate 1' (e.g., in the downward direction of the carrier substrate 1'). The coefficient of thermal expansion of the carrier substrate 1' to which the third layer 115' has been added can be greater than that of the carrier substrate 1' before the addition of the third layer 115'. For example, the coefficient of thermal expansion of the carrier substrate 1' to which the third layer 115' has been added can become close to the coefficient of thermal expansion of the components on the carrier substrate 1'. The thickness and coefficient of thermal expansion of the third layer 115' to be added can be appropriately selected by taking into account the coefficient of thermal expansion of the components on the carrier substrate 1'.

[0097] In some embodiments, the third layer 115' may include glass, metal, or organic material. In some embodiments, the third layer 115' may include other suitable materials whose coefficient of thermal expansion is greater than that of the first layer 111' and / or the second layer 113'.

[0098] In step S6', a third process can be performed to complete the semiconductor package. The carrier substrate 1' and / or its covering components can be heated and / or cooled.

[0099] In step S7', the carrier substrate 1' can be completely removed. The carrier substrate 1' can be separated from the semiconductor package.

[0100] In one embodiment, the carrier substrate 1' may include three layers 111', 113', and 115'. In another embodiment, the number of layers to be added to the carrier substrate 1' may be determined differently, taking into account the coefficient of thermal expansion of the components on the carrier substrate 1' and the number of processes.

[0101] In a semiconductor packaging method S' according to some exemplary embodiments, when performing the packaging process, one or more components constituting the carrier substrate 1' may be added to change the coefficient of thermal expansion of the carrier substrate 1'. This can prevent large differences in the coefficients of thermal expansion between the carrier substrate 1' and its overlying components. Although the carrier substrate 1' and its overlying components can be heated or cooled, warpage of the carrier substrate 1' and its overlying components can be reduced or prevented. The carrier substrate 1' and its overlying components will not warp. The semiconductor package can reduce stress. The semiconductor package can maintain its structure and function. The packaging process can be performed continuously, and subsequent processes can be performed. The packaging process can be performed at high speed. The packaging process can increase throughput. The semiconductor package can reduce processing costs.

[0102] In the semiconductor packaging method S' according to some exemplary embodiments, by adding materials with different coefficients of thermal expansion, the carrier substrate 1' can control its coefficient of thermal expansion at each step, which overcomes the limitations in developing raw materials for the carrier substrate 1'. The carrier substrate 1' can be formed from various materials. The carrier substrate 1' can reduce processing costs. Furthermore, materials can be freely selected to form the substrate and molding layer constituting the semiconductor package. The semiconductor package is unrestricted in the selection of raw materials.

[0103] According to the embodiments, the difference in the coefficient of thermal expansion can be balanced in the carrier substrate and the packaging method using the carrier substrate.

[0104] It can suppress warping during the packaging process.

[0105] Subsequent processing can be performed continuously during the packaging process, which can increase packaging throughput.

[0106] It can overcome the limitations of developing raw materials for carrier substrates.

[0107] For example, the overall CTE of the carrier substrate can be gradually adjusted (e.g., increased or decreased) to adapt to the CTE of the chip or other device mounted on the carrier substrate during continuous operations of performing or forming the chip or other device. This adaptation between the CTE of the carrier substrate and the CTE of the chip or other device mounted thereon can help reduce or prevent warpage during semiconductor device packaging.

[0108] One or more embodiments may provide a carrier substrate capable of balancing differences in thermal expansion coefficients and a packaging method using the carrier substrate.

[0109] One or more embodiments may provide a carrier substrate capable of preventing warping during the packaging process and a packaging method using the carrier substrate.

[0110] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is for general and descriptive purposes only and not for limiting purposes. In some cases, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A packaging method, comprising: A carrier substrate is prepared such that the carrier substrate includes a first layer and a second layer on the first layer, wherein the coefficient of thermal expansion of the second layer is less than the coefficient of thermal expansion of the first layer; A first process is performed on the carrier substrate, wherein performing the first process includes placing a semiconductor chip on the first layer; Remove the second layer from the first layer; After the second layer is removed, a second process is performed on the carrier substrate, wherein performing the second process includes forming a molding layer covering the semiconductor chip on the first layer; and heating and / or cooling the semiconductor chip and / or the molding layer.

2. The packaging method according to claim 1, wherein, Performing the first process further includes: Heating the semiconductor chip; and Cool the semiconductor chip.

3. The packaging method according to claim 1, wherein, The carrier substrate further includes a third layer between the first layer and the second layer.

4. The packaging method according to claim 3 further includes: Remove the third layer from the first layer; and A third process is performed on the carrier substrate, wherein performing the third process includes heating and / or cooling the carrier substrate and / or the components on the carrier substrate.

5. The packaging method according to claim 4, wherein, The coefficient of thermal expansion of the third layer is less than that of the first layer.

6. A packaging method, comprising: Prepare a carrier substrate such that the carrier substrate includes a first layer; Perform a first process on the carrier substrate, wherein performing the first process includes: placing a semiconductor chip on the first layer; A second layer is added to the side of the first layer away from the semiconductor chip, wherein the coefficient of thermal expansion of the second layer is greater than that of the first layer; After the second layer is added, a second process is performed on the carrier substrate, wherein performing the second process includes molding and heating and / or cooling a semiconductor chip on the first layer.

7. The packaging method according to claim 6, wherein, Performing the first process further includes heating the semiconductor chip.

8. The packaging method according to claim 6, further comprising: Add a third layer on top of the second layer; and A third process is performed on the carrier substrate, wherein performing the third process includes heating and / or cooling the carrier substrate and / or the components on the carrier substrate.

9. The packaging method according to claim 8, wherein, The coefficient of thermal expansion of the third layer is greater than that of the second layer.

Images