Semiconductor device manufacturing method and semiconductor device

Abstract

The present disclosure provides a semiconductor device manufacturing method and a semiconductor device, belonging to the field of semiconductor technology. The method includes: providing a semiconductor substrate, including a first region and a second region, the upper surface of the first region is a dielectric layer; using a first mask layer to form a first conductive layer on the upper surface of the second region; using a second mask layer to selectively etch the dielectric layer and the first conductive layer to form a bit line contact hole in the first region and a gate electrode in the second region; forming a barrier layer; forming a second conductive layer to fill the gap between the bit line contact hole and the gate electrode, and cover the upper surface of the gate electrode; using a third mask layer to selectively etch the second conductive layer and the barrier layer to form a bit line structure in the first region and a gate structure in the second region. The present disclosure can improve the bit line contact, reduce the RC delay of the capacitor, and improve the poor contour depression of the peripheral gate structure, thereby improving device performance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device manufacturing method and a semiconductor device. Background Art

[0002] As the size of semiconductor devices decreases, the difficulty of semiconductor manufacturing processes also increases. In the case of small sizes, the contact resistance in the bit line structure has a greater impact on the overall resistance, resulting in an increase in the RC delay of the capacitor and a decrease in the read rate; in the gate structure of the peripheral circuit area, due to the reduction in size, when forming the gate electrode and the gate conductive layer, the junction is prone to the undesirable situation of contour depression, which affects the device performance.

[0003] The above two problems have become urgent issues to be solved in the industry, so it is necessary to propose a new semiconductor device manufacturing method.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a semiconductor device manufacturing method and a semiconductor device, thereby overcoming the problems of high capacitance RC delay and concave profile of peripheral gate structure in existing semiconductor devices at least to a certain extent.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region, the upper surface of the first region being a dielectric layer; forming a first conductive layer on the upper surface of the second region using a first mask layer; selectively etching the dielectric layer and the first conductive layer using a second mask layer to form a bit line contact hole of the first region and a gate electrode of the second region; forming a barrier layer, the barrier layer covering the upper surfaces of the first region and the second region, the inner wall of the bit line contact hole and the side wall of the gate electrode; forming a second conductive layer, the second conductive layer filling the gap between the bit line contact hole and the gate electrode and covering the upper surface of the gate electrode; and selectively etching the second conductive layer and the barrier layer using a third mask layer to form a bit line structure of the first region and a gate structure of the second region.

[0008] In an exemplary embodiment of the present disclosure, after forming the second conductive layer, the method further includes: forming an insulating layer; the selective etching of the second conductive layer and the barrier layer using a third mask layer to form a bit line structure of the first region and a gate structure of the second region includes: forming a third mask layer, the third mask layer defining a bit line pattern of the first region and a gate pattern of the second region; etching the insulating layer, the second conductive layer and the barrier layer, and removing the third mask layer to form a bit line structure of the first region and a gate structure of the second region.

[0009] In an exemplary embodiment of the present disclosure, the material of the insulating layer includes silicon nitride.

[0010] In an exemplary embodiment of the present disclosure, a shallow trench isolation structure and a buried gate are provided in the first region.

[0011] In an exemplary embodiment of the present disclosure, the forming of the barrier layer includes: depositing the barrier layer by using an ALD (Atomic Layer Deposition) process.

[0012] In an exemplary embodiment of the present disclosure, the forming of the second conductive layer includes: depositing a metal material using a HDPCVD (High Density Plasma Chemical Vapor Deposition) process to form the second conductive layer.

[0013] In an exemplary embodiment of the present disclosure, the metal material includes tungsten.

[0014] In an exemplary embodiment of the present disclosure, the material of the dielectric layer includes silicon nitride, the material of the first conductive layer includes polysilicon (Poly-Si), and the barrier layer includes a titanium nitride layer or a titanium nitride / tungsten silicide stack.

[0015] In an exemplary embodiment of the present disclosure, the third mask layer includes a hard mask layer, an anti-reflective layer and a photoresist layer.

[0016] In an exemplary embodiment of the present disclosure, the material of the hard mask layer includes one or more of silicon dioxide, silicon nitride and silicon oxynitride.

[0017] In an exemplary embodiment of the present disclosure, the first region is used to form a device cell array, and the second region is used to form a peripheral circuit.

[0018] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate, comprising a first region and a second region, the upper surface of the first region being a dielectric layer, and shallow trenches being provided in both the first region and the second region; a buried gate located in the first region; a gate electrode located on the upper surface of the second region; a bit line located in the first region; a barrier layer covering the upper surface of the gate electrode, the bottom and a portion of the sidewall of the bit line, separating the bit line from the dielectric layer; and a gate conductive layer covering the barrier layer above the gate electrode.

[0019] In an exemplary embodiment of the present disclosure, the semiconductor device further includes: an insulating layer covering upper surfaces of the bit line and the gate conductive layer.

[0020] The exemplary embodiments of the present disclosure have the following beneficial effects:

[0021] On the one hand, in the bit line structure, a barrier layer plus a single conductive material is used, so that the barrier layer and the conductive material together form a bit line contact, and the barrier layer has good adhesion to the lower area, which improves the effect of the bit line contact, reduces the contact resistance, and thus reduces the RC delay of the capacitor. On the other hand, in the gate structure of the peripheral circuit area, a multilayer structure of a gate electrode, a barrier layer, and a gate conductive layer is set. During the etching process of forming the gate structure, the barrier layer can protect the top and bottom contours of the gate electrode and prevent depressions at the corners, so that the formed gate structure has a higher quality, which is beneficial to improving the performance of the device. On the other hand, this exemplary embodiment simultaneously defines the bit line structure of the device unit array area and the gate structure of the peripheral circuit area through the second mask layer and the third mask layer, and improves the bit line contact of the device unit array area and the gate contour of the peripheral circuit area through the same barrier layer. The process flow is simple and the practicability is strong.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 A flowchart showing a method for manufacturing a semiconductor device in this exemplary embodiment;

[0025] Figures 2 to 13A schematic flow chart showing a method for manufacturing a semiconductor device in this exemplary embodiment;

[0026] Figures 14 to 16 A schematic diagram of a sub-flow diagram of a method for manufacturing a semiconductor device in this exemplary embodiment is shown;

[0027] Fig.17 A schematic structural diagram of a semiconductor device in this exemplary embodiment is shown;

[0028] Fig.18 A schematic diagram showing the structure of another semiconductor device in this exemplary embodiment;

[0029] Fig.19 A schematic structural diagram of yet another semiconductor device in this exemplary embodiment is shown. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0031] The exemplary embodiment of the present disclosure first provides a method for manufacturing a semiconductor device, referring to Figure 1 and Figure 2 to Figure 13 As shown, the method may include the following steps S110 to S160:

[0032] In step S110, reference Figure 2 and Figure 3 , a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a first region 110 and a second region 120 . The upper surface of the first region 110 is a dielectric layer 101 .

[0033] The first region 110 and the second region 120 are respectively used to form devices with different functions. In an exemplary embodiment, the first region 110 can be used to form a device unit array, and the second region 120 can be used to form a peripheral circuit.

[0034] Figure 2It is a top view, the semiconductor substrate 100 includes a first region 110 and a second region 120; the first region 110 defines a cell array of an active region 111, the active region 111 is separated by a shallow trench 112, and a buried gate 113 intersects with the active region 111; a peripheral active region 121 is also defined in the second region 120 of the peripheral circuit, and the peripheral active region 121 is also separated by a shallow trench 112. The semiconductor substrate 100 can be a p-type silicon substrate, an n-type silicon substrate, a silicon germanium substrate, etc., and a source and a drain can be set in the active region 111 and the peripheral active region 121. The side views of the first region 110 and the second region 120 are taken from AA' and BB' respectively, and the following is obtained: Figure 3 The upper surface of the first region 110 is covered with a dielectric layer 101 . In the semiconductor substrate 100 , shallow trenches 112 are formed on both sides of an active region 111 , and a buried gate 113 is formed inside.

[0035] It should be noted that Figure 2 and Figure 3 The structure shown is only exemplary, and the shallow trench 112 and the buried gate 113 can also be formed after the entire process of this embodiment, that is, a semiconductor substrate is initially provided to define a first region and a second region, wherein the first region is defined as an active region for forming a device unit array, and the top of the first region is covered by a dielectric layer, and the semiconductor substrate structure can be used for subsequent steps.

[0036] In step S120, reference Figure 4 and Figure 5 , a first conductive layer 102 is formed on the upper surface of the second region 120 using the first mask layer 103 .

[0037] Specifically, a first conductive layer 102 can be deposited on the upper surfaces of the first region 110 and the second region 120, and then a first mask layer 103 can be formed on the upper surface of the second region 120. The first conductive layer 102 is then etched, and the first conductive layer 102 on the upper surface of the first region 110 is removed. Finally, the first mask layer 103 is removed, and the first conductive layer 102 on the upper surface of the second region 120 is retained.

[0038] In an exemplary embodiment, the first mask layer 103 may be composed of an anti-reflection coating (ARC) and a photoresist layer (PR), which can achieve more accurate selective etching.

[0039] In an exemplary embodiment, before forming the first conductive layer, a gate oxide layer may be formed first, and the first conductive layer may be deposited on the gate oxide layer, which is beneficial for subsequently forming a more complete gate structure.

[0040] In step S130, reference Figure 6 , Figure 7 and Figure 8 , the dielectric layer 101 and the first conductive layer 102 are selectively etched using the second mask layer 104 to form a bit line contact hole 105 in the first region 110 and a gate electrode 106 in the second region 120 .

[0041] Figure 7 is a top view, Figure 8 for Figure 7 . The material of the second mask layer 104 may be the same as or different from that of the first mask layer 103. The second mask layer 104 may define the bit line contact pattern of the first region 110 and the gate electrode pattern of the second region 120. Specifically, the region of the bit line contact hole 105 of the first region 110 may be reserved, and the region of the gate electrode 106 of the second region 120 may be covered. Then, during the etching process, the dielectric layer 101 in the region of the bit line contact hole 105 in the first region 110 is etched, and the semiconductor substrate 100 may be used as an etching stop layer, and the rest is retained; the first conductive layer 102 in the region other than the gate electrode 106 in the second region 120 is etched, and the semiconductor substrate 100 is also used as an etching stop layer, and the retained first conductive layer 102 is the gate electrode 106. The gate electrode 106 is distributed in the peripheral active region 121 of the second region 120, and is a discrete structure, and there is a gap between each discrete gate electrode 106. By controlling the thickness of the dielectric layer 101, a bit line contact hole 105 of an ideal depth can be obtained, which is beneficial to the subsequent filling of the bit line contact hole 105 and prevents the occurrence of holes. After the etching is completed, the second mask layer 104 can be removed. Thus, the bit line contact hole 105 of the first area 110 and the gate electrode 106 of the second area 120 are defined simultaneously through one photolithography and etching.

[0042] In step S140, reference Fig. 9 , a barrier layer 107 is formed, and the barrier layer 107 covers the upper surfaces of the first region 110 and the second region 120 , the inner wall of the bit line contact hole 105 , and the side wall of the gate electrode 106 .

[0043] The blocking layer 107 should retain the pattern of the bit line contact hole 105 and the gate electrode 106, and usually has a small thickness. In addition, the blocking layer 107 covers the inner wall of the bit line contact hole 105 and may have a certain conductivity. The blocking layer 107 can usually be deposited using a CVD (Chemical Vapor Deposition) process, and the raw material gas can be selected according to the material composition of the blocking layer 107, and the raw material gas can be reacted by setting a suitable deposition temperature, pressure, etc., to deposit the material of the blocking layer 107.

[0044] In an exemplary embodiment, the barrier layer 107 may be deposited by using an ALD process, so that the thickness of the barrier layer 107 may be precisely controlled and have good thickness uniformity.

[0045] In step S150, reference Fig.10 , forming a second conductive layer 108 , the second conductive layer 108 fills the gap between the bit line contact hole 105 and the gate electrode 106 , and covers the upper surface of the gate electrode 106 .

[0046] When filling the second conductive layer 108, the gap between the bit line contact hole 105 and the gate electrode 106 is filled first, and then the filling can be continued so that the second conductive layer 108 covers the upper surface of the gate electrode 106, and also covers the upper surface of the first region 110. The second conductive layer 108 filled in the bit line contact hole 105 can be used to form a bit line contact, and the second conductive layer 108 above it can be used to form a bit line. The second conductive layer 108 directly above the gate electrode 106 can be used to form a gate conductive layer. The barrier layer 107 can prevent the second conductive layer 108 from interdiffusion with the semiconductor substrate 100, the dielectric layer 101, and the gate electrode 106.

[0047] In step S160, reference Figures 11 to 13 , the second conductive layer 108 and the barrier layer 107 are selectively etched using the third mask layer 109 to form a bit line structure 114 in the first region 110 and a gate structure 115 in the second region 120 .

[0048] Fig.11 It is a top view, and the third mask layer 109 defines a bit line pattern in the first region 110 and a gate pattern in the second region 120 . Fig.12 and Fig.13 AA', BB' and CC' are side views. It should be noted that the bit line pattern includes the barrier layer 107 region on the inner wall of the bit line contact hole 105, while the gate pattern does not include the barrier layer 107 region on the side wall of the gate electrode 106. After the third mask layer 109 is formed, the second conductive layer 108 and the barrier layer 107 are etched, and the dielectric layer 101 and the semiconductor substrate 100 are used as etching stop layers, and then the third mask layer 109 is removed, so that on the basis of the structure of the bit line contact hole 105 and the gate electrode 106, the bit line structure 114 of the first area 110 and the gate structure 115 of the second area 120 are simultaneously defined by one photolithography and etching.

[0049] The bit line structure 114 is composed of a barrier layer 107 and a second conductive layer 108 in the region of the bit line contact hole 105, wherein the barrier layer 107 and a portion of the second conductive layer 108 form a bit line contact, and the remaining portion of the second conductive layer 108 forms a bit line, thereby improving the effect of the bit line contact and reducing the contact resistance. The gate structure 115 is composed of a gate electrode 106, a barrier layer 107 and a second conductive layer 108, wherein the second conductive layer 108 can be regarded as a gate conductive layer. Due to the adhesion and protection of the barrier layer 107, when etching the material on both sides of the gate structure 115, the corners on both sides of the top of the gate electrode 106 and the corners on both sides of the bottom can retain a good profile to prevent depression, so that the gate structure 115 has a higher quality, which is conducive to improving the performance of the device.

[0050] It should be noted that during the etching process, the second conductive layer 108 and the barrier layer 107 in the area not covered by the third mask layer 109 need to be completely etched. Usually, the dielectric layer 101 in the first area 110 or the semiconductor substrate 100 in the second area 120 can be over-etched to a certain extent to prevent conduction between the bit lines or the gate conductive layers, which would affect the device performance.

[0051] It should be added that, in the above method, after a specific graphic structure is formed using a mask layer, the mask layer needs to be removed. After removing the mask layer, the upper surfaces of the first region and the second region can be planarized using a CMP (Chemical Mechanical Polishing) process to improve the quality of the semiconductor device structure.

[0052] Based on the above description, in this exemplary embodiment, on the one hand, in the bit line structure, a barrier layer plus a single conductive material is used, so that the barrier layer and the conductive material together form a bit line contact, and the barrier layer has good adhesion to the lower area, which improves the effect of the bit line contact, reduces the contact resistance, and thus reduces the RC delay of the capacitor. On the other hand, in the gate structure of the peripheral circuit area, a multilayer structure of a gate electrode, a barrier layer, and a gate conductive layer is set. During the etching process of forming the gate structure, the barrier layer can protect the top and bottom contours of the gate electrode and prevent the corners from being recessed, so that the formed gate structure has a higher quality, which is conducive to improving the performance of the device. On the other hand, this exemplary embodiment simultaneously defines the bit line structure of the device unit array area and the gate structure of the peripheral circuit area through the second mask layer and the third mask layer, and improves the bit line contact of the device unit array area and the gate contour of the peripheral circuit area through the same barrier layer. The process flow is simple and practical.

[0053] In an exemplary embodiment, after forming the second conductive layer 108, the semiconductor device manufacturing method may further include the following steps:

[0054] refer to Fig.14 , forming an insulating layer 116 . The insulating layer 116 can be deposited on the second conductive layer 108 to cover the entire first region 110 and the second region 120 .

[0055] Accordingly, step S160 may include the following steps:

[0056] refer to Fig.15 , forming a third mask layer 109, the third mask layer defines a bit line pattern of the first region 110 and a gate pattern of the second region 120;

[0057] refer to Fig.16 , the insulating layer 116 , the second conductive layer 108 and the blocking layer 107 are etched, and the third mask layer 109 is removed to form the bit line structure 114 in the first region 110 and the gate structure 115 in the second region 120 .

[0058] The insulating layer 116 is used to isolate the bit line structure 114, the gate structure 115 and the structure above them (the structure formed by the subsequent process). The materials of the insulating layer 116 and the dielectric layer 101 can be the same or different. When the materials of the two are the same, when etching the insulating layer 116, the second conductive layer 108 and the barrier layer 107, step-by-step etching can be adopted. First, a dielectric with a good etching effect on the insulating layer 116 is used for the first step of etching, and then a dielectric with a good etching effect on the second conductive layer 108 and the barrier layer 107 is used for the second step of etching. The second step of etching can use the dielectric layer 101 as an etching stop layer; when the materials of the two are different, the dielectric layer 101 can also be directly used as an etching stop layer, and the insulating layer 116, the second conductive layer 108 and the barrier layer 107 that are not covered by the third mask layer 109 can be removed by one etching. This embodiment does not specifically limit this.

[0059] The insulating layer 116 may be made of silicon oxide, silicon nitride, etc. In an exemplary embodiment, the material of the insulating layer 116 may be SiN. SiN has good insulating properties and is easy to deposit to form a silicon nitride layer through a CVD process, which has low cost and simple process.

[0060] In an exemplary embodiment, the first region has a shallow trench isolation structure and a buried gate. That is, before the process of this embodiment is performed, the shallow trench isolation structure and the buried gate are pre-formed, which is beneficial for accurately controlling the position and size of the peripheral gate, bit line contact and other patterns during the process of this embodiment.

[0061] For further reference, Fig.17As shown, the buried gate 113 may be composed of a buried gate oxide layer 117, an adhesion layer 118 and a buried gate conductive layer 119, wherein the buried gate oxide layer 117 may be a SiO2 layer, the adhesion layer 118 may be a TiN layer, and the buried gate conductive layer may be tungsten. The buried gate 113 of this structure forms a good active structure with the source and drain electrodes on both sides.

[0062] In an exemplary embodiment, a metal material may be deposited using a HDPCVD process to form a second conductive layer. Since the second conductive layer needs to fill the bit line contact holes and the trenches between the gate electrodes, the HDPCVD process may achieve a nearly complete filling effect, preventing the generation of a large number of holes that affect device performance.

[0063] Furthermore, the metal material of the second conductive layer may be tungsten, which is suitable as a gate conductive material, has good conductivity, high melting point, and has less temperature restrictions on subsequent processes.

[0064] In an exemplary embodiment, the material of the dielectric layer may be SiN, which has good dielectric properties and good isolation. The material of the first conductive layer may be polysilicon, which is suitable as a gate electrode material and has good electrical properties. In step S130, Cl2 / SF6 / Ar / O2 may be used as the dielectric gas for dry etching, which has good etching effects on SiN and polysilicon. The barrier layer may be a TiN layer or a TiN / WSi stack. The TiN layer has high adhesion to the dielectric layer and the second conductive layer, good contact effects, and good high temperature resistance and conductivity. Adding a WSi stack structure can further improve the contact effects.

[0065] In particular, when the material of the insulating layer is SiN, the material of the second conductive layer is metal W, and the material of the barrier layer is TiN, after forming the third mask layer, dry etching can be performed using a dielectric gas with a higher etching selectivity than W / SiN and TiN / SiN to completely remove the insulating layer, the second conductive layer and the barrier layer in the area outside the third mask layer.

[0066] In an exemplary embodiment, the third mask layer may include a hard mask layer, an anti-reflection layer and a photoresist layer. In step S160, in order to form the bit line structure of the first region and the gate structure of the second region, the second conductive layer and the barrier layer need to be etched away, and the etching depth is high. In this process, the structure below the third mask layer may be damaged. On the basis of the anti-reflection layer and the photoresist layer, adding a hard mask layer can produce a better etching prevention effect on the structure below.

[0067] Furthermore, the material of the hard mask layer may include one or more of SiO2, SiN and SiON. The above materials can provide good protection for the anti-reflection layer and the photoresist layer during the etching process to prevent the underlying structure from being etched. In addition, since the material of the hard mask layer is a commonly used dielectric material, the hard mask layer can be formed using a SOD (Spin-on Dielectric) process or a CVD process.

[0068] In an exemplary embodiment, before forming the first conductive layer in step S120, a gate oxide layer may be formed at the gate position of the second region, the first conductive layer may be deposited on the gate oxide layer, and subsequent steps may be performed. The semiconductor device structure finally obtained may be as follows: Fig.18 As shown, the gate structure 115 of the second region 120 may be composed of a gate oxide layer 122 , a gate electrode 106 , a barrier layer 107 and a second conductive layer 108 . The gate structure 115 is more complete and may form a better transistor structure with the source and drain in the semiconductor substrate 100 .

[0069] The exemplary embodiments of the present disclosure also provide a semiconductor device, referring to Fig.19 As shown, the semiconductor device may include: a semiconductor substrate 100, including a first region 110 and a second region 120, the upper surface of the first region 110 is a dielectric layer 101, and shallow trenches 112 are provided in the first region 110 and the second region 120; a buried gate 113, located in the first region 110; a gate electrode 106, located on the upper surface of the second region 120; a bit line 117, located in the first region 110; a barrier layer 107, covering the upper surface of the gate electrode 106, the bottom and a portion of the sidewall of the bit line 117, separating the bit line 117 from the dielectric layer 101; and a gate conductive layer 118, covering the barrier layer 107 above the gate electrode 106.

[0070] The bit line 117 may be a single film layer or a stack of a bit line contact layer and a bit line conductive layer. The bottom of the bit line 117 may be located in the semiconductor substrate 100 or the dielectric layer 101, and the top of the bit line 117 may exceed the upper surface of the dielectric layer 101 or may be flush with the upper surface of the dielectric layer 101, which is not particularly limited in this embodiment.

[0071] In the first region 110, the barrier layer 107 separates the bit line 117 from the dielectric layer 101, and separates the bit line 117 from the semiconductor substrate 100 at the bottom, which can protect the structure of the bit line 117, especially the contour of the bottom corner, and can prevent the mutual diffusion between the bit line 117 and the dielectric layer 101 or the semiconductor substrate 100. In the second region 120, the barrier layer 107 separates the gate electrode 106 from the gate conductive layer 118, which can protect the top corner structure of the gate electrode, and can prevent the mutual diffusion between the gate electrode 106 and the gate conductive layer 118.

[0072] In an exemplary embodiment, the material of the bit line 117 and the gate conductive layer 118 can be the same, for example, the material of both can be tungsten, so that when manufacturing the semiconductor device, the bit line 117 and the gate conductive layer 118 can be formed simultaneously through a one-step process (such as chemical vapor deposition or physical vapor deposition), thereby simplifying the process flow and reducing the production cost.

[0073] In particular, when the bit line 117 is composed of a bit line contact layer and a bit line conductive layer, the material of the bit line conductive layer and the gate conductive layer 118 may be the same. For example, the material of the bit line contact layer may be titanium nitride, and the material of the bit line conductive layer and the gate conductive layer 118 may be tungsten, etc., which is not particularly limited in this embodiment.

[0074] In an exemplary embodiment, the semiconductor device may further include an insulating layer covering the upper surfaces of the bit line 117 and the gate conductive layer 118 to isolate the bit line structure, the gate structure and the structure thereon (structure formed in a later process) to improve the stability of the semiconductor device.

[0075] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0076] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region, wherein an upper surface of the first region is a dielectric layer; forming a first conductive layer on the upper surface of the second region using a first mask layer; Selectively etching the dielectric layer and the first conductive layer using the second mask layer to form a bit line contact hole in the first region and a gate electrode in the second region; forming a barrier layer, the barrier layer covering the upper surfaces of the first region and the second region, the inner wall of the bit line contact hole and the side wall of the gate electrode; forming a second conductive layer, wherein the second conductive layer fills the gap between the bit line contact hole and the gate electrode and covers the upper surface of the gate electrode; The second conductive layer and the barrier layer are selectively etched using a third mask layer to form a bit line structure in the first region and a gate structure in the second region.

2. The method according to claim 1, characterized in that After forming the second conductive layer, the method further comprises: forming an insulating layer; The selective etching of the second conductive layer and the barrier layer by using the third mask layer to form the bit line structure of the first region and the gate structure of the second region comprises: forming a third mask layer, wherein the third mask layer defines a bit line pattern of the first region and a gate pattern of the second region; The insulating layer, the second conductive layer and the blocking layer are etched, and the third mask layer is removed to form a bit line structure in the first region and a gate structure in the second region.

3. The method according to claim 2, characterized in that The material of the insulating layer includes silicon nitride.

4. The method according to claim 1, characterized in that: The first region has a shallow trench isolation structure and a buried gate.

5. The method according to claim 1, characterized in that The forming of the barrier layer comprises: The barrier layer is deposited using an atomic layer deposition (ALD) process.

6. The method according to claim 1, characterized in that The forming of the second conductive layer comprises: The metal material is deposited by using a high density plasma chemical vapor deposition (HDPCVD) process to form the second conductive layer.

7. The method according to claim 6, characterized in that The metal material includes tungsten.

8. The method according to claim 1, characterized in that The material of the dielectric layer includes silicon nitride, the material of the first conductive layer includes polysilicon, and the barrier layer includes a titanium nitride layer or a titanium nitride / tungsten silicide stack.

9. The method according to claim 1, characterized in that: The third mask layer includes a hard mask layer, an anti-reflection layer and a photoresist layer.

10. The method according to claim 9, characterized in that The material of the hard mask layer includes one or more of silicon dioxide, silicon nitride and silicon oxynitride.

11. The method according to claim 1, characterized in that: The first region is used to form a device cell array, and the second region is used to form a peripheral circuit.

12. A semiconductor device, characterized in that: include: The semiconductor substrate comprises a first region and a second region, wherein the upper surface of the first region is a dielectric layer, and shallow trenches are provided in both the first region and the second region; A buried gate located in the first region; a gate electrode, located on an upper surface of the second region; A bit line located in the first region; a barrier layer covering the upper surface of the gate electrode, the bottom and a portion of the sidewall of the bit line, and separating the bit line from the dielectric layer; The gate conductive layer covers the barrier layer above the gate electrode.

13. The semiconductor device according to claim 12, characterized in that Also includes: The insulating layer covers the upper surfaces of the bit line and the gate conductive layer.

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